2 * Copyright (c) 2016 The FreeBSD Foundation
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6 * modification, are permitted provided that the following conditions
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30 compatible = "xlnx,zynq-7000";
33 interrupt-parent = <&GIC>;
35 // Reserve first half megabyte because it is not accessible to all
37 memreserve = <0x00000000 0x00080000>;
39 // Zynq PS System registers.
43 compatible = "simple-bus";
46 ranges = <0x0 0xf8000000 0xf10000>;
50 compatible = "xlnx,zy7_slcr";
54 // Interrupt controller
56 compatible = "arm,gic";
59 #interrupt-cells = <3>;
60 reg = <0xf01000 0x1000>, // distributer registers
61 <0xf00100 0x0100>; // CPU if registers
64 // L2 cache controller
66 compatible = "arm,pl310";
67 reg = <0xf02000 0x1000>;
69 interrupt-parent = <&GIC>;
74 compatible = "xlnx,zy7_devcfg";
75 reg = <0x7000 0x1000>;
77 interrupt-parent = <&GIC>;
80 // triple timer counters0,1
82 compatible = "xlnx,ttc";
83 reg = <0x1000 0x1000>;
87 compatible = "xlnx,ttc";
88 reg = <0x2000 0x1000>;
91 // ARM Cortex A9 TWD Timer
92 global_timer: timer@f00600 {
93 compatible = "arm,mpcore-timers";
96 reg = <0xf00200 0x100>, // Global Timer Regs
97 <0xf00600 0x20>; // Private Timer Regs
98 interrupts = <1 11 1>, <1 13 1>;
99 interrupt-parent = <&GIC>;
102 // system watch-dog timer
104 device_type = "watchdog";
105 compatible = "xlnx,zy7_wdt";
106 reg = <0x5000 0x1000>;
107 interrupts = <0 9 1>;
108 interrupt-parent = <&GIC>;
112 device_type = "watchdog";
113 compatible = "arm,mpcore_wdt";
114 reg = <0xf00620 0x20>;
115 interrupts = <1 14 1>;
116 interrupt-parent = <&GIC>;
122 // Zynq PS I/O Peripheral registers.
126 compatible = "simple-bus";
127 #address-cells = <1>;
129 ranges = <0x0 0xe0000000 0x300000>;
133 device_type = "serial";
134 compatible = "cadence,uart";
136 reg = <0x0000 0x1000>;
137 interrupts = <0 27 4>;
138 interrupt-parent = <&GIC>;
139 clock-frequency = <50000000>;
143 device_type = "serial";
144 compatible = "cadence,uart";
146 reg = <0x1000 0x1000>;
147 interrupts = <0 50 4>;
148 interrupt-parent = <&GIC>;
149 clock-frequency = <50000000>;
154 compatible = "xlnx,zy7_ehci";
156 reg = <0x2000 0x1000>;
157 interrupts = <0 21 4>;
158 interrupt-parent = <&GIC>;
162 compatible = "xlnx,zy7_ehci";
164 reg = <0x3000 0x1000>;
165 interrupts = <0 44 4>;
166 interrupt-parent = <&GIC>;
171 compatible = "xlnx,zy7_gpio";
172 reg = <0xa000 0x1000>;
173 interrupts = <0 20 4>;
174 interrupt-parent = <&GIC>;
177 // Gigabit Ethernet controllers
179 device_type = "network";
180 compatible = "cadence,gem";
182 reg = <0xb000 0x1000>;
183 interrupts = <0 22 4>;
184 interrupt-parent = <&GIC>;
189 device_type = "network";
190 compatible = "cadence,gem";
192 reg = <0xc000 0x1000>;
193 interrupts = <0 45 4>;
194 interrupt-parent = <&GIC>;
198 // Quad-SPI controller
200 compatible = "xlnx,zy7_qspi";
202 reg = <0xd000 0x1000>;
203 interrupts = <0 19 4>;
204 interrupt-parent = <&GIC>;
205 spi-clock = <50000000>;
209 sdhci0: sdhci@100000 {
210 compatible = "xlnx,zy7_sdhci";
212 reg = <0x100000 0x1000>;
213 interrupts = <0 24 4>;
214 interrupt-parent = <&GIC>;
215 max-frequency = <50000000>;
218 sdhci1: sdhci@101000 {
219 compatible = "xlnx,zy7_sdhci";
221 reg = <0x101000 0x1000>;
222 interrupts = <0 47 4>;
223 interrupt-parent = <&GIC>;
224 max-frequency = <50000000>;