2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
38 #include <sys/types.h>
39 #include <sys/malloc.h>
40 #include <sys/socket.h>
41 #include <sys/socketvar.h>
42 #include <sys/sockio.h>
43 #include <sys/taskqueue.h>
44 #include <netinet/in.h>
45 #include <net/route.h>
47 #include <netinet/in_systm.h>
48 #include <netinet/in_pcb.h>
49 #include <netinet/ip.h>
50 #include <netinet/ip_var.h>
51 #include <netinet/tcp_var.h>
52 #include <netinet/tcp.h>
53 #include <netinet/tcpip.h>
55 #include <netinet/toecore.h>
59 #include <linux/types.h>
61 #include "tom/t4_tom.h"
66 extern int db_delay_usecs;
67 extern int db_fc_threshold;
68 static void creds(struct toepcb *toep, size_t wrsize);
71 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
74 spin_lock_irqsave(&qhp->lock, flag);
75 qhp->attr.state = state;
76 spin_unlock_irqrestore(&qhp->lock, flag);
79 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
82 contigfree(sq->queue, sq->memsize, M_DEVBUF);
85 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
88 dealloc_host_sq(rdev, sq);
91 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
93 sq->queue = contigmalloc(sq->memsize, M_DEVBUF, M_NOWAIT, 0ul, ~0ul,
97 sq->dma_addr = vtophys(sq->queue);
100 sq->phys_addr = vtophys(sq->queue);
101 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
102 CTR4(KTR_IW_CXGBE, "%s sq %p dma_addr %p phys_addr %p", __func__,
103 sq->queue, sq->dma_addr, sq->phys_addr);
107 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
108 struct c4iw_dev_ucontext *uctx)
111 * uP clears EQ contexts when the connection exits rdma mode,
112 * so no need to post a RESET WR for these EQs.
114 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF);
115 dealloc_sq(rdev, &wq->sq);
116 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
119 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
120 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
124 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
125 struct t4_cq *rcq, struct t4_cq *scq,
126 struct c4iw_dev_ucontext *uctx)
128 struct adapter *sc = rdev->adap;
129 int user = (uctx != &rdev->uctx);
130 struct fw_ri_res_wr *res_wr;
131 struct fw_ri_res *res;
133 struct c4iw_wr_wait wr_wait;
138 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
142 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
147 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
152 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
158 /* RQT must be a power of 2. */
159 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
160 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
161 if (!wq->rq.rqt_hwaddr)
164 if (alloc_host_sq(rdev, &wq->sq))
167 memset(wq->sq.queue, 0, wq->sq.memsize);
168 pci_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
170 wq->rq.queue = contigmalloc(wq->rq.memsize,
171 M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 4096, 0);
173 wq->rq.dma_addr = vtophys(wq->rq.queue);
177 "%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx", __func__,
178 wq->sq.queue, (unsigned long long)vtophys(wq->sq.queue),
179 wq->rq.queue, (unsigned long long)vtophys(wq->rq.queue));
180 memset(wq->rq.queue, 0, wq->rq.memsize);
181 pci_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
183 wq->db = (void *)((unsigned long)rman_get_virtual(sc->regs_res) +
184 MYPF_REG(SGE_PF_KDOORBELL));
185 wq->gts = (void *)((unsigned long)rman_get_virtual(rdev->adap->regs_res)
186 + MYPF_REG(SGE_PF_GTS));
188 wq->sq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) +
189 (wq->sq.qid << rdev->qpshift));
190 wq->sq.udb &= PAGE_MASK;
191 wq->rq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) +
192 (wq->rq.qid << rdev->qpshift));
193 wq->rq.udb &= PAGE_MASK;
198 /* build fw_ri_res_wr */
199 wr_len = sizeof *res_wr + 2 * sizeof *res;
201 wr = alloc_wrqe(wr_len, &sc->sge.mgmtq);
206 memset(res_wr, 0, wr_len);
207 res_wr->op_nres = cpu_to_be32(
208 V_FW_WR_OP(FW_RI_RES_WR) |
209 V_FW_RI_RES_WR_NRES(2) |
211 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
212 res_wr->cookie = (unsigned long) &wr_wait;
214 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
215 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
217 /* eqsize is the number of 64B entries plus the status page size. */
218 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + spg_creds;
220 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
221 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
222 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
223 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
224 V_FW_RI_RES_WR_IQID(scq->cqid));
225 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
226 V_FW_RI_RES_WR_DCAEN(0) |
227 V_FW_RI_RES_WR_DCACPU(0) |
228 V_FW_RI_RES_WR_FBMIN(2) |
229 V_FW_RI_RES_WR_FBMAX(2) |
230 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
231 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
232 V_FW_RI_RES_WR_EQSIZE(eqsize));
233 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
234 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
236 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
237 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
239 /* eqsize is the number of 64B entries plus the status page size. */
240 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + spg_creds ;
241 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
242 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
243 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
244 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
245 V_FW_RI_RES_WR_IQID(rcq->cqid));
246 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
247 V_FW_RI_RES_WR_DCAEN(0) |
248 V_FW_RI_RES_WR_DCACPU(0) |
249 V_FW_RI_RES_WR_FBMIN(2) |
250 V_FW_RI_RES_WR_FBMAX(2) |
251 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
252 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
253 V_FW_RI_RES_WR_EQSIZE(eqsize));
254 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
255 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
257 c4iw_init_wr_wait(&wr_wait);
260 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
265 "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx",
266 __func__, wq->sq.qid, wq->rq.qid, wq->db,
267 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
271 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF);
273 dealloc_sq(rdev, &wq->sq);
275 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
281 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
283 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
287 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
288 struct ib_send_wr *wr, int max, u32 *plenp)
295 dstp = (u8 *)immdp->data;
296 for (i = 0; i < wr->num_sge; i++) {
297 if ((plen + wr->sg_list[i].length) > max)
299 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
300 plen += wr->sg_list[i].length;
301 rem = wr->sg_list[i].length;
303 if (dstp == (u8 *)&sq->queue[sq->size])
304 dstp = (u8 *)sq->queue;
305 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
308 len = (u8 *)&sq->queue[sq->size] - dstp;
309 memcpy(dstp, srcp, len);
315 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
317 memset(dstp, 0, len);
318 immdp->op = FW_RI_DATA_IMMD;
321 immdp->immdlen = cpu_to_be32(plen);
326 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
327 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
328 int num_sge, u32 *plenp)
333 __be64 *flitp = (__be64 *)isglp->sge;
335 for (i = 0; i < num_sge; i++) {
336 if ((plen + sg_list[i].length) < plen)
338 plen += sg_list[i].length;
339 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
341 if (++flitp == queue_end)
343 *flitp = cpu_to_be64(sg_list[i].addr);
344 if (++flitp == queue_end)
347 *flitp = (__force __be64)0;
348 isglp->op = FW_RI_DATA_ISGL;
350 isglp->nsge = cpu_to_be16(num_sge);
357 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
358 struct ib_send_wr *wr, u8 *len16)
364 if (wr->num_sge > T4_MAX_SEND_SGE)
366 switch (wr->opcode) {
368 if (wr->send_flags & IB_SEND_SOLICITED)
369 wqe->send.sendop_pkd = cpu_to_be32(
370 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
372 wqe->send.sendop_pkd = cpu_to_be32(
373 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
374 wqe->send.stag_inv = 0;
376 case IB_WR_SEND_WITH_INV:
377 if (wr->send_flags & IB_SEND_SOLICITED)
378 wqe->send.sendop_pkd = cpu_to_be32(
379 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
381 wqe->send.sendop_pkd = cpu_to_be32(
382 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
383 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
392 if (wr->send_flags & IB_SEND_INLINE) {
393 ret = build_immd(sq, wqe->send.u.immd_src, wr,
394 T4_MAX_SEND_INLINE, &plen);
397 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
400 ret = build_isgl((__be64 *)sq->queue,
401 (__be64 *)&sq->queue[sq->size],
402 wqe->send.u.isgl_src,
403 wr->sg_list, wr->num_sge, &plen);
406 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
407 wr->num_sge * sizeof(struct fw_ri_sge);
410 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
411 wqe->send.u.immd_src[0].r1 = 0;
412 wqe->send.u.immd_src[0].r2 = 0;
413 wqe->send.u.immd_src[0].immdlen = 0;
414 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
417 *len16 = DIV_ROUND_UP(size, 16);
418 wqe->send.plen = cpu_to_be32(plen);
422 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
423 struct ib_send_wr *wr, u8 *len16)
429 if (wr->num_sge > T4_MAX_SEND_SGE)
432 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
433 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
435 if (wr->send_flags & IB_SEND_INLINE) {
436 ret = build_immd(sq, wqe->write.u.immd_src, wr,
437 T4_MAX_WRITE_INLINE, &plen);
440 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
443 ret = build_isgl((__be64 *)sq->queue,
444 (__be64 *)&sq->queue[sq->size],
445 wqe->write.u.isgl_src,
446 wr->sg_list, wr->num_sge, &plen);
449 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
450 wr->num_sge * sizeof(struct fw_ri_sge);
453 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
454 wqe->write.u.immd_src[0].r1 = 0;
455 wqe->write.u.immd_src[0].r2 = 0;
456 wqe->write.u.immd_src[0].immdlen = 0;
457 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
460 *len16 = DIV_ROUND_UP(size, 16);
461 wqe->write.plen = cpu_to_be32(plen);
465 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
470 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
471 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
473 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
474 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
475 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
476 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
478 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
480 wqe->read.stag_src = cpu_to_be32(2);
481 wqe->read.to_src_hi = 0;
482 wqe->read.to_src_lo = 0;
483 wqe->read.stag_sink = cpu_to_be32(2);
485 wqe->read.to_sink_hi = 0;
486 wqe->read.to_sink_lo = 0;
490 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
494 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
495 struct ib_recv_wr *wr, u8 *len16)
499 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
500 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
501 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
504 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
505 wr->num_sge * sizeof(struct fw_ri_sge), 16);
509 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
510 struct ib_send_wr *wr, u8 *len16)
513 struct fw_ri_immd *imdp;
516 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
519 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
522 wqe->fr.qpbinde_to_dcacpu = 0;
523 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
524 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
525 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
527 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
528 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
529 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
530 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
532 WARN_ON(pbllen > T4_MAX_FR_IMMD);
533 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
534 imdp->op = FW_RI_DATA_IMMD;
537 imdp->immdlen = cpu_to_be32(pbllen);
538 p = (__be64 *)(imdp + 1);
540 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
541 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
543 if (++p == (__be64 *)&sq->queue[sq->size])
544 p = (__be64 *)sq->queue;
550 if (++p == (__be64 *)&sq->queue[sq->size])
551 p = (__be64 *)sq->queue;
553 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
557 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
560 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
562 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
566 void c4iw_qp_add_ref(struct ib_qp *qp)
568 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp);
569 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
572 void c4iw_qp_rem_ref(struct ib_qp *qp)
574 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp);
575 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
576 wake_up(&(to_c4iw_qp(qp)->wait));
579 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
580 struct ib_send_wr **bad_wr)
584 enum fw_wr_opcodes fw_opcode = 0;
585 enum fw_ri_wr_flags fw_flags;
589 struct t4_swsqe *swsqe;
593 qhp = to_c4iw_qp(ibqp);
594 spin_lock_irqsave(&qhp->lock, flag);
595 if (t4_wq_in_error(&qhp->wq)) {
596 spin_unlock_irqrestore(&qhp->lock, flag);
599 num_wrs = t4_sq_avail(&qhp->wq);
601 spin_unlock_irqrestore(&qhp->lock, flag);
610 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
611 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
614 if (wr->send_flags & IB_SEND_SOLICITED)
615 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
616 if (wr->send_flags & IB_SEND_SIGNALED)
617 fw_flags |= FW_RI_COMPLETION_FLAG;
618 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
619 switch (wr->opcode) {
620 case IB_WR_SEND_WITH_INV:
622 if (wr->send_flags & IB_SEND_FENCE)
623 fw_flags |= FW_RI_READ_FENCE_FLAG;
624 fw_opcode = FW_RI_SEND_WR;
625 if (wr->opcode == IB_WR_SEND)
626 swsqe->opcode = FW_RI_SEND;
628 swsqe->opcode = FW_RI_SEND_WITH_INV;
629 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
631 case IB_WR_RDMA_WRITE:
632 fw_opcode = FW_RI_RDMA_WRITE_WR;
633 swsqe->opcode = FW_RI_RDMA_WRITE;
634 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
636 case IB_WR_RDMA_READ:
637 case IB_WR_RDMA_READ_WITH_INV:
638 fw_opcode = FW_RI_RDMA_READ_WR;
639 swsqe->opcode = FW_RI_READ_REQ;
640 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
641 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
644 err = build_rdma_read(wqe, wr, &len16);
647 swsqe->read_len = wr->sg_list[0].length;
648 if (!qhp->wq.sq.oldest_read)
649 qhp->wq.sq.oldest_read = swsqe;
651 case IB_WR_FAST_REG_MR:
652 fw_opcode = FW_RI_FR_NSMR_WR;
653 swsqe->opcode = FW_RI_FAST_REGISTER;
654 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
656 case IB_WR_LOCAL_INV:
657 if (wr->send_flags & IB_SEND_FENCE)
658 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
659 fw_opcode = FW_RI_INV_LSTAG_WR;
660 swsqe->opcode = FW_RI_LOCAL_INV;
661 err = build_inv_stag(wqe, wr, &len16);
664 CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__,
672 swsqe->idx = qhp->wq.sq.pidx;
674 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
675 swsqe->wr_id = wr->wr_id;
677 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
680 "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u",
681 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
682 swsqe->opcode, swsqe->read_len);
685 t4_sq_produce(&qhp->wq, len16);
686 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
688 if (t4_wq_db_enabled(&qhp->wq))
689 t4_ring_sq_db(&qhp->wq, idx);
690 spin_unlock_irqrestore(&qhp->lock, flag);
694 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
695 struct ib_recv_wr **bad_wr)
699 union t4_recv_wr *wqe;
705 qhp = to_c4iw_qp(ibqp);
706 spin_lock_irqsave(&qhp->lock, flag);
707 if (t4_wq_in_error(&qhp->wq)) {
708 spin_unlock_irqrestore(&qhp->lock, flag);
711 num_wrs = t4_rq_avail(&qhp->wq);
713 spin_unlock_irqrestore(&qhp->lock, flag);
717 if (wr->num_sge > T4_MAX_RECV_SGE) {
722 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
726 err = build_rdma_recv(qhp, wqe, wr, &len16);
734 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
736 wqe->recv.opcode = FW_RI_RECV_WR;
738 wqe->recv.wrid = qhp->wq.rq.pidx;
742 wqe->recv.len16 = len16;
743 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__,
744 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
745 t4_rq_produce(&qhp->wq, len16);
746 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
750 if (t4_wq_db_enabled(&qhp->wq))
751 t4_ring_rq_db(&qhp->wq, idx);
752 spin_unlock_irqrestore(&qhp->lock, flag);
756 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
761 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
771 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
776 status = CQE_STATUS(err_cqe);
777 opcode = CQE_OPCODE(err_cqe);
778 rqtype = RQ_TYPE(err_cqe);
779 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
780 (opcode == FW_RI_SEND_WITH_SE_INV);
781 tagged = (opcode == FW_RI_RDMA_WRITE) ||
782 (rqtype && (opcode == FW_RI_READ_RESP));
787 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
788 *ecode = RDMAP_CANT_INV_STAG;
790 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
791 *ecode = RDMAP_INV_STAG;
795 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
796 if ((opcode == FW_RI_SEND_WITH_INV) ||
797 (opcode == FW_RI_SEND_WITH_SE_INV))
798 *ecode = RDMAP_CANT_INV_STAG;
800 *ecode = RDMAP_STAG_NOT_ASSOC;
803 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
804 *ecode = RDMAP_STAG_NOT_ASSOC;
807 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
808 *ecode = RDMAP_ACC_VIOL;
811 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
812 *ecode = RDMAP_TO_WRAP;
816 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
817 *ecode = DDPT_BASE_BOUNDS;
819 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
820 *ecode = RDMAP_BASE_BOUNDS;
823 case T4_ERR_INVALIDATE_SHARED_MR:
824 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
825 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
826 *ecode = RDMAP_CANT_INV_STAG;
829 case T4_ERR_ECC_PSTAG:
830 case T4_ERR_INTERNAL_ERR:
831 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
834 case T4_ERR_OUT_OF_RQE:
835 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
836 *ecode = DDPU_INV_MSN_NOBUF;
838 case T4_ERR_PBL_ADDR_BOUND:
839 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
840 *ecode = DDPT_BASE_BOUNDS;
843 *layer_type = LAYER_MPA|DDP_LLP;
844 *ecode = MPA_CRC_ERR;
847 *layer_type = LAYER_MPA|DDP_LLP;
848 *ecode = MPA_MARKER_ERR;
850 case T4_ERR_PDU_LEN_ERR:
851 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
852 *ecode = DDPU_MSG_TOOBIG;
854 case T4_ERR_DDP_VERSION:
856 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
857 *ecode = DDPT_INV_VERS;
859 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
860 *ecode = DDPU_INV_VERS;
863 case T4_ERR_RDMA_VERSION:
864 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
865 *ecode = RDMAP_INV_VERS;
868 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
869 *ecode = RDMAP_INV_OPCODE;
871 case T4_ERR_DDP_QUEUE_NUM:
872 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
873 *ecode = DDPU_INV_QN;
877 case T4_ERR_MSN_RANGE:
878 case T4_ERR_IRD_OVERFLOW:
879 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
880 *ecode = DDPU_INV_MSN_RANGE;
883 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
887 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
888 *ecode = DDPU_INV_MO;
891 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
897 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
900 struct fw_ri_wr *wqe;
901 struct terminate_message *term;
903 struct socket *so = qhp->ep->com.so;
904 struct inpcb *inp = sotoinpcb(so);
905 struct tcpcb *tp = intotcpcb(inp);
906 struct toepcb *toep = tp->t_toe;
908 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp,
909 qhp->wq.sq.qid, qhp->ep->hwtid);
911 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq);
916 memset(wqe, 0, sizeof *wqe);
917 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR));
918 wqe->flowid_len16 = cpu_to_be32(
919 V_FW_WR_FLOWID(qhp->ep->hwtid) |
920 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
922 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
923 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
924 term = (struct terminate_message *)wqe->u.terminate.termmsg;
925 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
926 term->layer_etype = qhp->attr.layer_etype;
927 term->ecode = qhp->attr.ecode;
929 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
930 creds(toep, sizeof(*wqe));
931 t4_wrq_tx(qhp->rhp->rdev.adap, wr);
934 /* Assumes qhp lock is held. */
935 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
936 struct c4iw_cq *schp)
942 CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp,
945 /* locking hierarchy: cq lock first, then qp lock. */
946 spin_lock_irqsave(&rchp->lock, flag);
947 spin_lock(&qhp->lock);
948 c4iw_flush_hw_cq(&rchp->cq);
949 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
950 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
951 spin_unlock(&qhp->lock);
952 spin_unlock_irqrestore(&rchp->lock, flag);
954 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
955 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
956 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
959 /* locking hierarchy: cq lock first, then qp lock. */
960 spin_lock_irqsave(&schp->lock, flag);
961 spin_lock(&qhp->lock);
962 c4iw_flush_hw_cq(&schp->cq);
963 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
964 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
965 spin_unlock(&qhp->lock);
966 spin_unlock_irqrestore(&schp->lock, flag);
968 spin_lock_irqsave(&schp->comp_handler_lock, flag);
969 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
970 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
974 static void flush_qp(struct c4iw_qp *qhp)
976 struct c4iw_cq *rchp, *schp;
979 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
980 schp = get_chp(qhp->rhp, qhp->attr.scq);
982 if (qhp->ibqp.uobject) {
983 t4_set_wq_in_error(&qhp->wq);
984 t4_set_cq_in_error(&rchp->cq);
985 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
986 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
987 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
989 t4_set_cq_in_error(&schp->cq);
990 spin_lock_irqsave(&schp->comp_handler_lock, flag);
991 (*schp->ibcq.comp_handler)(&schp->ibcq,
992 schp->ibcq.cq_context);
993 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
997 __flush_qp(qhp, rchp, schp);
1001 rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep)
1003 struct c4iw_rdev *rdev = &rhp->rdev;
1004 struct adapter *sc = rdev->adap;
1005 struct fw_ri_wr *wqe;
1008 struct socket *so = ep->com.so;
1009 struct inpcb *inp = sotoinpcb(so);
1010 struct tcpcb *tp = intotcpcb(inp);
1011 struct toepcb *toep = tp->t_toe;
1013 KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__));
1015 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp,
1016 qhp->wq.sq.qid, ep->hwtid);
1018 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq);
1023 memset(wqe, 0, sizeof *wqe);
1025 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL);
1026 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) |
1027 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1028 wqe->cookie = (unsigned long) &ep->com.wr_wait;
1029 wqe->u.fini.type = FW_RI_TYPE_FINI;
1031 c4iw_init_wr_wait(&ep->com.wr_wait);
1033 creds(toep, sizeof(*wqe));
1036 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid,
1037 qhp->wq.sq.qid, __func__);
1041 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1043 CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type);
1044 memset(&init->u, 0, sizeof init->u);
1046 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1047 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1048 init->u.write.stag_sink = cpu_to_be32(1);
1049 init->u.write.to_sink = cpu_to_be64(1);
1050 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1051 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1052 sizeof(struct fw_ri_immd),
1055 case FW_RI_INIT_P2PTYPE_READ_REQ:
1056 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1057 init->u.read.stag_src = cpu_to_be32(1);
1058 init->u.read.to_src_lo = cpu_to_be32(1);
1059 init->u.read.stag_sink = cpu_to_be32(1);
1060 init->u.read.to_sink_lo = cpu_to_be32(1);
1061 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1067 creds(struct toepcb *toep, size_t wrsize)
1069 struct ofld_tx_sdesc *txsd;
1071 CTR3(KTR_IW_CXGBE, "%s:creB %p %u", __func__, toep , wrsize);
1072 INP_WLOCK(toep->inp);
1073 txsd = &toep->txsd[toep->txsd_pidx];
1074 txsd->tx_credits = howmany(wrsize, 16);
1076 KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0,
1077 ("%s: not enough credits (%d)", __func__, toep->tx_credits));
1078 toep->tx_credits -= txsd->tx_credits;
1079 if (__predict_false(++toep->txsd_pidx == toep->txsd_total))
1080 toep->txsd_pidx = 0;
1082 INP_WUNLOCK(toep->inp);
1083 CTR5(KTR_IW_CXGBE, "%s:creE %p %u %u %u", __func__, toep ,
1084 txsd->tx_credits, toep->tx_credits, toep->txsd_pidx);
1087 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1089 struct fw_ri_wr *wqe;
1092 struct c4iw_ep *ep = qhp->ep;
1093 struct c4iw_rdev *rdev = &qhp->rhp->rdev;
1094 struct adapter *sc = rdev->adap;
1095 struct socket *so = ep->com.so;
1096 struct inpcb *inp = sotoinpcb(so);
1097 struct tcpcb *tp = intotcpcb(inp);
1098 struct toepcb *toep = tp->t_toe;
1100 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp,
1101 qhp->wq.sq.qid, ep->hwtid);
1103 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq);
1108 memset(wqe, 0, sizeof *wqe);
1110 wqe->op_compl = cpu_to_be32(
1111 V_FW_WR_OP(FW_RI_WR) |
1113 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) |
1114 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1116 wqe->cookie = (unsigned long) &ep->com.wr_wait;
1118 wqe->u.init.type = FW_RI_TYPE_INIT;
1119 wqe->u.init.mpareqbit_p2ptype =
1120 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1121 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1122 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1123 if (qhp->attr.mpa_attr.recv_marker_enabled)
1124 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1125 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1126 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1127 if (qhp->attr.mpa_attr.crc_enabled)
1128 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1130 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1131 FW_RI_QP_RDMA_WRITE_ENABLE |
1132 FW_RI_QP_BIND_ENABLE;
1133 if (!qhp->ibqp.uobject)
1134 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1135 FW_RI_QP_STAG0_ENABLE;
1136 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1137 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1138 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1139 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1140 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1141 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1142 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1143 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1144 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1145 wqe->u.init.iss = cpu_to_be32(ep->snd_seq);
1146 wqe->u.init.irs = cpu_to_be32(ep->rcv_seq);
1147 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1148 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1150 if (qhp->attr.mpa_attr.initiator)
1151 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1153 c4iw_init_wr_wait(&ep->com.wr_wait);
1155 creds(toep, sizeof(*wqe));
1158 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid,
1159 qhp->wq.sq.qid, __func__);
1161 toep->ulp_mode = ULP_MODE_RDMA;
1166 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1167 enum c4iw_qp_attr_mask mask,
1168 struct c4iw_qp_attributes *attrs,
1172 struct c4iw_qp_attributes newattr = qhp->attr;
1177 struct c4iw_ep *ep = NULL;
1179 CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp,
1180 qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep);
1181 CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state,
1182 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1184 mutex_lock(&qhp->mutex);
1186 /* Process attr changes if in IDLE */
1187 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1188 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1192 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1193 newattr.enable_rdma_read = attrs->enable_rdma_read;
1194 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1195 newattr.enable_rdma_write = attrs->enable_rdma_write;
1196 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1197 newattr.enable_bind = attrs->enable_bind;
1198 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1199 if (attrs->max_ord > c4iw_max_read_depth) {
1203 newattr.max_ord = attrs->max_ord;
1205 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1206 if (attrs->max_ird > c4iw_max_read_depth) {
1210 newattr.max_ird = attrs->max_ird;
1212 qhp->attr = newattr;
1215 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1217 if (qhp->attr.state == attrs->next_state)
1220 switch (qhp->attr.state) {
1221 case C4IW_QP_STATE_IDLE:
1222 switch (attrs->next_state) {
1223 case C4IW_QP_STATE_RTS:
1224 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1228 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1232 qhp->attr.mpa_attr = attrs->mpa_attr;
1233 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1234 qhp->ep = qhp->attr.llp_stream_handle;
1235 set_state(qhp, C4IW_QP_STATE_RTS);
1238 * Ref the endpoint here and deref when we
1239 * disassociate the endpoint from the QP. This
1240 * happens in CLOSING->IDLE transition or *->ERROR
1243 c4iw_get_ep(&qhp->ep->com);
1244 ret = rdma_init(rhp, qhp);
1248 case C4IW_QP_STATE_ERROR:
1249 set_state(qhp, C4IW_QP_STATE_ERROR);
1257 case C4IW_QP_STATE_RTS:
1258 switch (attrs->next_state) {
1259 case C4IW_QP_STATE_CLOSING:
1260 //Fixme: Use atomic_read as same as Linux
1261 BUG_ON(qhp->ep->com.kref.count < 2);
1262 set_state(qhp, C4IW_QP_STATE_CLOSING);
1267 c4iw_get_ep(&qhp->ep->com);
1269 if (qhp->ibqp.uobject)
1270 t4_set_wq_in_error(&qhp->wq);
1271 ret = rdma_fini(rhp, qhp, ep);
1275 case C4IW_QP_STATE_TERMINATE:
1276 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1277 qhp->attr.layer_etype = attrs->layer_etype;
1278 qhp->attr.ecode = attrs->ecode;
1279 if (qhp->ibqp.uobject)
1280 t4_set_wq_in_error(&qhp->wq);
1285 c4iw_get_ep(&qhp->ep->com);
1287 case C4IW_QP_STATE_ERROR:
1288 set_state(qhp, C4IW_QP_STATE_ERROR);
1289 if (qhp->ibqp.uobject)
1290 t4_set_wq_in_error(&qhp->wq);
1295 c4iw_get_ep(&qhp->ep->com);
1304 case C4IW_QP_STATE_CLOSING:
1309 switch (attrs->next_state) {
1310 case C4IW_QP_STATE_IDLE:
1312 set_state(qhp, C4IW_QP_STATE_IDLE);
1313 qhp->attr.llp_stream_handle = NULL;
1314 c4iw_put_ep(&qhp->ep->com);
1316 wake_up(&qhp->wait);
1318 case C4IW_QP_STATE_ERROR:
1325 case C4IW_QP_STATE_ERROR:
1326 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1330 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1334 set_state(qhp, C4IW_QP_STATE_IDLE);
1336 case C4IW_QP_STATE_TERMINATE:
1344 printf("%s in a bad state %d\n",
1345 __func__, qhp->attr.state);
1352 CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__,
1353 qhp->ep, qhp->wq.sq.qid);
1355 /* disassociate the LLP connection */
1356 qhp->attr.llp_stream_handle = NULL;
1360 set_state(qhp, C4IW_QP_STATE_ERROR);
1362 wake_up(&qhp->wait);
1366 mutex_unlock(&qhp->mutex);
1369 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1372 * If disconnect is 1, then we need to initiate a disconnect
1373 * on the EP. This can be a normal close (RTS->CLOSING) or
1374 * an abnormal close (RTS/CLOSING->ERROR).
1377 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1379 c4iw_put_ep(&ep->com);
1383 * If free is 1, then we've disassociated the EP from the QP
1384 * and we need to dereference the EP.
1387 c4iw_put_ep(&ep->com);
1388 CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state);
1392 static int enable_qp_db(int id, void *p, void *data)
1394 struct c4iw_qp *qp = p;
1396 t4_enable_wq_db(&qp->wq);
1400 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1402 struct c4iw_dev *rhp;
1403 struct c4iw_qp *qhp;
1404 struct c4iw_qp_attributes attrs;
1405 struct c4iw_ucontext *ucontext;
1407 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp);
1408 qhp = to_c4iw_qp(ib_qp);
1411 attrs.next_state = C4IW_QP_STATE_ERROR;
1412 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1413 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1415 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1416 wait_event(qhp->wait, !qhp->ep);
1418 spin_lock_irq(&rhp->lock);
1419 remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1421 BUG_ON(rhp->qpcnt < 0);
1422 if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) {
1423 rhp->rdev.stats.db_state_transitions++;
1424 rhp->db_state = NORMAL;
1425 idr_for_each(&rhp->qpidr, enable_qp_db, NULL);
1427 spin_unlock_irq(&rhp->lock);
1428 atomic_dec(&qhp->refcnt);
1429 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1431 ucontext = ib_qp->uobject ?
1432 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1433 destroy_qp(&rhp->rdev, &qhp->wq,
1434 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1436 CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp,
1442 static int disable_qp_db(int id, void *p, void *data)
1444 struct c4iw_qp *qp = p;
1446 t4_disable_wq_db(&qp->wq);
1451 c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1452 struct ib_udata *udata)
1454 struct c4iw_dev *rhp;
1455 struct c4iw_qp *qhp;
1456 struct c4iw_pd *php;
1457 struct c4iw_cq *schp;
1458 struct c4iw_cq *rchp;
1459 struct c4iw_create_qp_resp uresp;
1461 struct c4iw_ucontext *ucontext;
1463 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4;
1465 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd);
1467 if (attrs->qp_type != IB_QPT_RC)
1468 return ERR_PTR(-EINVAL);
1470 php = to_c4iw_pd(pd);
1472 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1473 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1475 return ERR_PTR(-EINVAL);
1477 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1478 return ERR_PTR(-EINVAL);
1480 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1481 if (rqsize > T4_MAX_RQ_SIZE)
1482 return ERR_PTR(-E2BIG);
1484 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1485 if (sqsize > T4_MAX_SQ_SIZE)
1486 return ERR_PTR(-E2BIG);
1488 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1491 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1493 return ERR_PTR(-ENOMEM);
1494 qhp->wq.sq.size = sqsize;
1495 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1496 qhp->wq.rq.size = rqsize;
1497 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1500 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1501 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1504 CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu",
1505 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1507 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1508 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1512 attrs->cap.max_recv_wr = rqsize - 1;
1513 attrs->cap.max_send_wr = sqsize - 1;
1514 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1517 qhp->attr.pd = php->pdid;
1518 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1519 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1520 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1521 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1522 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1523 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1524 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1525 qhp->attr.state = C4IW_QP_STATE_IDLE;
1526 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1527 qhp->attr.enable_rdma_read = 1;
1528 qhp->attr.enable_rdma_write = 1;
1529 qhp->attr.enable_bind = 1;
1530 qhp->attr.max_ord = 1;
1531 qhp->attr.max_ird = 1;
1532 spin_lock_init(&qhp->lock);
1533 mutex_init(&qhp->mutex);
1534 init_waitqueue_head(&qhp->wait);
1535 atomic_set(&qhp->refcnt, 1);
1537 spin_lock_irq(&rhp->lock);
1538 if (rhp->db_state != NORMAL)
1539 t4_disable_wq_db(&qhp->wq);
1540 if (++rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) {
1541 rhp->rdev.stats.db_state_transitions++;
1542 rhp->db_state = FLOW_CONTROL;
1543 idr_for_each(&rhp->qpidr, disable_qp_db, NULL);
1545 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1546 spin_unlock_irq(&rhp->lock);
1551 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1556 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1561 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1566 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1572 uresp.qid_mask = rhp->rdev.qpmask;
1573 uresp.sqid = qhp->wq.sq.qid;
1574 uresp.sq_size = qhp->wq.sq.size;
1575 uresp.sq_memsize = qhp->wq.sq.memsize;
1576 uresp.rqid = qhp->wq.rq.qid;
1577 uresp.rq_size = qhp->wq.rq.size;
1578 uresp.rq_memsize = qhp->wq.rq.memsize;
1579 spin_lock(&ucontext->mmap_lock);
1580 uresp.sq_key = ucontext->key;
1581 ucontext->key += PAGE_SIZE;
1582 uresp.rq_key = ucontext->key;
1583 ucontext->key += PAGE_SIZE;
1584 uresp.sq_db_gts_key = ucontext->key;
1585 ucontext->key += PAGE_SIZE;
1586 uresp.rq_db_gts_key = ucontext->key;
1587 ucontext->key += PAGE_SIZE;
1588 spin_unlock(&ucontext->mmap_lock);
1589 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1592 mm1->key = uresp.sq_key;
1593 mm1->addr = qhp->wq.sq.phys_addr;
1594 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1595 CTR4(KTR_IW_CXGBE, "%s mm1 %x, %x, %d", __func__, mm1->key,
1596 mm1->addr, mm1->len);
1597 insert_mmap(ucontext, mm1);
1598 mm2->key = uresp.rq_key;
1599 mm2->addr = vtophys(qhp->wq.rq.queue);
1600 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1601 CTR4(KTR_IW_CXGBE, "%s mm2 %x, %x, %d", __func__, mm2->key,
1602 mm2->addr, mm2->len);
1603 insert_mmap(ucontext, mm2);
1604 mm3->key = uresp.sq_db_gts_key;
1605 mm3->addr = qhp->wq.sq.udb;
1606 mm3->len = PAGE_SIZE;
1607 CTR4(KTR_IW_CXGBE, "%s mm3 %x, %x, %d", __func__, mm3->key,
1608 mm3->addr, mm3->len);
1609 insert_mmap(ucontext, mm3);
1610 mm4->key = uresp.rq_db_gts_key;
1611 mm4->addr = qhp->wq.rq.udb;
1612 mm4->len = PAGE_SIZE;
1613 CTR4(KTR_IW_CXGBE, "%s mm4 %x, %x, %d", __func__, mm4->key,
1614 mm4->addr, mm4->len);
1615 insert_mmap(ucontext, mm4);
1617 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1618 init_timer(&(qhp->timer));
1620 "%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x",
1621 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1633 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1635 destroy_qp(&rhp->rdev, &qhp->wq,
1636 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1639 return ERR_PTR(ret);
1642 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1643 int attr_mask, struct ib_udata *udata)
1645 struct c4iw_dev *rhp;
1646 struct c4iw_qp *qhp;
1647 enum c4iw_qp_attr_mask mask = 0;
1648 struct c4iw_qp_attributes attrs;
1650 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp);
1652 /* iwarp does not support the RTR state */
1653 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1654 attr_mask &= ~IB_QP_STATE;
1656 /* Make sure we still have something left to do */
1660 memset(&attrs, 0, sizeof attrs);
1661 qhp = to_c4iw_qp(ibqp);
1664 attrs.next_state = c4iw_convert_state(attr->qp_state);
1665 attrs.enable_rdma_read = (attr->qp_access_flags &
1666 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1667 attrs.enable_rdma_write = (attr->qp_access_flags &
1668 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1669 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1672 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1673 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1674 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1675 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1676 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1679 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1680 * ringing the queue db when we're in DB_FULL mode.
1682 attrs.sq_db_inc = attr->sq_psn;
1683 attrs.rq_db_inc = attr->rq_psn;
1684 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1685 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1687 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1690 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1692 CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn);
1693 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1696 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1697 int attr_mask, struct ib_qp_init_attr *init_attr)
1699 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1701 memset(attr, 0, sizeof *attr);
1702 memset(init_attr, 0, sizeof *init_attr);
1703 attr->qp_state = to_ib_qp_state(qhp->attr.state);