2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
30 #include "opt_inet6.h"
32 #include "opt_sched.h"
34 #include <sys/param.h>
35 #include <sys/types.h>
37 #include <sys/eventhandler.h>
38 #include <sys/kernel.h>
40 #include <sys/mutex.h>
41 #include <sys/module.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/syslog.h>
50 #include <sys/taskqueue.h>
51 #include <sys/limits.h>
54 #include <net/if_var.h>
55 #include <net/if_private.h>
56 #include <net/if_types.h>
57 #include <net/if_media.h>
59 #include <net/ethernet.h>
60 #include <net/mp_ring.h>
61 #include <net/debugnet.h>
65 #include <netinet/in.h>
66 #include <netinet/in_pcb.h>
67 #include <netinet/tcp_lro.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip6.h>
72 #include <netinet/tcp.h>
73 #include <netinet/ip_var.h>
74 #include <netinet6/ip6_var.h>
76 #include <machine/bus.h>
77 #include <machine/in_cksum.h>
82 #include <dev/led/led.h>
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85 #include <dev/pci/pci_private.h>
87 #include <net/iflib.h>
92 #include <dev/pci/pci_iov.h>
95 #include <sys/bitstring.h>
97 * enable accounting of every mbuf as it comes in to and goes out of
98 * iflib's software descriptor references
100 #define MEMORY_LOGGING 0
102 * Enable mbuf vectors for compressing long mbuf chains
107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
108 * we prefetch needs to be determined by the time spent in m_free vis a vis
109 * the cost of a prefetch. This will of course vary based on the workload:
110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
111 * is quite expensive, thus suggesting very little prefetch.
112 * - small packet forwarding which is just returning a single mbuf to
113 * UMA will typically be very fast vis a vis the cost of a memory
119 * - private structures
120 * - iflib private utility functions
122 * - vlan registry and other exported functions
123 * - iflib public core functions
127 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
129 #define IFLIB_RXEOF_MORE (1U << 0)
130 #define IFLIB_RXEOF_EMPTY (2U << 0)
133 typedef struct iflib_txq *iflib_txq_t;
135 typedef struct iflib_rxq *iflib_rxq_t;
137 typedef struct iflib_fl *iflib_fl_t;
141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
142 static void iflib_timer(void *arg);
143 static void iflib_tqg_detach(if_ctx_t ctx);
145 typedef struct iflib_filter_info {
146 driver_filter_t *ifi_filter;
147 void *ifi_filter_arg;
148 struct grouptask *ifi_task;
150 } *iflib_filter_info_t;
155 * Pointer to hardware driver's softc
162 if_shared_ctx_t ifc_sctx;
163 struct if_softc_ctx ifc_softc_ctx;
165 struct sx ifc_ctx_sx;
166 struct mtx ifc_state_mtx;
168 iflib_txq_t ifc_txqs;
169 iflib_rxq_t ifc_rxqs;
170 uint32_t ifc_if_flags;
172 uint32_t ifc_max_fl_buf_size;
173 uint32_t ifc_rx_mbuf_sz;
176 int ifc_watchdog_events;
177 struct cdev *ifc_led_dev;
178 struct resource *ifc_msix_mem;
180 struct if_irq ifc_legacy_irq;
181 struct grouptask ifc_admin_task;
182 struct grouptask ifc_vflr_task;
183 struct iflib_filter_info ifc_filter_info;
184 struct ifmedia ifc_media;
185 struct ifmedia *ifc_mediap;
187 struct sysctl_oid *ifc_sysctl_node;
188 uint16_t ifc_sysctl_ntxqs;
189 uint16_t ifc_sysctl_nrxqs;
190 uint16_t ifc_sysctl_qs_eq_override;
191 uint16_t ifc_sysctl_rx_budget;
192 uint16_t ifc_sysctl_tx_abdicate;
193 uint16_t ifc_sysctl_core_offset;
194 #define CORE_OFFSET_UNSPECIFIED 0xffff
195 uint8_t ifc_sysctl_separate_txrx;
196 uint8_t ifc_sysctl_use_logical_cores;
197 bool ifc_cpus_are_physical_cores;
199 qidx_t ifc_sysctl_ntxds[8];
200 qidx_t ifc_sysctl_nrxds[8];
201 struct if_txrx ifc_txrx;
202 #define isc_txd_encap ifc_txrx.ift_txd_encap
203 #define isc_txd_flush ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
210 #define isc_txq_select ifc_txrx.ift_txq_select
211 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2
213 eventhandler_tag ifc_vlan_attach_event;
214 eventhandler_tag ifc_vlan_detach_event;
215 struct ether_addr ifc_mac;
219 iflib_get_softc(if_ctx_t ctx)
222 return (ctx->ifc_softc);
226 iflib_get_dev(if_ctx_t ctx)
229 return (ctx->ifc_dev);
233 iflib_get_ifp(if_ctx_t ctx)
236 return (ctx->ifc_ifp);
240 iflib_get_media(if_ctx_t ctx)
243 return (ctx->ifc_mediap);
247 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
250 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
254 iflib_get_softc_ctx(if_ctx_t ctx)
257 return (&ctx->ifc_softc_ctx);
261 iflib_get_sctx(if_ctx_t ctx)
264 return (ctx->ifc_sctx);
267 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
268 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
269 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
271 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
272 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
274 typedef struct iflib_sw_rx_desc_array {
275 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
276 struct mbuf **ifsd_m; /* pkthdr mbufs */
277 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
278 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
279 } iflib_rxsd_array_t;
281 typedef struct iflib_sw_tx_desc_array {
282 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
283 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
284 struct mbuf **ifsd_m; /* pkthdr mbufs */
287 /* magic number that should be high enough for any hardware */
288 #define IFLIB_MAX_TX_SEGS 128
289 #define IFLIB_RX_COPY_THRESH 128
290 #define IFLIB_MAX_RX_REFRESH 32
291 /* The minimum descriptors per second before we start coalescing */
292 #define IFLIB_MIN_DESC_SEC 16384
293 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
294 #define IFLIB_QUEUE_IDLE 0
295 #define IFLIB_QUEUE_HUNG 1
296 #define IFLIB_QUEUE_WORKING 2
297 /* maximum number of txqs that can share an rx interrupt */
298 #define IFLIB_MAX_TX_SHARED_INTR 4
300 /* this should really scale with ring size - this is a fairly arbitrary value */
301 #define TX_BATCH_SIZE 32
303 #define IFLIB_RESTART_BUDGET 8
305 #define IFC_LEGACY 0x001
306 #define IFC_QFLUSH 0x002
307 #define IFC_MULTISEG 0x004
308 #define IFC_SPARE1 0x008
309 #define IFC_SC_ALLOCATED 0x010
310 #define IFC_INIT_DONE 0x020
311 #define IFC_PREFETCH 0x040
312 #define IFC_DO_RESET 0x080
313 #define IFC_DO_WATCHDOG 0x100
314 #define IFC_SPARE0 0x200
315 #define IFC_SPARE2 0x400
316 #define IFC_IN_DETACH 0x800
318 #define IFC_NETMAP_TX_IRQ 0x80000000
320 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
321 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
322 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
327 qidx_t ift_cidx_processed;
330 uint8_t ift_br_offset;
331 uint16_t ift_npending;
332 uint16_t ift_db_pending;
333 uint16_t ift_rs_pending;
335 uint8_t ift_txd_size[8];
336 uint64_t ift_processed;
337 uint64_t ift_cleaned;
338 uint64_t ift_cleaned_prev;
340 uint64_t ift_enqueued;
341 uint64_t ift_dequeued;
343 uint64_t ift_no_tx_dma_setup;
344 uint64_t ift_no_desc_avail;
345 uint64_t ift_mbuf_defrag_failed;
346 uint64_t ift_mbuf_defrag;
347 uint64_t ift_map_failed;
348 uint64_t ift_txd_encap_efbig;
349 uint64_t ift_pullups;
350 uint64_t ift_last_timer_tick;
353 struct mtx ift_db_mtx;
355 /* constant values */
357 struct ifmp_ring *ift_br;
358 struct grouptask ift_task;
361 struct callout ift_timer;
363 struct callout ift_netmap_timer;
364 #endif /* DEV_NETMAP */
366 if_txsd_vec_t ift_sds;
369 uint8_t ift_update_freq;
370 struct iflib_filter_info ift_filter_info;
371 bus_dma_tag_t ift_buf_tag;
372 bus_dma_tag_t ift_tso_buf_tag;
373 iflib_dma_info_t ift_ifdi;
374 #define MTX_NAME_LEN 32
375 char ift_mtx_name[MTX_NAME_LEN];
376 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
377 #ifdef IFLIB_DIAGNOSTICS
378 uint64_t ift_cpu_exec_count[256];
380 } __aligned(CACHE_LINE_SIZE);
387 uint8_t ifl_rxd_size;
389 uint64_t ifl_m_enqueued;
390 uint64_t ifl_m_dequeued;
391 uint64_t ifl_cl_enqueued;
392 uint64_t ifl_cl_dequeued;
395 bitstr_t *ifl_rx_bitmap;
399 uint16_t ifl_buf_size;
402 iflib_rxsd_array_t ifl_sds;
405 bus_dma_tag_t ifl_buf_tag;
406 iflib_dma_info_t ifl_ifdi;
407 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
408 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
409 } __aligned(CACHE_LINE_SIZE);
412 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
418 else if (pidx < cidx)
419 used = size - cidx + pidx;
420 else if (gen == 0 && pidx == cidx)
422 else if (gen == 1 && pidx == cidx)
430 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
432 #define IDXDIFF(head, tail, wrap) \
433 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
439 struct pfil_head *pfil;
441 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
442 * the completion queue consumer index. Otherwise it's unused.
448 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
449 uint8_t ifr_fl_offset;
450 struct lro_ctrl ifr_lc;
451 struct grouptask ifr_task;
452 struct callout ifr_watchdog;
453 struct iflib_filter_info ifr_filter_info;
454 iflib_dma_info_t ifr_ifdi;
456 /* dynamically allocate if any drivers need a value substantially larger than this */
457 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
458 #ifdef IFLIB_DIAGNOSTICS
459 uint64_t ifr_cpu_exec_count[256];
461 } __aligned(CACHE_LINE_SIZE);
463 typedef struct if_rxsd {
468 /* multiple of word size */
470 #define PKT_INFO_SIZE 6
471 #define RXD_INFO_SIZE 5
472 #define PKT_TYPE uint64_t
474 #define PKT_INFO_SIZE 11
475 #define RXD_INFO_SIZE 8
476 #define PKT_TYPE uint32_t
478 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
479 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
481 typedef struct if_pkt_info_pad {
482 PKT_TYPE pkt_val[PKT_INFO_SIZE];
483 } *if_pkt_info_pad_t;
484 typedef struct if_rxd_info_pad {
485 PKT_TYPE rxd_val[RXD_INFO_SIZE];
486 } *if_rxd_info_pad_t;
488 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
489 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
492 pkt_info_zero(if_pkt_info_t pi)
494 if_pkt_info_pad_t pi_pad;
496 pi_pad = (if_pkt_info_pad_t)pi;
497 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
498 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
500 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
501 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
506 rxd_info_zero(if_rxd_info_t ri)
508 if_rxd_info_pad_t ri_pad;
511 ri_pad = (if_rxd_info_pad_t)ri;
512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
513 ri_pad->rxd_val[i] = 0;
514 ri_pad->rxd_val[i+1] = 0;
515 ri_pad->rxd_val[i+2] = 0;
516 ri_pad->rxd_val[i+3] = 0;
519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
524 * Only allow a single packet to take up most 1/nth of the tx ring
526 #define MAX_SINGLE_PACKET_FRACTION 12
527 #define IF_BAD_DMA (bus_addr_t)-1
529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
531 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
532 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
533 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
534 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
536 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
537 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
538 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
539 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
544 /* Our boot-time initialization hook */
545 static int iflib_module_event_handler(module_t, int, void *);
547 static moduledata_t iflib_moduledata = {
549 iflib_module_event_handler,
553 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
554 MODULE_VERSION(iflib, 1);
556 MODULE_DEPEND(iflib, pci, 1, 1, 1);
557 MODULE_DEPEND(iflib, ether, 1, 1, 1);
559 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
560 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
562 #ifndef IFLIB_DEBUG_COUNTERS
564 #define IFLIB_DEBUG_COUNTERS 1
566 #define IFLIB_DEBUG_COUNTERS 0
567 #endif /* !INVARIANTS */
570 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
571 "iflib driver parameters");
574 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
576 static int iflib_min_tx_latency = 0;
577 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
578 &iflib_min_tx_latency, 0,
579 "minimize transmit latency at the possible expense of throughput");
580 static int iflib_no_tx_batch = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
582 &iflib_no_tx_batch, 0,
583 "minimize transmit latency at the possible expense of throughput");
584 static int iflib_timer_default = 1000;
585 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW,
586 &iflib_timer_default, 0, "number of ticks between iflib_timer calls");
589 #if IFLIB_DEBUG_COUNTERS
591 static int iflib_tx_seen;
592 static int iflib_tx_sent;
593 static int iflib_tx_encap;
594 static int iflib_rx_allocs;
595 static int iflib_fl_refills;
596 static int iflib_fl_refills_large;
597 static int iflib_tx_frees;
599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0,
601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0,
603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0,
604 "# TX mbufs encapped");
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0,
607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0,
609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0,
611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
612 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 &iflib_txq_drain_notready, 0, "# drain notready");
625 static int iflib_encap_load_mbuf_fail;
626 static int iflib_encap_pad_mbuf_fail;
627 static int iflib_encap_txq_avail_fail;
628 static int iflib_encap_txd_encap_fail;
630 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
631 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
632 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
633 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
635 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
637 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
639 static int iflib_task_fn_rxs;
640 static int iflib_rx_intr_enables;
641 static int iflib_fast_intrs;
642 static int iflib_rx_unavail;
643 static int iflib_rx_ctx_inactive;
644 static int iflib_rx_if_input;
645 static int iflib_rxd_flush;
647 static int iflib_verbose_debug;
649 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0,
650 "# task_fn_rx calls");
651 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
652 &iflib_rx_intr_enables, 0, "# RX intr enables");
653 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0,
654 "# fast_intr calls");
655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0,
656 "# times rxeof called with no available data");
657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
658 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input,
660 0, "# times rxeof called if_input");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0,
662 "# times rxd_flush called");
663 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
664 &iflib_verbose_debug, 0, "enable verbose debugging");
666 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
668 iflib_debug_reset(void)
670 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
671 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
672 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
673 iflib_txq_drain_notready =
674 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
675 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
676 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
678 iflib_rx_ctx_inactive = iflib_rx_if_input =
683 #define DBG_COUNTER_INC(name)
684 static void iflib_debug_reset(void) {}
687 #define IFLIB_DEBUG 0
689 static void iflib_tx_structures_free(if_ctx_t ctx);
690 static void iflib_rx_structures_free(if_ctx_t ctx);
691 static int iflib_queues_alloc(if_ctx_t ctx);
692 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
693 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
694 static int iflib_qset_structures_setup(if_ctx_t ctx);
695 static int iflib_msix_init(if_ctx_t ctx);
696 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
697 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
698 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
700 static void iflib_altq_if_start(if_t ifp);
701 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
703 static int iflib_register(if_ctx_t);
704 static void iflib_deregister(if_ctx_t);
705 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
706 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
707 static void iflib_init_locked(if_ctx_t ctx);
708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
710 static void iflib_ifmp_purge(iflib_txq_t txq);
711 static void _iflib_pre_assert(if_softc_ctx_t scctx);
712 static void iflib_stop(if_ctx_t ctx);
713 static void iflib_if_init_locked(if_ctx_t ctx);
714 static void iflib_free_intr_mem(if_ctx_t ctx);
715 #ifndef __NO_STRICT_ALIGNMENT
716 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
719 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
720 SLIST_HEAD_INITIALIZER(cpu_offsets);
722 SLIST_ENTRY(cpu_offset) entries;
724 unsigned int refcount;
727 static struct mtx cpu_offset_mtx;
728 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
731 DEBUGNET_DEFINE(iflib);
734 iflib_num_rx_descs(if_ctx_t ctx)
736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
737 if_shared_ctx_t sctx = ctx->ifc_sctx;
738 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
740 return scctx->isc_nrxd[first_rxq];
744 iflib_num_tx_descs(if_ctx_t ctx)
746 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
747 if_shared_ctx_t sctx = ctx->ifc_sctx;
748 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
750 return scctx->isc_ntxd[first_txq];
754 #include <sys/selinfo.h>
755 #include <net/netmap.h>
756 #include <dev/netmap/netmap_kern.h>
758 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
760 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
761 static void iflib_netmap_timer(void *arg);
764 * device-specific sysctl variables:
766 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
767 * During regular operations the CRC is stripped, but on some
768 * hardware reception of frames not multiple of 64 is slower,
769 * so using crcstrip=0 helps in benchmarks.
771 * iflib_rx_miss, iflib_rx_miss_bufs:
772 * count packets that might be missed due to lost interrupts.
774 SYSCTL_DECL(_dev_netmap);
776 * The xl driver by default strips CRCs and we do not override it.
779 int iflib_crcstrip = 1;
780 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
781 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
783 int iflib_rx_miss, iflib_rx_miss_bufs;
784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
785 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
786 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
787 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
790 * Register/unregister. We are already under netmap lock.
791 * Only called on the first register or the last unregister.
794 iflib_netmap_register(struct netmap_adapter *na, int onoff)
797 if_ctx_t ctx = if_getsoftc(ifp);
802 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
807 * Enable (or disable) netmap flags, and intercept (or restore)
808 * ifp->if_transmit. This is done once the device has been stopped
809 * to prevent race conditions. Also, this must be done after
810 * calling netmap_disable_all_rings() and before calling
811 * netmap_enable_all_rings(), so that these two functions see the
812 * updated state of the NAF_NETMAP_ON bit.
815 nm_set_native_flags(na);
817 nm_clear_native_flags(na);
820 iflib_init_locked(ctx);
821 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
822 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1;
824 nm_clear_native_flags(na);
830 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info)
833 if_ctx_t ctx = if_getsoftc(ifp);
834 iflib_rxq_t rxq = &ctx->ifc_rxqs[0];
835 iflib_fl_t fl = &rxq->ifr_fl[0];
837 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
838 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
839 info->num_tx_descs = iflib_num_tx_descs(ctx);
840 info->num_rx_descs = iflib_num_rx_descs(ctx);
841 info->rx_buf_maxsize = fl->ifl_buf_size;
842 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u",
843 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs,
844 info->num_rx_descs, info->rx_buf_maxsize);
850 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
852 struct netmap_adapter *na = kring->na;
853 u_int const lim = kring->nkr_num_slots - 1;
854 struct netmap_ring *ring = kring->ring;
856 struct if_rxd_update iru;
857 if_ctx_t ctx = rxq->ifr_ctx;
858 iflib_fl_t fl = &rxq->ifr_fl[0];
859 u_int nic_i_first, nic_i;
862 #if IFLIB_DEBUG_COUNTERS
867 * This function is used both at initialization and in rxsync.
868 * At initialization we need to prepare (with isc_rxd_refill())
869 * all the netmap buffers currently owned by the kernel, in
870 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync
871 * (except for kring->nkr_hwofs). These may be less than
872 * kring->nkr_num_slots if netmap_reset() was called while
873 * an application using the kring that still owned some
875 * At rxsync time, both indexes point to the next buffer to be
877 * In any case we publish (with isc_rxd_flush()) up to
878 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod
879 * pointer to overrun the head/cons pointer, although this is
880 * not necessary for some NICs (e.g. vmx).
882 if (__predict_false(init)) {
883 n = kring->nkr_num_slots - nm_kr_rxspace(kring);
885 n = kring->rhead - kring->nr_hwcur;
887 return (0); /* Nothing to do. */
889 n += kring->nkr_num_slots;
892 iru_init(&iru, rxq, 0 /* flid */);
893 map = fl->ifl_sds.ifsd_map;
894 nic_i = fl->ifl_pidx;
895 nm_i = netmap_idx_n2k(kring, nic_i);
896 if (__predict_false(init)) {
898 * On init/reset, nic_i must be 0, and we must
899 * start to refill from hwtail (see netmap_reset()).
902 MPASS(nm_i == kring->nr_hwtail);
904 MPASS(nm_i == kring->nr_hwcur);
905 DBG_COUNTER_INC(fl_refills);
907 #if IFLIB_DEBUG_COUNTERS
909 DBG_COUNTER_INC(fl_refills_large);
912 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) {
913 struct netmap_slot *slot = &ring->slot[nm_i];
915 void *addr = PNMB(na, slot, &paddr);
917 MPASS(i < IFLIB_MAX_RX_REFRESH);
919 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
920 return netmap_ring_reinit(kring);
922 fl->ifl_bus_addrs[i] = paddr +
923 nm_get_offset(kring, slot);
924 fl->ifl_rxd_idxs[i] = nic_i;
926 if (__predict_false(init)) {
927 netmap_load_map(na, fl->ifl_buf_tag,
929 } else if (slot->flags & NS_BUF_CHANGED) {
930 /* buffer has changed, reload map */
931 netmap_reload_map(na, fl->ifl_buf_tag,
934 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
935 BUS_DMASYNC_PREREAD);
936 slot->flags &= ~NS_BUF_CHANGED;
938 nm_i = nm_next(nm_i, lim);
939 nic_i = nm_next(nic_i, lim);
942 iru.iru_pidx = nic_i_first;
944 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
946 fl->ifl_pidx = nic_i;
948 * At the end of the loop we must have refilled everything
949 * we could possibly refill.
951 MPASS(nm_i == kring->rhead);
952 kring->nr_hwcur = nm_i;
954 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
956 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
957 nm_prev(nic_i, lim));
958 DBG_COUNTER_INC(rxd_flush);
963 #define NETMAP_TX_TIMER_US 90
966 * Reconcile kernel and user view of the transmit ring.
968 * All information is in the kring.
969 * Userspace wants to send packets up to the one before kring->rhead,
970 * kernel knows kring->nr_hwcur is the first unsent packet.
972 * Here we push packets out (as many as possible), and possibly
973 * reclaim buffers from previously completed transmission.
975 * The caller (netmap) guarantees that there is only one instance
976 * running at any time. Any interference with other driver
977 * methods should be handled by the individual drivers.
980 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
982 struct netmap_adapter *na = kring->na;
984 struct netmap_ring *ring = kring->ring;
985 u_int nm_i; /* index into the netmap kring */
986 u_int nic_i; /* index into the NIC ring */
987 u_int const lim = kring->nkr_num_slots - 1;
988 u_int const head = kring->rhead;
989 struct if_pkt_info pi;
990 int tx_pkts = 0, tx_bytes = 0;
993 * interrupts on every tx packet are expensive so request
994 * them every half ring, or where NS_REPORT is set
996 u_int report_frequency = kring->nkr_num_slots >> 1;
997 /* device-specific */
998 if_ctx_t ctx = if_getsoftc(ifp);
999 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
1001 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1002 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1005 * First part: process new packets to send.
1006 * nm_i is the current index in the netmap kring,
1007 * nic_i is the corresponding index in the NIC ring.
1009 * If we have packets to send (nm_i != head)
1010 * iterate over the netmap ring, fetch length and update
1011 * the corresponding slot in the NIC ring. Some drivers also
1012 * need to update the buffer's physical address in the NIC slot
1013 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
1015 * The netmap_reload_map() calls is especially expensive,
1016 * even when (as in this case) the tag is 0, so do only
1017 * when the buffer has actually changed.
1019 * If possible do not set the report/intr bit on all slots,
1020 * but only a few times per ring or when NS_REPORT is set.
1022 * Finally, on 10G and faster drivers, it might be useful
1023 * to prefetch the next slot and txr entry.
1026 nm_i = kring->nr_hwcur;
1027 if (nm_i != head) { /* we have new packets to send */
1028 uint32_t pkt_len = 0, seg_idx = 0;
1029 int nic_i_start = -1, flags = 0;
1031 pi.ipi_segs = txq->ift_segs;
1032 pi.ipi_qsidx = kring->ring_id;
1033 nic_i = netmap_idx_k2n(kring, nm_i);
1035 __builtin_prefetch(&ring->slot[nm_i]);
1036 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
1037 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
1039 while (nm_i != head) {
1040 struct netmap_slot *slot = &ring->slot[nm_i];
1041 uint64_t offset = nm_get_offset(kring, slot);
1042 u_int len = slot->len;
1044 void *addr = PNMB(na, slot, &paddr);
1046 flags |= (slot->flags & NS_REPORT ||
1047 nic_i == 0 || nic_i == report_frequency) ?
1051 * If this is the first packet fragment, save the
1052 * index of the first NIC slot for later.
1054 if (nic_i_start < 0)
1055 nic_i_start = nic_i;
1057 pi.ipi_segs[seg_idx].ds_addr = paddr + offset;
1058 pi.ipi_segs[seg_idx].ds_len = len;
1064 if (!(slot->flags & NS_MOREFRAG)) {
1065 pi.ipi_len = pkt_len;
1066 pi.ipi_nsegs = seg_idx;
1067 pi.ipi_pidx = nic_i_start;
1069 pi.ipi_flags = flags;
1071 /* Prepare the NIC TX ring. */
1072 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1073 DBG_COUNTER_INC(tx_encap);
1075 /* Update transmit counters */
1076 tx_bytes += pi.ipi_len;
1079 /* Reinit per-packet info for the next one. */
1080 flags = seg_idx = pkt_len = 0;
1084 /* prefetch for next round */
1085 __builtin_prefetch(&ring->slot[nm_i + 1]);
1086 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1087 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1089 NM_CHECK_ADDR_LEN_OFF(na, len, offset);
1091 if (slot->flags & NS_BUF_CHANGED) {
1092 /* buffer has changed, reload map */
1093 netmap_reload_map(na, txq->ift_buf_tag,
1094 txq->ift_sds.ifsd_map[nic_i], addr);
1096 /* make sure changes to the buffer are synced */
1097 bus_dmamap_sync(txq->ift_buf_tag,
1098 txq->ift_sds.ifsd_map[nic_i],
1099 BUS_DMASYNC_PREWRITE);
1101 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG);
1102 nm_i = nm_next(nm_i, lim);
1103 nic_i = nm_next(nic_i, lim);
1105 kring->nr_hwcur = nm_i;
1107 /* synchronize the NIC ring */
1108 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1109 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1111 /* (re)start the tx unit up to slot nic_i (excluded) */
1112 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1116 * Second part: reclaim buffers for completed transmissions.
1118 * If there are unclaimed buffers, attempt to reclaim them.
1119 * If we don't manage to reclaim them all, and TX IRQs are not in use,
1120 * trigger a per-tx-queue timer to try again later.
1122 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1123 if (iflib_tx_credits_update(ctx, txq)) {
1124 /* some tx completed, increment avail */
1125 nic_i = txq->ift_cidx_processed;
1126 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1130 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1131 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1132 callout_reset_sbt_on(&txq->ift_netmap_timer,
1133 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US,
1134 iflib_netmap_timer, txq,
1135 txq->ift_netmap_timer.c_cpu, 0);
1138 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes);
1139 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts);
1145 * Reconcile kernel and user view of the receive ring.
1146 * Same as for the txsync, this routine must be efficient.
1147 * The caller guarantees a single invocations, but races against
1148 * the rest of the driver should be handled here.
1150 * On call, kring->rhead is the first packet that userspace wants
1151 * to keep, and kring->rcur is the wakeup point.
1152 * The kernel has previously reported packets up to kring->rtail.
1154 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1155 * of whether or not we received an interrupt.
1158 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1160 struct netmap_adapter *na = kring->na;
1161 struct netmap_ring *ring = kring->ring;
1163 uint32_t nm_i; /* index into the netmap ring */
1164 uint32_t nic_i; /* index into the NIC ring */
1166 u_int const lim = kring->nkr_num_slots - 1;
1167 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1168 int i = 0, rx_bytes = 0, rx_pkts = 0;
1170 if_ctx_t ctx = if_getsoftc(ifp);
1171 if_shared_ctx_t sctx = ctx->ifc_sctx;
1172 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1173 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1174 iflib_fl_t fl = &rxq->ifr_fl[0];
1175 struct if_rxd_info ri;
1179 * netmap only uses free list 0, to avoid out of order consumption
1180 * of receive buffers
1183 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1184 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1187 * First part: import newly received packets.
1189 * nm_i is the index of the next free slot in the netmap ring,
1190 * nic_i is the index of the next received packet in the NIC ring
1191 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1192 * differ in case if_init() has been called while
1193 * in netmap mode. For the receive ring we have
1195 * nic_i = fl->ifl_cidx;
1196 * nm_i = kring->nr_hwtail (previous)
1198 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1200 * fl->ifl_cidx is set to 0 on a ring reinit
1202 if (netmap_no_pendintr || force_update) {
1203 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1204 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1205 int crclen = iflib_crcstrip ? 0 : 4;
1209 * For the free list consumer index, we use the same
1210 * logic as in iflib_rxeof().
1213 cidxp = &rxq->ifr_cq_cidx;
1215 cidxp = &fl->ifl_cidx;
1216 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1217 rxq->ifr_id, *cidxp, USHRT_MAX);
1219 nic_i = fl->ifl_cidx;
1220 nm_i = netmap_idx_n2k(kring, nic_i);
1221 MPASS(nm_i == kring->nr_hwtail);
1222 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1224 ri.iri_frags = rxq->ifr_frags;
1225 ri.iri_qsidx = kring->ring_id;
1226 ri.iri_ifp = ctx->ifc_ifp;
1227 ri.iri_cidx = *cidxp;
1229 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1230 for (i = 0; i < ri.iri_nfrags; i++) {
1232 ring->slot[nm_i].len = 0;
1233 ring->slot[nm_i].flags = 0;
1235 ring->slot[nm_i].len = ri.iri_frags[i].irf_len;
1236 if (i == (ri.iri_nfrags - 1)) {
1237 ring->slot[nm_i].len -= crclen;
1238 ring->slot[nm_i].flags = 0;
1240 /* Update receive counters */
1241 rx_bytes += ri.iri_len;
1244 ring->slot[nm_i].flags = NS_MOREFRAG;
1247 bus_dmamap_sync(fl->ifl_buf_tag,
1248 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1249 nm_i = nm_next(nm_i, lim);
1250 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1254 *cidxp = ri.iri_cidx;
1255 while (*cidxp >= scctx->isc_nrxd[0])
1256 *cidxp -= scctx->isc_nrxd[0];
1260 if (n) { /* update the state variables */
1261 if (netmap_no_pendintr && !force_update) {
1264 iflib_rx_miss_bufs += n;
1266 kring->nr_hwtail = nm_i;
1268 kring->nr_kflags &= ~NKR_PENDINTR;
1271 * Second part: skip past packets that userspace has released.
1272 * (kring->nr_hwcur to head excluded),
1273 * and make the buffers available for reception.
1274 * As usual nm_i is the index in the netmap ring,
1275 * nic_i is the index in the NIC ring, and
1276 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1278 netmap_fl_refill(rxq, kring, false);
1280 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
1281 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
1287 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1289 if_ctx_t ctx = if_getsoftc(na->ifp);
1293 IFDI_INTR_ENABLE(ctx);
1295 IFDI_INTR_DISABLE(ctx);
1301 iflib_netmap_attach(if_ctx_t ctx)
1303 struct netmap_adapter na;
1305 bzero(&na, sizeof(na));
1307 na.ifp = ctx->ifc_ifp;
1308 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS;
1309 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1310 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1312 na.num_tx_desc = iflib_num_tx_descs(ctx);
1313 na.num_rx_desc = iflib_num_rx_descs(ctx);
1314 na.nm_txsync = iflib_netmap_txsync;
1315 na.nm_rxsync = iflib_netmap_rxsync;
1316 na.nm_register = iflib_netmap_register;
1317 na.nm_intr = iflib_netmap_intr;
1318 na.nm_config = iflib_netmap_config;
1319 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1320 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1321 return (netmap_attach(&na));
1325 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1327 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1328 struct netmap_slot *slot;
1330 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1333 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1335 * In netmap mode, set the map for the packet buffer.
1336 * NOTE: Some drivers (not this one) also need to set
1337 * the physical buffer address in the NIC ring.
1338 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1339 * netmap slot index, si
1341 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1342 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1343 NMB(na, slot + si));
1349 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1351 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1352 struct netmap_kring *kring;
1353 struct netmap_slot *slot;
1355 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1358 kring = na->rx_rings[rxq->ifr_id];
1359 netmap_fl_refill(rxq, kring, true);
1364 iflib_netmap_timer(void *arg)
1366 iflib_txq_t txq = arg;
1367 if_ctx_t ctx = txq->ift_ctx;
1370 * Wake up the netmap application, to give it a chance to
1371 * call txsync and reclaim more completed TX buffers.
1373 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id);
1376 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1379 #define iflib_netmap_txq_init(ctx, txq) (0)
1380 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1381 #define iflib_netmap_detach(ifp)
1382 #define netmap_enable_all_rings(ifp)
1383 #define netmap_disable_all_rings(ifp)
1385 #define iflib_netmap_attach(ctx) (0)
1386 #define netmap_rx_irq(ifp, qid, budget) (0)
1389 #if defined(__i386__) || defined(__amd64__)
1390 static __inline void
1393 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1396 static __inline void
1397 prefetch2cachelines(void *x)
1399 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1400 #if (CACHE_LINE_SIZE < 128)
1401 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1405 static __inline void
1410 static __inline void
1411 prefetch2cachelines(void *x)
1417 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1421 fl = &rxq->ifr_fl[flid];
1422 iru->iru_paddrs = fl->ifl_bus_addrs;
1423 iru->iru_idxs = fl->ifl_rxd_idxs;
1424 iru->iru_qsidx = rxq->ifr_id;
1425 iru->iru_buf_size = fl->ifl_buf_size;
1426 iru->iru_flidx = fl->ifl_id;
1430 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1434 *(bus_addr_t *) arg = segs[0].ds_addr;
1437 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \
1438 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \
1439 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL)
1442 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1445 device_t dev = ctx->ifc_dev;
1448 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width);
1450 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1451 align, 0, /* alignment, bounds */
1452 lowaddr, /* lowaddr */
1453 BUS_SPACE_MAXADDR, /* highaddr */
1454 NULL, NULL, /* filter, filterarg */
1457 size, /* maxsegsize */
1458 BUS_DMA_ALLOCNOW, /* flags */
1459 NULL, /* lockfunc */
1464 "%s: bus_dma_tag_create failed: %d\n",
1469 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1470 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1473 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1474 __func__, (uintmax_t)size, err);
1478 dma->idi_paddr = IF_BAD_DMA;
1479 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1480 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1481 if (err || dma->idi_paddr == IF_BAD_DMA) {
1483 "%s: bus_dmamap_load failed: %d\n",
1488 dma->idi_size = size;
1492 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1494 bus_dma_tag_destroy(dma->idi_tag);
1496 dma->idi_tag = NULL;
1502 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1504 if_shared_ctx_t sctx = ctx->ifc_sctx;
1506 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1508 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1512 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1515 iflib_dma_info_t *dmaiter;
1518 for (i = 0; i < count; i++, dmaiter++) {
1519 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1523 iflib_dma_free_multi(dmalist, i);
1528 iflib_dma_free(iflib_dma_info_t dma)
1530 if (dma->idi_tag == NULL)
1532 if (dma->idi_paddr != IF_BAD_DMA) {
1533 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1534 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1535 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1536 dma->idi_paddr = IF_BAD_DMA;
1538 if (dma->idi_vaddr != NULL) {
1539 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1540 dma->idi_vaddr = NULL;
1542 bus_dma_tag_destroy(dma->idi_tag);
1543 dma->idi_tag = NULL;
1547 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1550 iflib_dma_info_t *dmaiter = dmalist;
1552 for (i = 0; i < count; i++, dmaiter++)
1553 iflib_dma_free(*dmaiter);
1557 iflib_fast_intr(void *arg)
1559 iflib_filter_info_t info = arg;
1560 struct grouptask *gtask = info->ifi_task;
1563 DBG_COUNTER_INC(fast_intrs);
1564 if (info->ifi_filter != NULL) {
1565 result = info->ifi_filter(info->ifi_filter_arg);
1566 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1570 GROUPTASK_ENQUEUE(gtask);
1571 return (FILTER_HANDLED);
1575 iflib_fast_intr_rxtx(void *arg)
1577 iflib_filter_info_t info = arg;
1578 struct grouptask *gtask = info->ifi_task;
1580 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1583 int i, cidx, result;
1585 bool intr_enable, intr_legacy;
1587 DBG_COUNTER_INC(fast_intrs);
1588 if (info->ifi_filter != NULL) {
1589 result = info->ifi_filter(info->ifi_filter_arg);
1590 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1595 sc = ctx->ifc_softc;
1596 intr_enable = false;
1597 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1598 MPASS(rxq->ifr_ntxqirq);
1599 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1600 txqid = rxq->ifr_txqid[i];
1601 txq = &ctx->ifc_txqs[txqid];
1602 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1603 BUS_DMASYNC_POSTREAD);
1604 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1608 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1611 GROUPTASK_ENQUEUE(&txq->ift_task);
1613 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1614 cidx = rxq->ifr_cq_cidx;
1616 cidx = rxq->ifr_fl[0].ifl_cidx;
1617 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1618 GROUPTASK_ENQUEUE(gtask);
1623 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1624 DBG_COUNTER_INC(rx_intr_enables);
1627 IFDI_INTR_ENABLE(ctx);
1628 return (FILTER_HANDLED);
1632 iflib_fast_intr_ctx(void *arg)
1634 iflib_filter_info_t info = arg;
1635 struct grouptask *gtask = info->ifi_task;
1638 DBG_COUNTER_INC(fast_intrs);
1639 if (info->ifi_filter != NULL) {
1640 result = info->ifi_filter(info->ifi_filter_arg);
1641 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1645 if (gtask->gt_taskqueue != NULL)
1646 GROUPTASK_ENQUEUE(gtask);
1647 return (FILTER_HANDLED);
1651 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1652 driver_filter_t filter, driver_intr_t handler, void *arg,
1655 struct resource *res;
1657 device_t dev = ctx->ifc_dev;
1661 if (ctx->ifc_flags & IFC_LEGACY)
1662 flags |= RF_SHAREABLE;
1665 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1668 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1672 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1673 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1674 filter, handler, arg, &tag);
1677 "failed to setup interrupt for rid %d, name %s: %d\n",
1678 rid, name ? name : "unknown", rc);
1681 bus_describe_intr(dev, res, tag, "%s", name);
1687 /*********************************************************************
1689 * Allocate DMA resources for TX buffers as well as memory for the TX
1690 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1691 * iflib_sw_tx_desc_array structure, storing all the information that
1692 * is needed to transmit a packet on the wire. This is called only
1693 * once at attach, setup is done every reset.
1695 **********************************************************************/
1697 iflib_txsd_alloc(iflib_txq_t txq)
1699 if_ctx_t ctx = txq->ift_ctx;
1700 if_shared_ctx_t sctx = ctx->ifc_sctx;
1701 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1702 device_t dev = ctx->ifc_dev;
1703 bus_size_t tsomaxsize;
1705 int err, nsegments, ntsosegments;
1708 nsegments = scctx->isc_tx_nsegments;
1709 ntsosegments = scctx->isc_tx_tso_segments_max;
1710 tsomaxsize = scctx->isc_tx_tso_size_max;
1711 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1712 tsomaxsize += sizeof(struct ether_vlan_header);
1713 MPASS(scctx->isc_ntxd[0] > 0);
1714 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1715 MPASS(nsegments > 0);
1716 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1717 MPASS(ntsosegments > 0);
1718 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1721 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1724 * Set up DMA tags for TX buffers.
1726 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1727 1, 0, /* alignment, bounds */
1728 lowaddr, /* lowaddr */
1729 BUS_SPACE_MAXADDR, /* highaddr */
1730 NULL, NULL, /* filter, filterarg */
1731 sctx->isc_tx_maxsize, /* maxsize */
1732 nsegments, /* nsegments */
1733 sctx->isc_tx_maxsegsize, /* maxsegsize */
1735 NULL, /* lockfunc */
1736 NULL, /* lockfuncarg */
1737 &txq->ift_buf_tag))) {
1738 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1739 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1740 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1743 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1744 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1745 1, 0, /* alignment, bounds */
1746 lowaddr, /* lowaddr */
1747 BUS_SPACE_MAXADDR, /* highaddr */
1748 NULL, NULL, /* filter, filterarg */
1749 tsomaxsize, /* maxsize */
1750 ntsosegments, /* nsegments */
1751 sctx->isc_tso_maxsegsize,/* maxsegsize */
1753 NULL, /* lockfunc */
1754 NULL, /* lockfuncarg */
1755 &txq->ift_tso_buf_tag))) {
1756 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1761 /* Allocate memory for the TX mbuf map. */
1762 if (!(txq->ift_sds.ifsd_m =
1763 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1764 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1765 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1771 * Create the DMA maps for TX buffers.
1773 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1774 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1775 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1777 "Unable to allocate TX buffer DMA map memory\n");
1781 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1782 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1783 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1785 "Unable to allocate TSO TX buffer map memory\n");
1789 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1790 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1791 &txq->ift_sds.ifsd_map[i]);
1793 device_printf(dev, "Unable to create TX DMA map\n");
1798 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1799 &txq->ift_sds.ifsd_tso_map[i]);
1801 device_printf(dev, "Unable to create TSO TX DMA map\n");
1807 /* We free all, it handles case where we are in the middle */
1808 iflib_tx_structures_free(ctx);
1813 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1817 if (txq->ift_sds.ifsd_map != NULL) {
1818 map = txq->ift_sds.ifsd_map[i];
1819 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1820 bus_dmamap_unload(txq->ift_buf_tag, map);
1821 bus_dmamap_destroy(txq->ift_buf_tag, map);
1822 txq->ift_sds.ifsd_map[i] = NULL;
1825 if (txq->ift_sds.ifsd_tso_map != NULL) {
1826 map = txq->ift_sds.ifsd_tso_map[i];
1827 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1828 BUS_DMASYNC_POSTWRITE);
1829 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1830 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1831 txq->ift_sds.ifsd_tso_map[i] = NULL;
1836 iflib_txq_destroy(iflib_txq_t txq)
1838 if_ctx_t ctx = txq->ift_ctx;
1840 for (int i = 0; i < txq->ift_size; i++)
1841 iflib_txsd_destroy(ctx, txq, i);
1843 if (txq->ift_br != NULL) {
1844 ifmp_ring_free(txq->ift_br);
1848 mtx_destroy(&txq->ift_mtx);
1850 if (txq->ift_sds.ifsd_map != NULL) {
1851 free(txq->ift_sds.ifsd_map, M_IFLIB);
1852 txq->ift_sds.ifsd_map = NULL;
1854 if (txq->ift_sds.ifsd_tso_map != NULL) {
1855 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1856 txq->ift_sds.ifsd_tso_map = NULL;
1858 if (txq->ift_sds.ifsd_m != NULL) {
1859 free(txq->ift_sds.ifsd_m, M_IFLIB);
1860 txq->ift_sds.ifsd_m = NULL;
1862 if (txq->ift_buf_tag != NULL) {
1863 bus_dma_tag_destroy(txq->ift_buf_tag);
1864 txq->ift_buf_tag = NULL;
1866 if (txq->ift_tso_buf_tag != NULL) {
1867 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1868 txq->ift_tso_buf_tag = NULL;
1870 if (txq->ift_ifdi != NULL) {
1871 free(txq->ift_ifdi, M_IFLIB);
1876 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1880 mp = &txq->ift_sds.ifsd_m[i];
1884 if (txq->ift_sds.ifsd_map != NULL) {
1885 bus_dmamap_sync(txq->ift_buf_tag,
1886 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1887 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1889 if (txq->ift_sds.ifsd_tso_map != NULL) {
1890 bus_dmamap_sync(txq->ift_tso_buf_tag,
1891 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1892 bus_dmamap_unload(txq->ift_tso_buf_tag,
1893 txq->ift_sds.ifsd_tso_map[i]);
1896 DBG_COUNTER_INC(tx_frees);
1901 iflib_txq_setup(iflib_txq_t txq)
1903 if_ctx_t ctx = txq->ift_ctx;
1904 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1905 if_shared_ctx_t sctx = ctx->ifc_sctx;
1906 iflib_dma_info_t di;
1909 /* Set number of descriptors available */
1910 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1911 /* XXX make configurable */
1912 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1915 txq->ift_cidx_processed = 0;
1916 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1917 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1919 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1920 bzero((void *)di->idi_vaddr, di->idi_size);
1922 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1923 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1924 bus_dmamap_sync(di->idi_tag, di->idi_map,
1925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1929 /*********************************************************************
1931 * Allocate DMA resources for RX buffers as well as memory for the RX
1932 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1933 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1934 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1935 * Since we use use one entry in iflib_sw_rx_desc_array per received
1936 * packet, the maximum number of entries we'll need is equal to the
1937 * number of hardware receive descriptors that we've allocated.
1939 **********************************************************************/
1941 iflib_rxsd_alloc(iflib_rxq_t rxq)
1943 if_ctx_t ctx = rxq->ifr_ctx;
1944 if_shared_ctx_t sctx = ctx->ifc_sctx;
1945 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1946 device_t dev = ctx->ifc_dev;
1951 MPASS(scctx->isc_nrxd[0] > 0);
1952 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1954 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1957 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1958 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1959 /* Set up DMA tag for RX buffers. */
1960 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1961 1, 0, /* alignment, bounds */
1962 lowaddr, /* lowaddr */
1963 BUS_SPACE_MAXADDR, /* highaddr */
1964 NULL, NULL, /* filter, filterarg */
1965 sctx->isc_rx_maxsize, /* maxsize */
1966 sctx->isc_rx_nsegments, /* nsegments */
1967 sctx->isc_rx_maxsegsize, /* maxsegsize */
1969 NULL, /* lockfunc */
1974 "Unable to allocate RX DMA tag: %d\n", err);
1978 /* Allocate memory for the RX mbuf map. */
1979 if (!(fl->ifl_sds.ifsd_m =
1980 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1981 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1983 "Unable to allocate RX mbuf map memory\n");
1988 /* Allocate memory for the direct RX cluster pointer map. */
1989 if (!(fl->ifl_sds.ifsd_cl =
1990 (caddr_t *) malloc(sizeof(caddr_t) *
1991 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1993 "Unable to allocate RX cluster map memory\n");
1998 /* Allocate memory for the RX cluster bus address map. */
1999 if (!(fl->ifl_sds.ifsd_ba =
2000 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
2001 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2003 "Unable to allocate RX bus address map memory\n");
2009 * Create the DMA maps for RX buffers.
2011 if (!(fl->ifl_sds.ifsd_map =
2012 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2014 "Unable to allocate RX buffer DMA map memory\n");
2018 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
2019 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
2020 &fl->ifl_sds.ifsd_map[i]);
2022 device_printf(dev, "Unable to create RX buffer DMA map\n");
2030 iflib_rx_structures_free(ctx);
2035 * Internal service routines
2038 struct rxq_refill_cb_arg {
2040 bus_dma_segment_t seg;
2045 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2047 struct rxq_refill_cb_arg *cb_arg = arg;
2049 cb_arg->error = error;
2050 cb_arg->seg = segs[0];
2051 cb_arg->nseg = nseg;
2055 * iflib_fl_refill - refill an rxq free-buffer list
2056 * @ctx: the iflib context
2057 * @fl: the free list to refill
2058 * @count: the number of new buffers to allocate
2060 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
2061 * The caller must assure that @count does not exceed the queue's capacity
2062 * minus one (since we always leave a descriptor unavailable).
2065 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
2067 struct if_rxd_update iru;
2068 struct rxq_refill_cb_arg cb_arg;
2072 bus_dmamap_t *sd_map;
2073 bus_addr_t bus_addr, *sd_ba;
2074 int err, frag_idx, i, idx, n, pidx;
2077 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1);
2079 sd_m = fl->ifl_sds.ifsd_m;
2080 sd_map = fl->ifl_sds.ifsd_map;
2081 sd_cl = fl->ifl_sds.ifsd_cl;
2082 sd_ba = fl->ifl_sds.ifsd_ba;
2083 pidx = fl->ifl_pidx;
2085 frag_idx = fl->ifl_fragidx;
2086 credits = fl->ifl_credits;
2091 MPASS(credits + n <= fl->ifl_size);
2093 if (pidx < fl->ifl_cidx)
2094 MPASS(pidx + n <= fl->ifl_cidx);
2095 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
2096 MPASS(fl->ifl_gen == 0);
2097 if (pidx > fl->ifl_cidx)
2098 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
2100 DBG_COUNTER_INC(fl_refills);
2102 DBG_COUNTER_INC(fl_refills_large);
2103 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2106 * We allocate an uninitialized mbuf + cluster, mbuf is
2107 * initialized after rx.
2109 * If the cluster is still set then we know a minimum sized
2110 * packet was received
2112 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2115 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2116 MPASS(frag_idx >= 0);
2117 if ((cl = sd_cl[frag_idx]) == NULL) {
2118 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2119 if (__predict_false(cl == NULL))
2123 MPASS(sd_map != NULL);
2124 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2125 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2127 if (__predict_false(err != 0 || cb_arg.error)) {
2128 uma_zfree(fl->ifl_zone, cl);
2132 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2133 sd_cl[frag_idx] = cl;
2135 fl->ifl_cl_enqueued++;
2138 bus_addr = sd_ba[frag_idx];
2140 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2141 BUS_DMASYNC_PREREAD);
2143 if (sd_m[frag_idx] == NULL) {
2144 m = m_gethdr_raw(M_NOWAIT, 0);
2145 if (__predict_false(m == NULL))
2149 bit_set(fl->ifl_rx_bitmap, frag_idx);
2151 fl->ifl_m_enqueued++;
2154 DBG_COUNTER_INC(rx_allocs);
2155 fl->ifl_rxd_idxs[i] = frag_idx;
2156 fl->ifl_bus_addrs[i] = bus_addr;
2159 MPASS(credits <= fl->ifl_size);
2160 if (++idx == fl->ifl_size) {
2166 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2167 iru.iru_pidx = pidx;
2169 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2171 fl->ifl_credits = credits;
2177 if (n < count - 1) {
2179 iru.iru_pidx = pidx;
2181 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2183 fl->ifl_credits = credits;
2185 DBG_COUNTER_INC(rxd_flush);
2186 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2187 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2188 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2189 fl->ifl_id, fl->ifl_pidx);
2190 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2191 fl->ifl_fragidx = frag_idx + 1;
2192 if (fl->ifl_fragidx == fl->ifl_size)
2193 fl->ifl_fragidx = 0;
2195 fl->ifl_fragidx = frag_idx;
2199 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2202 static inline uint8_t
2203 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2206 * We leave an unused descriptor to avoid pidx to catch up with cidx.
2207 * This is important as it confuses most NICs. For instance,
2208 * Intel NICs have (per receive ring) RDH and RDT registers, where
2209 * RDH points to the next receive descriptor to be used by the NIC,
2210 * and RDT for the next receive descriptor to be published by the
2211 * driver to the NIC (RDT - 1 is thus the last valid one).
2212 * The condition RDH == RDT means no descriptors are available to
2213 * the NIC, and thus it would be ambiguous if it also meant that
2214 * all the descriptors are available to the NIC.
2216 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2218 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2221 MPASS(fl->ifl_credits <= fl->ifl_size);
2222 MPASS(reclaimable == delta);
2224 if (reclaimable > 0)
2225 return (iflib_fl_refill(ctx, fl, reclaimable));
2230 iflib_in_detach(if_ctx_t ctx)
2235 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2241 iflib_fl_bufs_free(iflib_fl_t fl)
2243 iflib_dma_info_t idi = fl->ifl_ifdi;
2244 bus_dmamap_t sd_map;
2247 for (i = 0; i < fl->ifl_size; i++) {
2248 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2249 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2251 if (*sd_cl != NULL) {
2252 sd_map = fl->ifl_sds.ifsd_map[i];
2253 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2254 BUS_DMASYNC_POSTREAD);
2255 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2256 uma_zfree(fl->ifl_zone, *sd_cl);
2258 if (*sd_m != NULL) {
2259 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2264 MPASS(*sd_m == NULL);
2267 fl->ifl_m_dequeued++;
2268 fl->ifl_cl_dequeued++;
2272 for (i = 0; i < fl->ifl_size; i++) {
2273 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2274 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2278 * Reset free list values
2280 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2281 bzero(idi->idi_vaddr, idi->idi_size);
2284 /*********************************************************************
2286 * Initialize a free list and its buffers.
2288 **********************************************************************/
2290 iflib_fl_setup(iflib_fl_t fl)
2292 iflib_rxq_t rxq = fl->ifl_rxq;
2293 if_ctx_t ctx = rxq->ifr_ctx;
2294 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2297 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2299 ** Free current RX buffer structs and their mbufs
2301 iflib_fl_bufs_free(fl);
2302 /* Now replenish the mbufs */
2303 MPASS(fl->ifl_credits == 0);
2304 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2305 if (scctx->isc_rxd_buf_size[qidx] != 0)
2306 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2308 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2310 * ifl_buf_size may be a driver-supplied value, so pull it up
2311 * to the selected mbuf size.
2313 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2314 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2315 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2316 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2317 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2320 * Avoid pre-allocating zillions of clusters to an idle card
2321 * potentially speeding up attach. In any case make sure
2322 * to leave a descriptor unavailable. See the comment in
2323 * iflib_fl_refill_all().
2325 MPASS(fl->ifl_size > 0);
2326 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1));
2327 if (min(128, fl->ifl_size - 1) != fl->ifl_credits)
2333 MPASS(fl->ifl_ifdi != NULL);
2334 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2335 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2339 /*********************************************************************
2341 * Free receive ring data structures
2343 **********************************************************************/
2345 iflib_rx_sds_free(iflib_rxq_t rxq)
2350 if (rxq->ifr_fl != NULL) {
2351 for (i = 0; i < rxq->ifr_nfl; i++) {
2352 fl = &rxq->ifr_fl[i];
2353 if (fl->ifl_buf_tag != NULL) {
2354 if (fl->ifl_sds.ifsd_map != NULL) {
2355 for (j = 0; j < fl->ifl_size; j++) {
2358 fl->ifl_sds.ifsd_map[j],
2359 BUS_DMASYNC_POSTREAD);
2362 fl->ifl_sds.ifsd_map[j]);
2365 fl->ifl_sds.ifsd_map[j]);
2368 bus_dma_tag_destroy(fl->ifl_buf_tag);
2369 fl->ifl_buf_tag = NULL;
2371 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2372 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2373 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2374 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2375 free(fl->ifl_rx_bitmap, M_IFLIB);
2376 fl->ifl_sds.ifsd_m = NULL;
2377 fl->ifl_sds.ifsd_cl = NULL;
2378 fl->ifl_sds.ifsd_ba = NULL;
2379 fl->ifl_sds.ifsd_map = NULL;
2380 fl->ifl_rx_bitmap = NULL;
2382 free(rxq->ifr_fl, M_IFLIB);
2384 free(rxq->ifr_ifdi, M_IFLIB);
2385 rxq->ifr_ifdi = NULL;
2386 rxq->ifr_cq_cidx = 0;
2394 iflib_timer(void *arg)
2396 iflib_txq_t txq = arg;
2397 if_ctx_t ctx = txq->ift_ctx;
2398 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2399 uint64_t this_tick = ticks;
2401 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2405 ** Check on the state of the TX queue(s), this
2406 ** can be done without the lock because its RO
2407 ** and the HUNG state will be static if set.
2409 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) {
2410 txq->ift_last_timer_tick = this_tick;
2411 IFDI_TIMER(ctx, txq->ift_id);
2412 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2413 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2414 (sctx->isc_pause_frames == 0)))
2417 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2418 ifmp_ring_is_stalled(txq->ift_br)) {
2419 KASSERT(ctx->ifc_link_state == LINK_STATE_UP,
2420 ("queue can't be marked as hung if interface is down"));
2421 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2423 txq->ift_cleaned_prev = txq->ift_cleaned;
2425 /* handle any laggards */
2426 if (txq->ift_db_pending)
2427 GROUPTASK_ENQUEUE(&txq->ift_task);
2429 sctx->isc_pause_frames = 0;
2430 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2431 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer,
2432 txq, txq->ift_timer.c_cpu);
2436 device_printf(ctx->ifc_dev,
2437 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2438 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2440 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2441 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2442 iflib_admin_intr_deferred(ctx);
2447 iflib_get_mbuf_size_for(unsigned int size)
2450 if (size <= MCLBYTES)
2453 return (MJUMPAGESIZE);
2457 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2459 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2462 * XXX don't set the max_frame_size to larger
2463 * than the hardware can handle
2465 ctx->ifc_rx_mbuf_sz =
2466 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2470 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2473 return (ctx->ifc_rx_mbuf_sz);
2477 iflib_init_locked(if_ctx_t ctx)
2479 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2480 if_t ifp = ctx->ifc_ifp;
2484 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2486 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2487 IFDI_INTR_DISABLE(ctx);
2490 * See iflib_stop(). Useful in case iflib_init_locked() is
2491 * called without first calling iflib_stop().
2493 netmap_disable_all_rings(ifp);
2495 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2496 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2497 /* Set hardware offload abilities */
2498 if_clearhwassist(ifp);
2499 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2500 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2501 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2502 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2503 if (if_getcapenable(ifp) & IFCAP_TSO4)
2504 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2505 if (if_getcapenable(ifp) & IFCAP_TSO6)
2506 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2508 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
2510 callout_stop(&txq->ift_timer);
2512 callout_stop(&txq->ift_netmap_timer);
2513 #endif /* DEV_NETMAP */
2514 CALLOUT_UNLOCK(txq);
2515 (void)iflib_netmap_txq_init(ctx, txq);
2519 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2520 * that drivers can use the value when setting up the hardware receive
2523 iflib_calc_rx_mbuf_sz(ctx);
2526 i = if_getdrvflags(ifp);
2529 MPASS(if_getdrvflags(ifp) == i);
2530 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
2531 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2532 /* This rxq is in netmap mode. Skip normal init. */
2535 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2536 if (iflib_fl_setup(fl)) {
2537 device_printf(ctx->ifc_dev,
2538 "setting up free list %d failed - "
2539 "check cluster settings\n", j);
2545 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2546 IFDI_INTR_ENABLE(ctx);
2547 txq = ctx->ifc_txqs;
2548 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++)
2549 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
2550 txq->ift_timer.c_cpu);
2552 /* Re-enable txsync/rxsync. */
2553 netmap_enable_all_rings(ifp);
2557 iflib_media_change(if_t ifp)
2559 if_ctx_t ctx = if_getsoftc(ifp);
2563 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2564 iflib_if_init_locked(ctx);
2570 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2572 if_ctx_t ctx = if_getsoftc(ifp);
2575 IFDI_UPDATE_ADMIN_STATUS(ctx);
2576 IFDI_MEDIA_STATUS(ctx, ifmr);
2581 iflib_stop(if_ctx_t ctx)
2583 iflib_txq_t txq = ctx->ifc_txqs;
2584 iflib_rxq_t rxq = ctx->ifc_rxqs;
2585 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2586 if_shared_ctx_t sctx = ctx->ifc_sctx;
2587 iflib_dma_info_t di;
2591 /* Tell the stack that the interface is no longer active */
2592 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2594 IFDI_INTR_DISABLE(ctx);
2600 * Stop any pending txsync/rxsync and prevent new ones
2601 * form starting. Processes blocked in poll() will get
2604 netmap_disable_all_rings(ctx->ifc_ifp);
2606 iflib_debug_reset();
2607 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2608 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2609 /* make sure all transmitters have completed before proceeding XXX */
2612 callout_stop(&txq->ift_timer);
2614 callout_stop(&txq->ift_netmap_timer);
2615 #endif /* DEV_NETMAP */
2616 CALLOUT_UNLOCK(txq);
2618 /* clean any enqueued buffers */
2619 iflib_ifmp_purge(txq);
2620 /* Free any existing tx buffers. */
2621 for (j = 0; j < txq->ift_size; j++) {
2622 iflib_txsd_free(ctx, txq, j);
2624 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2625 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0;
2626 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES)
2627 txq->ift_cidx = txq->ift_pidx;
2629 txq->ift_cidx = txq->ift_pidx = 0;
2631 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2632 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2633 txq->ift_pullups = 0;
2634 ifmp_ring_reset_stats(txq->ift_br);
2635 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2636 bzero((void *)di->idi_vaddr, di->idi_size);
2638 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2639 if (rxq->ifr_task.gt_taskqueue != NULL)
2640 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue,
2641 &rxq->ifr_task.gt_task);
2643 rxq->ifr_cq_cidx = 0;
2644 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2645 bzero((void *)di->idi_vaddr, di->idi_size);
2646 /* also resets the free lists pidx/cidx */
2647 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2648 iflib_fl_bufs_free(fl);
2652 static inline caddr_t
2653 calc_next_rxd(iflib_fl_t fl, int cidx)
2657 caddr_t start, end, cur, next;
2659 nrxd = fl->ifl_size;
2660 size = fl->ifl_rxd_size;
2661 start = fl->ifl_ifdi->idi_vaddr;
2663 if (__predict_false(size == 0))
2665 cur = start + size*cidx;
2666 end = start + size*nrxd;
2667 next = CACHE_PTR_NEXT(cur);
2668 return (next < end ? next : start);
2672 prefetch_pkts(iflib_fl_t fl, int cidx)
2675 int nrxd = fl->ifl_size;
2678 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2679 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2680 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2681 next_rxd = calc_next_rxd(fl, cidx);
2683 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2684 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2685 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2686 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2687 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2688 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2689 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2690 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2693 static struct mbuf *
2694 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2695 int *pf_rv, if_rxd_info_t ri)
2701 int flid, cidx, len, next;
2704 flid = irf->irf_flid;
2705 cidx = irf->irf_idx;
2706 fl = &rxq->ifr_fl[flid];
2708 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2711 fl->ifl_m_dequeued++;
2713 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2714 prefetch_pkts(fl, cidx);
2715 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2716 prefetch(&fl->ifl_sds.ifsd_map[next]);
2717 map = fl->ifl_sds.ifsd_map[cidx];
2719 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2721 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2722 irf->irf_len != 0) {
2723 payload = *sd->ifsd_cl;
2724 payload += ri->iri_pad;
2725 len = ri->iri_len - ri->iri_pad;
2726 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m);
2731 * The filter ate it. Everything is recycled.
2736 case PFIL_REALLOCED:
2738 * The filter copied it. Everything is recycled.
2739 * 'm' points at new mbuf.
2745 * Filter said it was OK, so receive like
2748 m = fl->ifl_sds.ifsd_m[cidx];
2749 fl->ifl_sds.ifsd_m[cidx] = NULL;
2755 m = fl->ifl_sds.ifsd_m[cidx];
2756 fl->ifl_sds.ifsd_m[cidx] = NULL;
2761 if (unload && irf->irf_len != 0)
2762 bus_dmamap_unload(fl->ifl_buf_tag, map);
2763 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2764 if (__predict_false(fl->ifl_cidx == 0))
2766 bit_clear(fl->ifl_rx_bitmap, cidx);
2770 static struct mbuf *
2771 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2773 struct mbuf *m, *mh, *mt;
2775 int *pf_rv_ptr, flags, i, padlen;
2784 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2787 MPASS(*sd->ifsd_cl != NULL);
2790 * Exclude zero-length frags & frags from
2791 * packets the filter has consumed or dropped
2793 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2794 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2796 /* everything saved here */
2801 /* XXX we can save the cluster here, but not the mbuf */
2802 m_init(m, M_NOWAIT, MT_DATA, 0);
2807 flags = M_PKTHDR|M_EXT;
2809 padlen = ri->iri_pad;
2814 /* assuming padding is only on the first fragment */
2818 *sd->ifsd_cl = NULL;
2820 /* Can these two be made one ? */
2821 m_init(m, M_NOWAIT, MT_DATA, flags);
2822 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2824 * These must follow m_init and m_cljset
2826 m->m_data += padlen;
2827 ri->iri_len -= padlen;
2828 m->m_len = ri->iri_frags[i].irf_len;
2829 } while (++i < ri->iri_nfrags);
2835 * Process one software descriptor
2837 static struct mbuf *
2838 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2844 /* should I merge this back in now that the two paths are basically duplicated? */
2845 if (ri->iri_nfrags == 1 &&
2846 ri->iri_frags[0].irf_len != 0 &&
2847 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2848 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2850 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2852 if (pf_rv == PFIL_PASS) {
2853 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2854 #ifndef __NO_STRICT_ALIGNMENT
2855 if (!IP_ALIGNED(m) && ri->iri_pad == 0)
2858 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2859 m->m_len = ri->iri_frags[0].irf_len;
2860 m->m_data += ri->iri_pad;
2861 ri->iri_len -= ri->iri_pad;
2864 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2867 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2870 m->m_pkthdr.len = ri->iri_len;
2871 m->m_pkthdr.rcvif = ri->iri_ifp;
2872 m->m_flags |= ri->iri_flags;
2873 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2874 m->m_pkthdr.flowid = ri->iri_flowid;
2875 M_HASHTYPE_SET(m, ri->iri_rsstype);
2876 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2877 m->m_pkthdr.csum_data = ri->iri_csum_data;
2881 #if defined(INET6) || defined(INET)
2883 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2885 CURVNET_SET(if_getvnet(lc->ifp));
2887 *v6 = V_ip6_forwarding;
2890 *v4 = V_ipforwarding;
2896 * Returns true if it's possible this packet could be LROed.
2897 * if it returns false, it is guaranteed that tcp_lro_rx()
2898 * would not return zero.
2901 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2903 struct ether_header *eh;
2905 eh = mtod(m, struct ether_header *);
2906 switch (eh->ether_type) {
2908 case htons(ETHERTYPE_IPV6):
2909 return (!v6_forwarding);
2912 case htons(ETHERTYPE_IP):
2913 return (!v4_forwarding);
2921 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2927 _task_fn_rx_watchdog(void *context)
2929 iflib_rxq_t rxq = context;
2931 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2935 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2938 if_ctx_t ctx = rxq->ifr_ctx;
2939 if_shared_ctx_t sctx = ctx->ifc_sctx;
2940 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2943 struct if_rxd_info ri;
2944 int err, budget_left, rx_bytes, rx_pkts;
2947 bool v4_forwarding, v6_forwarding, lro_possible;
2951 * XXX early demux data packets so that if_input processing only handles
2952 * acks in interrupt context
2954 struct mbuf *m, *mh, *mt, *mf;
2958 lro_possible = v4_forwarding = v6_forwarding = false;
2962 rx_pkts = rx_bytes = 0;
2963 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2964 cidxp = &rxq->ifr_cq_cidx;
2966 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2967 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2968 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2969 retval |= iflib_fl_refill_all(ctx, fl);
2970 DBG_COUNTER_INC(rx_unavail);
2974 /* pfil needs the vnet to be set */
2975 CURVNET_SET_QUIET(if_getvnet(ifp));
2976 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2977 if (__predict_false(!CTX_ACTIVE(ctx))) {
2978 DBG_COUNTER_INC(rx_ctx_inactive);
2982 * Reset client set fields to their default values
2985 ri.iri_qsidx = rxq->ifr_id;
2986 ri.iri_cidx = *cidxp;
2988 ri.iri_frags = rxq->ifr_frags;
2989 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2994 rx_bytes += ri.iri_len;
2995 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2996 *cidxp = ri.iri_cidx;
2997 /* Update our consumer index */
2998 /* XXX NB: shurd - check if this is still safe */
2999 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
3000 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
3001 /* was this only a completion queue message? */
3002 if (__predict_false(ri.iri_nfrags == 0))
3005 MPASS(ri.iri_nfrags != 0);
3006 MPASS(ri.iri_len != 0);
3008 /* will advance the cidx on the corresponding free lists */
3009 m = iflib_rxd_pkt_get(rxq, &ri);
3012 if (avail == 0 && budget_left)
3013 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
3015 if (__predict_false(m == NULL))
3018 /* imm_pkt: -- cxgb */
3027 /* make sure that we can refill faster than drain */
3028 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
3029 retval |= iflib_fl_refill_all(ctx, fl);
3031 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
3033 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
3035 while (mh != NULL) {
3038 m->m_nextpkt = NULL;
3039 #ifndef __NO_STRICT_ALIGNMENT
3040 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
3043 #if defined(INET6) || defined(INET)
3045 if (!lro_possible) {
3046 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
3047 if (lro_possible && mf != NULL) {
3049 DBG_COUNTER_INC(rx_if_input);
3053 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
3054 (CSUM_L4_CALC|CSUM_L4_VALID)) {
3055 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
3062 DBG_COUNTER_INC(rx_if_input);
3074 DBG_COUNTER_INC(rx_if_input);
3077 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
3078 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
3081 * Flush any outstanding LRO work
3083 #if defined(INET6) || defined(INET)
3084 tcp_lro_flush_all(&rxq->ifr_lc);
3086 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
3087 retval |= IFLIB_RXEOF_MORE;
3091 ctx->ifc_flags |= IFC_DO_RESET;
3092 iflib_admin_intr_deferred(ctx);
3097 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
3098 static inline qidx_t
3099 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
3101 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3102 qidx_t minthresh = txq->ift_size / 8;
3103 if (in_use > 4*minthresh)
3104 return (notify_count);
3105 if (in_use > 2*minthresh)
3106 return (notify_count >> 1);
3107 if (in_use > minthresh)
3108 return (notify_count >> 3);
3112 static inline qidx_t
3113 txq_max_rs_deferred(iflib_txq_t txq)
3115 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3116 qidx_t minthresh = txq->ift_size / 8;
3117 if (txq->ift_in_use > 4*minthresh)
3118 return (notify_count);
3119 if (txq->ift_in_use > 2*minthresh)
3120 return (notify_count >> 1);
3121 if (txq->ift_in_use > minthresh)
3122 return (notify_count >> 2);
3126 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
3127 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
3129 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
3130 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
3131 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
3133 /* forward compatibility for cxgb */
3134 #define FIRST_QSET(ctx) 0
3135 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
3136 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
3137 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
3138 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
3140 /* XXX we should be setting this to something other than zero */
3141 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
3142 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3143 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3146 iflib_txd_db_check(iflib_txq_t txq, int ring)
3148 if_ctx_t ctx = txq->ift_ctx;
3151 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use);
3153 /* force || threshold exceeded || at the edge of the ring */
3154 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) {
3157 * 'npending' is used if the card's doorbell is in terms of the number of descriptors
3158 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the
3159 * producer index explicitly (INTC).
3161 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3162 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3163 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3164 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3167 * Absent bugs there are zero packets pending so reset pending counts to zero.
3169 txq->ift_db_pending = txq->ift_npending = 0;
3177 print_pkt(if_pkt_info_t pi)
3179 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3180 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3181 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3182 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3183 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3184 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3188 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3189 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3190 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3191 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3194 * Parses out ethernet header information in the given mbuf.
3195 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length)
3197 * This will account for the VLAN header if present.
3199 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those
3203 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups)
3205 struct ether_vlan_header *eh;
3209 if (__predict_false(m->m_len < sizeof(*eh))) {
3211 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3214 eh = mtod(m, struct ether_vlan_header *);
3215 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3216 pi->ipi_etype = ntohs(eh->evl_proto);
3217 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3219 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3220 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3228 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi.
3229 * Currently this information includes: IP ToS value, IP header version/presence
3231 * This is missing some checks and doesn't edit the packet content as it goes,
3232 * unlike iflib_parse_header(), in order to keep the amount of code here minimal.
3235 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups)
3242 if (!M_WRITABLE(m)) {
3243 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3247 DBG_COUNTER_INC(tx_frees);
3252 /* Fills out pi->ipi_etype */
3253 err = iflib_parse_ether_header(pi, mp, pullups);
3258 switch (pi->ipi_etype) {
3263 struct ip *ip = NULL;
3266 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip));
3267 if (__predict_false(m->m_len < miniplen)) {
3269 * Check for common case where the first mbuf only contains
3270 * the Ethernet header
3272 if (m->m_len == pi->ipi_ehdrlen) {
3275 /* If next mbuf contains at least the minimal IP header, then stop */
3276 if (n->m_len >= sizeof(*ip)) {
3277 ip = (struct ip *)n->m_data;
3280 if (__predict_false((m = m_pullup(m, miniplen)) == NULL))
3282 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3286 if (__predict_false((m = m_pullup(m, miniplen)) == NULL))
3288 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3291 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3294 /* Have the IPv4 header w/ no options here */
3295 pi->ipi_ip_hlen = ip->ip_hl << 2;
3296 pi->ipi_ipproto = ip->ip_p;
3297 pi->ipi_ip_tos = ip->ip_tos;
3298 pi->ipi_flags |= IPI_TX_IPV4;
3304 case ETHERTYPE_IPV6:
3306 struct ip6_hdr *ip6;
3308 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3310 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3313 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3315 /* Have the IPv6 fixed header here */
3316 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3317 pi->ipi_ipproto = ip6->ip6_nxt;
3318 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6);
3319 pi->ipi_flags |= IPI_TX_IPV6;
3325 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3326 pi->ipi_ip_hlen = 0;
3336 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3338 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3343 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3344 M_WRITABLE(m) == 0) {
3345 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3349 DBG_COUNTER_INC(tx_frees);
3354 /* Fills out pi->ipi_etype */
3355 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups);
3356 if (__predict_false(err))
3360 switch (pi->ipi_etype) {
3365 struct ip *ip = NULL;
3366 struct tcphdr *th = NULL;
3369 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3370 if (__predict_false(m->m_len < minthlen)) {
3372 * if this code bloat is causing too much of a hit
3373 * move it to a separate function and mark it noinline
3375 if (m->m_len == pi->ipi_ehdrlen) {
3378 if (n->m_len >= sizeof(*ip)) {
3379 ip = (struct ip *)n->m_data;
3380 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3381 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3384 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3386 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3390 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3392 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3393 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3394 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3397 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3398 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3399 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3401 pi->ipi_ip_hlen = ip->ip_hl << 2;
3402 pi->ipi_ipproto = ip->ip_p;
3403 pi->ipi_ip_tos = ip->ip_tos;
3404 pi->ipi_flags |= IPI_TX_IPV4;
3406 /* TCP checksum offload may require TCP header length */
3407 if (IS_TX_OFFLOAD4(pi)) {
3408 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3409 if (__predict_false(th == NULL)) {
3411 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3413 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3415 pi->ipi_tcp_hflags = th->th_flags;
3416 pi->ipi_tcp_hlen = th->th_off << 2;
3417 pi->ipi_tcp_seq = th->th_seq;
3420 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3423 * TSO always requires hardware checksum offload.
3425 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3426 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3427 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3428 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3429 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3431 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3435 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3442 case ETHERTYPE_IPV6:
3444 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3446 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3448 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3450 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3453 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3455 /* XXX-BZ this will go badly in case of ext hdrs. */
3456 pi->ipi_ipproto = ip6->ip6_nxt;
3457 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6);
3458 pi->ipi_flags |= IPI_TX_IPV6;
3460 /* TCP checksum offload may require TCP header length */
3461 if (IS_TX_OFFLOAD6(pi)) {
3462 if (pi->ipi_ipproto == IPPROTO_TCP) {
3463 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3465 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3468 pi->ipi_tcp_hflags = th->th_flags;
3469 pi->ipi_tcp_hlen = th->th_off << 2;
3470 pi->ipi_tcp_seq = th->th_seq;
3473 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3476 * TSO always requires hardware checksum offload.
3478 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3479 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3480 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3487 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3488 pi->ipi_ip_hlen = 0;
3497 * If dodgy hardware rejects the scatter gather chain we've handed it
3498 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3501 static __noinline struct mbuf *
3502 iflib_remove_mbuf(iflib_txq_t txq)
3505 struct mbuf *m, **ifsd_m;
3507 ifsd_m = txq->ift_sds.ifsd_m;
3508 ntxd = txq->ift_size;
3509 pidx = txq->ift_pidx & (ntxd - 1);
3510 ifsd_m = txq->ift_sds.ifsd_m;
3512 ifsd_m[pidx] = NULL;
3513 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3514 if (txq->ift_sds.ifsd_tso_map != NULL)
3515 bus_dmamap_unload(txq->ift_tso_buf_tag,
3516 txq->ift_sds.ifsd_tso_map[pidx]);
3518 txq->ift_dequeued++;
3523 static inline caddr_t
3524 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3528 caddr_t start, end, cur, next;
3530 ntxd = txq->ift_size;
3531 size = txq->ift_txd_size[qid];
3532 start = txq->ift_ifdi[qid].idi_vaddr;
3534 if (__predict_false(size == 0))
3536 cur = start + size*cidx;
3537 end = start + size*ntxd;
3538 next = CACHE_PTR_NEXT(cur);
3539 return (next < end ? next : start);
3543 * Pad an mbuf to ensure a minimum ethernet frame size.
3544 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3546 static __noinline int
3547 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3550 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3551 * and ARP message is the smallest common payload I can think of
3553 static char pad[18]; /* just zeros */
3555 struct mbuf *new_head;
3557 if (!M_WRITABLE(*m_head)) {
3558 new_head = m_dup(*m_head, M_NOWAIT);
3559 if (new_head == NULL) {
3561 device_printf(dev, "cannot pad short frame, m_dup() failed");
3562 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3563 DBG_COUNTER_INC(tx_frees);
3570 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3571 n > 0; n -= sizeof(pad))
3572 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3577 device_printf(dev, "cannot pad short frame\n");
3578 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3579 DBG_COUNTER_INC(tx_frees);
3587 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3590 if_shared_ctx_t sctx;
3591 if_softc_ctx_t scctx;
3592 bus_dma_tag_t buf_tag;
3593 bus_dma_segment_t *segs;
3594 struct mbuf *m_head, **ifsd_m;
3597 struct if_pkt_info pi;
3599 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3602 sctx = ctx->ifc_sctx;
3603 scctx = &ctx->ifc_softc_ctx;
3604 segs = txq->ift_segs;
3605 ntxd = txq->ift_size;
3610 * If we're doing TSO the next descriptor to clean may be quite far ahead
3612 cidx = txq->ift_cidx;
3613 pidx = txq->ift_pidx;
3614 if (ctx->ifc_flags & IFC_PREFETCH) {
3615 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3616 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3617 next_txd = calc_next_txd(txq, cidx, 0);
3621 /* prefetch the next cache line of mbuf pointers and flags */
3622 prefetch(&txq->ift_sds.ifsd_m[next]);
3623 prefetch(&txq->ift_sds.ifsd_map[next]);
3624 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3626 map = txq->ift_sds.ifsd_map[pidx];
3627 ifsd_m = txq->ift_sds.ifsd_m;
3629 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3630 buf_tag = txq->ift_tso_buf_tag;
3631 max_segs = scctx->isc_tx_tso_segments_max;
3632 map = txq->ift_sds.ifsd_tso_map[pidx];
3633 MPASS(buf_tag != NULL);
3634 MPASS(max_segs > 0);
3636 buf_tag = txq->ift_buf_tag;
3637 max_segs = scctx->isc_tx_nsegments;
3638 map = txq->ift_sds.ifsd_map[pidx];
3640 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3641 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3642 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3644 DBG_COUNTER_INC(encap_txd_encap_fail);
3651 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3653 pi.ipi_qsidx = txq->ift_id;
3654 pi.ipi_len = m_head->m_pkthdr.len;
3655 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3656 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3658 /* deliberate bitwise OR to make one condition */
3659 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3660 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3661 DBG_COUNTER_INC(encap_txd_encap_fail);
3668 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3671 if (__predict_false(err)) {
3674 /* try collapse once and defrag once */
3676 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3677 /* try defrag if collapsing fails */
3682 txq->ift_mbuf_defrag++;
3683 m_head = m_defrag(*m_headp, M_NOWAIT);
3686 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3687 * failed to map an mbuf that was run through m_defrag
3690 if (__predict_false(m_head == NULL || remap > 1))
3697 txq->ift_no_tx_dma_setup++;
3700 txq->ift_no_tx_dma_setup++;
3702 DBG_COUNTER_INC(tx_frees);
3706 txq->ift_map_failed++;
3707 DBG_COUNTER_INC(encap_load_mbuf_fail);
3708 DBG_COUNTER_INC(encap_txd_encap_fail);
3711 ifsd_m[pidx] = m_head;
3713 * XXX assumes a 1 to 1 relationship between segments and
3714 * descriptors - this does not hold true on all drivers, e.g.
3717 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3718 txq->ift_no_desc_avail++;
3719 bus_dmamap_unload(buf_tag, map);
3720 DBG_COUNTER_INC(encap_txq_avail_fail);
3721 DBG_COUNTER_INC(encap_txd_encap_fail);
3722 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3723 GROUPTASK_ENQUEUE(&txq->ift_task);
3727 * On Intel cards we can greatly reduce the number of TX interrupts
3728 * we see by only setting report status on every Nth descriptor.
3729 * However, this also means that the driver will need to keep track
3730 * of the descriptors that RS was set on to check them for the DD bit.
3732 txq->ift_rs_pending += nsegs + 1;
3733 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3734 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3735 pi.ipi_flags |= IPI_TX_INTR;
3736 txq->ift_rs_pending = 0;
3740 pi.ipi_nsegs = nsegs;
3742 MPASS(pidx >= 0 && pidx < txq->ift_size);
3746 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3747 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3748 DBG_COUNTER_INC(tx_encap);
3749 MPASS(pi.ipi_new_pidx < txq->ift_size);
3751 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3752 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3753 ndesc += txq->ift_size;
3757 * drivers can need as many as
3760 MPASS(ndesc <= pi.ipi_nsegs + 2);
3761 MPASS(pi.ipi_new_pidx != pidx);
3763 txq->ift_in_use += ndesc;
3764 txq->ift_db_pending += ndesc;
3767 * We update the last software descriptor again here because there may
3768 * be a sentinel and/or there may be more mbufs than segments
3770 txq->ift_pidx = pi.ipi_new_pidx;
3771 txq->ift_npending += pi.ipi_ndescs;
3773 *m_headp = m_head = iflib_remove_mbuf(txq);
3775 txq->ift_txd_encap_efbig++;
3784 * err can't possibly be non-zero here, so we don't neet to test it
3785 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3790 txq->ift_mbuf_defrag_failed++;
3791 txq->ift_map_failed++;
3793 DBG_COUNTER_INC(tx_frees);
3795 DBG_COUNTER_INC(encap_txd_encap_fail);
3800 iflib_tx_desc_free(iflib_txq_t txq, int n)
3802 uint32_t qsize, cidx, mask, gen;
3803 struct mbuf *m, **ifsd_m;
3806 cidx = txq->ift_cidx;
3808 qsize = txq->ift_size;
3810 ifsd_m = txq->ift_sds.ifsd_m;
3811 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3815 prefetch(ifsd_m[(cidx + 3) & mask]);
3816 prefetch(ifsd_m[(cidx + 4) & mask]);
3818 if ((m = ifsd_m[cidx]) != NULL) {
3819 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3820 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3821 bus_dmamap_sync(txq->ift_tso_buf_tag,
3822 txq->ift_sds.ifsd_tso_map[cidx],
3823 BUS_DMASYNC_POSTWRITE);
3824 bus_dmamap_unload(txq->ift_tso_buf_tag,
3825 txq->ift_sds.ifsd_tso_map[cidx]);
3827 bus_dmamap_sync(txq->ift_buf_tag,
3828 txq->ift_sds.ifsd_map[cidx],
3829 BUS_DMASYNC_POSTWRITE);
3830 bus_dmamap_unload(txq->ift_buf_tag,
3831 txq->ift_sds.ifsd_map[cidx]);
3833 /* XXX we don't support any drivers that batch packets yet */
3834 MPASS(m->m_nextpkt == NULL);
3836 ifsd_m[cidx] = NULL;
3838 txq->ift_dequeued++;
3840 DBG_COUNTER_INC(tx_frees);
3842 if (__predict_false(++cidx == qsize)) {
3847 txq->ift_cidx = cidx;
3852 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3855 if_ctx_t ctx = txq->ift_ctx;
3857 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3858 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3861 * Need a rate-limiting check so that this isn't called every time
3863 iflib_tx_credits_update(ctx, txq);
3864 reclaim = DESC_RECLAIMABLE(txq);
3866 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3868 if (iflib_verbose_debug) {
3869 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3870 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3876 iflib_tx_desc_free(txq, reclaim);
3877 txq->ift_cleaned += reclaim;
3878 txq->ift_in_use -= reclaim;
3883 static struct mbuf **
3884 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3887 struct mbuf **items;
3890 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3891 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3893 prefetch(items[(cidx + offset) & (size-1)]);
3894 if (remaining > 1) {
3895 prefetch2cachelines(&items[next]);
3896 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3897 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3898 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3900 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3904 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3907 ifmp_ring_check_drainage(txq->ift_br, budget);
3911 iflib_txq_can_drain(struct ifmp_ring *r)
3913 iflib_txq_t txq = r->cookie;
3914 if_ctx_t ctx = txq->ift_ctx;
3916 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3918 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3919 BUS_DMASYNC_POSTREAD);
3920 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3925 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3927 iflib_txq_t txq = r->cookie;
3928 if_ctx_t ctx = txq->ift_ctx;
3929 if_t ifp = ctx->ifc_ifp;
3930 struct mbuf *m, **mp;
3931 int avail, bytes_sent, skipped, count, err, i;
3932 int mcast_sent, pkt_sent, reclaimed;
3933 bool do_prefetch, rang, ring;
3935 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3936 !LINK_ACTIVE(ctx))) {
3937 DBG_COUNTER_INC(txq_drain_notready);
3940 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3941 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending);
3942 avail = IDXDIFF(pidx, cidx, r->size);
3944 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3946 * The driver is unloading so we need to free all pending packets.
3948 DBG_COUNTER_INC(txq_drain_flushing);
3949 for (i = 0; i < avail; i++) {
3950 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3951 m_freem(r->items[(cidx + i) & (r->size-1)]);
3952 r->items[(cidx + i) & (r->size-1)] = NULL;
3957 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3958 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3960 callout_stop(&txq->ift_timer);
3961 CALLOUT_UNLOCK(txq);
3962 DBG_COUNTER_INC(txq_drain_oactive);
3967 * If we've reclaimed any packets this queue cannot be hung.
3970 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3971 skipped = mcast_sent = bytes_sent = pkt_sent = 0;
3972 count = MIN(avail, TX_BATCH_SIZE);
3974 if (iflib_verbose_debug)
3975 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3976 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3978 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3980 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) {
3981 int rem = do_prefetch ? count - i : 0;
3983 mp = _ring_peek_one(r, cidx, i, rem);
3984 MPASS(mp != NULL && *mp != NULL);
3987 * Completion interrupts will use the address of the txq
3988 * as a sentinel to enqueue _something_ in order to acquire
3989 * the lock on the mp_ring (there's no direct lock call).
3990 * We obviously whave to check for these sentinel cases
3993 if (__predict_false(*mp == (struct mbuf *)txq)) {
3997 err = iflib_encap(txq, mp);
3998 if (__predict_false(err)) {
3999 /* no room - bail out */
4003 /* we can't send this packet - skip it */
4008 DBG_COUNTER_INC(tx_sent);
4009 bytes_sent += m->m_pkthdr.len;
4010 mcast_sent += !!(m->m_flags & M_MCAST);
4012 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)))
4014 ETHER_BPF_MTAP(ifp, m);
4015 rang = iflib_txd_db_check(txq, false);
4018 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
4019 ring = rang ? false : (iflib_min_tx_latency | err);
4020 iflib_txd_db_check(txq, ring);
4021 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
4022 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
4024 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
4026 if (iflib_verbose_debug)
4027 printf("consumed=%d\n", skipped + pkt_sent);
4029 return (skipped + pkt_sent);
4033 iflib_txq_drain_always(struct ifmp_ring *r)
4039 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
4047 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
4049 callout_stop(&txq->ift_timer);
4050 CALLOUT_UNLOCK(txq);
4052 avail = IDXDIFF(pidx, cidx, r->size);
4053 for (i = 0; i < avail; i++) {
4054 mp = _ring_peek_one(r, cidx, i, avail - i);
4055 if (__predict_false(*mp == (struct mbuf *)txq))
4058 DBG_COUNTER_INC(tx_frees);
4060 MPASS(ifmp_ring_is_stalled(r) == 0);
4065 iflib_ifmp_purge(iflib_txq_t txq)
4067 struct ifmp_ring *r;
4070 r->drain = iflib_txq_drain_free;
4071 r->can_drain = iflib_txq_drain_always;
4073 ifmp_ring_check_drainage(r, r->size);
4075 r->drain = iflib_txq_drain;
4076 r->can_drain = iflib_txq_can_drain;
4080 _task_fn_tx(void *context)
4082 iflib_txq_t txq = context;
4083 if_ctx_t ctx = txq->ift_ctx;
4084 if_t ifp = ctx->ifc_ifp;
4085 int abdicate = ctx->ifc_sysctl_tx_abdicate;
4087 #ifdef IFLIB_DIAGNOSTICS
4088 txq->ift_cpu_exec_count[curcpu]++;
4090 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4093 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
4094 netmap_tx_irq(ifp, txq->ift_id))
4098 if (if_altq_is_enabled(ifp))
4099 iflib_altq_if_start(ifp);
4101 if (txq->ift_db_pending)
4102 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
4104 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4106 * When abdicating, we always need to check drainage, not just when we don't enqueue
4109 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4113 if (ctx->ifc_flags & IFC_LEGACY)
4114 IFDI_INTR_ENABLE(ctx);
4116 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
4120 _task_fn_rx(void *context)
4122 iflib_rxq_t rxq = context;
4123 if_ctx_t ctx = rxq->ifr_ctx;
4131 #ifdef IFLIB_DIAGNOSTICS
4132 rxq->ifr_cpu_exec_count[curcpu]++;
4134 DBG_COUNTER_INC(task_fn_rxs);
4135 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4138 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
4139 if (nmirq != NM_IRQ_PASS) {
4140 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
4144 budget = ctx->ifc_sysctl_rx_budget;
4146 budget = 16; /* XXX */
4147 more = iflib_rxeof(rxq, budget);
4151 if ((more & IFLIB_RXEOF_MORE) == 0) {
4152 if (ctx->ifc_flags & IFC_LEGACY)
4153 IFDI_INTR_ENABLE(ctx);
4155 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
4156 DBG_COUNTER_INC(rx_intr_enables);
4158 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4161 if (more & IFLIB_RXEOF_MORE)
4162 GROUPTASK_ENQUEUE(&rxq->ifr_task);
4163 else if (more & IFLIB_RXEOF_EMPTY)
4164 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
4168 _task_fn_admin(void *context)
4170 if_ctx_t ctx = context;
4171 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
4174 bool oactive, running, do_reset, do_watchdog, in_detach;
4177 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
4178 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
4179 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
4180 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
4181 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
4182 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
4185 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4191 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4193 callout_stop(&txq->ift_timer);
4194 CALLOUT_UNLOCK(txq);
4196 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ)
4197 IFDI_ADMIN_COMPLETION_HANDLE(ctx);
4199 ctx->ifc_watchdog_events++;
4200 IFDI_WATCHDOG_RESET(ctx);
4202 IFDI_UPDATE_ADMIN_STATUS(ctx);
4203 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4204 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
4205 txq->ift_timer.c_cpu);
4207 IFDI_LINK_INTR_ENABLE(ctx);
4209 iflib_if_init_locked(ctx);
4212 if (LINK_ACTIVE(ctx) == 0)
4214 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
4215 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4219 _task_fn_iov(void *context)
4221 if_ctx_t ctx = context;
4223 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
4224 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4228 IFDI_VFLR_HANDLE(ctx);
4233 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4236 if_int_delay_info_t info;
4239 info = (if_int_delay_info_t)arg1;
4240 ctx = info->iidi_ctx;
4241 info->iidi_req = req;
4242 info->iidi_oidp = oidp;
4244 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
4249 /*********************************************************************
4253 **********************************************************************/
4256 iflib_if_init_locked(if_ctx_t ctx)
4259 iflib_init_locked(ctx);
4263 iflib_if_init(void *arg)
4268 iflib_if_init_locked(ctx);
4273 iflib_if_transmit(if_t ifp, struct mbuf *m)
4275 if_ctx_t ctx = if_getsoftc(ifp);
4280 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
4281 DBG_COUNTER_INC(tx_frees);
4286 MPASS(m->m_nextpkt == NULL);
4287 /* ALTQ-enabled interfaces always use queue 0. */
4289 /* Use driver-supplied queue selection method if it exists */
4290 if (ctx->isc_txq_select_v2) {
4291 struct if_pkt_info pi;
4292 uint64_t early_pullups = 0;
4295 err = iflib_parse_header_partial(&pi, &m, &early_pullups);
4296 if (__predict_false(err != 0)) {
4297 /* Assign pullups for bad pkts to default queue */
4298 ctx->ifc_txqs[0].ift_pullups += early_pullups;
4299 DBG_COUNTER_INC(encap_txd_encap_fail);
4302 /* Let driver make queueing decision */
4303 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi);
4304 ctx->ifc_txqs[qidx].ift_pullups += early_pullups;
4306 /* Backwards compatibility w/ simpler queue select */
4307 else if (ctx->isc_txq_select)
4308 qidx = ctx->isc_txq_select(ctx->ifc_softc, m);
4309 /* If not, use iflib's standard method */
4310 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp))
4311 qidx = QIDX(ctx, m);
4314 txq = &ctx->ifc_txqs[qidx];
4316 #ifdef DRIVER_BACKPRESSURE
4317 if (txq->ift_closed) {
4319 next = m->m_nextpkt;
4320 m->m_nextpkt = NULL;
4322 DBG_COUNTER_INC(tx_frees);
4334 next = next->m_nextpkt;
4335 } while (next != NULL);
4337 if (count > nitems(marr))
4338 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4339 /* XXX check nextpkt */
4341 /* XXX simplify for now */
4342 DBG_COUNTER_INC(tx_frees);
4345 for (next = m, i = 0; next != NULL; i++) {
4347 next = next->m_nextpkt;
4348 mp[i]->m_nextpkt = NULL;
4351 DBG_COUNTER_INC(tx_seen);
4352 abdicate = ctx->ifc_sysctl_tx_abdicate;
4354 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4357 GROUPTASK_ENQUEUE(&txq->ift_task);
4360 GROUPTASK_ENQUEUE(&txq->ift_task);
4361 /* support forthcoming later */
4362 #ifdef DRIVER_BACKPRESSURE
4363 txq->ift_closed = TRUE;
4365 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4367 DBG_COUNTER_INC(tx_frees);
4375 * The overall approach to integrating iflib with ALTQ is to continue to use
4376 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4377 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4378 * is redundant/unnecessary, but doing so minimizes the amount of
4379 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4380 * redundantly queueing to an intermediate mp_ring is swamped by the
4381 * performance limitations inherent in using ALTQ.
4383 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4384 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4385 * given interface. If ALTQ is enabled for an interface, then all
4386 * transmitted packets for that interface will be submitted to the ALTQ
4387 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4388 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4389 * update stats that the iflib machinery handles, and which is sensitve to
4390 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4391 * will be installed as the start routine for use by ALTQ facilities that
4392 * need to trigger queue drains on a scheduled basis.
4396 iflib_altq_if_start(if_t ifp)
4398 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */
4402 IFQ_DEQUEUE_NOLOCK(ifq, m);
4404 iflib_if_transmit(ifp, m);
4405 IFQ_DEQUEUE_NOLOCK(ifq, m);
4411 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4415 if (if_altq_is_enabled(ifp)) {
4416 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */
4418 iflib_altq_if_start(ifp);
4420 err = iflib_if_transmit(ifp, m);
4427 iflib_if_qflush(if_t ifp)
4429 if_ctx_t ctx = if_getsoftc(ifp);
4430 iflib_txq_t txq = ctx->ifc_txqs;
4434 ctx->ifc_flags |= IFC_QFLUSH;
4436 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4437 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4438 iflib_txq_check_drain(txq, 0);
4440 ctx->ifc_flags &= ~IFC_QFLUSH;
4444 * When ALTQ is enabled, this will also take care of purging the
4450 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4451 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4452 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4453 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG)
4456 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4458 if_ctx_t ctx = if_getsoftc(ifp);
4459 struct ifreq *ifr = (struct ifreq *)data;
4460 #if defined(INET) || defined(INET6)
4461 struct ifaddr *ifa = (struct ifaddr *)data;
4463 bool avoid_reset = false;
4464 int err = 0, reinit = 0, bits;
4469 if (ifa->ifa_addr->sa_family == AF_INET)
4473 if (ifa->ifa_addr->sa_family == AF_INET6)
4477 ** Calling init results in link renegotiation,
4478 ** so we avoid doing it when possible.
4481 if_setflagbits(ifp, IFF_UP,0);
4482 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4485 if (!(if_getflags(ifp) & IFF_NOARP))
4486 arp_ifinit(ifp, ifa);
4489 err = ether_ioctl(ifp, command, data);
4493 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4497 bits = if_getdrvflags(ifp);
4498 /* stop the driver and free any clusters before proceeding */
4501 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4503 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4504 ctx->ifc_flags |= IFC_MULTISEG;
4506 ctx->ifc_flags &= ~IFC_MULTISEG;
4508 err = if_setmtu(ifp, ifr->ifr_mtu);
4510 iflib_init_locked(ctx);
4512 if_setdrvflags(ifp, bits);
4518 if (if_getflags(ifp) & IFF_UP) {
4519 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4520 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4521 (IFF_PROMISC | IFF_ALLMULTI)) {
4523 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4528 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4531 ctx->ifc_if_flags = if_getflags(ifp);
4536 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4538 IFDI_INTR_DISABLE(ctx);
4539 IFDI_MULTI_SET(ctx);
4540 IFDI_INTR_ENABLE(ctx);
4546 IFDI_MEDIA_SET(ctx);
4551 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4555 struct ifi2creq i2c;
4557 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4560 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4564 if (i2c.len > sizeof(i2c.data)) {
4569 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4570 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4576 int mask, setmask, oldmask;
4578 oldmask = if_getcapenable(ifp);
4579 mask = ifr->ifr_reqcap ^ oldmask;
4580 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG;
4583 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4585 setmask |= (mask & IFCAP_FLAGS);
4586 setmask |= (mask & IFCAP_WOL);
4589 * If any RX csum has changed, change all the ones that
4590 * are supported by the driver.
4592 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4593 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4594 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4598 * want to ensure that traffic has stopped before we change any of the flags
4602 bits = if_getdrvflags(ifp);
4603 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4606 if_togglecapenable(ifp, setmask);
4607 ctx->ifc_softc_ctx.isc_capenable ^= setmask;
4609 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4610 iflib_init_locked(ctx);
4612 if_setdrvflags(ifp, bits);
4619 case SIOCGPRIVATE_0:
4623 err = IFDI_PRIV_IOCTL(ctx, command, data);
4627 err = ether_ioctl(ifp, command, data);
4636 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4638 if_ctx_t ctx = if_getsoftc(ifp);
4640 return (IFDI_GET_COUNTER(ctx, cnt));
4643 /*********************************************************************
4645 * OTHER FUNCTIONS EXPORTED TO THE STACK
4647 **********************************************************************/
4650 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4652 if_ctx_t ctx = if_getsoftc(ifp);
4654 if ((void *)ctx != arg)
4657 if ((vtag == 0) || (vtag > 4095))
4660 if (iflib_in_detach(ctx))
4664 /* Driver may need all untagged packets to be flushed */
4665 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4667 IFDI_VLAN_REGISTER(ctx, vtag);
4668 /* Re-init to load the changes, if required */
4669 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4670 iflib_init_locked(ctx);
4675 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4677 if_ctx_t ctx = if_getsoftc(ifp);
4679 if ((void *)ctx != arg)
4682 if ((vtag == 0) || (vtag > 4095))
4686 /* Driver may need all tagged packets to be flushed */
4687 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4689 IFDI_VLAN_UNREGISTER(ctx, vtag);
4690 /* Re-init to load the changes, if required */
4691 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4692 iflib_init_locked(ctx);
4697 iflib_led_func(void *arg, int onoff)
4702 IFDI_LED_FUNC(ctx, onoff);
4706 /*********************************************************************
4708 * BUS FUNCTION DEFINITIONS
4710 **********************************************************************/
4713 iflib_device_probe(device_t dev)
4715 const pci_vendor_info_t *ent;
4716 if_shared_ctx_t sctx;
4717 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4718 uint16_t pci_vendor_id;
4720 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4723 pci_vendor_id = pci_get_vendor(dev);
4724 pci_device_id = pci_get_device(dev);
4725 pci_subvendor_id = pci_get_subvendor(dev);
4726 pci_subdevice_id = pci_get_subdevice(dev);
4727 pci_rev_id = pci_get_revid(dev);
4728 if (sctx->isc_parse_devinfo != NULL)
4729 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4731 ent = sctx->isc_vendor_info;
4732 while (ent->pvi_vendor_id != 0) {
4733 if (pci_vendor_id != ent->pvi_vendor_id) {
4737 if ((pci_device_id == ent->pvi_device_id) &&
4738 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4739 (ent->pvi_subvendor_id == 0)) &&
4740 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4741 (ent->pvi_subdevice_id == 0)) &&
4742 ((pci_rev_id == ent->pvi_rev_id) ||
4743 (ent->pvi_rev_id == 0))) {
4744 device_set_desc_copy(dev, ent->pvi_name);
4745 /* this needs to be changed to zero if the bus probing code
4746 * ever stops re-probing on best match because the sctx
4747 * may have its values over written by register calls
4748 * in subsequent probes
4750 return (BUS_PROBE_DEFAULT);
4758 iflib_device_probe_vendor(device_t dev)
4762 probe = iflib_device_probe(dev);
4763 if (probe == BUS_PROBE_DEFAULT)
4764 return (BUS_PROBE_VENDOR);
4770 iflib_reset_qvalues(if_ctx_t ctx)
4772 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4773 if_shared_ctx_t sctx = ctx->ifc_sctx;
4774 device_t dev = ctx->ifc_dev;
4777 if (ctx->ifc_sysctl_ntxqs != 0)
4778 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4779 if (ctx->ifc_sysctl_nrxqs != 0)
4780 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4782 for (i = 0; i < sctx->isc_ntxqs; i++) {
4783 if (ctx->ifc_sysctl_ntxds[i] != 0)
4784 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4786 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4789 for (i = 0; i < sctx->isc_nrxqs; i++) {
4790 if (ctx->ifc_sysctl_nrxds[i] != 0)
4791 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4793 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4796 for (i = 0; i < sctx->isc_nrxqs; i++) {
4797 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4798 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4799 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4800 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4802 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4803 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4804 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4805 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4807 if (!powerof2(scctx->isc_nrxd[i])) {
4808 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4809 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4810 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4814 for (i = 0; i < sctx->isc_ntxqs; i++) {
4815 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4816 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4817 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4818 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4820 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4821 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4822 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4823 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4825 if (!powerof2(scctx->isc_ntxd[i])) {
4826 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4827 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4828 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4834 iflib_add_pfil(if_ctx_t ctx)
4836 struct pfil_head *pfil;
4837 struct pfil_head_args pa;
4841 pa.pa_version = PFIL_VERSION;
4842 pa.pa_flags = PFIL_IN;
4843 pa.pa_type = PFIL_TYPE_ETHERNET;
4844 pa.pa_headname = if_name(ctx->ifc_ifp);
4845 pfil = pfil_head_register(&pa);
4847 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4853 iflib_rem_pfil(if_ctx_t ctx)
4855 struct pfil_head *pfil;
4859 rxq = ctx->ifc_rxqs;
4861 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4864 pfil_head_unregister(pfil);
4869 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from
4870 * cpuid and wrapping as necessary.
4873 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n)
4875 unsigned int first_valid;
4876 unsigned int last_valid;
4878 /* cpuid should always be in the valid set */
4879 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus));
4881 /* valid set should never be empty */
4882 MPASS(!CPU_EMPTY(&ctx->ifc_cpus));
4884 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
4885 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
4886 n = n % CPU_COUNT(&ctx->ifc_cpus);
4890 if (cpuid > last_valid)
4891 cpuid = first_valid;
4892 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus));
4899 #if defined(SMP) && defined(SCHED_ULE)
4900 extern struct cpu_group *cpu_top; /* CPU topology */
4903 find_child_with_core(int cpu, struct cpu_group *grp)
4907 if (grp->cg_children == 0)
4910 MPASS(grp->cg_child);
4911 for (i = 0; i < grp->cg_children; i++) {
4912 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
4921 * Find an L2 neighbor of the given CPU or return -1 if none found. This
4922 * does not distinguish among multiple L2 neighbors if the given CPU has
4923 * more than one (it will always return the same result in that case).
4926 find_l2_neighbor(int cpu)
4928 struct cpu_group *grp;
4936 * Find the smallest CPU group that contains the given core.
4939 while ((i = find_child_with_core(cpu, grp)) != -1) {
4941 * If the smallest group containing the given CPU has less
4942 * than two members, we conclude the given CPU has no
4945 if (grp->cg_child[i].cg_count <= 1)
4947 grp = &grp->cg_child[i];
4950 /* Must share L2. */
4951 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
4955 * Select the first member of the set that isn't the reference
4956 * CPU, which at this point is guaranteed to exist.
4958 for (i = 0; i < CPU_SETSIZE; i++) {
4959 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu)
4963 /* Should never be reached */
4969 find_l2_neighbor(int cpu)
4977 * CPU mapping behaviors
4978 * ---------------------
4979 * 'separate txrx' refers to the separate_txrx sysctl
4980 * 'use logical' refers to the use_logical_cores sysctl
4981 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded
4984 * txrx logical CPUS result
4985 * ---------- --------- ------ ------------------------------------------------
4986 * - - X RX and TX queues mapped to consecutive physical
4987 * cores with RX/TX pairs on same core and excess
4988 * of either following
4989 * - X X RX and TX queues mapped to consecutive cores
4990 * of any type with RX/TX pairs on same core and
4991 * excess of either following
4992 * X - X RX and TX queues mapped to consecutive physical
4993 * cores; all RX then all TX
4994 * X X X RX queues mapped to consecutive physical cores
4995 * first, then TX queues mapped to L2 neighbor of
4996 * the corresponding RX queue if one exists,
4997 * otherwise to consecutive physical cores
4998 * - n/a - RX and TX queues mapped to consecutive cores of
4999 * any type with RX/TX pairs on same core and excess
5000 * of either following
5001 * X n/a - RX and TX queues mapped to consecutive cores of
5002 * any type; all RX then all TX
5005 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid,
5008 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5009 unsigned int core_index;
5011 if (ctx->ifc_sysctl_separate_txrx) {
5013 * When using separate CPUs for TX and RX, the assignment
5014 * will always be of a consecutive CPU out of the set of
5015 * context CPUs, except for the specific case where the
5016 * context CPUs are phsyical cores, the use of logical cores
5017 * has been enabled, the assignment is for TX, the TX qid
5018 * corresponds to an RX qid, and the CPU assigned to the
5019 * corresponding RX queue has an L2 neighbor.
5021 if (ctx->ifc_sysctl_use_logical_cores &&
5022 ctx->ifc_cpus_are_physical_cores &&
5023 is_tx && qid < scctx->isc_nrxqsets) {
5025 unsigned int rx_cpuid;
5027 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid);
5028 l2_neighbor = find_l2_neighbor(rx_cpuid);
5029 if (l2_neighbor != -1) {
5030 return (l2_neighbor);
5033 * ... else fall through to the normal
5034 * consecutive-after-RX assignment scheme.
5036 * Note that we are assuming that all RX queue CPUs
5037 * have an L2 neighbor, or all do not. If a mixed
5038 * scenario is possible, we will have to keep track
5039 * separately of how many queues prior to this one
5040 * were not able to be assigned to an L2 neighbor.
5044 core_index = scctx->isc_nrxqsets + qid;
5051 return (cpuid_advance(ctx, base_cpuid, core_index));
5055 get_ctx_core_offset(if_ctx_t ctx)
5057 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5058 struct cpu_offset *op;
5059 cpuset_t assigned_cpus;
5060 unsigned int cores_consumed;
5061 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset;
5062 unsigned int first_valid;
5063 unsigned int last_valid;
5066 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
5067 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
5069 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) {
5071 * Align the user-chosen base CPU ID to the next valid CPU
5072 * for this device. If the chosen base CPU ID is smaller
5073 * than the first valid CPU or larger than the last valid
5074 * CPU, we assume the user does not know what the valid
5075 * range is for this device and is thinking in terms of a
5076 * zero-based reference frame, and so we shift the given
5077 * value into the valid range (and wrap accordingly) so the
5078 * intent is translated to the proper frame of reference.
5079 * If the base CPU ID is within the valid first/last, but
5080 * does not correspond to a valid CPU, it is advanced to the
5081 * next valid CPU (wrapping if necessary).
5083 if (base_cpuid < first_valid || base_cpuid > last_valid) {
5084 /* shift from zero-based to first_valid-based */
5085 base_cpuid += first_valid;
5086 /* wrap to range [first_valid, last_valid] */
5087 base_cpuid = (base_cpuid - first_valid) %
5088 (last_valid - first_valid + 1);
5090 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) {
5092 * base_cpuid is in [first_valid, last_valid], but
5093 * not a member of the valid set. In this case,
5094 * there will always be a member of the valid set
5095 * with a CPU ID that is greater than base_cpuid,
5096 * and we simply advance to it.
5098 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus))
5101 return (base_cpuid);
5105 * Determine how many cores will be consumed by performing the CPU
5106 * assignments and counting how many of the assigned CPUs correspond
5107 * to CPUs in the set of context CPUs. This is done using the CPU
5108 * ID first_valid as the base CPU ID, as the base CPU must be within
5109 * the set of context CPUs.
5111 * Note not all assigned CPUs will be in the set of context CPUs
5112 * when separate CPUs are being allocated to TX and RX queues,
5113 * assignment to logical cores has been enabled, the set of context
5114 * CPUs contains only physical CPUs, and TX queues are mapped to L2
5115 * neighbors of CPUs that RX queues have been mapped to - in this
5116 * case we do only want to count how many CPUs in the set of context
5117 * CPUs have been consumed, as that determines the next CPU in that
5118 * set to start allocating at for the next device for which
5119 * core_offset is not set.
5121 CPU_ZERO(&assigned_cpus);
5122 for (i = 0; i < scctx->isc_ntxqsets; i++)
5123 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true),
5125 for (i = 0; i < scctx->isc_nrxqsets; i++)
5126 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false),
5128 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus);
5129 cores_consumed = CPU_COUNT(&assigned_cpus);
5131 mtx_lock(&cpu_offset_mtx);
5132 SLIST_FOREACH(op, &cpu_offsets, entries) {
5133 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
5134 base_cpuid = op->next_cpuid;
5135 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid,
5137 MPASS(op->refcount < UINT_MAX);
5142 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) {
5143 base_cpuid = first_valid;
5144 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
5147 device_printf(ctx->ifc_dev,
5148 "allocation for cpu offset failed.\n");
5150 op->next_cpuid = cpuid_advance(ctx, base_cpuid,
5153 CPU_COPY(&ctx->ifc_cpus, &op->set);
5154 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
5157 mtx_unlock(&cpu_offset_mtx);
5159 return (base_cpuid);
5163 unref_ctx_core_offset(if_ctx_t ctx)
5165 struct cpu_offset *op, *top;
5167 mtx_lock(&cpu_offset_mtx);
5168 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
5169 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
5170 MPASS(op->refcount > 0);
5172 if (op->refcount == 0) {
5173 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
5179 mtx_unlock(&cpu_offset_mtx);
5183 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
5187 if_softc_ctx_t scctx;
5188 kobjop_desc_t kobj_desc;
5189 kobj_method_t *kobj_method;
5191 int num_txd, num_rxd;
5193 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
5196 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
5197 device_set_softc(dev, ctx);
5198 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5201 ctx->ifc_sctx = sctx;
5203 ctx->ifc_softc = sc;
5205 if ((err = iflib_register(ctx)) != 0) {
5206 device_printf(dev, "iflib_register failed %d\n", err);
5209 iflib_add_device_sysctl_pre(ctx);
5211 scctx = &ctx->ifc_softc_ctx;
5214 iflib_reset_qvalues(ctx);
5217 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5218 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5221 _iflib_pre_assert(scctx);
5222 ctx->ifc_txrx = *scctx->isc_txrx;
5224 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR));
5226 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
5227 ctx->ifc_mediap = scctx->isc_media;
5230 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5231 MPASS(scctx->isc_tx_csum_flags);
5234 if_setcapabilities(ifp,
5235 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG);
5236 if_setcapenable(ifp,
5237 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG);
5239 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5240 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5241 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5242 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5244 num_txd = iflib_num_tx_descs(ctx);
5245 num_rxd = iflib_num_rx_descs(ctx);
5247 /* XXX change for per-queue sizes */
5248 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5251 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5252 scctx->isc_tx_nsegments = max(1, num_txd /
5253 MAX_SINGLE_PACKET_FRACTION);
5254 if (scctx->isc_tx_tso_segments_max > num_txd /
5255 MAX_SINGLE_PACKET_FRACTION)
5256 scctx->isc_tx_tso_segments_max = max(1,
5257 num_txd / MAX_SINGLE_PACKET_FRACTION);
5259 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5260 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5262 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5265 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5268 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5269 * into account. In the worst case, each of these calls will
5270 * add another mbuf and, thus, the requirement for another DMA
5271 * segment. So for best performance, it doesn't make sense to
5272 * advertize a maximum of TSO segments that typically will
5273 * require defragmentation in iflib_encap().
5275 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5276 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5278 if (scctx->isc_rss_table_size == 0)
5279 scctx->isc_rss_table_size = 64;
5280 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5282 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5283 /* XXX format name */
5284 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5285 NULL, NULL, "admin");
5287 /* Set up cpu set. If it fails, use the set of all CPUs. */
5288 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
5289 device_printf(dev, "Unable to fetch CPU list\n");
5290 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
5291 ctx->ifc_cpus_are_physical_cores = false;
5293 ctx->ifc_cpus_are_physical_cores = true;
5294 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
5297 ** Now set up MSI or MSI-X, should return us the number of supported
5298 ** vectors (will be 1 for a legacy interrupt and MSI).
5300 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
5301 msix = scctx->isc_vectors;
5302 } else if (scctx->isc_msix_bar != 0)
5304 * The simple fact that isc_msix_bar is not 0 does not mean we
5305 * we have a good value there that is known to work.
5307 msix = iflib_msix_init(ctx);
5309 scctx->isc_vectors = 1;
5310 scctx->isc_ntxqsets = 1;
5311 scctx->isc_nrxqsets = 1;
5312 scctx->isc_intr = IFLIB_INTR_LEGACY;
5315 /* Get memory for the station queues */
5316 if ((err = iflib_queues_alloc(ctx))) {
5317 device_printf(dev, "Unable to allocate queue memory\n");
5318 goto fail_intr_free;
5321 if ((err = iflib_qset_structures_setup(ctx)))
5325 * Now that we know how many queues there are, get the core offset.
5327 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
5331 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
5332 * aren't the default NULL implementation.
5334 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
5335 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5337 if (kobj_method == &kobj_desc->deflt) {
5339 "MSI-X requires ifdi_rx_queue_intr_enable method");
5343 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
5344 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5346 if (kobj_method == &kobj_desc->deflt) {
5348 "MSI-X requires ifdi_tx_queue_intr_enable method");
5354 * Assign the MSI-X vectors.
5355 * Note that the default NULL ifdi_msix_intr_assign method will
5358 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
5360 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
5364 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
5366 if (scctx->isc_intr == IFLIB_INTR_MSI) {
5370 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
5371 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
5376 "Cannot use iflib with only 1 MSI-X interrupt!\n");
5382 * It prevents a double-locking panic with iflib_media_status when
5386 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5389 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5390 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5395 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5396 * This must appear after the call to ether_ifattach() because
5397 * ether_ifattach() sets if_hdrlen to the default value.
5399 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5400 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5402 if ((err = iflib_netmap_attach(ctx))) {
5403 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
5408 DEBUGNET_SET(ctx->ifc_ifp, iflib);
5410 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5411 iflib_add_device_sysctl_post(ctx);
5412 iflib_add_pfil(ctx);
5413 ctx->ifc_flags |= IFC_INIT_DONE;
5420 ether_ifdetach(ctx->ifc_ifp);
5422 iflib_tqg_detach(ctx);
5423 iflib_tx_structures_free(ctx);
5424 iflib_rx_structures_free(ctx);
5426 IFDI_QUEUES_FREE(ctx);
5428 iflib_free_intr_mem(ctx);
5432 iflib_deregister(ctx);
5434 device_set_softc(ctx->ifc_dev, NULL);
5435 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5436 free(ctx->ifc_softc, M_IFLIB);
5442 iflib_device_attach(device_t dev)
5445 if_shared_ctx_t sctx;
5447 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5450 pci_enable_busmaster(dev);
5452 return (iflib_device_register(dev, NULL, sctx, &ctx));
5456 iflib_device_deregister(if_ctx_t ctx)
5458 if_t ifp = ctx->ifc_ifp;
5459 device_t dev = ctx->ifc_dev;
5461 /* Make sure VLANS are not using driver */
5462 if (if_vlantrunkinuse(ifp)) {
5463 device_printf(dev, "Vlan in use, detach first\n");
5467 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5468 device_printf(dev, "SR-IOV in use; detach first.\n");
5474 ctx->ifc_flags |= IFC_IN_DETACH;
5477 /* Unregister VLAN handlers before calling iflib_stop() */
5478 iflib_unregister_vlan_handlers(ctx);
5480 iflib_netmap_detach(ifp);
5481 ether_ifdetach(ifp);
5487 iflib_rem_pfil(ctx);
5488 if (ctx->ifc_led_dev != NULL)
5489 led_destroy(ctx->ifc_led_dev);
5491 iflib_tqg_detach(ctx);
5492 iflib_tx_structures_free(ctx);
5493 iflib_rx_structures_free(ctx);
5497 IFDI_QUEUES_FREE(ctx);
5500 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5501 iflib_free_intr_mem(ctx);
5503 bus_generic_detach(dev);
5505 iflib_deregister(ctx);
5507 device_set_softc(ctx->ifc_dev, NULL);
5508 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5509 free(ctx->ifc_softc, M_IFLIB);
5510 unref_ctx_core_offset(ctx);
5516 iflib_tqg_detach(if_ctx_t ctx)
5521 struct taskqgroup *tqg;
5523 /* XXX drain any dependent tasks */
5524 tqg = qgroup_if_io_tqg;
5525 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5526 callout_drain(&txq->ift_timer);
5528 callout_drain(&txq->ift_netmap_timer);
5529 #endif /* DEV_NETMAP */
5530 if (txq->ift_task.gt_uniq != NULL)
5531 taskqgroup_detach(tqg, &txq->ift_task);
5533 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5534 if (rxq->ifr_task.gt_uniq != NULL)
5535 taskqgroup_detach(tqg, &rxq->ifr_task);
5537 tqg = qgroup_if_config_tqg;
5538 if (ctx->ifc_admin_task.gt_uniq != NULL)
5539 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5540 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5541 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5545 iflib_free_intr_mem(if_ctx_t ctx)
5548 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5549 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5551 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5552 pci_release_msi(ctx->ifc_dev);
5554 if (ctx->ifc_msix_mem != NULL) {
5555 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5556 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5557 ctx->ifc_msix_mem = NULL;
5562 iflib_device_detach(device_t dev)
5564 if_ctx_t ctx = device_get_softc(dev);
5566 return (iflib_device_deregister(ctx));
5570 iflib_device_suspend(device_t dev)
5572 if_ctx_t ctx = device_get_softc(dev);
5578 return bus_generic_suspend(dev);
5581 iflib_device_shutdown(device_t dev)
5583 if_ctx_t ctx = device_get_softc(dev);
5589 return bus_generic_suspend(dev);
5593 iflib_device_resume(device_t dev)
5595 if_ctx_t ctx = device_get_softc(dev);
5596 iflib_txq_t txq = ctx->ifc_txqs;
5600 iflib_if_init_locked(ctx);
5602 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5603 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5605 return (bus_generic_resume(dev));
5609 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5612 if_ctx_t ctx = device_get_softc(dev);
5615 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5622 iflib_device_iov_uninit(device_t dev)
5624 if_ctx_t ctx = device_get_softc(dev);
5627 IFDI_IOV_UNINIT(ctx);
5632 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5635 if_ctx_t ctx = device_get_softc(dev);
5638 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5644 /*********************************************************************
5646 * MODULE FUNCTION DEFINITIONS
5648 **********************************************************************/
5651 * - Start a fast taskqueue thread for each core
5652 * - Start a taskqueue for control operations
5655 iflib_module_init(void)
5657 iflib_timer_default = hz / 2;
5662 iflib_module_event_handler(module_t mod, int what, void *arg)
5668 if ((err = iflib_module_init()) != 0)
5674 return (EOPNOTSUPP);
5680 /*********************************************************************
5682 * PUBLIC FUNCTION DEFINITIONS
5683 * ordered as in iflib.h
5685 **********************************************************************/
5688 _iflib_assert(if_shared_ctx_t sctx)
5692 MPASS(sctx->isc_tx_maxsize);
5693 MPASS(sctx->isc_tx_maxsegsize);
5695 MPASS(sctx->isc_rx_maxsize);
5696 MPASS(sctx->isc_rx_nsegments);
5697 MPASS(sctx->isc_rx_maxsegsize);
5699 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5700 for (i = 0; i < sctx->isc_nrxqs; i++) {
5701 MPASS(sctx->isc_nrxd_min[i]);
5702 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5703 MPASS(sctx->isc_nrxd_max[i]);
5704 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5705 MPASS(sctx->isc_nrxd_default[i]);
5706 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5709 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5710 for (i = 0; i < sctx->isc_ntxqs; i++) {
5711 MPASS(sctx->isc_ntxd_min[i]);
5712 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5713 MPASS(sctx->isc_ntxd_max[i]);
5714 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5715 MPASS(sctx->isc_ntxd_default[i]);
5716 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5721 _iflib_pre_assert(if_softc_ctx_t scctx)
5724 MPASS(scctx->isc_txrx->ift_txd_encap);
5725 MPASS(scctx->isc_txrx->ift_txd_flush);
5726 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5727 MPASS(scctx->isc_txrx->ift_rxd_available);
5728 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5729 MPASS(scctx->isc_txrx->ift_rxd_refill);
5730 MPASS(scctx->isc_txrx->ift_rxd_flush);
5734 iflib_register(if_ctx_t ctx)
5736 if_shared_ctx_t sctx = ctx->ifc_sctx;
5737 driver_t *driver = sctx->isc_driver;
5738 device_t dev = ctx->ifc_dev;
5741 _iflib_assert(sctx);
5744 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5745 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5747 device_printf(dev, "can not allocate ifnet structure\n");
5752 * Initialize our context's device specific methods
5754 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5755 kobj_class_compile((kobj_class_t) driver);
5757 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5758 if_setsoftc(ifp, ctx);
5759 if_setdev(ifp, dev);
5760 if_setinitfn(ifp, iflib_if_init);
5761 if_setioctlfn(ifp, iflib_if_ioctl);
5763 if_setstartfn(ifp, iflib_altq_if_start);
5764 if_settransmitfn(ifp, iflib_altq_if_transmit);
5765 if_setsendqready(ifp);
5767 if_settransmitfn(ifp, iflib_if_transmit);
5769 if_setqflushfn(ifp, iflib_if_qflush);
5770 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5771 ctx->ifc_vlan_attach_event =
5772 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5773 EVENTHANDLER_PRI_FIRST);
5774 ctx->ifc_vlan_detach_event =
5775 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5776 EVENTHANDLER_PRI_FIRST);
5778 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5779 ctx->ifc_mediap = &ctx->ifc_media;
5780 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5781 iflib_media_change, iflib_media_status);
5787 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5789 /* Unregister VLAN events */
5790 if (ctx->ifc_vlan_attach_event != NULL) {
5791 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5792 ctx->ifc_vlan_attach_event = NULL;
5794 if (ctx->ifc_vlan_detach_event != NULL) {
5795 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5796 ctx->ifc_vlan_detach_event = NULL;
5802 iflib_deregister(if_ctx_t ctx)
5804 if_t ifp = ctx->ifc_ifp;
5806 /* Remove all media */
5807 ifmedia_removeall(&ctx->ifc_media);
5809 /* Ensure that VLAN event handlers are unregistered */
5810 iflib_unregister_vlan_handlers(ctx);
5812 /* Release kobject reference */
5813 kobj_delete((kobj_t) ctx, NULL);
5815 /* Free the ifnet structure */
5818 STATE_LOCK_DESTROY(ctx);
5820 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5821 CTX_LOCK_DESTROY(ctx);
5825 iflib_queues_alloc(if_ctx_t ctx)
5827 if_shared_ctx_t sctx = ctx->ifc_sctx;
5828 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5829 device_t dev = ctx->ifc_dev;
5830 int nrxqsets = scctx->isc_nrxqsets;
5831 int ntxqsets = scctx->isc_ntxqsets;
5834 iflib_fl_t fl = NULL;
5835 int i, j, cpu, err, txconf, rxconf;
5836 iflib_dma_info_t ifdip;
5837 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5838 uint32_t *txqsizes = scctx->isc_txqsizes;
5839 uint8_t nrxqs = sctx->isc_nrxqs;
5840 uint8_t ntxqs = sctx->isc_ntxqs;
5841 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5842 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0);
5846 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5847 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5848 KASSERT(nrxqs >= fl_offset + nfree_lists,
5849 ("there must be at least a rxq for each free list"));
5851 /* Allocate the TX ring struct memory */
5852 if (!(ctx->ifc_txqs =
5853 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5854 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5855 device_printf(dev, "Unable to allocate TX ring memory\n");
5860 /* Now allocate the RX */
5861 if (!(ctx->ifc_rxqs =
5862 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5863 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5864 device_printf(dev, "Unable to allocate RX ring memory\n");
5869 txq = ctx->ifc_txqs;
5870 rxq = ctx->ifc_rxqs;
5873 * XXX handle allocation failure
5875 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5876 /* Set up some basics */
5878 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5879 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5881 "Unable to allocate TX DMA info memory\n");
5885 txq->ift_ifdi = ifdip;
5886 for (j = 0; j < ntxqs; j++, ifdip++) {
5887 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5889 "Unable to allocate TX descriptors\n");
5893 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5894 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5898 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5899 txq->ift_br_offset = 1;
5901 txq->ift_br_offset = 0;
5904 if (iflib_txsd_alloc(txq)) {
5905 device_printf(dev, "Critical Failure setting up TX buffers\n");
5910 /* Initialize the TX lock */
5911 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5912 device_get_nameunit(dev), txq->ift_id);
5913 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5914 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5915 txq->ift_timer.c_cpu = cpu;
5917 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0);
5918 txq->ift_netmap_timer.c_cpu = cpu;
5919 #endif /* DEV_NETMAP */
5921 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5922 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5924 /* XXX free any allocated rings */
5925 device_printf(dev, "Unable to allocate buf_ring\n");
5930 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5931 /* Set up some basics */
5932 callout_init(&rxq->ifr_watchdog, 1);
5934 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5935 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5937 "Unable to allocate RX DMA info memory\n");
5942 rxq->ifr_ifdi = ifdip;
5943 /* XXX this needs to be changed if #rx queues != #tx queues */
5944 rxq->ifr_ntxqirq = 1;
5945 rxq->ifr_txqid[0] = i;
5946 for (j = 0; j < nrxqs; j++, ifdip++) {
5947 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5949 "Unable to allocate RX descriptors\n");
5953 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5957 rxq->ifr_fl_offset = fl_offset;
5958 rxq->ifr_nfl = nfree_lists;
5960 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5961 device_printf(dev, "Unable to allocate free list memory\n");
5966 for (j = 0; j < nfree_lists; j++) {
5967 fl[j].ifl_rxq = rxq;
5969 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5970 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5972 /* Allocate receive buffers for the ring */
5973 if (iflib_rxsd_alloc(rxq)) {
5975 "Critical Failure setting up receive buffers\n");
5980 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5981 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5986 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5987 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5988 for (i = 0; i < ntxqsets; i++) {
5989 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5991 for (j = 0; j < ntxqs; j++, di++) {
5992 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5993 paddrs[i*ntxqs + j] = di->idi_paddr;
5996 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5997 device_printf(ctx->ifc_dev,
5998 "Unable to allocate device TX queue\n");
5999 iflib_tx_structures_free(ctx);
6000 free(vaddrs, M_IFLIB);
6001 free(paddrs, M_IFLIB);
6004 free(vaddrs, M_IFLIB);
6005 free(paddrs, M_IFLIB);
6008 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
6009 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
6010 for (i = 0; i < nrxqsets; i++) {
6011 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
6013 for (j = 0; j < nrxqs; j++, di++) {
6014 vaddrs[i*nrxqs + j] = di->idi_vaddr;
6015 paddrs[i*nrxqs + j] = di->idi_paddr;
6018 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
6019 device_printf(ctx->ifc_dev,
6020 "Unable to allocate device RX queue\n");
6021 iflib_tx_structures_free(ctx);
6022 free(vaddrs, M_IFLIB);
6023 free(paddrs, M_IFLIB);
6026 free(vaddrs, M_IFLIB);
6027 free(paddrs, M_IFLIB);
6031 /* XXX handle allocation failure changes */
6035 if (ctx->ifc_rxqs != NULL)
6036 free(ctx->ifc_rxqs, M_IFLIB);
6037 ctx->ifc_rxqs = NULL;
6038 if (ctx->ifc_txqs != NULL)
6039 free(ctx->ifc_txqs, M_IFLIB);
6040 ctx->ifc_txqs = NULL;
6046 iflib_tx_structures_setup(if_ctx_t ctx)
6048 iflib_txq_t txq = ctx->ifc_txqs;
6051 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
6052 iflib_txq_setup(txq);
6058 iflib_tx_structures_free(if_ctx_t ctx)
6060 iflib_txq_t txq = ctx->ifc_txqs;
6061 if_shared_ctx_t sctx = ctx->ifc_sctx;
6064 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
6065 for (j = 0; j < sctx->isc_ntxqs; j++)
6066 iflib_dma_free(&txq->ift_ifdi[j]);
6067 iflib_txq_destroy(txq);
6069 free(ctx->ifc_txqs, M_IFLIB);
6070 ctx->ifc_txqs = NULL;
6073 /*********************************************************************
6075 * Initialize all receive rings.
6077 **********************************************************************/
6079 iflib_rx_structures_setup(if_ctx_t ctx)
6081 iflib_rxq_t rxq = ctx->ifc_rxqs;
6083 #if defined(INET6) || defined(INET)
6087 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
6088 #if defined(INET6) || defined(INET)
6089 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
6090 TCP_LRO_ENTRIES, min(1024,
6091 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
6093 device_printf(ctx->ifc_dev,
6094 "LRO Initialization failed!\n");
6098 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
6101 #if defined(INET6) || defined(INET)
6104 * Free LRO resources allocated so far, we will only handle
6105 * the rings that completed, the failing case will have
6106 * cleaned up for itself. 'q' failed, so its the terminus.
6108 rxq = ctx->ifc_rxqs;
6109 for (i = 0; i < q; ++i, rxq++) {
6110 tcp_lro_free(&rxq->ifr_lc);
6116 /*********************************************************************
6118 * Free all receive rings.
6120 **********************************************************************/
6122 iflib_rx_structures_free(if_ctx_t ctx)
6124 iflib_rxq_t rxq = ctx->ifc_rxqs;
6125 if_shared_ctx_t sctx = ctx->ifc_sctx;
6128 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
6129 for (j = 0; j < sctx->isc_nrxqs; j++)
6130 iflib_dma_free(&rxq->ifr_ifdi[j]);
6131 iflib_rx_sds_free(rxq);
6132 #if defined(INET6) || defined(INET)
6133 tcp_lro_free(&rxq->ifr_lc);
6136 free(ctx->ifc_rxqs, M_IFLIB);
6137 ctx->ifc_rxqs = NULL;
6141 iflib_qset_structures_setup(if_ctx_t ctx)
6146 * It is expected that the caller takes care of freeing queues if this
6149 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
6150 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
6154 if ((err = iflib_rx_structures_setup(ctx)) != 0)
6155 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
6161 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
6162 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
6165 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
6168 /* Just to avoid copy/paste */
6170 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6171 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
6175 unsigned int base_cpuid, cpuid;
6179 base_cpuid = ctx->ifc_sysctl_core_offset;
6180 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX);
6181 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev,
6182 irq ? irq->ii_res : NULL, name);
6184 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
6188 if (cpuid > ctx->ifc_cpuid_highest)
6189 ctx->ifc_cpuid_highest = cpuid;
6195 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6196 iflib_intr_type_t type, driver_filter_t *filter,
6197 void *filter_arg, int qid, const char *name)
6200 struct grouptask *gtask;
6201 struct taskqgroup *tqg;
6202 iflib_filter_info_t info;
6205 driver_filter_t *intr_fast;
6208 info = &ctx->ifc_filter_info;
6212 /* XXX merge tx/rx for netmap? */
6214 q = &ctx->ifc_txqs[qid];
6215 info = &ctx->ifc_txqs[qid].ift_filter_info;
6216 gtask = &ctx->ifc_txqs[qid].ift_task;
6217 tqg = qgroup_if_io_tqg;
6219 intr_fast = iflib_fast_intr;
6220 GROUPTASK_INIT(gtask, 0, fn, q);
6221 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6224 q = &ctx->ifc_rxqs[qid];
6225 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6226 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6227 tqg = qgroup_if_io_tqg;
6229 intr_fast = iflib_fast_intr;
6230 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6232 case IFLIB_INTR_RXTX:
6233 q = &ctx->ifc_rxqs[qid];
6234 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6235 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6236 tqg = qgroup_if_io_tqg;
6238 intr_fast = iflib_fast_intr_rxtx;
6239 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6241 case IFLIB_INTR_ADMIN:
6244 info = &ctx->ifc_filter_info;
6245 gtask = &ctx->ifc_admin_task;
6246 tqg = qgroup_if_config_tqg;
6247 fn = _task_fn_admin;
6248 intr_fast = iflib_fast_intr_ctx;
6251 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6256 info->ifi_filter = filter;
6257 info->ifi_filter_arg = filter_arg;
6258 info->ifi_task = gtask;
6262 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6264 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6267 if (type == IFLIB_INTR_ADMIN)
6271 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q,
6276 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6283 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6284 void *arg, int qid, const char *name)
6287 struct grouptask *gtask;
6288 struct taskqgroup *tqg;
6295 q = &ctx->ifc_txqs[qid];
6296 gtask = &ctx->ifc_txqs[qid].ift_task;
6297 tqg = qgroup_if_io_tqg;
6299 GROUPTASK_INIT(gtask, 0, fn, q);
6302 q = &ctx->ifc_rxqs[qid];
6303 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6304 tqg = qgroup_if_io_tqg;
6306 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6308 case IFLIB_INTR_IOV:
6310 gtask = &ctx->ifc_vflr_task;
6311 tqg = qgroup_if_config_tqg;
6313 GROUPTASK_INIT(gtask, 0, fn, q);
6316 panic("unknown net intr type");
6318 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name);
6321 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL,
6327 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6331 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6334 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6335 rman_get_rid(irq->ii_res), irq->ii_res);
6339 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6341 iflib_txq_t txq = ctx->ifc_txqs;
6342 iflib_rxq_t rxq = ctx->ifc_rxqs;
6343 if_irq_t irq = &ctx->ifc_legacy_irq;
6344 iflib_filter_info_t info;
6346 struct grouptask *gtask;
6347 struct resource *res;
6348 struct taskqgroup *tqg;
6353 q = &ctx->ifc_rxqs[0];
6354 info = &rxq[0].ifr_filter_info;
6355 gtask = &rxq[0].ifr_task;
6356 tqg = qgroup_if_io_tqg;
6358 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6360 ctx->ifc_flags |= IFC_LEGACY;
6361 info->ifi_filter = filter;
6362 info->ifi_filter_arg = filter_arg;
6363 info->ifi_task = gtask;
6364 info->ifi_ctx = rx_only ? ctx : q;
6367 /* We allocate a single interrupt resource */
6368 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6369 iflib_fast_intr_rxtx, NULL, info, name);
6372 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6374 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6376 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6377 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6383 iflib_led_create(if_ctx_t ctx)
6386 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6387 device_get_nameunit(ctx->ifc_dev));
6391 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6394 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6398 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6401 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6405 iflib_admin_intr_deferred(if_ctx_t ctx)
6408 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6409 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6413 iflib_iov_intr_deferred(if_ctx_t ctx)
6416 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6420 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6423 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6428 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6432 GROUPTASK_INIT(gtask, 0, fn, ctx);
6433 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6438 iflib_config_gtask_deinit(struct grouptask *gtask)
6441 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6445 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6447 if_t ifp = ctx->ifc_ifp;
6448 iflib_txq_t txq = ctx->ifc_txqs;
6450 if_setbaudrate(ifp, baudrate);
6451 if (baudrate >= IF_Gbps(10)) {
6453 ctx->ifc_flags |= IFC_PREFETCH;
6456 /* If link down, disable watchdog */
6457 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6458 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6459 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6461 ctx->ifc_link_state = link_state;
6462 if_link_state_change(ifp, link_state);
6466 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6470 int credits_pre = txq->ift_cidx_processed;
6473 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6474 BUS_DMASYNC_POSTREAD);
6475 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6478 txq->ift_processed += credits;
6479 txq->ift_cidx_processed += credits;
6481 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6482 if (txq->ift_cidx_processed >= txq->ift_size)
6483 txq->ift_cidx_processed -= txq->ift_size;
6488 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6493 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6494 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6495 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6496 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6501 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6502 const char *description, if_int_delay_info_t info,
6503 int offset, int value)
6505 info->iidi_ctx = ctx;
6506 info->iidi_offset = offset;
6507 info->iidi_value = value;
6508 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6509 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6510 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6511 info, 0, iflib_sysctl_int_delay, "I", description);
6515 iflib_ctx_lock_get(if_ctx_t ctx)
6518 return (&ctx->ifc_ctx_sx);
6522 iflib_msix_init(if_ctx_t ctx)
6524 device_t dev = ctx->ifc_dev;
6525 if_shared_ctx_t sctx = ctx->ifc_sctx;
6526 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6527 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6528 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6530 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6531 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6534 device_printf(dev, "msix_init qsets capped at %d\n",
6535 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6537 /* Override by tuneable */
6538 if (scctx->isc_disable_msix)
6541 /* First try MSI-X */
6542 if ((msgs = pci_msix_count(dev)) == 0) {
6544 device_printf(dev, "MSI-X not supported or disabled\n");
6548 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6550 * bar == -1 => "trust me I know what I'm doing"
6551 * Some drivers are for hardware that is so shoddily
6552 * documented that no one knows which bars are which
6553 * so the developer has to map all bars. This hack
6554 * allows shoddy garbage to use MSI-X in this framework.
6557 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6558 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6559 if (ctx->ifc_msix_mem == NULL) {
6560 device_printf(dev, "Unable to map MSI-X table\n");
6565 admincnt = sctx->isc_admin_intrcnt;
6567 /* use only 1 qset in debug mode */
6568 queuemsgs = min(msgs - admincnt, 1);
6570 queuemsgs = msgs - admincnt;
6573 queues = imin(queuemsgs, rss_getnumbuckets());
6577 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6580 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6581 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6583 /* If we're doing RSS, clamp at the number of RSS buckets */
6584 if (queues > rss_getnumbuckets())
6585 queues = rss_getnumbuckets();
6587 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6588 rx_queues = iflib_num_rx_queues;
6592 if (rx_queues > scctx->isc_nrxqsets)
6593 rx_queues = scctx->isc_nrxqsets;
6596 * We want this to be all logical CPUs by default
6598 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6599 tx_queues = iflib_num_tx_queues;
6601 tx_queues = mp_ncpus;
6603 if (tx_queues > scctx->isc_ntxqsets)
6604 tx_queues = scctx->isc_ntxqsets;
6606 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6608 if (tx_queues != rx_queues)
6610 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6611 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6613 tx_queues = min(rx_queues, tx_queues);
6614 rx_queues = min(rx_queues, tx_queues);
6617 vectors = rx_queues + admincnt;
6618 if (msgs < vectors) {
6620 "insufficient number of MSI-X vectors "
6621 "(supported %d, need %d)\n", msgs, vectors);
6625 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6628 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6629 if (vectors != msgs) {
6631 "Unable to allocate sufficient MSI-X vectors "
6632 "(got %d, need %d)\n", vectors, msgs);
6633 pci_release_msi(dev);
6635 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6637 ctx->ifc_msix_mem = NULL;
6641 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6643 scctx->isc_vectors = vectors;
6644 scctx->isc_nrxqsets = rx_queues;
6645 scctx->isc_ntxqsets = tx_queues;
6646 scctx->isc_intr = IFLIB_INTR_MSIX;
6651 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6654 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6656 ctx->ifc_msix_mem = NULL;
6661 vectors = pci_msi_count(dev);
6662 scctx->isc_nrxqsets = 1;
6663 scctx->isc_ntxqsets = 1;
6664 scctx->isc_vectors = vectors;
6665 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6666 device_printf(dev,"Using an MSI interrupt\n");
6667 scctx->isc_intr = IFLIB_INTR_MSI;
6669 scctx->isc_vectors = 1;
6670 device_printf(dev,"Using a Legacy interrupt\n");
6671 scctx->isc_intr = IFLIB_INTR_LEGACY;
6677 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6680 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6683 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6685 const char *ring_state = "UNKNOWN";
6688 rc = sysctl_wire_old_buffer(req, 0);
6692 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6697 ring_state = ring_states[state[3]];
6699 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6700 state[0], state[1], state[2], ring_state);
6701 rc = sbuf_finish(sb);
6706 enum iflib_ndesc_handler {
6712 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6714 if_ctx_t ctx = (void *)arg1;
6715 enum iflib_ndesc_handler type = arg2;
6716 char buf[256] = {0};
6723 case IFLIB_NTXD_HANDLER:
6724 ndesc = ctx->ifc_sysctl_ntxds;
6726 nqs = ctx->ifc_sctx->isc_ntxqs;
6728 case IFLIB_NRXD_HANDLER:
6729 ndesc = ctx->ifc_sysctl_nrxds;
6731 nqs = ctx->ifc_sctx->isc_nrxqs;
6734 printf("%s: unhandled type\n", __func__);
6740 for (i=0; i<8; i++) {
6745 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6748 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6749 if (rc || req->newptr == NULL)
6752 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6753 i++, p = strsep(&next, " ,")) {
6754 ndesc[i] = strtoul(p, NULL, 10);
6760 #define NAME_BUFLEN 32
6762 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6764 device_t dev = iflib_get_dev(ctx);
6765 struct sysctl_oid_list *child, *oid_list;
6766 struct sysctl_ctx_list *ctx_list;
6767 struct sysctl_oid *node;
6769 ctx_list = device_get_sysctl_ctx(dev);
6770 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6771 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child,
6772 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
6774 oid_list = SYSCTL_CHILDREN(node);
6776 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6777 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version");
6779 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6780 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6781 "# of txqs to use, 0 => use default #");
6782 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6783 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6784 "# of rxqs to use, 0 => use default #");
6785 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6786 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6787 "permit #txq != #rxq");
6788 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6789 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6790 "disable MSI-X (default 0)");
6791 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6792 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget");
6793 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6794 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6795 "cause TX to abdicate instead of running to completion");
6796 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6797 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6798 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6799 "offset to start using cores at");
6800 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6801 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6802 "use separate cores for TX and RX");
6803 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores",
6804 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0,
6805 "try to make use of logical cores for TX and RX");
6807 /* XXX change for per-queue sizes */
6808 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6809 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6810 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6811 "list of # of TX descriptors to use, 0 = use default #");
6812 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6813 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6814 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6815 "list of # of RX descriptors to use, 0 = use default #");
6819 iflib_add_device_sysctl_post(if_ctx_t ctx)
6821 if_shared_ctx_t sctx = ctx->ifc_sctx;
6822 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6823 device_t dev = iflib_get_dev(ctx);
6824 struct sysctl_oid_list *child;
6825 struct sysctl_ctx_list *ctx_list;
6830 char namebuf[NAME_BUFLEN];
6832 struct sysctl_oid *queue_node, *fl_node, *node;
6833 struct sysctl_oid_list *queue_list, *fl_list;
6834 ctx_list = device_get_sysctl_ctx(dev);
6836 node = ctx->ifc_sysctl_node;
6837 child = SYSCTL_CHILDREN(node);
6839 if (scctx->isc_ntxqsets > 100)
6841 else if (scctx->isc_ntxqsets > 10)
6845 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6846 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6847 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6848 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6849 queue_list = SYSCTL_CHILDREN(queue_node);
6850 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
6851 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0,
6852 "cpu this queue is bound to");
6854 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6855 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed");
6856 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6857 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued");
6859 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6860 CTLFLAG_RD, &txq->ift_mbuf_defrag,
6861 "# of times m_defrag was called");
6862 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6863 CTLFLAG_RD, &txq->ift_pullups,
6864 "# of times m_pullup was called");
6865 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6866 "mbuf_defrag_failed", CTLFLAG_RD,
6867 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6868 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6869 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail,
6870 "# of times no descriptors were available");
6871 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6872 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed,
6873 "# of times DMA map failed");
6874 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6875 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig,
6876 "# of times txd_encap returned EFBIG");
6877 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6878 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup,
6879 "# of times map failed for other than EFBIG");
6880 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6881 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index");
6882 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6883 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index");
6884 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO,
6885 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed,
6886 1, "Consumer Index seen by credit update");
6887 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6888 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use");
6889 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6890 "txq_processed", CTLFLAG_RD, &txq->ift_processed,
6891 "descriptors procesed for clean");
6892 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6893 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned");
6894 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6895 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6896 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6897 mp_ring_state_handler, "A", "soft ring state");
6898 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6899 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues,
6900 "# of enqueues to the mp_ring for this queue");
6901 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6902 "r_drops", CTLFLAG_RD, &txq->ift_br->drops,
6903 "# of drops in the mp_ring for this queue");
6904 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6905 "r_starts", CTLFLAG_RD, &txq->ift_br->starts,
6906 "# of normal consumer starts in mp_ring for this queue");
6907 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6908 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls,
6909 "# of consumer stalls in the mp_ring for this queue");
6910 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6911 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts,
6912 "# of consumer restarts in the mp_ring for this queue");
6913 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6914 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications,
6915 "# of consumer abdications in the mp_ring for this queue");
6918 if (scctx->isc_nrxqsets > 100)
6920 else if (scctx->isc_nrxqsets > 10)
6924 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6925 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6926 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6927 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6928 queue_list = SYSCTL_CHILDREN(queue_node);
6929 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
6930 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0,
6931 "cpu this queue is bound to");
6932 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6933 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO,
6934 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1,
6938 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6939 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6940 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list,
6941 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE,
6942 NULL, "freelist Name");
6943 fl_list = SYSCTL_CHILDREN(fl_node);
6944 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6945 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index");
6946 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6947 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index");
6948 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6949 CTLFLAG_RD, &fl->ifl_credits, 1,
6950 "credits available");
6951 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6952 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size");
6954 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
6955 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued,
6957 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
6958 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued,
6960 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
6961 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued,
6962 "clusters allocated");
6963 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
6964 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued,
6973 iflib_request_reset(if_ctx_t ctx)
6977 ctx->ifc_flags |= IFC_DO_RESET;
6981 #ifndef __NO_STRICT_ALIGNMENT
6982 static struct mbuf *
6983 iflib_fixup_rx(struct mbuf *m)
6987 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6988 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6989 m->m_data += ETHER_HDR_LEN;
6992 MGETHDR(n, M_NOWAIT, MT_DATA);
6997 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6998 m->m_data += ETHER_HDR_LEN;
6999 m->m_len -= ETHER_HDR_LEN;
7000 n->m_len = ETHER_HDR_LEN;
7001 M_MOVE_PKTHDR(n, m);
7010 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
7014 ctx = if_getsoftc(ifp);
7016 *nrxr = NRXQSETS(ctx);
7017 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
7018 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
7023 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
7026 if_softc_ctx_t scctx;
7031 ctx = if_getsoftc(ifp);
7032 scctx = &ctx->ifc_softc_ctx;
7035 case DEBUGNET_START:
7036 for (i = 0; i < scctx->isc_nrxqsets; i++) {
7037 rxq = &ctx->ifc_rxqs[i];
7038 for (j = 0; j < rxq->ifr_nfl; j++) {
7040 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
7043 iflib_no_tx_batch = 1;
7051 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
7057 ctx = if_getsoftc(ifp);
7058 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7062 txq = &ctx->ifc_txqs[0];
7063 error = iflib_encap(txq, &m);
7065 (void)iflib_txd_db_check(txq, true);
7070 iflib_debugnet_poll(if_t ifp, int count)
7072 struct epoch_tracker et;
7074 if_softc_ctx_t scctx;
7078 ctx = if_getsoftc(ifp);
7079 scctx = &ctx->ifc_softc_ctx;
7081 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7085 txq = &ctx->ifc_txqs[0];
7086 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
7088 NET_EPOCH_ENTER(et);
7089 for (i = 0; i < scctx->isc_nrxqsets; i++)
7090 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
7094 #endif /* DEBUGNET */