contrib/llvm-project/llvm/lib/Target/X86/X86SchedSkylakeServer.td

   1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Skylake Server to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def SkylakeServerModel : SchedMachineModel {
  15   // All x86 instructions are modeled as a single micro-op, and SKylake can
  16   // decode 6 instructions per cycle.
  17   let IssueWidth = 6;
  18   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  19   let LoadLatency = 5;
  20   let MispredictPenalty = 14;
  21
  22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  23   let LoopMicroOpBufferSize = 50;
  24
  25   // This flag is set to allow the scheduler to assign a default model to
  26   // unrecognized opcodes.
  27   let CompleteModel = 0;
  28 }
  29
  30 let SchedModel = SkylakeServerModel in {
  31
  32 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
  33
  34 // Ports 0, 1, 5, and 6 handle all computation.
  35 // Port 4 gets the data half of stores. Store data can be available later than
  36 // the store address, but since we don't model the latency of stores, we can
  37 // ignore that.
  38 // Ports 2 and 3 are identical. They handle loads and the address half of
  39 // stores. Port 7 can handle address calculations.
  40 def SKXPort0 : ProcResource<1>;
  41 def SKXPort1 : ProcResource<1>;
  42 def SKXPort2 : ProcResource<1>;
  43 def SKXPort3 : ProcResource<1>;
  44 def SKXPort4 : ProcResource<1>;
  45 def SKXPort5 : ProcResource<1>;
  46 def SKXPort6 : ProcResource<1>;
  47 def SKXPort7 : ProcResource<1>;
  48
  49 // Many micro-ops are capable of issuing on multiple ports.
  50 def SKXPort01  : ProcResGroup<[SKXPort0, SKXPort1]>;
  51 def SKXPort23  : ProcResGroup<[SKXPort2, SKXPort3]>;
  52 def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;
  53 def SKXPort04  : ProcResGroup<[SKXPort0, SKXPort4]>;
  54 def SKXPort05  : ProcResGroup<[SKXPort0, SKXPort5]>;
  55 def SKXPort06  : ProcResGroup<[SKXPort0, SKXPort6]>;
  56 def SKXPort15  : ProcResGroup<[SKXPort1, SKXPort5]>;
  57 def SKXPort16  : ProcResGroup<[SKXPort1, SKXPort6]>;
  58 def SKXPort56  : ProcResGroup<[SKXPort5, SKXPort6]>;
  59 def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
  60 def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
  61 def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
  62
  63 def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
  64 // FP division and sqrt on port 0.
  65 def SKXFPDivider : ProcResource<1>;
  66
  67 // 60 Entry Unified Scheduler
  68 def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
  69                               SKXPort5, SKXPort6, SKXPort7]> {
  70   let BufferSize=60;
  71 }
  72
  73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  74 // cycles after the memory operand.
  75 def : ReadAdvance<ReadAfterLd, 5>;
  76
  77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
  78 // until 5/6/7 cycles after the memory operand.
  79 def : ReadAdvance<ReadAfterVecLd, 5>;
  80 def : ReadAdvance<ReadAfterVecXLd, 6>;
  81 def : ReadAdvance<ReadAfterVecYLd, 7>;
  82
  83 def : ReadAdvance<ReadInt2Fpu, 0>;
  84
  85 // Many SchedWrites are defined in pairs with and without a folded load.
  86 // Instructions with folded loads are usually micro-fused, so they only appear
  87 // as two micro-ops when queued in the reservation station.
  88 // This multiclass defines the resource usage for variants with and without
  89 // folded loads.
  90 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
  91                           list<ProcResourceKind> ExePorts,
  92                           int Lat, list<int> Res = [1], int UOps = 1,
  93                           int LoadLat = 5> {
  94   // Register variant is using a single cycle on ExePort.
  95   def : WriteRes<SchedRW, ExePorts> {
  96     let Latency = Lat;
  97     let ResourceCycles = Res;
  98     let NumMicroOps = UOps;
  99   }
 100
 101   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 102   // the latency (default = 5).
 103   def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
 104     let Latency = !add(Lat, LoadLat);
 105     let ResourceCycles = !listconcat([1], Res);
 106     let NumMicroOps = !add(UOps, 1);
 107   }
 108 }
 109
 110 // A folded store needs a cycle on port 4 for the store data, and an extra port
 111 // 2/3/7 cycle to recompute the address.
 112 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
 113
 114 // Arithmetic.
 115 defm : SKXWriteResPair<WriteALU,    [SKXPort0156], 1>; // Simple integer ALU op.
 116 defm : SKXWriteResPair<WriteADC,    [SKXPort06],   1>; // Integer ALU + flags op.
 117
 118 // Integer multiplication.
 119 defm : SKXWriteResPair<WriteIMul8,     [SKXPort1],   3>;
 120 defm : SKXWriteResPair<WriteIMul16,    [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>;
 121 defm : X86WriteRes<WriteIMul16Imm,     [SKXPort1,SKXPort0156], 4, [1,1], 2>;
 122 defm : X86WriteRes<WriteIMul16ImmLd,   [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
 123 defm : X86WriteRes<WriteIMul16Reg,     [SKXPort1],   3, [1], 1>;
 124 defm : X86WriteRes<WriteIMul16RegLd,   [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
 125 defm : SKXWriteResPair<WriteIMul32,    [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
 126 defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1],   3>;
 127 defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1],   3>;
 128 defm : SKXWriteResPair<WriteIMul64,    [SKXPort1,SKXPort5], 4, [1,1], 2>;
 129 defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1],   3>;
 130 defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1],   3>;
 131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 132
 133 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
 134 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
 135 defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
 136 defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;
 137 defm : X86WriteRes<WriteXCHG,       [SKXPort0156], 2, [3], 3>;
 138
 139 // TODO: Why isn't the SKXDivider used?
 140 defm : SKXWriteResPair<WriteDiv8,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 141 defm : X86WriteRes<WriteDiv16,     [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
 142 defm : X86WriteRes<WriteDiv32,     [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
 143 defm : X86WriteRes<WriteDiv64,     [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
 144 defm : X86WriteRes<WriteDiv16Ld,   [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
 145 defm : X86WriteRes<WriteDiv32Ld,   [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
 146 defm : X86WriteRes<WriteDiv64Ld,   [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
 147
 148 defm : X86WriteRes<WriteIDiv8,     [SKXPort0, SKXDivider], 25, [1,10], 1>;
 149 defm : X86WriteRes<WriteIDiv16,    [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
 150 defm : X86WriteRes<WriteIDiv32,    [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
 151 defm : X86WriteRes<WriteIDiv64,    [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
 152 defm : X86WriteRes<WriteIDiv8Ld,   [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
 153 defm : X86WriteRes<WriteIDiv16Ld,  [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
 154 defm : X86WriteRes<WriteIDiv32Ld,  [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
 155 defm : X86WriteRes<WriteIDiv64Ld,  [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
 156
 157 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
 158
 159 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
 160
 161 defm : SKXWriteResPair<WriteCMOV,  [SKXPort06], 1, [1], 1>; // Conditional move.
 162 defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.
 163 def  : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
 164 def  : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
 165   let Latency = 2;
 166   let NumMicroOps = 3;
 167 }
 168 defm : X86WriteRes<WriteLAHFSAHF,        [SKXPort06], 1, [1], 1>;
 169 defm : X86WriteRes<WriteBitTest,         [SKXPort06], 1, [1], 1>;
 170 defm : X86WriteRes<WriteBitTestImmLd,    [SKXPort06,SKXPort23], 6, [1,1], 2>;
 171 defm : X86WriteRes<WriteBitTestRegLd,    [SKXPort0156,SKXPort23], 6, [1,1], 2>;
 172 defm : X86WriteRes<WriteBitTestSet,      [SKXPort06], 1, [1], 1>;
 173 defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>;
 174 defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>;
 175
 176 // Integer shifts and rotates.
 177 defm : SKXWriteResPair<WriteShift,    [SKXPort06],  1>;
 178 defm : SKXWriteResPair<WriteShiftCL,  [SKXPort06],  3, [3], 3>;
 179 defm : SKXWriteResPair<WriteRotate,   [SKXPort06],  1, [1], 1>;
 180 defm : SKXWriteResPair<WriteRotateCL, [SKXPort06],  3, [3], 3>;
 181
 182 // SHLD/SHRD.
 183 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
 184 defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;
 185 defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;
 186 defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;
 187
 188 // Bit counts.
 189 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
 190 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
 191 defm : SKXWriteResPair<WriteLZCNT,          [SKXPort1], 3>;
 192 defm : SKXWriteResPair<WriteTZCNT,          [SKXPort1], 3>;
 193 defm : SKXWriteResPair<WritePOPCNT,         [SKXPort1], 3>;
 194
 195 // BMI1 BEXTR/BLS, BMI2 BZHI
 196 defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
 197 defm : SKXWriteResPair<WriteBLS,   [SKXPort15], 1>;
 198 defm : SKXWriteResPair<WriteBZHI,  [SKXPort15], 1>;
 199
 200 // Loads, stores, and moves, not folded with other operations.
 201 defm : X86WriteRes<WriteLoad,    [SKXPort23], 5, [1], 1>;
 202 defm : X86WriteRes<WriteStore,   [SKXPort237, SKXPort4], 1, [1,1], 1>;
 203 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
 204 defm : X86WriteRes<WriteMove,    [SKXPort0156], 1, [1], 1>;
 205
 206 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 207 // These can often bypass execution ports completely.
 208 def : WriteRes<WriteZero,  []>;
 209
 210 // Branches don't produce values, so they have no latency, but they still
 211 // consume resources. Indirect branches can fold loads.
 212 defm : SKXWriteResPair<WriteJump,  [SKXPort06],   1>;
 213
 214 // Floating point. This covers both scalar and vector operations.
 215 defm : X86WriteRes<WriteFLD0,          [SKXPort05], 1, [1], 1>;
 216 defm : X86WriteRes<WriteFLD1,          [SKXPort05], 1, [2], 2>;
 217 defm : X86WriteRes<WriteFLDC,          [SKXPort05], 1, [2], 2>;
 218 defm : X86WriteRes<WriteFLoad,         [SKXPort23], 5, [1], 1>;
 219 defm : X86WriteRes<WriteFLoadX,        [SKXPort23], 6, [1], 1>;
 220 defm : X86WriteRes<WriteFLoadY,        [SKXPort23], 7, [1], 1>;
 221 defm : X86WriteRes<WriteFMaskedLoad,   [SKXPort23,SKXPort015], 7, [1,1], 2>;
 222 defm : X86WriteRes<WriteFMaskedLoadY,  [SKXPort23,SKXPort015], 8, [1,1], 2>;
 223 defm : X86WriteRes<WriteFStore,        [SKXPort237,SKXPort4], 1, [1,1], 2>;
 224 defm : X86WriteRes<WriteFStoreX,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 225 defm : X86WriteRes<WriteFStoreY,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 226 defm : X86WriteRes<WriteFStoreNT,      [SKXPort237,SKXPort4], 1, [1,1], 2>;
 227 defm : X86WriteRes<WriteFStoreNTX,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 228 defm : X86WriteRes<WriteFStoreNTY,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 229
 230 defm : X86WriteRes<WriteFMaskedStore32,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 231 defm : X86WriteRes<WriteFMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 232 defm : X86WriteRes<WriteFMaskedStore64,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 233 defm : X86WriteRes<WriteFMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 234
 235 defm : X86WriteRes<WriteFMove,         [SKXPort015], 1, [1], 1>;
 236 defm : X86WriteRes<WriteFMoveX,        [SKXPort015], 1, [1], 1>;
 237 defm : X86WriteRes<WriteFMoveY,        [SKXPort015], 1, [1], 1>;
 238 defm : X86WriteRes<WriteEMMS,          [SKXPort05,SKXPort0156], 10, [9,1], 10>;
 239
 240 defm : SKXWriteResPair<WriteFAdd,      [SKXPort01],  4, [1], 1, 5>; // Floating point add/sub.
 241 defm : SKXWriteResPair<WriteFAddX,     [SKXPort01],  4, [1], 1, 6>;
 242 defm : SKXWriteResPair<WriteFAddY,     [SKXPort01],  4, [1], 1, 7>;
 243 defm : SKXWriteResPair<WriteFAddZ,     [SKXPort05],  4, [1], 1, 7>;
 244 defm : SKXWriteResPair<WriteFAdd64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 245 defm : SKXWriteResPair<WriteFAdd64X,   [SKXPort01],  4, [1], 1, 6>;
 246 defm : SKXWriteResPair<WriteFAdd64Y,   [SKXPort01],  4, [1], 1, 7>;
 247 defm : SKXWriteResPair<WriteFAdd64Z,   [SKXPort05],  4, [1], 1, 7>;
 248
 249 defm : SKXWriteResPair<WriteFCmp,      [SKXPort01],  4, [1], 1, 5>; // Floating point compare.
 250 defm : SKXWriteResPair<WriteFCmpX,     [SKXPort01],  4, [1], 1, 6>;
 251 defm : SKXWriteResPair<WriteFCmpY,     [SKXPort01],  4, [1], 1, 7>;
 252 defm : SKXWriteResPair<WriteFCmpZ,     [SKXPort05],  4, [1], 1, 7>;
 253 defm : SKXWriteResPair<WriteFCmp64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double compare.
 254 defm : SKXWriteResPair<WriteFCmp64X,   [SKXPort01],  4, [1], 1, 6>;
 255 defm : SKXWriteResPair<WriteFCmp64Y,   [SKXPort01],  4, [1], 1, 7>;
 256 defm : SKXWriteResPair<WriteFCmp64Z,   [SKXPort05],  4, [1], 1, 7>;
 257
 258 defm : SKXWriteResPair<WriteFCom,       [SKXPort0],  2>; // Floating point compare to flags (X87).
 259 defm : SKXWriteResPair<WriteFComX,      [SKXPort0],  2>; // Floating point compare to flags (SSE).
 260
 261 defm : SKXWriteResPair<WriteFMul,      [SKXPort01],  4, [1], 1, 5>; // Floating point multiplication.
 262 defm : SKXWriteResPair<WriteFMulX,     [SKXPort01],  4, [1], 1, 6>;
 263 defm : SKXWriteResPair<WriteFMulY,     [SKXPort01],  4, [1], 1, 7>;
 264 defm : SKXWriteResPair<WriteFMulZ,     [SKXPort05],  4, [1], 1, 7>;
 265 defm : SKXWriteResPair<WriteFMul64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 266 defm : SKXWriteResPair<WriteFMul64X,   [SKXPort01],  4, [1], 1, 6>;
 267 defm : SKXWriteResPair<WriteFMul64Y,   [SKXPort01],  4, [1], 1, 7>;
 268 defm : SKXWriteResPair<WriteFMul64Z,   [SKXPort05],  4, [1], 1, 7>;
 269
 270 defm : SKXWriteResPair<WriteFDiv,     [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
 271 //defm : SKXWriteResPair<WriteFDivX,    [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.
 272 defm : SKXWriteResPair<WriteFDivY,    [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
 273 defm : SKXWriteResPair<WriteFDivZ,    [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.
 274 //defm : SKXWriteResPair<WriteFDiv64,   [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
 275 //defm : SKXWriteResPair<WriteFDiv64X,  [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles.
 276 //defm : SKXWriteResPair<WriteFDiv64Y,  [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles.
 277 defm : SKXWriteResPair<WriteFDiv64Z,  [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.
 278
 279 defm : SKXWriteResPair<WriteFSqrt,    [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 280 defm : SKXWriteResPair<WriteFSqrtX,   [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;
 281 defm : SKXWriteResPair<WriteFSqrtY,   [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
 282 defm : SKXWriteResPair<WriteFSqrtZ,   [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
 283 defm : SKXWriteResPair<WriteFSqrt64,  [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 284 defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;
 285 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
 286 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
 287 defm : SKXWriteResPair<WriteFSqrt80,  [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.
 288
 289 defm : SKXWriteResPair<WriteFRcp,   [SKXPort0],  4, [1], 1, 5>; // Floating point reciprocal estimate.
 290 defm : SKXWriteResPair<WriteFRcpX,  [SKXPort0],  4, [1], 1, 6>;
 291 defm : SKXWriteResPair<WriteFRcpY,  [SKXPort0],  4, [1], 1, 7>;
 292 defm : SKXWriteResPair<WriteFRcpZ,  [SKXPort0,SKXPort5],  4, [2,1], 3, 7>;
 293
 294 defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0],  4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 295 defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0],  4, [1], 1, 6>;
 296 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0],  4, [1], 1, 7>;
 297 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5],  9, [2,1], 3, 7>;
 298
 299 defm : SKXWriteResPair<WriteFMA,  [SKXPort01],  4, [1], 1, 5>; // Fused Multiply Add.
 300 defm : SKXWriteResPair<WriteFMAX, [SKXPort01],  4, [1], 1, 6>;
 301 defm : SKXWriteResPair<WriteFMAY, [SKXPort01],  4, [1], 1, 7>;
 302 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05],  4, [1], 1, 7>;
 303 defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015],  9, [1,2], 3, 6>; // Floating point double dot product.
 304 defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>;
 305 defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
 306 defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
 307 defm : SKXWriteResPair<WriteFSign,  [SKXPort0],  1>; // Floating point fabs/fchs.
 308 defm : SKXWriteResPair<WriteFRnd,   [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.
 309 defm : SKXWriteResPair<WriteFRndY,  [SKXPort01], 8, [2], 2, 7>;
 310 defm : SKXWriteResPair<WriteFRndZ,  [SKXPort05], 8, [2], 2, 7>;
 311 defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 312 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
 313 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
 314 defm : SKXWriteResPair<WriteFTest,  [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 315 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
 316 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
 317 defm : SKXWriteResPair<WriteFShuffle,  [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 318 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
 319 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 320 defm : SKXWriteResPair<WriteFVarShuffle,  [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
 321 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
 322 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 323 defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.
 324 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
 325 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
 326 defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 327 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
 328 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
 329
 330 // FMA Scheduling helper class.
 331 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 332
 333 // Vector integer operations.
 334 defm : X86WriteRes<WriteVecLoad,         [SKXPort23], 5, [1], 1>;
 335 defm : X86WriteRes<WriteVecLoadX,        [SKXPort23], 6, [1], 1>;
 336 defm : X86WriteRes<WriteVecLoadY,        [SKXPort23], 7, [1], 1>;
 337 defm : X86WriteRes<WriteVecLoadNT,       [SKXPort23], 6, [1], 1>;
 338 defm : X86WriteRes<WriteVecLoadNTY,      [SKXPort23], 7, [1], 1>;
 339 defm : X86WriteRes<WriteVecMaskedLoad,   [SKXPort23,SKXPort015], 7, [1,1], 2>;
 340 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKXPort23,SKXPort015], 8, [1,1], 2>;
 341 defm : X86WriteRes<WriteVecStore,        [SKXPort237,SKXPort4], 1, [1,1], 2>;
 342 defm : X86WriteRes<WriteVecStoreX,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 343 defm : X86WriteRes<WriteVecStoreY,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 344 defm : X86WriteRes<WriteVecStoreNT,      [SKXPort237,SKXPort4], 1, [1,1], 2>;
 345 defm : X86WriteRes<WriteVecStoreNTY,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 346 defm : X86WriteRes<WriteVecMaskedStore32,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 347 defm : X86WriteRes<WriteVecMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 348 defm : X86WriteRes<WriteVecMaskedStore64,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 349 defm : X86WriteRes<WriteVecMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 350 defm : X86WriteRes<WriteVecMove,         [SKXPort05],  1, [1], 1>;
 351 defm : X86WriteRes<WriteVecMoveX,        [SKXPort015], 1, [1], 1>;
 352 defm : X86WriteRes<WriteVecMoveY,        [SKXPort015], 1, [1], 1>;
 353 defm : X86WriteRes<WriteVecMoveToGpr,    [SKXPort0], 2, [1], 1>;
 354 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKXPort5], 1, [1], 1>;
 355
 356 defm : SKXWriteResPair<WriteVecALU,   [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 357 defm : SKXWriteResPair<WriteVecALUX,  [SKXPort01], 1, [1], 1, 6>;
 358 defm : SKXWriteResPair<WriteVecALUY,  [SKXPort01], 1, [1], 1, 7>;
 359 defm : SKXWriteResPair<WriteVecALUZ,  [SKXPort0], 1, [1], 1, 7>;
 360 defm : SKXWriteResPair<WriteVecLogic, [SKXPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 361 defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;
 362 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
 363 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
 364 defm : SKXWriteResPair<WriteVecTest,  [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 365 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
 366 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
 367 defm : SKXWriteResPair<WriteVecIMul,  [SKXPort0],   5, [1], 1, 5>; // Vector integer multiply.
 368 defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01],  5, [1], 1, 6>;
 369 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01],  5, [1], 1, 7>;
 370 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05],  5, [1], 1, 7>;
 371 defm : SKXWriteResPair<WritePMULLD,   [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.
 372 defm : SKXWriteResPair<WritePMULLDY,  [SKXPort01], 10, [2], 2, 7>;
 373 defm : SKXWriteResPair<WritePMULLDZ,  [SKXPort05], 10, [2], 2, 7>;
 374 defm : SKXWriteResPair<WriteShuffle,  [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
 375 defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;
 376 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
 377 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 378 defm : SKXWriteResPair<WriteVarShuffle,  [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 379 defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;
 380 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
 381 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 382 defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
 383 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
 384 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
 385 defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
 386 defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;
 387 defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05],  2, [1], 1, 6>;
 388 defm : SKXWriteResPair<WriteMPSAD,   [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
 389 defm : SKXWriteResPair<WriteMPSADY,  [SKXPort5], 4, [2], 2, 7>;
 390 defm : SKXWriteResPair<WriteMPSADZ,  [SKXPort5], 4, [2], 2, 7>;
 391 defm : SKXWriteResPair<WritePSADBW,  [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.
 392 defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;
 393 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
 394 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>;
 395 defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
 396
 397 // Vector integer shifts.
 398 defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;
 399 defm : X86WriteRes<WriteVecShiftX,    [SKXPort5,SKXPort01],  2, [1,1], 2>;
 400 defm : X86WriteRes<WriteVecShiftY,    [SKXPort5,SKXPort01],  4, [1,1], 2>;
 401 defm : X86WriteRes<WriteVecShiftZ,    [SKXPort5,SKXPort0],   4, [1,1], 2>;
 402 defm : X86WriteRes<WriteVecShiftXLd,  [SKXPort01,SKXPort23], 7, [1,1], 2>;
 403 defm : X86WriteRes<WriteVecShiftYLd,  [SKXPort01,SKXPort23], 8, [1,1], 2>;
 404 defm : X86WriteRes<WriteVecShiftZLd,  [SKXPort0,SKXPort23],  8, [1,1], 2>;
 405
 406 defm : SKXWriteResPair<WriteVecShiftImm,  [SKXPort0],  1, [1], 1, 5>;
 407 defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.
 408 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
 409 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
 410 defm : SKXWriteResPair<WriteVarVecShift,  [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
 411 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
 412 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
 413
 414 // Vector insert/extract operations.
 415 def : WriteRes<WriteVecInsert, [SKXPort5]> {
 416   let Latency = 2;
 417   let NumMicroOps = 2;
 418   let ResourceCycles = [2];
 419 }
 420 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
 421   let Latency = 6;
 422   let NumMicroOps = 2;
 423 }
 424 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 425
 426 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {
 427   let Latency = 3;
 428   let NumMicroOps = 2;
 429 }
 430 def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {
 431   let Latency = 2;
 432   let NumMicroOps = 3;
 433 }
 434
 435 // Conversion between integer and float.
 436 defm : SKXWriteResPair<WriteCvtSS2I,   [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
 437 defm : SKXWriteResPair<WriteCvtPS2I,   [SKXPort01], 3>;
 438 defm : SKXWriteResPair<WriteCvtPS2IY,  [SKXPort01], 3>;
 439 defm : SKXWriteResPair<WriteCvtPS2IZ,  [SKXPort05], 3>;
 440 defm : SKXWriteResPair<WriteCvtSD2I,   [SKXPort01], 6, [2], 2>;
 441 defm : SKXWriteResPair<WriteCvtPD2I,   [SKXPort01], 3>;
 442 defm : SKXWriteResPair<WriteCvtPD2IY,  [SKXPort01], 3>;
 443 defm : SKXWriteResPair<WriteCvtPD2IZ,  [SKXPort05], 3>;
 444
 445 defm : SKXWriteResPair<WriteCvtI2SS,   [SKXPort1], 4>;
 446 defm : SKXWriteResPair<WriteCvtI2PS,   [SKXPort01], 4>;
 447 defm : SKXWriteResPair<WriteCvtI2PSY,  [SKXPort01], 4>;
 448 defm : SKXWriteResPair<WriteCvtI2PSZ,  [SKXPort05], 4>;  // Needs more work: DD vs DQ.
 449 defm : SKXWriteResPair<WriteCvtI2SD,   [SKXPort1], 4>;
 450 defm : SKXWriteResPair<WriteCvtI2PD,   [SKXPort01], 4>;
 451 defm : SKXWriteResPair<WriteCvtI2PDY,  [SKXPort01], 4>;
 452 defm : SKXWriteResPair<WriteCvtI2PDZ,  [SKXPort05], 4>;
 453
 454 defm : SKXWriteResPair<WriteCvtSS2SD,  [SKXPort1], 3>;
 455 defm : SKXWriteResPair<WriteCvtPS2PD,  [SKXPort1], 3>;
 456 defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
 457 defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;
 458 defm : SKXWriteResPair<WriteCvtSD2SS,  [SKXPort1], 3>;
 459 defm : SKXWriteResPair<WriteCvtPD2PS,  [SKXPort1], 3>;
 460 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
 461 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>;
 462
 463 defm : X86WriteRes<WriteCvtPH2PS,     [SKXPort5,SKXPort01],  5, [1,1], 2>;
 464 defm : X86WriteRes<WriteCvtPH2PSY,    [SKXPort5,SKXPort01],  7, [1,1], 2>;
 465 defm : X86WriteRes<WriteCvtPH2PSZ,    [SKXPort5,SKXPort0],   7, [1,1], 2>;
 466 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKXPort23,SKXPort01],  9, [1,1], 2>;
 467 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;
 468 defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;
 469
 470 defm : X86WriteRes<WriteCvtPS2PH,    [SKXPort5,SKXPort01], 5, [1,1], 2>;
 471 defm : X86WriteRes<WriteCvtPS2PHY,   [SKXPort5,SKXPort01], 7, [1,1], 2>;
 472 defm : X86WriteRes<WriteCvtPS2PHZ,   [SKXPort5,SKXPort05], 7, [1,1], 2>;
 473 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;
 474 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;
 475 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
 476
 477 // Strings instructions.
 478
 479 // Packed Compare Implicit Length Strings, Return Mask
 480 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
 481   let Latency = 10;
 482   let NumMicroOps = 3;
 483   let ResourceCycles = [3];
 484 }
 485 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
 486   let Latency = 16;
 487   let NumMicroOps = 4;
 488   let ResourceCycles = [3,1];
 489 }
 490
 491 // Packed Compare Explicit Length Strings, Return Mask
 492 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
 493   let Latency = 19;
 494   let NumMicroOps = 9;
 495   let ResourceCycles = [4,3,1,1];
 496 }
 497 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
 498   let Latency = 25;
 499   let NumMicroOps = 10;
 500   let ResourceCycles = [4,3,1,1,1];
 501 }
 502
 503 // Packed Compare Implicit Length Strings, Return Index
 504 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
 505   let Latency = 10;
 506   let NumMicroOps = 3;
 507   let ResourceCycles = [3];
 508 }
 509 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
 510   let Latency = 16;
 511   let NumMicroOps = 4;
 512   let ResourceCycles = [3,1];
 513 }
 514
 515 // Packed Compare Explicit Length Strings, Return Index
 516 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
 517   let Latency = 18;
 518   let NumMicroOps = 8;
 519   let ResourceCycles = [4,3,1];
 520 }
 521 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
 522   let Latency = 24;
 523   let NumMicroOps = 9;
 524   let ResourceCycles = [4,3,1,1];
 525 }
 526
 527 // MOVMSK Instructions.
 528 def : WriteRes<WriteFMOVMSK,    [SKXPort0]> { let Latency = 2; }
 529 def : WriteRes<WriteVecMOVMSK,  [SKXPort0]> { let Latency = 2; }
 530 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
 531 def : WriteRes<WriteMMXMOVMSK,  [SKXPort0]> { let Latency = 2; }
 532
 533 // AES instructions.
 534 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
 535   let Latency = 4;
 536   let NumMicroOps = 1;
 537   let ResourceCycles = [1];
 538 }
 539 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
 540   let Latency = 10;
 541   let NumMicroOps = 2;
 542   let ResourceCycles = [1,1];
 543 }
 544
 545 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
 546   let Latency = 8;
 547   let NumMicroOps = 2;
 548   let ResourceCycles = [2];
 549 }
 550 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
 551   let Latency = 14;
 552   let NumMicroOps = 3;
 553   let ResourceCycles = [2,1];
 554 }
 555
 556 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
 557   let Latency = 20;
 558   let NumMicroOps = 11;
 559   let ResourceCycles = [3,6,2];
 560 }
 561 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
 562   let Latency = 25;
 563   let NumMicroOps = 11;
 564   let ResourceCycles = [3,6,1,1];
 565 }
 566
 567 // Carry-less multiplication instructions.
 568 def : WriteRes<WriteCLMul, [SKXPort5]> {
 569   let Latency = 6;
 570   let NumMicroOps = 1;
 571   let ResourceCycles = [1];
 572 }
 573 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
 574   let Latency = 12;
 575   let NumMicroOps = 2;
 576   let ResourceCycles = [1,1];
 577 }
 578
 579 // Catch-all for expensive system instructions.
 580 def : WriteRes<WriteSystem,     [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 581
 582 // AVX2.
 583 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 584 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 585 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 586 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 587
 588 // Old microcoded instructions that nobody use.
 589 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 590
 591 // Fence instructions.
 592 def : WriteRes<WriteFence,  [SKXPort23, SKXPort4]>;
 593
 594 // Load/store MXCSR.
 595 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 596 def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 597
 598 // Nop, not very useful expect it provides a model for nops!
 599 def : WriteRes<WriteNop, []>;
 600
 601 ////////////////////////////////////////////////////////////////////////////////
 602 // Horizontal add/sub  instructions.
 603 ////////////////////////////////////////////////////////////////////////////////
 604
 605 defm : SKXWriteResPair<WriteFHAdd,  [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
 606 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>;
 607 defm : SKXWriteResPair<WritePHAdd,  [SKXPort5,SKXPort05],  3, [2,1], 3, 5>;
 608 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
 609 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
 610
 611 // Remaining instrs.
 612
 613 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
 614   let Latency = 1;
 615   let NumMicroOps = 1;
 616   let ResourceCycles = [1];
 617 }
 618 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
 619                                             "KANDN(B|D|Q|W)rr",
 620                                             "KMOV(B|D|Q|W)kk",
 621                                             "KNOT(B|D|Q|W)rr",
 622                                             "KOR(B|D|Q|W)rr",
 623                                             "KXNOR(B|D|Q|W)rr",
 624                                             "KXOR(B|D|Q|W)rr",
 625                                             "KSET0(B|D|Q|W)", // Same as KXOR
 626                                             "KSET1(B|D|Q|W)", // Same as KXNOR
 627                                             "MMX_PADDS(B|W)irr",
 628                                             "MMX_PADDUS(B|W)irr",
 629                                             "MMX_PAVG(B|W)irr",
 630                                             "MMX_PCMPEQ(B|D|W)irr",
 631                                             "MMX_PCMPGT(B|D|W)irr",
 632                                             "MMX_P(MAX|MIN)SWirr",
 633                                             "MMX_P(MAX|MIN)UBirr",
 634                                             "MMX_PSUBS(B|W)irr",
 635                                             "MMX_PSUBUS(B|W)irr",
 636                                             "VPMOVB2M(Z|Z128|Z256)rr",
 637                                             "VPMOVD2M(Z|Z128|Z256)rr",
 638                                             "VPMOVQ2M(Z|Z128|Z256)rr",
 639                                             "VPMOVW2M(Z|Z128|Z256)rr")>;
 640
 641 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
 642   let Latency = 1;
 643   let NumMicroOps = 1;
 644   let ResourceCycles = [1];
 645 }
 646 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
 647                                             "KMOV(B|D|Q|W)kr",
 648                                             "UCOM_F(P?)r")>;
 649
 650 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
 651   let Latency = 1;
 652   let NumMicroOps = 1;
 653   let ResourceCycles = [1];
 654 }
 655 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 656
 657 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
 658   let Latency = 1;
 659   let NumMicroOps = 1;
 660   let ResourceCycles = [1];
 661 }
 662 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
 663
 664 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
 665   let Latency = 1;
 666   let NumMicroOps = 1;
 667   let ResourceCycles = [1];
 668 }
 669 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 670
 671 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
 672   let Latency = 1;
 673   let NumMicroOps = 1;
 674   let ResourceCycles = [1];
 675 }
 676 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 677
 678 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
 679   let Latency = 1;
 680   let NumMicroOps = 1;
 681   let ResourceCycles = [1];
 682 }
 683 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
 684                                             "VBLENDMPS(Z128|Z256)rr",
 685                                             "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
 686                                             "(V?)PADD(B|D|Q|W)rr",
 687                                             "VPBLENDD(Y?)rri",
 688                                             "VPBLENDMB(Z128|Z256)rr",
 689                                             "VPBLENDMD(Z128|Z256)rr",
 690                                             "VPBLENDMQ(Z128|Z256)rr",
 691                                             "VPBLENDMW(Z128|Z256)rr",
 692                                             "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk",
 693                                             "VPTERNLOGD(Z|Z128|Z256)rri",
 694                                             "VPTERNLOGQ(Z|Z128|Z256)rri")>;
 695
 696 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
 697   let Latency = 1;
 698   let NumMicroOps = 1;
 699   let ResourceCycles = [1];
 700 }
 701 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
 702                                           CMC, STC,
 703                                           SGDT64m,
 704                                           SIDT64m,
 705                                           SMSW16m,
 706                                           STRm,
 707                                           SYSCALL)>;
 708
 709 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
 710   let Latency = 1;
 711   let NumMicroOps = 2;
 712   let ResourceCycles = [1,1];
 713 }
 714 def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
 715 def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
 716                                              "ST_FP(32|64|80)m")>;
 717
 718 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
 719   let Latency = 2;
 720   let NumMicroOps = 2;
 721   let ResourceCycles = [2];
 722 }
 723 def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
 724
 725 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
 726   let Latency = 2;
 727   let NumMicroOps = 2;
 728   let ResourceCycles = [2];
 729 }
 730 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
 731                                           MMX_MOVDQ2Qrr)>;
 732
 733 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
 734   let Latency = 2;
 735   let NumMicroOps = 2;
 736   let ResourceCycles = [2];
 737 }
 738 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
 739                                           WAIT,
 740                                           XGETBV)>;
 741
 742 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
 743   let Latency = 2;
 744   let NumMicroOps = 2;
 745   let ResourceCycles = [1,1];
 746 }
 747 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
 748
 749 def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
 750   let Latency = 2;
 751   let NumMicroOps = 2;
 752   let ResourceCycles = [1,1];
 753 }
 754 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
 755
 756 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
 757   let Latency = 2;
 758   let NumMicroOps = 2;
 759   let ResourceCycles = [1,1];
 760 }
 761 def: InstRW<[SKXWriteResGroup23], (instrs CWD,
 762                                           JCXZ, JECXZ, JRCXZ,
 763                                           ADC8i8, SBB8i8,
 764                                           ADC16i16, SBB16i16,
 765                                           ADC32i32, SBB32i32,
 766                                           ADC64i32, SBB64i32)>;
 767
 768 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
 769   let Latency = 2;
 770   let NumMicroOps = 3;
 771   let ResourceCycles = [1,1,1];
 772 }
 773 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
 774
 775 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
 776   let Latency = 2;
 777   let NumMicroOps = 3;
 778   let ResourceCycles = [1,1,1];
 779 }
 780 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 781
 782 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
 783   let Latency = 2;
 784   let NumMicroOps = 3;
 785   let ResourceCycles = [1,1,1];
 786 }
 787 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 788                                           STOSB, STOSL, STOSQ, STOSW)>;
 789 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
 790
 791 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
 792   let Latency = 2;
 793   let NumMicroOps = 5;
 794   let ResourceCycles = [2,2,1];
 795 }
 796 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
 797
 798 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
 799   let Latency = 3;
 800   let NumMicroOps = 1;
 801   let ResourceCycles = [1];
 802 }
 803 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
 804                                              "KORTEST(B|D|Q|W)rr",
 805                                              "KTEST(B|D|Q|W)rr")>;
 806
 807 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
 808   let Latency = 3;
 809   let NumMicroOps = 1;
 810   let ResourceCycles = [1];
 811 }
 812 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
 813                                              "PEXT(32|64)rr")>;
 814
 815 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
 816   let Latency = 3;
 817   let NumMicroOps = 1;
 818   let ResourceCycles = [1];
 819 }
 820 def: InstRW<[SKXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined.
 821 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 822                                              "VALIGND(Z|Z128|Z256)rri",
 823                                              "VALIGNQ(Z|Z128|Z256)rri",
 824                                              "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined.
 825                                              "VPBROADCAST(B|W)rr",
 826                                              "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>;
 827
 828 def SKXWriteResGroup33 : SchedWriteRes<[SKXPort5]> {
 829   let Latency = 4;
 830   let NumMicroOps = 1;
 831   let ResourceCycles = [1];
 832 }
 833 def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr",
 834                                              "KSHIFTL(B|D|Q|W)ri",
 835                                              "KSHIFTR(B|D|Q|W)ri",
 836                                              "KUNPCK(BW|DQ|WD)rr",
 837                                              "VCMPPD(Z|Z128|Z256)rri",
 838                                              "VCMPPS(Z|Z128|Z256)rri",
 839                                              "VCMP(SD|SS)Zrr",
 840                                              "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
 841                                              "VFPCLASS(SD|SS)Zrr",
 842                                              "VPCMPB(Z|Z128|Z256)rri",
 843                                              "VPCMPD(Z|Z128|Z256)rri",
 844                                              "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
 845                                              "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
 846                                              "VPCMPQ(Z|Z128|Z256)rri",
 847                                              "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
 848                                              "VPCMPW(Z|Z128|Z256)rri",
 849                                              "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
 850
 851 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
 852   let Latency = 3;
 853   let NumMicroOps = 2;
 854   let ResourceCycles = [1,1];
 855 }
 856 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
 857
 858 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
 859   let Latency = 3;
 860   let NumMicroOps = 3;
 861   let ResourceCycles = [1,2];
 862 }
 863 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 864
 865 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
 866   let Latency = 3;
 867   let NumMicroOps = 3;
 868   let ResourceCycles = [2,1];
 869 }
 870 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
 871
 872 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
 873   let Latency = 3;
 874   let NumMicroOps = 3;
 875   let ResourceCycles = [2,1];
 876 }
 877 def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWirr,
 878                                           MMX_PACKSSWBirr,
 879                                           MMX_PACKUSWBirr)>;
 880
 881 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
 882   let Latency = 3;
 883   let NumMicroOps = 3;
 884   let ResourceCycles = [1,2];
 885 }
 886 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
 887
 888 def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
 889   let Latency = 3;
 890   let NumMicroOps = 3;
 891   let ResourceCycles = [1,2];
 892 }
 893 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
 894
 895 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
 896   let Latency = 3;
 897   let NumMicroOps = 3;
 898   let ResourceCycles = [1,2];
 899 }
 900 def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)",
 901                                              "RCR(8|16|32|64)r(1|i)")>;
 902
 903 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
 904   let Latency = 3;
 905   let NumMicroOps = 3;
 906   let ResourceCycles = [1,1,1];
 907 }
 908 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
 909
 910 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
 911   let Latency = 3;
 912   let NumMicroOps = 4;
 913   let ResourceCycles = [1,1,1,1];
 914 }
 915 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
 916
 917 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
 918   let Latency = 3;
 919   let NumMicroOps = 4;
 920   let ResourceCycles = [1,1,1,1];
 921 }
 922 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
 923
 924 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
 925   let Latency = 4;
 926   let NumMicroOps = 1;
 927   let ResourceCycles = [1];
 928 }
 929 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 930
 931 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
 932   let Latency = 4;
 933   let NumMicroOps = 1;
 934   let ResourceCycles = [1];
 935 }
 936 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
 937                                              "(V?)CVTDQ2PSrr",
 938                                              "VCVTPD2QQ(Z128|Z256)rr",
 939                                              "VCVTPD2UQQ(Z128|Z256)rr",
 940                                              "VCVTPS2DQ(Y|Z128|Z256)rr",
 941                                              "(V?)CVTPS2DQrr",
 942                                              "VCVTPS2UDQ(Z128|Z256)rr",
 943                                              "VCVTQQ2PD(Z128|Z256)rr",
 944                                              "VCVTTPD2QQ(Z128|Z256)rr",
 945                                              "VCVTTPD2UQQ(Z128|Z256)rr",
 946                                              "VCVTTPS2DQ(Z128|Z256)rr",
 947                                              "(V?)CVTTPS2DQrr",
 948                                              "VCVTTPS2UDQ(Z128|Z256)rr",
 949                                              "VCVTUDQ2PS(Z128|Z256)rr",
 950                                              "VCVTUQQ2PD(Z128|Z256)rr")>;
 951
 952 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
 953   let Latency = 4;
 954   let NumMicroOps = 1;
 955   let ResourceCycles = [1];
 956 }
 957 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
 958                                            VCVTPD2QQZrr,
 959                                            VCVTPD2UQQZrr,
 960                                            VCVTPS2DQZrr,
 961                                            VCVTPS2UDQZrr,
 962                                            VCVTQQ2PDZrr,
 963                                            VCVTTPD2QQZrr,
 964                                            VCVTTPD2UQQZrr,
 965                                            VCVTTPS2DQZrr,
 966                                            VCVTTPS2UDQZrr,
 967                                            VCVTUDQ2PSZrr,
 968                                            VCVTUQQ2PDZrr)>;
 969
 970 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
 971   let Latency = 4;
 972   let NumMicroOps = 2;
 973   let ResourceCycles = [2];
 974 }
 975 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
 976                                              "VEXPANDPS(Z|Z128|Z256)rr",
 977                                              "VPEXPANDD(Z|Z128|Z256)rr",
 978                                              "VPEXPANDQ(Z|Z128|Z256)rr",
 979                                              "VPMOVDB(Z|Z128|Z256)rr",
 980                                              "VPMOVDW(Z|Z128|Z256)rr",
 981                                              "VPMOVQB(Z|Z128|Z256)rr",
 982                                              "VPMOVQW(Z|Z128|Z256)rr",
 983                                              "VPMOVSDB(Z|Z128|Z256)rr",
 984                                              "VPMOVSDW(Z|Z128|Z256)rr",
 985                                              "VPMOVSQB(Z|Z128|Z256)rr",
 986                                              "VPMOVSQD(Z|Z128|Z256)rr",
 987                                              "VPMOVSQW(Z|Z128|Z256)rr",
 988                                              "VPMOVSWB(Z|Z128|Z256)rr",
 989                                              "VPMOVUSDB(Z|Z128|Z256)rr",
 990                                              "VPMOVUSDW(Z|Z128|Z256)rr",
 991                                              "VPMOVUSQB(Z|Z128|Z256)rr",
 992                                              "VPMOVUSQD(Z|Z128|Z256)rr",
 993                                              "VPMOVUSWB(Z|Z128|Z256)rr",
 994                                              "VPMOVWB(Z|Z128|Z256)rr")>;
 995
 996 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
 997   let Latency = 4;
 998   let NumMicroOps = 3;
 999   let ResourceCycles = [1,1,1];
1000 }
1001 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
1002                                              "IST_F(16|32)m",
1003                                              "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
1004
1005 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
1006   let Latency = 4;
1007   let NumMicroOps = 4;
1008   let ResourceCycles = [4];
1009 }
1010 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
1011
1012 def SKXWriteResGroup56 : SchedWriteRes<[]> {
1013   let Latency = 0;
1014   let NumMicroOps = 4;
1015   let ResourceCycles = [];
1016 }
1017 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
1018
1019 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
1020   let Latency = 4;
1021   let NumMicroOps = 4;
1022   let ResourceCycles = [1,1,2];
1023 }
1024 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1025
1026 def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> {
1027   let Latency = 5;
1028   let NumMicroOps = 1;
1029   let ResourceCycles = [1];
1030 }
1031 def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
1032                                              "MOVZX(16|32|64)rm(8|16)",
1033                                              "(V?)MOVDDUPrm")>;  // TODO: Should this be SKXWriteResGroup71?
1034
1035 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1036   let Latency = 5;
1037   let NumMicroOps = 2;
1038   let ResourceCycles = [1,1];
1039 }
1040 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1041                                              "MMX_CVT(T?)PS2PIirr",
1042                                              "VCVTDQ2PDZ128rr",
1043                                              "VCVTPD2DQZ128rr",
1044                                              "(V?)CVT(T?)PD2DQrr",
1045                                              "VCVTPD2PSZ128rr",
1046                                              "(V?)CVTPD2PSrr",
1047                                              "VCVTPD2UDQZ128rr",
1048                                              "VCVTPS2PDZ128rr",
1049                                              "(V?)CVTPS2PDrr",
1050                                              "VCVTPS2QQZ128rr",
1051                                              "VCVTPS2UQQZ128rr",
1052                                              "VCVTQQ2PSZ128rr",
1053                                              "(V?)CVTSD2SS(Z?)rr",
1054                                              "(V?)CVTSI(64)?2SDrr",
1055                                              "VCVTSI2SSZrr",
1056                                              "(V?)CVTSI2SSrr",
1057                                              "VCVTSI(64)?2SDZrr",
1058                                              "VCVTSS2SDZrr",
1059                                              "(V?)CVTSS2SDrr",
1060                                              "VCVTTPD2DQZ128rr",
1061                                              "VCVTTPD2UDQZ128rr",
1062                                              "VCVTTPS2QQZ128rr",
1063                                              "VCVTTPS2UQQZ128rr",
1064                                              "VCVTUDQ2PDZ128rr",
1065                                              "VCVTUQQ2PSZ128rr",
1066                                              "VCVTUSI2SSZrr",
1067                                              "VCVTUSI(64)?2SDZrr")>;
1068
1069 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1070   let Latency = 5;
1071   let NumMicroOps = 3;
1072   let ResourceCycles = [2,1];
1073 }
1074 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
1075
1076 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
1077   let Latency = 5;
1078   let NumMicroOps = 3;
1079   let ResourceCycles = [1,1,1];
1080 }
1081 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
1082
1083 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> {
1084   let Latency = 5;
1085   let NumMicroOps = 3;
1086   let ResourceCycles = [1,1,1];
1087 }
1088 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
1089                                              "VCVTPS2PHZ256mr(b?)",
1090                                              "VCVTPS2PHZmr(b?)")>;
1091
1092 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1093   let Latency = 5;
1094   let NumMicroOps = 4;
1095   let ResourceCycles = [1,2,1];
1096 }
1097 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1098                                              "VPMOVDW(Z|Z128|Z256)mr(b?)",
1099                                              "VPMOVQB(Z|Z128|Z256)mr(b?)",
1100                                              "VPMOVQW(Z|Z128|Z256)mr(b?)",
1101                                              "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1102                                              "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1103                                              "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1104                                              "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1105                                              "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1106                                              "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1107                                              "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1108                                              "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1109                                              "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1110                                              "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1111                                              "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1112                                              "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1113                                              "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1114
1115 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1116   let Latency = 5;
1117   let NumMicroOps = 5;
1118   let ResourceCycles = [1,4];
1119 }
1120 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
1121
1122 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
1123   let Latency = 5;
1124   let NumMicroOps = 6;
1125   let ResourceCycles = [1,1,4];
1126 }
1127 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
1128
1129 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
1130   let Latency = 6;
1131   let NumMicroOps = 1;
1132   let ResourceCycles = [1];
1133 }
1134 def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,
1135                                           VPBROADCASTDrm,
1136                                           VPBROADCASTQrm,
1137                                           VMOVSHDUPrm,
1138                                           VMOVSLDUPrm,
1139                                           MOVSHDUPrm,
1140                                           MOVSLDUPrm)>;
1141
1142 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
1143   let Latency = 6;
1144   let NumMicroOps = 2;
1145   let ResourceCycles = [2];
1146 }
1147 def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>;
1148 def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
1149                                              "VCOMPRESSPS(Z|Z128|Z256)rr",
1150                                              "VPCOMPRESSD(Z|Z128|Z256)rr",
1151                                              "VPCOMPRESSQ(Z|Z128|Z256)rr",
1152                                              "VPERMW(Z|Z128|Z256)rr")>;
1153
1154 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1155   let Latency = 6;
1156   let NumMicroOps = 2;
1157   let ResourceCycles = [1,1];
1158 }
1159 def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBirm,
1160                                           MMX_PADDSWirm,
1161                                           MMX_PADDUSBirm,
1162                                           MMX_PADDUSWirm,
1163                                           MMX_PAVGBirm,
1164                                           MMX_PAVGWirm,
1165                                           MMX_PCMPEQBirm,
1166                                           MMX_PCMPEQDirm,
1167                                           MMX_PCMPEQWirm,
1168                                           MMX_PCMPGTBirm,
1169                                           MMX_PCMPGTDirm,
1170                                           MMX_PCMPGTWirm,
1171                                           MMX_PMAXSWirm,
1172                                           MMX_PMAXUBirm,
1173                                           MMX_PMINSWirm,
1174                                           MMX_PMINUBirm,
1175                                           MMX_PSUBSBirm,
1176                                           MMX_PSUBSWirm,
1177                                           MMX_PSUBUSBirm,
1178                                           MMX_PSUBUSWirm)>;
1179
1180 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
1181   let Latency = 6;
1182   let NumMicroOps = 2;
1183   let ResourceCycles = [1,1];
1184 }
1185 def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64m)>;
1186 def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
1187
1188 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
1189   let Latency = 6;
1190   let NumMicroOps = 2;
1191   let ResourceCycles = [1,1];
1192 }
1193 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
1194                                              "MOVBE(16|32|64)rm")>;
1195
1196 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1197   let Latency = 6;
1198   let NumMicroOps = 2;
1199   let ResourceCycles = [1,1];
1200 }
1201 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
1202 def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
1203
1204 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1205   let Latency = 6;
1206   let NumMicroOps = 2;
1207   let ResourceCycles = [1,1];
1208 }
1209 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
1210 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
1211
1212 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1213   let Latency = 6;
1214   let NumMicroOps = 3;
1215   let ResourceCycles = [2,1];
1216 }
1217 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
1218                                              "VCVTSI642SSZrr",
1219                                              "VCVTUSI642SSZrr")>;
1220
1221 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
1222   let Latency = 6;
1223   let NumMicroOps = 4;
1224   let ResourceCycles = [1,1,1,1];
1225 }
1226 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
1227
1228 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1229   let Latency = 6;
1230   let NumMicroOps = 4;
1231   let ResourceCycles = [1,1,1,1];
1232 }
1233 def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
1234                                              "SHL(8|16|32|64)m(1|i)",
1235                                              "SHR(8|16|32|64)m(1|i)")>;
1236
1237 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1238   let Latency = 6;
1239   let NumMicroOps = 4;
1240   let ResourceCycles = [1,1,1,1];
1241 }
1242 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
1243                                              "PUSH(16|32|64)rmm")>;
1244
1245 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
1246   let Latency = 6;
1247   let NumMicroOps = 6;
1248   let ResourceCycles = [1,5];
1249 }
1250 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
1251
1252 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
1253   let Latency = 7;
1254   let NumMicroOps = 1;
1255   let ResourceCycles = [1];
1256 }
1257 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
1258 def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
1259                                           VBROADCASTI128,
1260                                           VBROADCASTSDYrm,
1261                                           VBROADCASTSSYrm,
1262                                           VMOVDDUPYrm,
1263                                           VMOVSHDUPYrm,
1264                                           VMOVSLDUPYrm,
1265                                           VPBROADCASTDYrm,
1266                                           VPBROADCASTQYrm)>;
1267
1268 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
1269   let Latency = 7;
1270   let NumMicroOps = 2;
1271   let ResourceCycles = [1,1];
1272 }
1273 def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
1274
1275 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1276   let Latency = 7;
1277   let NumMicroOps = 2;
1278   let ResourceCycles = [1,1];
1279 }
1280 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
1281                                              "VMOVSSZrm(b?)")>;
1282
1283 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
1284   let Latency = 6;
1285   let NumMicroOps = 2;
1286   let ResourceCycles = [1,1];
1287 }
1288 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1289                                               "(V?)PMOV(SX|ZX)BQrm",
1290                                               "(V?)PMOV(SX|ZX)BWrm",
1291                                               "(V?)PMOV(SX|ZX)DQrm",
1292                                               "(V?)PMOV(SX|ZX)WDrm",
1293                                               "(V?)PMOV(SX|ZX)WQrm")>;
1294
1295 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1296   let Latency = 7;
1297   let NumMicroOps = 2;
1298   let ResourceCycles = [1,1];
1299 }
1300 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
1301                                              "VCVTPD2DQ(Y|Z256)rr",
1302                                              "VCVTPD2PS(Y|Z256)rr",
1303                                              "VCVTPD2UDQZ256rr",
1304                                              "VCVTPS2PD(Y|Z256)rr",
1305                                              "VCVTPS2QQZ256rr",
1306                                              "VCVTPS2UQQZ256rr",
1307                                              "VCVTQQ2PSZ256rr",
1308                                              "VCVTTPD2DQ(Y|Z256)rr",
1309                                              "VCVTTPD2UDQZ256rr",
1310                                              "VCVTTPS2QQZ256rr",
1311                                              "VCVTTPS2UQQZ256rr",
1312                                              "VCVTUDQ2PDZ256rr",
1313                                              "VCVTUQQ2PSZ256rr")>;
1314
1315 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
1316   let Latency = 7;
1317   let NumMicroOps = 2;
1318   let ResourceCycles = [1,1];
1319 }
1320 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
1321                                            VCVTPD2DQZrr,
1322                                            VCVTPD2PSZrr,
1323                                            VCVTPD2UDQZrr,
1324                                            VCVTPS2PDZrr,
1325                                            VCVTPS2QQZrr,
1326                                            VCVTPS2UQQZrr,
1327                                            VCVTQQ2PSZrr,
1328                                            VCVTTPD2DQZrr,
1329                                            VCVTTPD2UDQZrr,
1330                                            VCVTTPS2QQZrr,
1331                                            VCVTTPS2UQQZrr,
1332                                            VCVTUDQ2PDZrr,
1333                                            VCVTUQQ2PSZrr)>;
1334
1335 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1336   let Latency = 7;
1337   let NumMicroOps = 2;
1338   let ResourceCycles = [1,1];
1339 }
1340 def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
1341                                           VPBLENDDrmi)>;
1342 def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],
1343                                   (instregex "VBLENDMPDZ128rm(b?)",
1344                                              "VBLENDMPSZ128rm(b?)",
1345                                              "VBROADCASTI32X2Z128rm(b?)",
1346                                              "VBROADCASTSSZ128rm(b?)",
1347                                              "VINSERT(F|I)128rm",
1348                                              "VMOVAPDZ128rm(b?)",
1349                                              "VMOVAPSZ128rm(b?)",
1350                                              "VMOVDDUPZ128rm(b?)",
1351                                              "VMOVDQA32Z128rm(b?)",
1352                                              "VMOVDQA64Z128rm(b?)",
1353                                              "VMOVDQU16Z128rm(b?)",
1354                                              "VMOVDQU32Z128rm(b?)",
1355                                              "VMOVDQU64Z128rm(b?)",
1356                                              "VMOVDQU8Z128rm(b?)",
1357                                              "VMOVSHDUPZ128rm(b?)",
1358                                              "VMOVSLDUPZ128rm(b?)",
1359                                              "VMOVUPDZ128rm(b?)",
1360                                              "VMOVUPSZ128rm(b?)",
1361                                              "VPADD(B|D|Q|W)Z128rm(b?)",
1362                                              "(V?)PADD(B|D|Q|W)rm",
1363                                              "VPBLENDM(B|D|Q|W)Z128rm(b?)",
1364                                              "VPBROADCASTDZ128rm(b?)",
1365                                              "VPBROADCASTQZ128rm(b?)",
1366                                              "VPSUB(B|D|Q|W)Z128rm(b?)",
1367                                              "(V?)PSUB(B|D|Q|W)rm",
1368                                              "VPTERNLOGDZ128rm(b?)i",
1369                                              "VPTERNLOGQZ128rm(b?)i")>;
1370
1371 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1372   let Latency = 7;
1373   let NumMicroOps = 3;
1374   let ResourceCycles = [2,1];
1375 }
1376 def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWirm,
1377                                           MMX_PACKSSWBirm,
1378                                           MMX_PACKUSWBirm)>;
1379
1380 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1381   let Latency = 7;
1382   let NumMicroOps = 3;
1383   let ResourceCycles = [2,1];
1384 }
1385 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
1386                                              "VPERMI2W256rr",
1387                                              "VPERMI2Wrr",
1388                                              "VPERMT2W128rr",
1389                                              "VPERMT2W256rr",
1390                                              "VPERMT2Wrr")>;
1391
1392 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1393   let Latency = 7;
1394   let NumMicroOps = 3;
1395   let ResourceCycles = [1,2];
1396 }
1397 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
1398                                           SCASB, SCASL, SCASQ, SCASW)>;
1399
1400 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
1401   let Latency = 7;
1402   let NumMicroOps = 3;
1403   let ResourceCycles = [1,1,1];
1404 }
1405 def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1406                                               "(V?)CVTSS2SI64(Z?)rr",
1407                                               "(V?)CVTTSS2SI64(Z?)rr",
1408                                               "VCVTTSS2USI64Zrr")>;
1409
1410 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
1411   let Latency = 7;
1412   let NumMicroOps = 3;
1413   let ResourceCycles = [1,1,1];
1414 }
1415 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
1416
1417 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
1418   let Latency = 7;
1419   let NumMicroOps = 3;
1420   let ResourceCycles = [1,1,1];
1421 }
1422 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
1423
1424 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
1425   let Latency = 7;
1426   let NumMicroOps = 3;
1427   let ResourceCycles = [1,1,1];
1428 }
1429 def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>;
1430
1431 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1432   let Latency = 7;
1433   let NumMicroOps = 4;
1434   let ResourceCycles = [1,2,1];
1435 }
1436 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1437                                               "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1438                                               "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1439                                               "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1440
1441 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1442   let Latency = 7;
1443   let NumMicroOps = 5;
1444   let ResourceCycles = [1,1,1,2];
1445 }
1446 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1447                                               "ROR(8|16|32|64)m(1|i)")>;
1448
1449 def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> {
1450   let Latency = 2;
1451   let NumMicroOps = 2;
1452   let ResourceCycles = [2];
1453 }
1454 def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1455                                              ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1456
1457 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1458   let Latency = 7;
1459   let NumMicroOps = 5;
1460   let ResourceCycles = [1,1,1,2];
1461 }
1462 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
1463
1464 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
1465   let Latency = 7;
1466   let NumMicroOps = 5;
1467   let ResourceCycles = [1,1,1,1,1];
1468 }
1469 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
1470 def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64m)>;
1471
1472 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1473   let Latency = 7;
1474   let NumMicroOps = 7;
1475   let ResourceCycles = [1,2,2,2];
1476 }
1477 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
1478                                            VPSCATTERQQZ128mr,
1479                                            VSCATTERDPDZ128mr,
1480                                            VSCATTERQPDZ128mr)>;
1481
1482 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
1483   let Latency = 7;
1484   let NumMicroOps = 7;
1485   let ResourceCycles = [1,3,1,2];
1486 }
1487 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
1488
1489 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1490   let Latency = 7;
1491   let NumMicroOps = 11;
1492   let ResourceCycles = [1,4,4,2];
1493 }
1494 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
1495                                            VPSCATTERQQZ256mr,
1496                                            VSCATTERDPDZ256mr,
1497                                            VSCATTERQPDZ256mr)>;
1498
1499 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1500   let Latency = 7;
1501   let NumMicroOps = 19;
1502   let ResourceCycles = [1,8,8,2];
1503 }
1504 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
1505                                            VPSCATTERQQZmr,
1506                                            VSCATTERDPDZmr,
1507                                            VSCATTERQPDZmr)>;
1508
1509 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1510   let Latency = 7;
1511   let NumMicroOps = 36;
1512   let ResourceCycles = [1,16,1,16,2];
1513 }
1514 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
1515
1516 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
1517   let Latency = 8;
1518   let NumMicroOps = 2;
1519   let ResourceCycles = [1,1];
1520 }
1521 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
1522                                               "PEXT(32|64)rm")>;
1523
1524 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1525   let Latency = 8;
1526   let NumMicroOps = 2;
1527   let ResourceCycles = [1,1];
1528 }
1529 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
1530                                               "VPBROADCASTB(Z|Z256)rm(b?)",
1531                                               "VPBROADCASTW(Z|Z256)rm(b?)")>;
1532 def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,
1533                                            VPBROADCASTWYrm,
1534                                            VPMOVSXBDYrm,
1535                                            VPMOVSXBQYrm,
1536                                            VPMOVSXWQYrm)>;
1537
1538 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1539   let Latency = 8;
1540   let NumMicroOps = 2;
1541   let ResourceCycles = [1,1];
1542 }
1543 def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
1544                                            VPBLENDDYrmi)>;
1545 def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],
1546                                    (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1547                                               "VBLENDMPS(Z|Z256)rm(b?)",
1548                                               "VBROADCASTF32X2Z256rm(b?)",
1549                                               "VBROADCASTF32X2Zrm(b?)",
1550                                               "VBROADCASTF32X4Z256rm(b?)",
1551                                               "VBROADCASTF32X4rm(b?)",
1552                                               "VBROADCASTF32X8rm(b?)",
1553                                               "VBROADCASTF64X2Z128rm(b?)",
1554                                               "VBROADCASTF64X2rm(b?)",
1555                                               "VBROADCASTF64X4rm(b?)",
1556                                               "VBROADCASTI32X2Z256rm(b?)",
1557                                               "VBROADCASTI32X2Zrm(b?)",
1558                                               "VBROADCASTI32X4Z256rm(b?)",
1559                                               "VBROADCASTI32X4rm(b?)",
1560                                               "VBROADCASTI32X8rm(b?)",
1561                                               "VBROADCASTI64X2Z128rm(b?)",
1562                                               "VBROADCASTI64X2rm(b?)",
1563                                               "VBROADCASTI64X4rm(b?)",
1564                                               "VBROADCASTSD(Z|Z256)rm(b?)",
1565                                               "VBROADCASTSS(Z|Z256)rm(b?)",
1566                                               "VINSERTF32x4(Z|Z256)rm(b?)",
1567                                               "VINSERTF32x8Zrm(b?)",
1568                                               "VINSERTF64x2(Z|Z256)rm(b?)",
1569                                               "VINSERTF64x4Zrm(b?)",
1570                                               "VINSERTI32x4(Z|Z256)rm(b?)",
1571                                               "VINSERTI32x8Zrm(b?)",
1572                                               "VINSERTI64x2(Z|Z256)rm(b?)",
1573                                               "VINSERTI64x4Zrm(b?)",
1574                                               "VMOVAPD(Z|Z256)rm(b?)",
1575                                               "VMOVAPS(Z|Z256)rm(b?)",
1576                                               "VMOVDDUP(Z|Z256)rm(b?)",
1577                                               "VMOVDQA32(Z|Z256)rm(b?)",
1578                                               "VMOVDQA64(Z|Z256)rm(b?)",
1579                                               "VMOVDQU16(Z|Z256)rm(b?)",
1580                                               "VMOVDQU32(Z|Z256)rm(b?)",
1581                                               "VMOVDQU64(Z|Z256)rm(b?)",
1582                                               "VMOVDQU8(Z|Z256)rm(b?)",
1583                                               "VMOVSHDUP(Z|Z256)rm(b?)",
1584                                               "VMOVSLDUP(Z|Z256)rm(b?)",
1585                                               "VMOVUPD(Z|Z256)rm(b?)",
1586                                               "VMOVUPS(Z|Z256)rm(b?)",
1587                                               "VPADD(B|D|Q|W)Yrm",
1588                                               "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1589                                               "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1590                                               "VPBROADCASTD(Z|Z256)rm(b?)",
1591                                               "VPBROADCASTQ(Z|Z256)rm(b?)",
1592                                               "VPSUB(B|D|Q|W)Yrm",
1593                                               "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1594                                               "VPTERNLOGD(Z|Z256)rm(b?)i",
1595                                               "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1596
1597 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1598   let Latency = 8;
1599   let NumMicroOps = 4;
1600   let ResourceCycles = [1,2,1];
1601 }
1602 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1603
1604 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1605   let Latency = 8;
1606   let NumMicroOps = 5;
1607   let ResourceCycles = [1,1,1,2];
1608 }
1609 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
1610                                               "RCR(8|16|32|64)m(1|i)")>;
1611
1612 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1613   let Latency = 8;
1614   let NumMicroOps = 6;
1615   let ResourceCycles = [1,1,1,3];
1616 }
1617 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
1618                                               "ROR(8|16|32|64)mCL",
1619                                               "SAR(8|16|32|64)mCL",
1620                                               "SHL(8|16|32|64)mCL",
1621                                               "SHR(8|16|32|64)mCL")>;
1622
1623 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1624   let Latency = 8;
1625   let NumMicroOps = 6;
1626   let ResourceCycles = [1,1,1,2,1];
1627 }
1628 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
1629
1630 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1631   let Latency = 8;
1632   let NumMicroOps = 8;
1633   let ResourceCycles = [1,2,1,2,2];
1634 }
1635 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
1636                                            VPSCATTERQDZ256mr,
1637                                            VSCATTERQPSZ128mr,
1638                                            VSCATTERQPSZ256mr)>;
1639
1640 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1641   let Latency = 8;
1642   let NumMicroOps = 12;
1643   let ResourceCycles = [1,4,1,4,2];
1644 }
1645 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
1646                                            VSCATTERDPSZ128mr)>;
1647
1648 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1649   let Latency = 8;
1650   let NumMicroOps = 20;
1651   let ResourceCycles = [1,8,1,8,2];
1652 }
1653 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
1654                                            VSCATTERDPSZ256mr)>;
1655
1656 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1657   let Latency = 8;
1658   let NumMicroOps = 36;
1659   let ResourceCycles = [1,16,1,16,2];
1660 }
1661 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
1662
1663 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1664   let Latency = 9;
1665   let NumMicroOps = 2;
1666   let ResourceCycles = [1,1];
1667 }
1668 def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>;
1669
1670 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1671   let Latency = 9;
1672   let NumMicroOps = 2;
1673   let ResourceCycles = [1,1];
1674 }
1675 def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,
1676                                            VPMOVSXDQYrm,
1677                                            VPMOVSXWDYrm,
1678                                            VPMOVZXWDYrm)>;
1679 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
1680                                               "VFPCLASSSDZrm(b?)",
1681                                               "VFPCLASSSSZrm(b?)",
1682                                               "(V?)PCMPGTQrm",
1683                                               "VPERMI2D128rm(b?)",
1684                                               "VPERMI2PD128rm(b?)",
1685                                               "VPERMI2PS128rm(b?)",
1686                                               "VPERMI2Q128rm(b?)",
1687                                               "VPERMT2D128rm(b?)",
1688                                               "VPERMT2PD128rm(b?)",
1689                                               "VPERMT2PS128rm(b?)",
1690                                               "VPERMT2Q128rm(b?)",
1691                                               "VPMAXSQZ128rm(b?)",
1692                                               "VPMAXUQZ128rm(b?)",
1693                                               "VPMINSQZ128rm(b?)",
1694                                               "VPMINUQZ128rm(b?)",
1695                                               "VPMOVSXBDZ128rm(b?)",
1696                                               "VPMOVSXBQZ128rm(b?)",
1697                                               "VPMOVSXBWZ128rm(b?)",
1698                                               "VPMOVSXDQZ128rm(b?)",
1699                                               "VPMOVSXWDZ128rm(b?)",
1700                                               "VPMOVSXWQZ128rm(b?)",
1701                                               "VPMOVZXBDZ128rm(b?)",
1702                                               "VPMOVZXBQZ128rm(b?)",
1703                                               "VPMOVZXBWZ128rm(b?)",
1704                                               "VPMOVZXDQZ128rm(b?)",
1705                                               "VPMOVZXWDZ128rm(b?)",
1706                                               "VPMOVZXWQZ128rm(b?)")>;
1707
1708 def SKXWriteResGroup136_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1709   let Latency = 10;
1710   let NumMicroOps = 2;
1711   let ResourceCycles = [1,1];
1712 }
1713 def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
1714                                                 "VCMP(SD|SS)Zrm",
1715                                                 "VFPCLASSPDZ128rm(b?)",
1716                                                 "VFPCLASSPSZ128rm(b?)",
1717                                                 "VPCMPBZ128rmi(b?)",
1718                                                 "VPCMPDZ128rmi(b?)",
1719                                                 "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
1720                                                 "VPCMPGT(B|D|Q|W)Z128rm(b?)",
1721                                                 "VPCMPQZ128rmi(b?)",
1722                                                 "VPCMPU(B|D|Q|W)Z128rmi(b?)",
1723                                                 "VPCMPWZ128rmi(b?)",
1724                                                 "VPTESTMBZ128rm(b?)",
1725                                                 "VPTESTMDZ128rm(b?)",
1726                                                 "VPTESTMQZ128rm(b?)",
1727                                                 "VPTESTMWZ128rm(b?)",
1728                                                 "VPTESTNMBZ128rm(b?)",
1729                                                 "VPTESTNMDZ128rm(b?)",
1730                                                 "VPTESTNMQZ128rm(b?)",
1731                                                 "VPTESTNMWZ128rm(b?)")>;
1732
1733 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1734   let Latency = 9;
1735   let NumMicroOps = 2;
1736   let ResourceCycles = [1,1];
1737 }
1738 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1739                                               "(V?)CVTPS2PDrm")>;
1740
1741 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1742   let Latency = 9;
1743   let NumMicroOps = 4;
1744   let ResourceCycles = [2,1,1];
1745 }
1746 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
1747                                               "(V?)PHSUBSWrm")>;
1748
1749 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
1750   let Latency = 9;
1751   let NumMicroOps = 5;
1752   let ResourceCycles = [1,2,1,1];
1753 }
1754 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
1755                                               "LSL(16|32|64)rm")>;
1756
1757 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1758   let Latency = 10;
1759   let NumMicroOps = 2;
1760   let ResourceCycles = [1,1];
1761 }
1762 def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;
1763 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1764                                               "ILD_F(16|32|64)m",
1765                                               "VALIGND(Z|Z256)rm(b?)i",
1766                                               "VALIGNQ(Z|Z256)rm(b?)i",
1767                                               "VPMAXSQ(Z|Z256)rm(b?)",
1768                                               "VPMAXUQ(Z|Z256)rm(b?)",
1769                                               "VPMINSQ(Z|Z256)rm(b?)",
1770                                               "VPMINUQ(Z|Z256)rm(b?)")>;
1771
1772 def SKXWriteResGroup148_2 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1773   let Latency = 11;
1774   let NumMicroOps = 2;
1775   let ResourceCycles = [1,1];
1776 }
1777 def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
1778                                                 "VCMPPS(Z|Z256)rm(b?)i",
1779                                                 "VFPCLASSPD(Z|Z256)rm(b?)",
1780                                                 "VFPCLASSPS(Z|Z256)rm(b?)",
1781                                                 "VPCMPB(Z|Z256)rmi(b?)",
1782                                                 "VPCMPD(Z|Z256)rmi(b?)",
1783                                                 "VPCMPEQB(Z|Z256)rm(b?)",
1784                                                 "VPCMPEQD(Z|Z256)rm(b?)",
1785                                                 "VPCMPEQQ(Z|Z256)rm(b?)",
1786                                                 "VPCMPEQW(Z|Z256)rm(b?)",
1787                                                 "VPCMPGTB(Z|Z256)rm(b?)",
1788                                                 "VPCMPGTD(Z|Z256)rm(b?)",
1789                                                 "VPCMPGTQ(Z|Z256)rm(b?)",
1790                                                 "VPCMPGTW(Z|Z256)rm(b?)",
1791                                                 "VPCMPQ(Z|Z256)rmi(b?)",
1792                                                 "VPCMPU(B|D|Q|W)Z256rmi(b?)",
1793                                                 "VPCMPU(B|D|Q|W)Zrmi(b?)",
1794                                                 "VPCMPW(Z|Z256)rmi(b?)",
1795                                                 "VPTESTM(B|D|Q|W)Z256rm(b?)",
1796                                                 "VPTESTM(B|D|Q|W)Zrm(b?)",
1797                                                 "VPTESTNM(B|D|Q|W)Z256rm(b?)",
1798                                                 "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
1799
1800 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1801   let Latency = 10;
1802   let NumMicroOps = 2;
1803   let ResourceCycles = [1,1];
1804 }
1805 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
1806                                               "VCVTDQ2PSZ128rm(b?)",
1807                                               "(V?)CVTDQ2PSrm",
1808                                               "VCVTPD2QQZ128rm(b?)",
1809                                               "VCVTPD2UQQZ128rm(b?)",
1810                                               "VCVTPH2PSZ128rm(b?)",
1811                                               "VCVTPS2DQZ128rm(b?)",
1812                                               "(V?)CVTPS2DQrm",
1813                                               "VCVTPS2PDZ128rm(b?)",
1814                                               "VCVTPS2QQZ128rm(b?)",
1815                                               "VCVTPS2UDQZ128rm(b?)",
1816                                               "VCVTPS2UQQZ128rm(b?)",
1817                                               "VCVTQQ2PDZ128rm(b?)",
1818                                               "VCVTQQ2PSZ128rm(b?)",
1819                                               "VCVTSS2SDZrm",
1820                                               "(V?)CVTSS2SDrm",
1821                                               "VCVTTPD2QQZ128rm(b?)",
1822                                               "VCVTTPD2UQQZ128rm(b?)",
1823                                               "VCVTTPS2DQZ128rm(b?)",
1824                                               "(V?)CVTTPS2DQrm",
1825                                               "VCVTTPS2QQZ128rm(b?)",
1826                                               "VCVTTPS2UDQZ128rm(b?)",
1827                                               "VCVTTPS2UQQZ128rm(b?)",
1828                                               "VCVTUDQ2PDZ128rm(b?)",
1829                                               "VCVTUDQ2PSZ128rm(b?)",
1830                                               "VCVTUQQ2PDZ128rm(b?)",
1831                                               "VCVTUQQ2PSZ128rm(b?)")>;
1832
1833 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1834   let Latency = 10;
1835   let NumMicroOps = 3;
1836   let ResourceCycles = [2,1];
1837 }
1838 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
1839                                               "VEXPANDPSZ128rm(b?)",
1840                                               "VPEXPANDDZ128rm(b?)",
1841                                               "VPEXPANDQZ128rm(b?)")>;
1842
1843 def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1844   let Latency = 10;
1845   let NumMicroOps = 3;
1846   let ResourceCycles = [1,1,1];
1847 }
1848 def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>;
1849
1850 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1851   let Latency = 10;
1852   let NumMicroOps = 4;
1853   let ResourceCycles = [2,1,1];
1854 }
1855 def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
1856                                            VPHSUBSWYrm)>;
1857
1858 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1859   let Latency = 10;
1860   let NumMicroOps = 8;
1861   let ResourceCycles = [1,1,1,1,1,3];
1862 }
1863 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
1864
1865 def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
1866   let Latency = 11;
1867   let NumMicroOps = 1;
1868   let ResourceCycles = [1,3];
1869 }
1870 def : SchedAlias<WriteFDivX,  SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair
1871
1872 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1873   let Latency = 11;
1874   let NumMicroOps = 2;
1875   let ResourceCycles = [1,1];
1876 }
1877 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
1878
1879 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1880   let Latency = 11;
1881   let NumMicroOps = 2;
1882   let ResourceCycles = [1,1];
1883 }
1884 def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,
1885                                            VCVTPS2PDYrm)>;
1886 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
1887                                               "VCVTPH2PS(Z|Z256)rm(b?)",
1888                                               "VCVTPS2PD(Z|Z256)rm(b?)",
1889                                               "VCVTQQ2PD(Z|Z256)rm(b?)",
1890                                               "VCVTQQ2PSZ256rm(b?)",
1891                                               "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1892                                               "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1893                                               "VCVT(T?)PS2DQYrm",
1894                                               "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1895                                               "VCVT(T?)PS2QQZ256rm(b?)",
1896                                               "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1897                                               "VCVT(T?)PS2UQQZ256rm(b?)",
1898                                               "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
1899                                               "VCVTUQQ2PD(Z|Z256)rm(b?)",
1900                                               "VCVTUQQ2PSZ256rm(b?)")>;
1901
1902 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1903   let Latency = 11;
1904   let NumMicroOps = 3;
1905   let ResourceCycles = [2,1];
1906 }
1907 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
1908                                               "VEXPANDPD(Z|Z256)rm(b?)",
1909                                               "VEXPANDPS(Z|Z256)rm(b?)",
1910                                               "VPEXPANDD(Z|Z256)rm(b?)",
1911                                               "VPEXPANDQ(Z|Z256)rm(b?)")>;
1912
1913 def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1914   let Latency = 11;
1915   let NumMicroOps = 3;
1916   let ResourceCycles = [1,2];
1917 }
1918 def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>;
1919
1920 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1921   let Latency = 11;
1922   let NumMicroOps = 3;
1923   let ResourceCycles = [1,1,1];
1924 }
1925 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
1926
1927 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1928   let Latency = 11;
1929   let NumMicroOps = 3;
1930   let ResourceCycles = [1,1,1];
1931 }
1932 def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm,
1933                                            CVTPD2DQrm,
1934                                            CVTTPD2DQrm,
1935                                            MMX_CVTPD2PIirm,
1936                                            MMX_CVTTPD2PIirm)>;
1937
1938 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1939   let Latency = 11;
1940   let NumMicroOps = 4;
1941   let ResourceCycles = [2,1,1];
1942 }
1943 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
1944
1945 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1946   let Latency = 11;
1947   let NumMicroOps = 7;
1948   let ResourceCycles = [2,3,2];
1949 }
1950 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
1951                                               "RCR(16|32|64)rCL")>;
1952
1953 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
1954   let Latency = 11;
1955   let NumMicroOps = 9;
1956   let ResourceCycles = [1,5,1,2];
1957 }
1958 def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;
1959
1960 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1961   let Latency = 11;
1962   let NumMicroOps = 11;
1963   let ResourceCycles = [2,9];
1964 }
1965 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
1966
1967 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
1968   let Latency = 15;
1969   let NumMicroOps = 3;
1970   let ResourceCycles = [3];
1971 }
1972 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
1973
1974 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
1975   let Latency = 15;
1976   let NumMicroOps = 3;
1977   let ResourceCycles = [3];
1978 }
1979 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
1980
1981 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1982   let Latency = 12;
1983   let NumMicroOps = 3;
1984   let ResourceCycles = [2,1];
1985 }
1986 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
1987
1988 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
1989   let Latency = 12;
1990   let NumMicroOps = 3;
1991   let ResourceCycles = [1,1,1];
1992 }
1993 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
1994                                               "VCVT(T?)SS2USI64Zrm(b?)")>;
1995
1996 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1997   let Latency = 12;
1998   let NumMicroOps = 3;
1999   let ResourceCycles = [1,1,1];
2000 }
2001 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
2002                                               "VCVT(T?)PS2UQQZrm(b?)")>;
2003
2004 def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
2005   let Latency = 12;
2006   let NumMicroOps = 4;
2007   let ResourceCycles = [1,1,1,1];
2008 }
2009 def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
2010
2011 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
2012   let Latency = 13;
2013   let NumMicroOps = 3;
2014   let ResourceCycles = [2,1];
2015 }
2016 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
2017                                               "VPERMWZ256rm(b?)",
2018                                               "VPERMWZrm(b?)")>;
2019
2020 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2021   let Latency = 13;
2022   let NumMicroOps = 3;
2023   let ResourceCycles = [1,1,1];
2024 }
2025 def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
2026
2027 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2028   let Latency = 13;
2029   let NumMicroOps = 4;
2030   let ResourceCycles = [2,1,1];
2031 }
2032 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
2033                                               "VPERMT2W128rm(b?)")>;
2034
2035 def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2036   let Latency = 14;
2037   let NumMicroOps = 1;
2038   let ResourceCycles = [1,3];
2039 }
2040 def : SchedAlias<WriteFDiv64,  SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2041 def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2042
2043 def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2044   let Latency = 14;
2045   let NumMicroOps = 1;
2046   let ResourceCycles = [1,5];
2047 }
2048 def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair
2049
2050 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2051   let Latency = 14;
2052   let NumMicroOps = 3;
2053   let ResourceCycles = [1,1,1];
2054 }
2055 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
2056
2057 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2058   let Latency = 14;
2059   let NumMicroOps = 3;
2060   let ResourceCycles = [1,1,1];
2061 }
2062 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
2063                                               "VCVTPD2PSZrm(b?)",
2064                                               "VCVTPD2UDQZrm(b?)",
2065                                               "VCVTQQ2PSZrm(b?)",
2066                                               "VCVTTPD2DQZrm(b?)",
2067                                               "VCVTTPD2UDQZrm(b?)",
2068                                               "VCVTUQQ2PSZrm(b?)")>;
2069
2070 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2071   let Latency = 14;
2072   let NumMicroOps = 4;
2073   let ResourceCycles = [2,1,1];
2074 }
2075 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
2076                                               "VPERMI2Wrm(b?)",
2077                                               "VPERMT2W256rm(b?)",
2078                                               "VPERMT2Wrm(b?)")>;
2079
2080 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2081   let Latency = 14;
2082   let NumMicroOps = 10;
2083   let ResourceCycles = [2,4,1,3];
2084 }
2085 def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;
2086
2087 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
2088   let Latency = 15;
2089   let NumMicroOps = 1;
2090   let ResourceCycles = [1];
2091 }
2092 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
2093
2094 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2095   let Latency = 15;
2096   let NumMicroOps = 8;
2097   let ResourceCycles = [1,2,2,1,2];
2098 }
2099 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
2100
2101 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2102   let Latency = 15;
2103   let NumMicroOps = 10;
2104   let ResourceCycles = [1,1,1,5,1,1];
2105 }
2106 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
2107
2108 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2109   let Latency = 16;
2110   let NumMicroOps = 14;
2111   let ResourceCycles = [1,1,1,4,2,5];
2112 }
2113 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
2114
2115 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> {
2116   let Latency = 12;
2117   let NumMicroOps = 34;
2118   let ResourceCycles = [1, 4, 5];
2119 }
2120 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
2121
2122 def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2123   let Latency = 17;
2124   let NumMicroOps = 2;
2125   let ResourceCycles = [1,1,5];
2126 }
2127 def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair
2128
2129 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2130   let Latency = 17;
2131   let NumMicroOps = 15;
2132   let ResourceCycles = [2,1,2,4,2,4];
2133 }
2134 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
2135
2136 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort01]> {
2137   let Latency = 21;
2138   let NumMicroOps = 4;
2139   let ResourceCycles = [1,3];
2140 }
2141 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
2142
2143 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2144   let Latency = 18;
2145   let NumMicroOps = 8;
2146   let ResourceCycles = [1,1,1,5];
2147 }
2148 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
2149
2150 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2151   let Latency = 18;
2152   let NumMicroOps = 11;
2153   let ResourceCycles = [2,1,1,4,1,2];
2154 }
2155 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
2156
2157 def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2158   let Latency = 19;
2159   let NumMicroOps = 2;
2160   let ResourceCycles = [1,1,4];
2161 }
2162 def : SchedAlias<WriteFDiv64Ld,  SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair
2163
2164 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort01]> {
2165   let Latency = 22;
2166   let NumMicroOps = 4;
2167   let ResourceCycles = [1,3];
2168 }
2169 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>;
2170
2171 def SKXWriteResGroup211_1 : SchedWriteRes<[SKXPort23,SKXPort05]> {
2172   let Latency = 22;
2173   let NumMicroOps = 4;
2174   let ResourceCycles = [1,3];
2175 }
2176 def: InstRW<[SKXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>;
2177
2178 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
2179   let Latency = 20;
2180   let NumMicroOps = 1;
2181   let ResourceCycles = [1];
2182 }
2183 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
2184
2185 def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2186   let Latency = 20;
2187   let NumMicroOps = 2;
2188   let ResourceCycles = [1,1,4];
2189 }
2190 def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair
2191
2192 def SKXWriteGatherEVEX2 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2193   let Latency = 17;
2194   let NumMicroOps = 5; // 2 uops perform multiple loads
2195   let ResourceCycles = [1,2,1,1];
2196 }
2197 def: InstRW<[SKXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm,
2198                                            VGATHERDPDZ128rm, VPGATHERDQZ128rm,
2199                                            VGATHERQPDZ128rm, VPGATHERQQZ128rm)>;
2200
2201 def SKXWriteGatherEVEX4 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2202   let Latency = 19;
2203   let NumMicroOps = 5; // 2 uops perform multiple loads
2204   let ResourceCycles = [1,4,1,1];
2205 }
2206 def: InstRW<[SKXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm,
2207                                            VGATHERQPDZ256rm, VPGATHERQQZ256rm,
2208                                            VGATHERDPSZ128rm, VPGATHERDDZ128rm,
2209                                            VGATHERDPDZ256rm, VPGATHERDQZ256rm)>;
2210
2211 def SKXWriteGatherEVEX8 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2212   let Latency = 21;
2213   let NumMicroOps = 5; // 2 uops perform multiple loads
2214   let ResourceCycles = [1,8,1,1];
2215 }
2216 def: InstRW<[SKXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm,
2217                                            VGATHERDPDZrm,    VPGATHERDQZrm,
2218                                            VGATHERQPDZrm,    VPGATHERQQZrm,
2219                                            VGATHERQPSZrm,    VPGATHERQDZrm)>;
2220
2221 def SKXWriteGatherEVEX16 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2222   let Latency = 25;
2223   let NumMicroOps = 5; // 2 uops perform multiple loads
2224   let ResourceCycles = [1,16,1,1];
2225 }
2226 def: InstRW<[SKXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>;
2227
2228 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2229   let Latency = 20;
2230   let NumMicroOps = 8;
2231   let ResourceCycles = [1,1,1,1,1,1,2];
2232 }
2233 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
2234
2235 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
2236   let Latency = 20;
2237   let NumMicroOps = 10;
2238   let ResourceCycles = [1,2,7];
2239 }
2240 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
2241
2242 def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2243   let Latency = 21;
2244   let NumMicroOps = 2;
2245   let ResourceCycles = [1,1,8];
2246 }
2247 def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair
2248
2249 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2250   let Latency = 22;
2251   let NumMicroOps = 2;
2252   let ResourceCycles = [1,1];
2253 }
2254 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
2255
2256 def SKXWriteResGroupVEX2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2257   let Latency = 18;
2258   let NumMicroOps = 5; // 2 uops perform multiple loads
2259   let ResourceCycles = [1,2,1,1];
2260 }
2261 def: InstRW<[SKXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
2262                                             VGATHERQPDrm, VPGATHERQQrm,
2263                                             VGATHERQPSrm, VPGATHERQDrm)>;
2264
2265 def SKXWriteResGroupVEX4 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2266   let Latency = 20;
2267   let NumMicroOps = 5; // 2 uops peform multiple loads
2268   let ResourceCycles = [1,4,1,1];
2269 }
2270 def: InstRW<[SKXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
2271                                             VGATHERDPSrm,  VPGATHERDDrm,
2272                                             VGATHERQPDYrm, VPGATHERQQYrm,
2273                                             VGATHERQPSYrm,  VPGATHERQDYrm)>;
2274
2275 def SKXWriteResGroupVEX8 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2276   let Latency = 22;
2277   let NumMicroOps = 5; // 2 uops perform multiple loads
2278   let ResourceCycles = [1,8,1,1];
2279 }
2280 def: InstRW<[SKXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
2281
2282 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2283   let Latency = 22;
2284   let NumMicroOps = 14;
2285   let ResourceCycles = [5,5,4];
2286 }
2287 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
2288                                               "VPCONFLICTQZ256rr")>;
2289
2290 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2291   let Latency = 23;
2292   let NumMicroOps = 19;
2293   let ResourceCycles = [2,1,4,1,1,4,6];
2294 }
2295 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
2296
2297 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2298   let Latency = 25;
2299   let NumMicroOps = 3;
2300   let ResourceCycles = [1,1,1];
2301 }
2302 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
2303
2304 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2305   let Latency = 27;
2306   let NumMicroOps = 2;
2307   let ResourceCycles = [1,1];
2308 }
2309 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
2310
2311 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2312   let Latency = 29;
2313   let NumMicroOps = 15;
2314   let ResourceCycles = [5,5,1,4];
2315 }
2316 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
2317
2318 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2319   let Latency = 30;
2320   let NumMicroOps = 3;
2321   let ResourceCycles = [1,1,1];
2322 }
2323 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
2324
2325 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
2326   let Latency = 35;
2327   let NumMicroOps = 23;
2328   let ResourceCycles = [1,5,3,4,10];
2329 }
2330 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
2331                                               "IN(8|16|32)rr")>;
2332
2333 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2334   let Latency = 35;
2335   let NumMicroOps = 23;
2336   let ResourceCycles = [1,5,2,1,4,10];
2337 }
2338 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
2339                                               "OUT(8|16|32)rr")>;
2340
2341 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2342   let Latency = 37;
2343   let NumMicroOps = 21;
2344   let ResourceCycles = [9,7,5];
2345 }
2346 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
2347                                               "VPCONFLICTQZrr")>;
2348
2349 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
2350   let Latency = 37;
2351   let NumMicroOps = 31;
2352   let ResourceCycles = [1,8,1,21];
2353 }
2354 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
2355
2356 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
2357   let Latency = 40;
2358   let NumMicroOps = 18;
2359   let ResourceCycles = [1,1,2,3,1,1,1,8];
2360 }
2361 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
2362
2363 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2364   let Latency = 41;
2365   let NumMicroOps = 39;
2366   let ResourceCycles = [1,10,1,1,26];
2367 }
2368 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
2369
2370 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
2371   let Latency = 42;
2372   let NumMicroOps = 22;
2373   let ResourceCycles = [2,20];
2374 }
2375 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
2376
2377 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2378   let Latency = 42;
2379   let NumMicroOps = 40;
2380   let ResourceCycles = [1,11,1,1,26];
2381 }
2382 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
2383 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
2384
2385 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2386   let Latency = 44;
2387   let NumMicroOps = 22;
2388   let ResourceCycles = [9,7,1,5];
2389 }
2390 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
2391                                               "VPCONFLICTQZrm(b?)")>;
2392
2393 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
2394   let Latency = 62;
2395   let NumMicroOps = 64;
2396   let ResourceCycles = [2,8,5,10,39];
2397 }
2398 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
2399
2400 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2401   let Latency = 63;
2402   let NumMicroOps = 88;
2403   let ResourceCycles = [4,4,31,1,2,1,45];
2404 }
2405 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
2406
2407 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2408   let Latency = 63;
2409   let NumMicroOps = 90;
2410   let ResourceCycles = [4,2,33,1,2,1,47];
2411 }
2412 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
2413
2414 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2415   let Latency = 67;
2416   let NumMicroOps = 35;
2417   let ResourceCycles = [17,11,7];
2418 }
2419 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
2420
2421 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2422   let Latency = 74;
2423   let NumMicroOps = 36;
2424   let ResourceCycles = [17,11,1,7];
2425 }
2426 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
2427
2428 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
2429   let Latency = 75;
2430   let NumMicroOps = 15;
2431   let ResourceCycles = [6,3,6];
2432 }
2433 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
2434
2435 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
2436   let Latency = 106;
2437   let NumMicroOps = 100;
2438   let ResourceCycles = [9,1,11,16,1,11,21,30];
2439 }
2440 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
2441
2442 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
2443   let Latency = 140;
2444   let NumMicroOps = 4;
2445   let ResourceCycles = [1,3];
2446 }
2447 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
2448
2449 def: InstRW<[WriteZero], (instrs CLC)>;
2450
2451
2452 // Instruction variants handled by the renamer. These might not need execution
2453 // ports in certain conditions.
2454 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
2455 // section "Skylake Pipeline" > "Register allocation and renaming".
2456 // These can be investigated with llvm-exegesis, e.g.
2457 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2458 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2459
2460 def SKXWriteZeroLatency : SchedWriteRes<[]> {
2461   let Latency = 0;
2462 }
2463
2464 def SKXWriteZeroIdiom : SchedWriteVariant<[
2465     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2466     SchedVar<NoSchedPred,                          [WriteALU]>
2467 ]>;
2468 def : InstRW<[SKXWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
2469                                           XOR32rr, XOR64rr)>;
2470
2471 def SKXWriteFZeroIdiom : SchedWriteVariant<[
2472     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2473     SchedVar<NoSchedPred,                          [WriteFLogic]>
2474 ]>;
2475 def : InstRW<[SKXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr,
2476                                            XORPDrr, VXORPDrr,
2477                                            VXORPSZ128rr,
2478                                            VXORPDZ128rr)>;
2479
2480 def SKXWriteFZeroIdiomY : SchedWriteVariant<[
2481     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2482     SchedVar<NoSchedPred,                          [WriteFLogicY]>
2483 ]>;
2484 def : InstRW<[SKXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
2485                                             VXORPSZ256rr, VXORPDZ256rr)>;
2486
2487 def SKXWriteFZeroIdiomZ : SchedWriteVariant<[
2488     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2489     SchedVar<NoSchedPred,                          [WriteFLogicZ]>
2490 ]>;
2491 def : InstRW<[SKXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>;
2492
2493 def SKXWriteVZeroIdiomLogicX : SchedWriteVariant<[
2494     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2495     SchedVar<NoSchedPred,                          [WriteVecLogicX]>
2496 ]>;
2497 def : InstRW<[SKXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr,
2498                                                  VPXORDZ128rr, VPXORQZ128rr)>;
2499
2500 def SKXWriteVZeroIdiomLogicY : SchedWriteVariant<[
2501     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2502     SchedVar<NoSchedPred,                          [WriteVecLogicY]>
2503 ]>;
2504 def : InstRW<[SKXWriteVZeroIdiomLogicY], (instrs VPXORYrr,
2505                                                  VPXORDZ256rr, VPXORQZ256rr)>;
2506
2507 def SKXWriteVZeroIdiomLogicZ : SchedWriteVariant<[
2508     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2509     SchedVar<NoSchedPred,                          [WriteVecLogicZ]>
2510 ]>;
2511 def : InstRW<[SKXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>;
2512
2513 def SKXWriteVZeroIdiomALUX : SchedWriteVariant<[
2514     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2515     SchedVar<NoSchedPred,                          [WriteVecALUX]>
2516 ]>;
2517 def : InstRW<[SKXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
2518                                                PCMPGTDrr, VPCMPGTDrr,
2519                                                PCMPGTWrr, VPCMPGTWrr)>;
2520
2521 def SKXWriteVZeroIdiomALUY : SchedWriteVariant<[
2522     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2523     SchedVar<NoSchedPred,                          [WriteVecALUY]>
2524 ]>;
2525 def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
2526                                                VPCMPGTDYrr,
2527                                                VPCMPGTWYrr)>;
2528
2529 def SKXWritePSUB : SchedWriteRes<[SKXPort015]> {
2530   let Latency = 1;
2531   let NumMicroOps = 1;
2532   let ResourceCycles = [1];
2533 }
2534
2535 def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[
2536     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2537     SchedVar<NoSchedPred,                          [SKXWritePSUB]>
2538 ]>;
2539
2540 def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,
2541                                                PSUBDrr, VPSUBDrr, VPSUBDZ128rr,
2542                                                PSUBQrr, VPSUBQrr, VPSUBQZ128rr,
2543                                                PSUBWrr, VPSUBWrr, VPSUBWZ128rr,
2544                                                VPSUBBYrr, VPSUBBZ256rr,
2545                                                VPSUBDYrr, VPSUBDZ256rr,
2546                                                VPSUBQYrr, VPSUBQZ256rr,
2547                                                VPSUBWYrr, VPSUBWZ256rr,
2548                                                VPSUBBZrr,
2549                                                VPSUBDZrr,
2550                                                VPSUBQZrr,
2551                                                VPSUBWZrr)>;
2552 def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> {
2553   let Latency = 3;
2554   let NumMicroOps = 1;
2555   let ResourceCycles = [1];
2556 }
2557
2558 def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
2559     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2560     SchedVar<NoSchedPred,                          [SKXWritePCMPGTQ]>
2561 ]>;
2562 def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
2563                                                   VPCMPGTQYrr)>;
2564
2565
2566 // CMOVs that use both Z and C flag require an extra uop.
2567 def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> {
2568   let Latency = 2;
2569   let ResourceCycles = [2];
2570   let NumMicroOps = 2;
2571 }
2572
2573 def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> {
2574   let Latency = 7;
2575   let ResourceCycles = [1,2];
2576   let NumMicroOps = 3;
2577 }
2578
2579 def SKXCMOVA_CMOVBErr :  SchedWriteVariant<[
2580   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>,
2581   SchedVar<NoSchedPred,                             [WriteCMOV]>
2582 ]>;
2583
2584 def SKXCMOVA_CMOVBErm :  SchedWriteVariant<[
2585   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>,
2586   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
2587 ]>;
2588
2589 def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
2590 def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
2591
2592 // SETCCs that use both Z and C flag require an extra uop.
2593 def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> {
2594   let Latency = 2;
2595   let ResourceCycles = [2];
2596   let NumMicroOps = 2;
2597 }
2598
2599 def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
2600   let Latency = 3;
2601   let ResourceCycles = [1,1,2];
2602   let NumMicroOps = 4;
2603 }
2604
2605 def SKXSETA_SETBErr :  SchedWriteVariant<[
2606   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>,
2607   SchedVar<NoSchedPred,                         [WriteSETCC]>
2608 ]>;
2609
2610 def SKXSETA_SETBErm :  SchedWriteVariant<[
2611   SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>,
2612   SchedVar<NoSchedPred,                         [WriteSETCCStore]>
2613 ]>;
2614
2615 def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>;
2616 def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>;
2617
2618 } // SchedModel