1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ARM Integrator/AP platform
7 /include/ "integrator.dtsi"
10 model = "ARM Integrator/AP";
11 compatible = "arm,integrator-ap";
12 dma-ranges = <0x80000000 0x0 0x80000000>;
21 * Since the board has pluggable CPU modules, we
22 * cannot define a proper compatible here. Let the
23 * boot loader fill in the apropriate compatible
24 * string if necessary.
26 /* compatible = "arm,arm926ej-s"; */
29 * The documentation in ARM DUI 0138E page 3-12 states
30 * that the maximum frequency for this clock is 200 MHz
31 * but painful trial-and-error has proved to me that it
32 * is actually just hanging the system above 71 MHz.
36 operating-points = <71000 0
45 clock-latency = <1000000>; /* 1 ms */
50 arm,timer-primary = &timer2;
51 arm,timer-secondary = &timer1;
55 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
58 /* 24 MHz chrystal on the Integrator/AP development board */
59 xtal24mhz: xtal24mhz@24M {
61 compatible = "fixed-clock";
62 clock-frequency = <24000000>;
67 compatible = "fixed-factor-clock";
70 clocks = <&xtal24mhz>;
73 /* The UART clock is 14.74 MHz divided by an ICS525 */
74 uartclk: uartclk@14.74M {
76 compatible = "fixed-clock";
77 clock-frequency = <14745600>;
78 clocks = <&xtal24mhz>;
81 core-module@10000000 {
82 /* 24 MHz chrystal on the core module */
83 cm24mhz: cm24mhz@24M {
85 compatible = "fixed-clock";
86 clock-frequency = <24000000>;
89 /* Oscillator on the core module, clocks the CPU core */
91 compatible = "arm,syscon-icst525-integratorap-cm";
98 /* Auxilary oscillator on the core module, 32.369MHz at boot */
100 compatible = "arm,syscon-icst525";
102 lock-offset = <0x14>;
109 compatible = "arm,integrator-ap-syscon", "syscon";
110 reg = <0x11000000 0x100>;
111 interrupt-parent = <&pic>;
112 /* These are the logical module IRQs */
113 interrupts = <9>, <10>, <11>, <12>;
116 * SYSCLK clocks PCIv3 bridge, system controller and the
120 compatible = "arm,syscon-icst525-integratorap-sys";
122 lock-offset = <0x1c>;
124 clocks = <&xtal24mhz>;
127 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
129 compatible = "arm,syscon-icst525-integratorap-pci";
131 lock-offset = <0x1c>;
133 clocks = <&xtal24mhz>;
137 timer0: timer@13000000 {
138 compatible = "arm,integrator-timer";
139 clocks = <&xtal24mhz>;
142 timer1: timer@13000100 {
143 compatible = "arm,integrator-timer";
144 clocks = <&xtal24mhz>;
147 timer2: timer@13000200 {
148 compatible = "arm,integrator-timer";
149 clocks = <&xtal24mhz>;
153 valid-mask = <0x003fffff>;
156 pci: pciv3@62000000 {
157 compatible = "v3,v360epc-pci";
158 #interrupt-cells = <1>;
160 #address-cells = <3>;
161 reg = <0x62000000 0x10000>;
162 interrupt-parent = <&pic>;
163 interrupts = <17>; /* Bus error IRQ */
164 ranges = <0x00000000 0 0x61000000 /* config space */
165 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
166 0x01000000 0 0x0 /* I/O space */
167 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
168 0x02000000 0 0x00000000 /* non-prefectable memory */
169 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
170 0x42000000 0 0x10000000 /* prefetchable memory */
171 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
172 interrupt-map-mask = <0xf800 0 0 0x7>;
175 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
176 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
177 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
178 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
180 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
181 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
182 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
183 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
185 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
186 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
187 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
188 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
190 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
191 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
192 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
193 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
199 * The Integator/AP predates the idea to have magic numbers
200 * identifying the PrimeCell in hardware, thus we have to
201 * supply these from the device tree.
204 compatible = "arm,pl030", "arm,primecell";
205 arm,primecell-periphid = <0x00041030>;
207 clock-names = "apb_pclk";
210 uart0: uart@16000000 {
211 compatible = "arm,pl010", "arm,primecell";
212 arm,primecell-periphid = <0x00041010>;
213 clocks = <&uartclk>, <&pclk>;
214 clock-names = "uartclk", "apb_pclk";
217 uart1: uart@17000000 {
218 compatible = "arm,pl010", "arm,primecell";
219 arm,primecell-periphid = <0x00041010>;
220 clocks = <&uartclk>, <&pclk>;
221 clock-names = "uartclk", "apb_pclk";
225 compatible = "arm,pl050", "arm,primecell";
226 arm,primecell-periphid = <0x00041050>;
227 clocks = <&xtal24mhz>, <&pclk>;
228 clock-names = "KMIREFCLK", "apb_pclk";
232 compatible = "arm,pl050", "arm,primecell";
233 arm,primecell-periphid = <0x00041050>;
234 clocks = <&xtal24mhz>, <&pclk>;
235 clock-names = "KMIREFCLK", "apb_pclk";