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(parent: 4dfb620) | patch
sdhci_fsl_fdt: specify base clk divisor per SoC
authorMarcin Wojtas <mw@FreeBSD.org>
Fri, 7 May 2021 01:45:22 +0000 (03:45 +0200)
committerMarcin Wojtas <mw@FreeBSD.org>
Fri, 7 May 2021 01:48:54 +0000 (03:48 +0200)
commitd5b20eaafc0bd8668e5deb8d2b4043c25df4134b
treef88f068ab387bfc4bab299967c756037b69583fftree | snapshot
parent4dfb620ea4a7a443284bdcf39c8de1f75cd8c80ccommit | diff
sdhci_fsl_fdt: specify base clk divisor per SoC

Only LS1046A and LS1028A require the base clk to be divided by 2.
Implement that by moving the divider to a SoC specific data.
This commit fixes base clk setup for the entire SoC family,
including the already suported LS2160A.

Submitted by: Lukasz Hajec <lha@semihalf.com>
Reviewed by: manu
Obtained from: Semihalf
Sponsored by: Alstom Group
Differential Revision: https://reviews.freebsd.org/D30120
sys/dev/sdhci/sdhci_fsl_fdt.c diff | blob | blame | history
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