2 * Copyright © 2008-2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #include <linux/dma-fence-array.h>
26 #include <linux/irq_work.h>
27 #include <linux/prefetch.h>
28 #include <linux/sched.h>
29 #include <linux/sched/clock.h>
30 #include <linux/sched/signal.h>
32 #include "gem/i915_gem_context.h"
33 #include "gt/intel_context.h"
34 #include "gt/intel_ring.h"
35 #include "gt/intel_rps.h"
37 #include "i915_active.h"
39 #include "i915_globals.h"
40 #include "i915_trace.h"
44 struct list_head link;
46 struct i915_sw_fence *fence;
47 void (*hook)(struct i915_request *rq, struct dma_fence *signal);
48 struct i915_request *signal;
51 static struct i915_global_request {
52 struct i915_global base;
53 struct kmem_cache *slab_requests;
54 struct kmem_cache *slab_dependencies;
55 struct kmem_cache *slab_execute_cbs;
58 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
63 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
66 * The timeline struct (as part of the ppgtt underneath a context)
67 * may be freed when the request is no longer in use by the GPU.
68 * We could extend the life of a context to beyond that of all
69 * fences, possibly keeping the hw resource around indefinitely,
70 * or we just give them a false name. Since
71 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
72 * lie seems justifiable.
74 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
77 return to_request(fence)->gem_context->name ?: "[i915]";
80 static bool i915_fence_signaled(struct dma_fence *fence)
82 return i915_request_completed(to_request(fence));
85 static bool i915_fence_enable_signaling(struct dma_fence *fence)
87 return i915_request_enable_breadcrumb(to_request(fence));
90 static signed long i915_fence_wait(struct dma_fence *fence,
94 return i915_request_wait(to_request(fence),
95 interruptible | I915_WAIT_PRIORITY,
99 static void i915_fence_release(struct dma_fence *fence)
101 struct i915_request *rq = to_request(fence);
104 * The request is put onto a RCU freelist (i.e. the address
105 * is immediately reused), mark the fences as being freed now.
106 * Otherwise the debugobjects for the fences are only marked as
107 * freed when the slab cache itself is freed, and so we would get
108 * caught trying to reuse dead objects.
110 i915_sw_fence_fini(&rq->submit);
111 i915_sw_fence_fini(&rq->semaphore);
113 kmem_cache_free(global.slab_requests, rq);
116 const struct dma_fence_ops i915_fence_ops = {
117 .get_driver_name = i915_fence_get_driver_name,
118 .get_timeline_name = i915_fence_get_timeline_name,
119 .enable_signaling = i915_fence_enable_signaling,
120 .signaled = i915_fence_signaled,
121 .wait = i915_fence_wait,
122 .release = i915_fence_release,
125 static void irq_execute_cb(struct irq_work *wrk)
127 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
129 i915_sw_fence_complete(cb->fence);
130 kmem_cache_free(global.slab_execute_cbs, cb);
133 static void irq_execute_cb_hook(struct irq_work *wrk)
135 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
137 cb->hook(container_of(cb->fence, struct i915_request, submit),
139 i915_request_put(cb->signal);
144 static void __notify_execute_cb(struct i915_request *rq)
146 struct execute_cb *cb;
148 lockdep_assert_held(&rq->lock);
150 if (list_empty(&rq->execute_cb))
153 list_for_each_entry(cb, &rq->execute_cb, link)
154 irq_work_queue(&cb->work);
157 * XXX Rollback on __i915_request_unsubmit()
159 * In the future, perhaps when we have an active time-slicing scheduler,
160 * it will be interesting to unsubmit parallel execution and remove
161 * busywaits from the GPU until their master is restarted. This is
162 * quite hairy, we have to carefully rollback the fence and do a
163 * preempt-to-idle cycle on the target engine, all the while the
164 * master execute_cb may refire.
166 INIT_LIST_HEAD(&rq->execute_cb);
170 remove_from_client(struct i915_request *request)
172 struct drm_i915_file_private *file_priv;
174 if (!READ_ONCE(request->file_priv))
178 file_priv = xchg(&request->file_priv, NULL);
180 spin_lock(&file_priv->mm.lock);
181 list_del(&request->client_link);
182 spin_unlock(&file_priv->mm.lock);
187 static void free_capture_list(struct i915_request *request)
189 struct i915_capture_list *capture;
191 capture = fetch_and_zero(&request->capture_list);
193 struct i915_capture_list *next = capture->next;
200 static void remove_from_engine(struct i915_request *rq)
202 struct intel_engine_cs *engine, *locked;
205 * Virtual engines complicate acquiring the engine timeline lock,
206 * as their rq->engine pointer is not stable until under that
207 * engine lock. The simple ploy we use is to take the lock then
208 * check that the rq still belongs to the newly locked engine.
210 locked = READ_ONCE(rq->engine);
211 spin_lock_irq(&locked->active.lock);
212 while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
213 spin_unlock(&locked->active.lock);
214 spin_lock(&engine->active.lock);
217 list_del_init(&rq->sched.link);
218 spin_unlock_irq(&locked->active.lock);
221 bool i915_request_retire(struct i915_request *rq)
223 if (!i915_request_completed(rq))
226 GEM_TRACE("%s fence %llx:%lld, current %d\n",
228 rq->fence.context, rq->fence.seqno,
231 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
232 trace_i915_request_retire(rq);
235 * We know the GPU must have read the request to have
236 * sent us the seqno + interrupt, so use the position
237 * of tail of the request to update the last known position
240 * Note this requires that we are always called in request
243 GEM_BUG_ON(!list_is_first(&rq->link,
244 &i915_request_timeline(rq)->requests));
245 rq->ring->head = rq->postfix;
248 * We only loosely track inflight requests across preemption,
249 * and so we may find ourselves attempting to retire a _completed_
250 * request that we have removed from the HW and put back on a run
253 remove_from_engine(rq);
255 spin_lock_irq(&rq->lock);
256 i915_request_mark_complete(rq);
257 if (!i915_request_signaled(rq))
258 dma_fence_signal_locked(&rq->fence);
259 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
260 i915_request_cancel_breadcrumb(rq);
261 if (i915_request_has_waitboost(rq)) {
262 GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters));
263 atomic_dec(&rq->engine->gt->rps.num_waiters);
265 if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) {
266 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
267 __notify_execute_cb(rq);
269 GEM_BUG_ON(!list_empty(&rq->execute_cb));
270 spin_unlock_irq(&rq->lock);
272 remove_from_client(rq);
275 intel_context_exit(rq->hw_context);
276 intel_context_unpin(rq->hw_context);
278 free_capture_list(rq);
279 i915_sched_node_fini(&rq->sched);
280 i915_request_put(rq);
285 void i915_request_retire_upto(struct i915_request *rq)
287 struct intel_timeline * const tl = i915_request_timeline(rq);
288 struct i915_request *tmp;
290 GEM_TRACE("%s fence %llx:%lld, current %d\n",
292 rq->fence.context, rq->fence.seqno,
295 GEM_BUG_ON(!i915_request_completed(rq));
298 tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
299 } while (i915_request_retire(tmp) && tmp != rq);
303 __i915_request_await_execution(struct i915_request *rq,
304 struct i915_request *signal,
305 void (*hook)(struct i915_request *rq,
306 struct dma_fence *signal),
309 struct execute_cb *cb;
311 if (i915_request_is_active(signal)) {
313 hook(rq, &signal->fence);
317 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
321 cb->fence = &rq->submit;
322 i915_sw_fence_await(cb->fence);
323 init_irq_work(&cb->work, irq_execute_cb);
327 cb->signal = i915_request_get(signal);
328 cb->work.func = irq_execute_cb_hook;
331 spin_lock_irq(&signal->lock);
332 if (i915_request_is_active(signal)) {
334 hook(rq, &signal->fence);
335 i915_request_put(signal);
337 i915_sw_fence_complete(cb->fence);
338 kmem_cache_free(global.slab_execute_cbs, cb);
340 list_add_tail(&cb->link, &signal->execute_cb);
342 spin_unlock_irq(&signal->lock);
347 bool __i915_request_submit(struct i915_request *request)
349 struct intel_engine_cs *engine = request->engine;
352 GEM_TRACE("%s fence %llx:%lld, current %d\n",
354 request->fence.context, request->fence.seqno,
355 hwsp_seqno(request));
357 GEM_BUG_ON(!irqs_disabled());
358 lockdep_assert_held(&engine->active.lock);
361 * With the advent of preempt-to-busy, we frequently encounter
362 * requests that we have unsubmitted from HW, but left running
363 * until the next ack and so have completed in the meantime. On
364 * resubmission of that completed request, we can skip
365 * updating the payload, and execlists can even skip submitting
368 * We must remove the request from the caller's priority queue,
369 * and the caller must only call us when the request is in their
370 * priority queue, under the active.lock. This ensures that the
371 * request has *not* yet been retired and we can safely move
372 * the request into the engine->active.list where it will be
373 * dropped upon retiring. (Otherwise if resubmit a *retired*
374 * request, this would be a horrible use-after-free.)
376 if (i915_request_completed(request))
379 if (i915_gem_context_is_banned(request->gem_context))
380 i915_request_skip(request, -EIO);
383 * Are we using semaphores when the gpu is already saturated?
385 * Using semaphores incurs a cost in having the GPU poll a
386 * memory location, busywaiting for it to change. The continual
387 * memory reads can have a noticeable impact on the rest of the
388 * system with the extra bus traffic, stalling the cpu as it too
389 * tries to access memory across the bus (perf stat -e bus-cycles).
391 * If we installed a semaphore on this request and we only submit
392 * the request after the signaler completed, that indicates the
393 * system is overloaded and using semaphores at this time only
394 * increases the amount of work we are doing. If so, we disable
395 * further use of semaphores until we are idle again, whence we
396 * optimistically try again.
398 if (request->sched.semaphores &&
399 i915_sw_fence_signaled(&request->semaphore))
400 engine->saturated |= request->sched.semaphores;
402 engine->emit_fini_breadcrumb(request,
403 request->ring->vaddr + request->postfix);
405 trace_i915_request_execute(request);
409 xfer: /* We may be recursing from the signal callback of another i915 fence */
410 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
412 if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags))
413 list_move_tail(&request->sched.link, &engine->active.requests);
415 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
416 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) &&
417 !i915_request_enable_breadcrumb(request))
418 intel_engine_queue_breadcrumbs(engine);
420 __notify_execute_cb(request);
422 spin_unlock(&request->lock);
427 void i915_request_submit(struct i915_request *request)
429 struct intel_engine_cs *engine = request->engine;
432 /* Will be called from irq-context when using foreign fences. */
433 spin_lock_irqsave(&engine->active.lock, flags);
435 __i915_request_submit(request);
437 spin_unlock_irqrestore(&engine->active.lock, flags);
440 void __i915_request_unsubmit(struct i915_request *request)
442 struct intel_engine_cs *engine = request->engine;
444 GEM_TRACE("%s fence %llx:%lld, current %d\n",
446 request->fence.context, request->fence.seqno,
447 hwsp_seqno(request));
449 GEM_BUG_ON(!irqs_disabled());
450 lockdep_assert_held(&engine->active.lock);
453 * Only unwind in reverse order, required so that the per-context list
454 * is kept in seqno/ring order.
457 /* We may be recursing from the signal callback of another i915 fence */
458 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
460 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
461 i915_request_cancel_breadcrumb(request);
463 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
464 clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
466 spin_unlock(&request->lock);
468 /* We've already spun, don't charge on resubmitting. */
469 if (request->sched.semaphores && i915_request_started(request)) {
470 request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE;
471 request->sched.semaphores = 0;
475 * We don't need to wake_up any waiters on request->execute, they
476 * will get woken by any other event or us re-adding this request
477 * to the engine timeline (__i915_request_submit()). The waiters
478 * should be quite adapt at finding that the request now has a new
479 * global_seqno to the one they went to sleep on.
483 void i915_request_unsubmit(struct i915_request *request)
485 struct intel_engine_cs *engine = request->engine;
488 /* Will be called from irq-context when using foreign fences. */
489 spin_lock_irqsave(&engine->active.lock, flags);
491 __i915_request_unsubmit(request);
493 spin_unlock_irqrestore(&engine->active.lock, flags);
496 static int __i915_sw_fence_call
497 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
499 struct i915_request *request =
500 container_of(fence, typeof(*request), submit);
504 trace_i915_request_submit(request);
506 if (unlikely(fence->error))
507 i915_request_skip(request, fence->error);
510 * We need to serialize use of the submit_request() callback
511 * with its hotplugging performed during an emergency
512 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
513 * critical section in order to force i915_gem_set_wedged() to
514 * wait until the submit_request() is completed before
518 request->engine->submit_request(request);
523 i915_request_put(request);
530 static int __i915_sw_fence_call
531 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
533 struct i915_request *request =
534 container_of(fence, typeof(*request), semaphore);
538 i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE);
542 i915_request_put(request);
549 static void retire_requests(struct intel_timeline *tl)
551 struct i915_request *rq, *rn;
553 list_for_each_entry_safe(rq, rn, &tl->requests, link)
554 if (!i915_request_retire(rq))
558 static noinline struct i915_request *
559 request_alloc_slow(struct intel_timeline *tl, gfp_t gfp)
561 struct i915_request *rq;
563 if (list_empty(&tl->requests))
566 if (!gfpflags_allow_blocking(gfp))
569 /* Move our oldest request to the slab-cache (if not in use!) */
570 rq = list_first_entry(&tl->requests, typeof(*rq), link);
571 i915_request_retire(rq);
573 rq = kmem_cache_alloc(global.slab_requests,
574 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
578 /* Ratelimit ourselves to prevent oom from malicious clients */
579 rq = list_last_entry(&tl->requests, typeof(*rq), link);
580 cond_synchronize_rcu(rq->rcustate);
582 /* Retire our old requests in the hope that we free some */
586 return kmem_cache_alloc(global.slab_requests, gfp);
589 static void __i915_request_ctor(void *arg)
591 struct i915_request *rq = arg;
593 spin_lock_init(&rq->lock);
594 i915_sched_node_init(&rq->sched);
595 i915_sw_fence_init(&rq->submit, submit_notify);
596 i915_sw_fence_init(&rq->semaphore, semaphore_notify);
598 rq->file_priv = NULL;
599 rq->capture_list = NULL;
601 INIT_LIST_HEAD(&rq->execute_cb);
604 struct i915_request *
605 __i915_request_create(struct intel_context *ce, gfp_t gfp)
607 struct intel_timeline *tl = ce->timeline;
608 struct i915_request *rq;
612 might_sleep_if(gfpflags_allow_blocking(gfp));
614 /* Check that the caller provided an already pinned context */
615 __intel_context_pin(ce);
618 * Beware: Dragons be flying overhead.
620 * We use RCU to look up requests in flight. The lookups may
621 * race with the request being allocated from the slab freelist.
622 * That is the request we are writing to here, may be in the process
623 * of being read by __i915_active_request_get_rcu(). As such,
624 * we have to be very careful when overwriting the contents. During
625 * the RCU lookup, we change chase the request->engine pointer,
626 * read the request->global_seqno and increment the reference count.
628 * The reference count is incremented atomically. If it is zero,
629 * the lookup knows the request is unallocated and complete. Otherwise,
630 * it is either still in use, or has been reallocated and reset
631 * with dma_fence_init(). This increment is safe for release as we
632 * check that the request we have a reference to and matches the active
635 * Before we increment the refcount, we chase the request->engine
636 * pointer. We must not call kmem_cache_zalloc() or else we set
637 * that pointer to NULL and cause a crash during the lookup. If
638 * we see the request is completed (based on the value of the
639 * old engine and seqno), the lookup is complete and reports NULL.
640 * If we decide the request is not completed (new engine or seqno),
641 * then we grab a reference and double check that it is still the
642 * active request - which it won't be and restart the lookup.
644 * Do not use kmem_cache_zalloc() here!
646 rq = kmem_cache_alloc(global.slab_requests,
647 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
649 rq = request_alloc_slow(tl, gfp);
656 ret = intel_timeline_get_seqno(tl, rq, &seqno);
660 rq->i915 = ce->engine->i915;
662 rq->gem_context = ce->gem_context;
663 rq->engine = ce->engine;
665 rq->execution_mask = ce->engine->mask;
668 rcu_assign_pointer(rq->timeline, tl);
669 rq->hwsp_seqno = tl->hwsp_seqno;
670 rq->hwsp_cacheline = tl->hwsp_cacheline;
672 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
674 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
675 tl->fence_context, seqno);
677 /* We bump the ref for the fence chain */
678 i915_sw_fence_reinit(&i915_request_get(rq)->submit);
679 i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
681 i915_sched_node_reinit(&rq->sched);
683 /* No zalloc, everything must be cleared after use */
685 GEM_BUG_ON(rq->file_priv);
686 GEM_BUG_ON(rq->capture_list);
687 GEM_BUG_ON(!list_empty(&rq->execute_cb));
690 * Reserve space in the ring buffer for all the commands required to
691 * eventually emit this request. This is to guarantee that the
692 * i915_request_add() call can't fail. Note that the reserve may need
693 * to be redone if the request is not actually submitted straight
694 * away, e.g. because a GPU scheduler has deferred it.
696 * Note that due to how we add reserved_space to intel_ring_begin()
697 * we need to double our request to ensure that if we need to wrap
698 * around inside i915_request_add() there is sufficient space at
699 * the beginning of the ring as well.
702 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
705 * Record the position of the start of the request so that
706 * should we detect the updated seqno part-way through the
707 * GPU processing the request, we never over-estimate the
708 * position of the head.
710 rq->head = rq->ring->emit;
712 ret = rq->engine->request_alloc(rq);
716 rq->infix = rq->ring->emit; /* end of header; start of user payload */
718 intel_context_mark_active(ce);
722 ce->ring->emit = rq->head;
724 /* Make sure we didn't add ourselves to external state before freeing */
725 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
726 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
729 kmem_cache_free(global.slab_requests, rq);
731 intel_context_unpin(ce);
735 struct i915_request *
736 i915_request_create(struct intel_context *ce)
738 struct i915_request *rq;
739 struct intel_timeline *tl;
741 tl = intel_context_timeline_lock(ce);
745 /* Move our oldest request to the slab-cache (if not in use!) */
746 rq = list_first_entry(&tl->requests, typeof(*rq), link);
747 if (!list_is_last(&rq->link, &tl->requests))
748 i915_request_retire(rq);
750 intel_context_enter(ce);
751 rq = __i915_request_create(ce, GFP_KERNEL);
752 intel_context_exit(ce); /* active reference transferred to request */
756 /* Check that we do not interrupt ourselves with a new request */
757 rq->cookie = lockdep_pin_lock(&tl->mutex);
762 intel_context_timeline_unlock(tl);
767 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
769 struct intel_timeline *tl;
770 struct dma_fence *fence;
773 GEM_BUG_ON(i915_request_timeline(rq) ==
774 rcu_access_pointer(signal->timeline));
777 tl = rcu_dereference(signal->timeline);
778 if (i915_request_started(signal) || !kref_get_unless_zero(&tl->kref))
781 if (!tl) /* already started or maybe even completed */
784 fence = ERR_PTR(-EBUSY);
785 if (mutex_trylock(&tl->mutex)) {
787 if (!i915_request_started(signal) &&
788 !list_is_first(&signal->link, &tl->requests)) {
789 signal = list_prev_entry(signal, link);
790 fence = dma_fence_get(&signal->fence);
792 mutex_unlock(&tl->mutex);
794 intel_timeline_put(tl);
795 if (IS_ERR_OR_NULL(fence))
796 return PTR_ERR_OR_ZERO(fence);
799 if (intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
800 err = i915_sw_fence_await_dma_fence(&rq->submit,
803 dma_fence_put(fence);
808 static intel_engine_mask_t
809 already_busywaiting(struct i915_request *rq)
812 * Polling a semaphore causes bus traffic, delaying other users of
813 * both the GPU and CPU. We want to limit the impact on others,
814 * while taking advantage of early submission to reduce GPU
815 * latency. Therefore we restrict ourselves to not using more
816 * than one semaphore from each source, and not using a semaphore
817 * if we have detected the engine is saturated (i.e. would not be
818 * submitted early and cause bus traffic reading an already passed
821 * See the are-we-too-late? check in __i915_request_submit().
823 return rq->sched.semaphores | rq->engine->saturated;
827 emit_semaphore_wait(struct i915_request *to,
828 struct i915_request *from,
831 const int has_token = INTEL_GEN(to->i915) >= 12;
836 GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
838 /* Just emit the first semaphore we see as request space is limited. */
839 if (already_busywaiting(to) & from->engine->mask)
842 if (i915_request_await_start(to, from) < 0)
845 /* Only submit our spinner after the signaler is running! */
846 if (__i915_request_await_execution(to, from, NULL, gfp))
849 /* We need to pin the signaler's HWSP until we are finished reading. */
850 if (intel_timeline_read_hwsp(from, to, &hwsp_offset))
857 cs = intel_ring_begin(to, len);
862 * Using greater-than-or-equal here means we have to worry
863 * about seqno wraparound. To side step that issue, we swap
864 * the timeline HWSP upon wrapping, so that everyone listening
865 * for the old (pre-wrap) values do not see the much smaller
866 * (post-wrap) values than they were expecting (and so wait
869 *cs++ = (MI_SEMAPHORE_WAIT |
870 MI_SEMAPHORE_GLOBAL_GTT |
872 MI_SEMAPHORE_SAD_GTE_SDD) +
874 *cs++ = from->fence.seqno;
882 intel_ring_advance(to, cs);
883 to->sched.semaphores |= from->engine->mask;
884 to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
888 return i915_sw_fence_await_dma_fence(&to->submit,
894 i915_request_await_request(struct i915_request *to, struct i915_request *from)
898 GEM_BUG_ON(to == from);
899 GEM_BUG_ON(to->timeline == from->timeline);
901 if (i915_request_completed(from))
904 if (to->engine->schedule) {
905 ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
910 if (to->engine == from->engine) {
911 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
914 } else if (intel_engine_has_semaphores(to->engine) &&
915 to->gem_context->sched.priority >= I915_PRIORITY_NORMAL) {
916 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
918 ret = i915_sw_fence_await_dma_fence(&to->submit,
925 if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) {
926 ret = i915_sw_fence_await_dma_fence(&to->semaphore,
937 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
939 struct dma_fence **child = &fence;
940 unsigned int nchild = 1;
944 * Note that if the fence-array was created in signal-on-any mode,
945 * we should *not* decompose it into its individual fences. However,
946 * we don't currently store which mode the fence-array is operating
947 * in. Fortunately, the only user of signal-on-any is private to
948 * amdgpu and we should not see any incoming fence-array from
949 * sync-file being in signal-on-any mode.
951 if (dma_fence_is_array(fence)) {
952 struct dma_fence_array *array = to_dma_fence_array(fence);
954 child = array->fences;
955 nchild = array->num_fences;
961 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
962 i915_sw_fence_set_error_once(&rq->submit, fence->error);
967 * Requests on the same timeline are explicitly ordered, along
968 * with their dependencies, by i915_request_add() which ensures
969 * that requests are submitted in-order through each ring.
971 if (fence->context == rq->fence.context)
974 /* Squash repeated waits to the same timelines */
975 if (fence->context &&
976 intel_timeline_sync_is_later(i915_request_timeline(rq),
980 if (dma_fence_is_i915(fence))
981 ret = i915_request_await_request(rq, to_request(fence));
983 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
984 fence->context ? I915_FENCE_TIMEOUT : 0,
989 /* Record the latest fence used against each timeline */
991 intel_timeline_sync_set(i915_request_timeline(rq),
999 i915_request_await_execution(struct i915_request *rq,
1000 struct dma_fence *fence,
1001 void (*hook)(struct i915_request *rq,
1002 struct dma_fence *signal))
1004 struct dma_fence **child = &fence;
1005 unsigned int nchild = 1;
1008 if (dma_fence_is_array(fence)) {
1009 struct dma_fence_array *array = to_dma_fence_array(fence);
1011 /* XXX Error for signal-on-any fence arrays */
1013 child = array->fences;
1014 nchild = array->num_fences;
1015 GEM_BUG_ON(!nchild);
1020 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1021 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1026 * We don't squash repeated fence dependencies here as we
1027 * want to run our callback in all cases.
1030 if (dma_fence_is_i915(fence))
1031 ret = __i915_request_await_execution(rq,
1036 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
1047 * i915_request_await_object - set this request to (async) wait upon a bo
1048 * @to: request we are wishing to use
1049 * @obj: object which may be in use on another ring.
1050 * @write: whether the wait is on behalf of a writer
1052 * This code is meant to abstract object synchronization with the GPU.
1053 * Conceptually we serialise writes between engines inside the GPU.
1054 * We only allow one engine to write into a buffer at any time, but
1055 * multiple readers. To ensure each has a coherent view of memory, we must:
1057 * - If there is an outstanding write request to the object, the new
1058 * request must wait for it to complete (either CPU or in hw, requests
1059 * on the same ring will be naturally ordered).
1061 * - If we are a write request (pending_write_domain is set), the new
1062 * request must wait for outstanding read requests to complete.
1064 * Returns 0 if successful, else propagates up the lower layer error.
1067 i915_request_await_object(struct i915_request *to,
1068 struct drm_i915_gem_object *obj,
1071 struct dma_fence *excl;
1075 struct dma_fence **shared;
1076 unsigned int count, i;
1078 ret = dma_resv_get_fences_rcu(obj->base.resv,
1079 &excl, &count, &shared);
1083 for (i = 0; i < count; i++) {
1084 ret = i915_request_await_dma_fence(to, shared[i]);
1088 dma_fence_put(shared[i]);
1091 for (; i < count; i++)
1092 dma_fence_put(shared[i]);
1095 excl = dma_resv_get_excl_rcu(obj->base.resv);
1100 ret = i915_request_await_dma_fence(to, excl);
1102 dma_fence_put(excl);
1108 void i915_request_skip(struct i915_request *rq, int error)
1110 void *vaddr = rq->ring->vaddr;
1113 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
1114 dma_fence_set_error(&rq->fence, error);
1116 if (rq->infix == rq->postfix)
1120 * As this request likely depends on state from the lost
1121 * context, clear out all the user operations leaving the
1122 * breadcrumb at the end (so we get the fence notifications).
1125 if (rq->postfix < head) {
1126 memset(vaddr + head, 0, rq->ring->size - head);
1129 memset(vaddr + head, 0, rq->postfix - head);
1130 rq->infix = rq->postfix;
1133 static struct i915_request *
1134 __i915_request_add_to_timeline(struct i915_request *rq)
1136 struct intel_timeline *timeline = i915_request_timeline(rq);
1137 struct i915_request *prev;
1140 * Dependency tracking and request ordering along the timeline
1141 * is special cased so that we can eliminate redundant ordering
1142 * operations while building the request (we know that the timeline
1143 * itself is ordered, and here we guarantee it).
1145 * As we know we will need to emit tracking along the timeline,
1146 * we embed the hooks into our request struct -- at the cost of
1147 * having to have specialised no-allocation interfaces (which will
1148 * be beneficial elsewhere).
1150 * A second benefit to open-coding i915_request_await_request is
1151 * that we can apply a slight variant of the rules specialised
1152 * for timelines that jump between engines (such as virtual engines).
1153 * If we consider the case of virtual engine, we must emit a dma-fence
1154 * to prevent scheduling of the second request until the first is
1155 * complete (to maximise our greedy late load balancing) and this
1156 * precludes optimising to use semaphores serialisation of a single
1157 * timeline across engines.
1159 prev = to_request(__i915_active_fence_set(&timeline->last_request,
1161 if (prev && !i915_request_completed(prev)) {
1162 if (is_power_of_2(prev->engine->mask | rq->engine->mask))
1163 i915_sw_fence_await_sw_fence(&rq->submit,
1167 __i915_sw_fence_await_dma_fence(&rq->submit,
1170 if (rq->engine->schedule)
1171 __i915_sched_node_add_dependency(&rq->sched,
1177 list_add_tail(&rq->link, &timeline->requests);
1180 * Make sure that no request gazumped us - if it was allocated after
1181 * our i915_request_alloc() and called __i915_request_add() before
1182 * us, the timeline will hold its seqno which is later than ours.
1184 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1190 * NB: This function is not allowed to fail. Doing so would mean the the
1191 * request is not being tracked for completion but the work itself is
1192 * going to happen on the hardware. This would be a Bad Thing(tm).
1194 struct i915_request *__i915_request_commit(struct i915_request *rq)
1196 struct intel_engine_cs *engine = rq->engine;
1197 struct intel_ring *ring = rq->ring;
1200 GEM_TRACE("%s fence %llx:%lld\n",
1201 engine->name, rq->fence.context, rq->fence.seqno);
1204 * To ensure that this call will not fail, space for its emissions
1205 * should already have been reserved in the ring buffer. Let the ring
1206 * know that it is time to use that space up.
1208 GEM_BUG_ON(rq->reserved_space > ring->space);
1209 rq->reserved_space = 0;
1210 rq->emitted_jiffies = jiffies;
1213 * Record the position of the start of the breadcrumb so that
1214 * should we detect the updated seqno part-way through the
1215 * GPU processing the request, we never over-estimate the
1216 * position of the ring's HEAD.
1218 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1219 GEM_BUG_ON(IS_ERR(cs));
1220 rq->postfix = intel_ring_offset(rq, cs);
1222 return __i915_request_add_to_timeline(rq);
1225 void __i915_request_queue(struct i915_request *rq,
1226 const struct i915_sched_attr *attr)
1229 * Let the backend know a new request has arrived that may need
1230 * to adjust the existing execution schedule due to a high priority
1231 * request - i.e. we may want to preempt the current request in order
1232 * to run a high priority dependency chain *before* we can execute this
1235 * This is called before the request is ready to run so that we can
1236 * decide whether to preempt the entire chain so that it is ready to
1237 * run at the earliest possible convenience.
1239 i915_sw_fence_commit(&rq->semaphore);
1240 if (attr && rq->engine->schedule)
1241 rq->engine->schedule(rq, attr);
1242 i915_sw_fence_commit(&rq->submit);
1245 void i915_request_add(struct i915_request *rq)
1247 struct i915_sched_attr attr = rq->gem_context->sched;
1248 struct intel_timeline * const tl = i915_request_timeline(rq);
1249 struct i915_request *prev;
1251 lockdep_assert_held(&tl->mutex);
1252 lockdep_unpin_lock(&tl->mutex, rq->cookie);
1254 trace_i915_request_add(rq);
1256 prev = __i915_request_commit(rq);
1259 * Boost actual workloads past semaphores!
1261 * With semaphores we spin on one engine waiting for another,
1262 * simply to reduce the latency of starting our work when
1263 * the signaler completes. However, if there is any other
1264 * work that we could be doing on this engine instead, that
1265 * is better utilisation and will reduce the overall duration
1266 * of the current work. To avoid PI boosting a semaphore
1267 * far in the distance past over useful work, we keep a history
1268 * of any semaphore use along our dependency chain.
1270 if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN))
1271 attr.priority |= I915_PRIORITY_NOSEMAPHORE;
1274 * Boost priorities to new clients (new request flows).
1276 * Allow interactive/synchronous clients to jump ahead of
1277 * the bulk clients. (FQ_CODEL)
1279 if (list_empty(&rq->sched.signalers_list))
1280 attr.priority |= I915_PRIORITY_WAIT;
1283 __i915_request_queue(rq, &attr);
1284 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
1287 * In typical scenarios, we do not expect the previous request on
1288 * the timeline to be still tracked by timeline->last_request if it
1289 * has been completed. If the completed request is still here, that
1290 * implies that request retirement is a long way behind submission,
1291 * suggesting that we haven't been retiring frequently enough from
1292 * the combination of retire-before-alloc, waiters and the background
1293 * retirement worker. So if the last request on this timeline was
1294 * already completed, do a catch up pass, flushing the retirement queue
1295 * up to this client. Since we have now moved the heaviest operations
1296 * during retirement onto secondary workers, such as freeing objects
1297 * or contexts, retiring a bunch of requests is mostly list management
1298 * (and cache misses), and so we should not be overly penalizing this
1299 * client by performing excess work, though we may still performing
1300 * work on behalf of others -- but instead we should benefit from
1301 * improved resource management. (Well, that's the theory at least.)
1304 i915_request_completed(prev) &&
1305 rcu_access_pointer(prev->timeline) == tl)
1306 i915_request_retire_upto(prev);
1308 mutex_unlock(&tl->mutex);
1311 static unsigned long local_clock_us(unsigned int *cpu)
1316 * Cheaply and approximately convert from nanoseconds to microseconds.
1317 * The result and subsequent calculations are also defined in the same
1318 * approximate microseconds units. The principal source of timing
1319 * error here is from the simple truncation.
1321 * Note that local_clock() is only defined wrt to the current CPU;
1322 * the comparisons are no longer valid if we switch CPUs. Instead of
1323 * blocking preemption for the entire busywait, we can detect the CPU
1324 * switch and use that as indicator of system load and a reason to
1325 * stop busywaiting, see busywait_stop().
1328 t = local_clock() >> 10;
1334 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1336 unsigned int this_cpu;
1338 if (time_after(local_clock_us(&this_cpu), timeout))
1341 return this_cpu != cpu;
1344 static bool __i915_spin_request(const struct i915_request * const rq,
1345 int state, unsigned long timeout_us)
1350 * Only wait for the request if we know it is likely to complete.
1352 * We don't track the timestamps around requests, nor the average
1353 * request length, so we do not have a good indicator that this
1354 * request will complete within the timeout. What we do know is the
1355 * order in which requests are executed by the context and so we can
1356 * tell if the request has been started. If the request is not even
1357 * running yet, it is a fair assumption that it will not complete
1358 * within our relatively short timeout.
1360 if (!i915_request_is_running(rq))
1364 * When waiting for high frequency requests, e.g. during synchronous
1365 * rendering split between the CPU and GPU, the finite amount of time
1366 * required to set up the irq and wait upon it limits the response
1367 * rate. By busywaiting on the request completion for a short while we
1368 * can service the high frequency waits as quick as possible. However,
1369 * if it is a slow request, we want to sleep as quickly as possible.
1370 * The tradeoff between waiting and sleeping is roughly the time it
1371 * takes to sleep on a request, on the order of a microsecond.
1374 timeout_us += local_clock_us(&cpu);
1376 if (i915_request_completed(rq))
1379 if (signal_pending_state(state, current))
1382 if (busywait_stop(timeout_us, cpu))
1386 } while (!need_resched());
1391 struct request_wait {
1392 struct dma_fence_cb cb;
1393 struct task_struct *tsk;
1396 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1398 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1400 wake_up_process(wait->tsk);
1404 * i915_request_wait - wait until execution of request has finished
1405 * @rq: the request to wait upon
1406 * @flags: how to wait
1407 * @timeout: how long to wait in jiffies
1409 * i915_request_wait() waits for the request to be completed, for a
1410 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1413 * Returns the remaining time (in jiffies) if the request completed, which may
1414 * be zero or -ETIME if the request is unfinished after the timeout expires.
1415 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1416 * pending before the request completes.
1418 long i915_request_wait(struct i915_request *rq,
1422 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1423 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1424 struct request_wait wait;
1427 GEM_BUG_ON(timeout < 0);
1429 if (dma_fence_is_signaled(&rq->fence))
1435 trace_i915_request_wait_begin(rq, flags);
1438 * We must never wait on the GPU while holding a lock as we
1439 * may need to perform a GPU reset. So while we don't need to
1440 * serialise wait/reset with an explicit lock, we do want
1441 * lockdep to detect potential dependency cycles.
1443 mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1446 * Optimistic spin before touching IRQs.
1448 * We may use a rather large value here to offset the penalty of
1449 * switching away from the active task. Frequently, the client will
1450 * wait upon an old swapbuffer to throttle itself to remain within a
1451 * frame of the gpu. If the client is running in lockstep with the gpu,
1452 * then it should not be waiting long at all, and a sleep now will incur
1453 * extra scheduler latency in producing the next frame. To try to
1454 * avoid adding the cost of enabling/disabling the interrupt to the
1455 * short wait, we first spin to see if the request would have completed
1456 * in the time taken to setup the interrupt.
1458 * We need upto 5us to enable the irq, and upto 20us to hide the
1459 * scheduler latency of a context switch, ignoring the secondary
1460 * impacts from a context switch such as cache eviction.
1462 * The scheme used for low-latency IO is called "hybrid interrupt
1463 * polling". The suggestion there is to sleep until just before you
1464 * expect to be woken by the device interrupt and then poll for its
1465 * completion. That requires having a good predictor for the request
1466 * duration, which we currently lack.
1468 if (IS_ACTIVE(CONFIG_DRM_I915_SPIN_REQUEST) &&
1469 __i915_spin_request(rq, state, CONFIG_DRM_I915_SPIN_REQUEST)) {
1470 dma_fence_signal(&rq->fence);
1475 * This client is about to stall waiting for the GPU. In many cases
1476 * this is undesirable and limits the throughput of the system, as
1477 * many clients cannot continue processing user input/output whilst
1478 * blocked. RPS autotuning may take tens of milliseconds to respond
1479 * to the GPU load and thus incurs additional latency for the client.
1480 * We can circumvent that by promoting the GPU frequency to maximum
1481 * before we sleep. This makes the GPU throttle up much more quickly
1482 * (good for benchmarks and user experience, e.g. window animations),
1483 * but at a cost of spending more power processing the workload
1484 * (bad for battery).
1486 if (flags & I915_WAIT_PRIORITY) {
1487 if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
1488 intel_rps_boost(rq);
1489 i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
1493 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1497 set_current_state(state);
1499 if (i915_request_completed(rq)) {
1500 dma_fence_signal(&rq->fence);
1504 if (signal_pending_state(state, current)) {
1505 timeout = -ERESTARTSYS;
1514 intel_engine_flush_submission(rq->engine);
1515 timeout = io_schedule_timeout(timeout);
1517 __set_current_state(TASK_RUNNING);
1519 dma_fence_remove_callback(&rq->fence, &wait.cb);
1522 mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
1523 trace_i915_request_wait_end(rq);
1527 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1528 #include "selftests/mock_request.c"
1529 #include "selftests/i915_request.c"
1532 static void i915_global_request_shrink(void)
1534 kmem_cache_shrink(global.slab_dependencies);
1535 kmem_cache_shrink(global.slab_execute_cbs);
1536 kmem_cache_shrink(global.slab_requests);
1539 static void i915_global_request_exit(void)
1541 kmem_cache_destroy(global.slab_dependencies);
1542 kmem_cache_destroy(global.slab_execute_cbs);
1543 kmem_cache_destroy(global.slab_requests);
1546 static struct i915_global_request global = { {
1547 .shrink = i915_global_request_shrink,
1548 .exit = i915_global_request_exit,
1551 int __init i915_global_request_init(void)
1553 global.slab_requests =
1554 kmem_cache_create("i915_request",
1555 sizeof(struct i915_request),
1556 __alignof__(struct i915_request),
1557 SLAB_HWCACHE_ALIGN |
1558 SLAB_RECLAIM_ACCOUNT |
1559 SLAB_TYPESAFE_BY_RCU,
1560 __i915_request_ctor);
1561 if (!global.slab_requests)
1564 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1565 SLAB_HWCACHE_ALIGN |
1566 SLAB_RECLAIM_ACCOUNT |
1567 SLAB_TYPESAFE_BY_RCU);
1568 if (!global.slab_execute_cbs)
1571 global.slab_dependencies = KMEM_CACHE(i915_dependency,
1572 SLAB_HWCACHE_ALIGN |
1573 SLAB_RECLAIM_ACCOUNT);
1574 if (!global.slab_dependencies)
1575 goto err_execute_cbs;
1577 i915_global_register(&global.base);
1581 kmem_cache_destroy(global.slab_execute_cbs);
1583 kmem_cache_destroy(global.slab_requests);