2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
31 #include <linux/backlight.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/hdmi.h>
34 #include <linux/component.h>
35 #include <linux/iopoll.h>
37 #include <drm/display/drm_dp_helper.h>
38 #include <drm/display/drm_scdc_helper.h>
39 #include <drm/drm_atomic.h>
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_edid.h>
42 #include <drm/drm_eld.h>
43 #include <drm/drm_fb_helper.h>
44 #include <drm/drm_fixed.h>
45 #include <drm/drm_probe_helper.h>
46 #include <drm/drm_vblank.h>
48 #include <nvif/push507c.h>
50 #include <nvif/class.h>
51 #include <nvif/cl0002.h>
52 #include <nvif/event.h>
53 #include <nvif/if0012.h>
54 #include <nvif/if0014.h>
55 #include <nvif/timer.h>
57 #include <nvhw/class/cl507c.h>
58 #include <nvhw/class/cl507d.h>
59 #include <nvhw/class/cl837d.h>
60 #include <nvhw/class/cl887d.h>
61 #include <nvhw/class/cl907d.h>
62 #include <nvhw/class/cl917d.h>
64 #include "nouveau_drv.h"
65 #include "nouveau_dma.h"
66 #include "nouveau_gem.h"
67 #include "nouveau_connector.h"
68 #include "nouveau_encoder.h"
69 #include "nouveau_fence.h"
70 #include "nv50_display.h"
72 /******************************************************************************
74 *****************************************************************************/
77 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
78 const s32 *oclass, u8 head, void *data, u32 size,
79 struct nv50_chan *chan)
81 struct nvif_sclass *sclass;
84 chan->device = device;
86 ret = n = nvif_object_sclass_get(disp, &sclass);
91 for (i = 0; i < n; i++) {
92 if (sclass[i].oclass == oclass[0]) {
93 ret = nvif_object_ctor(disp, "kmsChan", 0,
94 oclass[0], data, size,
97 nvif_object_map(&chan->user, NULL, 0);
98 nvif_object_sclass_put(&sclass);
105 nvif_object_sclass_put(&sclass);
110 nv50_chan_destroy(struct nv50_chan *chan)
112 nvif_object_dtor(&chan->user);
115 /******************************************************************************
117 *****************************************************************************/
120 nv50_dmac_destroy(struct nv50_dmac *dmac)
122 nvif_object_dtor(&dmac->vram);
123 nvif_object_dtor(&dmac->sync);
125 nv50_chan_destroy(&dmac->base);
127 nvif_mem_dtor(&dmac->_push.mem);
131 nv50_dmac_kick(struct nvif_push *push)
133 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
135 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
136 if (dmac->put != dmac->cur) {
137 /* Push buffer fetches are not coherent with BAR1, we need to ensure
138 * writes have been flushed right through to VRAM before writing PUT.
140 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
141 struct nvif_device *device = dmac->base.device;
142 nvif_wr32(&device->object, 0x070000, 0x00000001);
143 nvif_msec(device, 2000,
144 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
149 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
150 dmac->put = dmac->cur;
153 push->bgn = push->cur;
157 nv50_dmac_free(struct nv50_dmac *dmac)
159 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
160 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
161 return get - dmac->cur - 5;
162 return dmac->max - dmac->cur;
166 nv50_dmac_wind(struct nv50_dmac *dmac)
168 /* Wait for GET to depart from the beginning of the push buffer to
169 * prevent writing PUT == GET, which would be ignored by HW.
171 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
173 /* Corner-case, HW idle, but non-committed work pending. */
175 nv50_dmac_kick(dmac->push);
177 if (nvif_msec(dmac->base.device, 2000,
178 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
184 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
190 nv50_dmac_wait(struct nvif_push *push, u32 size)
192 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
195 if (WARN_ON(size > dmac->max))
198 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr;
199 if (dmac->cur + size >= dmac->max) {
200 int ret = nv50_dmac_wind(dmac);
204 push->cur = dmac->_push.mem.object.map.ptr;
205 push->cur = push->cur + dmac->cur;
206 nv50_dmac_kick(push);
209 if (nvif_msec(dmac->base.device, 2000,
210 if ((free = nv50_dmac_free(dmac)) >= size)
217 push->bgn = dmac->_push.mem.object.map.ptr;
218 push->bgn = push->bgn + dmac->cur;
219 push->cur = push->bgn;
220 push->end = push->cur + free;
224 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)");
225 static int nv50_dmac_vram_pushbuf = -1;
226 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400);
229 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
230 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
231 struct nv50_dmac *dmac)
233 struct nouveau_cli *cli = (void *)device->object.client;
234 struct nvif_disp_chan_v0 *args = data;
235 u8 type = NVIF_MEM_COHERENT;
238 mutex_init(&dmac->lock);
240 /* Pascal added support for 47-bit physical addresses, but some
241 * parts of EVO still only accept 40-bit PAs.
243 * To avoid issues on systems with large amounts of RAM, and on
244 * systems where an IOMMU maps pages at a high address, we need
245 * to allocate push buffers in VRAM instead.
247 * This appears to match NVIDIA's behaviour on Pascal.
249 if ((nv50_dmac_vram_pushbuf > 0) ||
250 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL))
251 type |= NVIF_MEM_VRAM;
253 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
258 dmac->ptr = dmac->_push.mem.object.map.ptr;
259 dmac->_push.wait = nv50_dmac_wait;
260 dmac->_push.kick = nv50_dmac_kick;
261 dmac->push = &dmac->_push;
262 dmac->push->bgn = dmac->_push.mem.object.map.ptr;
263 dmac->push->cur = dmac->push->bgn;
264 dmac->push->end = dmac->push->bgn;
265 dmac->max = 0x1000/4 - 1;
267 /* EVO channels are affected by a HW bug where the last 12 DWORDs
268 * of the push buffer aren't able to be used safely.
270 if (disp->oclass < GV100_DISP)
273 args->pushbuf = nvif_handle(&dmac->_push.mem.object);
275 ret = nv50_chan_create(device, disp, oclass, head, data, size,
283 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
285 &(struct nv_dma_v0) {
286 .target = NV_DMA_V0_TARGET_VRAM,
287 .access = NV_DMA_V0_ACCESS_RDWR,
288 .start = syncbuf + 0x0000,
289 .limit = syncbuf + 0x0fff,
290 }, sizeof(struct nv_dma_v0),
295 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
297 &(struct nv_dma_v0) {
298 .target = NV_DMA_V0_TARGET_VRAM,
299 .access = NV_DMA_V0_ACCESS_RDWR,
301 .limit = device->info.ram_user - 1,
302 }, sizeof(struct nv_dma_v0),
310 /******************************************************************************
311 * Output path helpers
312 *****************************************************************************/
314 nv50_outp_dump_caps(struct nouveau_drm *drm,
315 struct nouveau_encoder *outp)
317 NV_DEBUG(drm, "%s caps: dp_interlace=%d\n",
318 outp->base.base.name, outp->caps.dp_interlace);
322 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
323 struct drm_crtc_state *crtc_state,
324 struct drm_connector_state *conn_state,
325 struct drm_display_mode *native_mode)
327 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
328 struct drm_display_mode *mode = &crtc_state->mode;
329 struct drm_connector *connector = conn_state->connector;
330 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
331 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
333 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
334 asyc->scaler.full = false;
338 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
339 switch (connector->connector_type) {
340 case DRM_MODE_CONNECTOR_LVDS:
341 case DRM_MODE_CONNECTOR_eDP:
342 /* Don't force scaler for EDID modes with
343 * same size as the native one (e.g. different
346 if (mode->hdisplay == native_mode->hdisplay &&
347 mode->vdisplay == native_mode->vdisplay &&
348 mode->type & DRM_MODE_TYPE_DRIVER)
351 asyc->scaler.full = true;
360 if (!drm_mode_equal(adjusted_mode, mode)) {
361 drm_mode_copy(adjusted_mode, mode);
362 crtc_state->mode_changed = true;
369 nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
371 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
372 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
373 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
374 unsigned int max_rate, mode_rate;
376 switch (nv_encoder->dcb->type) {
378 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
380 /* we don't support more than 10 anyway */
381 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
383 /* reduce the bpc until it works out */
384 while (asyh->or.bpc > 6) {
385 mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
386 if (mode_rate <= max_rate)
398 nv50_outp_atomic_check(struct drm_encoder *encoder,
399 struct drm_crtc_state *crtc_state,
400 struct drm_connector_state *conn_state)
402 struct drm_connector *connector = conn_state->connector;
403 struct nouveau_connector *nv_connector = nouveau_connector(connector);
404 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
407 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
408 nv_connector->native_mode);
412 if (crtc_state->mode_changed || crtc_state->connectors_changed)
413 asyh->or.bpc = connector->display_info.bpc;
415 /* We might have to reduce the bpc */
416 nv50_outp_atomic_fix_depth(encoder, crtc_state);
421 struct nouveau_connector *
422 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
424 struct drm_connector *connector;
425 struct drm_connector_state *connector_state;
426 struct drm_encoder *encoder = to_drm_encoder(outp);
429 for_each_new_connector_in_state(state, connector, connector_state, i) {
430 if (connector_state->best_encoder == encoder)
431 return nouveau_connector(connector);
437 struct nouveau_connector *
438 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp)
440 struct drm_connector *connector;
441 struct drm_connector_state *connector_state;
442 struct drm_encoder *encoder = to_drm_encoder(outp);
445 for_each_old_connector_in_state(state, connector, connector_state, i) {
446 if (connector_state->best_encoder == encoder)
447 return nouveau_connector(connector);
453 static struct nouveau_crtc *
454 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp)
456 struct drm_crtc *crtc;
457 struct drm_crtc_state *crtc_state;
458 const u32 mask = drm_encoder_mask(&outp->base.base);
461 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
462 if (crtc_state->encoder_mask & mask)
463 return nouveau_crtc(crtc);
469 /******************************************************************************
471 *****************************************************************************/
473 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
475 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
476 struct nv50_core *core = nv50_disp(encoder->dev)->core;
477 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
479 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
480 nv_encoder->crtc = NULL;
484 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
486 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
487 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
488 struct nv50_head_atom *asyh =
489 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
490 struct nv50_core *core = nv50_disp(encoder->dev)->core;
493 switch (nv_crtc->index) {
494 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
495 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
496 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
497 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
503 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
505 if (!nvif_outp_acquired(&nv_encoder->outp))
506 nvif_outp_acquire_dac(&nv_encoder->outp);
508 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
511 nv_encoder->crtc = &nv_crtc->base;
514 static enum drm_connector_status
515 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
517 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
521 loadval = nouveau_drm(encoder->dev)->vbios.dactestval;
525 ret = nvif_outp_load_detect(&nv_encoder->outp, loadval);
527 return connector_status_disconnected;
529 return connector_status_connected;
532 static const struct drm_encoder_helper_funcs
534 .atomic_check = nv50_outp_atomic_check,
535 .atomic_enable = nv50_dac_atomic_enable,
536 .atomic_disable = nv50_dac_atomic_disable,
537 .detect = nv50_dac_detect
541 nv50_dac_destroy(struct drm_encoder *encoder)
543 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
545 nvif_outp_dtor(&nv_encoder->outp);
547 drm_encoder_cleanup(encoder);
551 static const struct drm_encoder_funcs
553 .destroy = nv50_dac_destroy,
557 nv50_dac_create(struct nouveau_encoder *nv_encoder)
559 struct drm_connector *connector = &nv_encoder->conn->base;
560 struct nouveau_drm *drm = nouveau_drm(connector->dev);
561 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
562 struct nvkm_i2c_bus *bus;
563 struct drm_encoder *encoder;
564 struct dcb_output *dcbe = nv_encoder->dcb;
565 int type = DRM_MODE_ENCODER_DAC;
567 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
569 nv_encoder->i2c = &bus->i2c;
571 encoder = to_drm_encoder(nv_encoder);
572 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
573 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
574 drm_encoder_helper_add(encoder, &nv50_dac_help);
576 drm_connector_attach_encoder(connector, encoder);
581 * audio component binding for ELD notification
584 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
587 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
588 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
593 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
594 bool *enabled, unsigned char *buf, int max_bytes)
596 struct drm_device *drm_dev = dev_get_drvdata(kdev);
597 struct nouveau_drm *drm = nouveau_drm(drm_dev);
598 struct drm_encoder *encoder;
599 struct nouveau_encoder *nv_encoder;
600 struct nouveau_crtc *nv_crtc;
605 mutex_lock(&drm->audio.lock);
607 drm_for_each_encoder(encoder, drm->dev) {
608 struct nouveau_connector *nv_connector = NULL;
610 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
613 nv_encoder = nouveau_encoder(encoder);
614 nv_connector = nv_encoder->conn;
615 nv_crtc = nouveau_crtc(nv_encoder->crtc);
617 if (!nv_crtc || nv_encoder->outp.or.id != port || nv_crtc->index != dev_id)
620 *enabled = nv_encoder->audio.enabled;
622 ret = drm_eld_size(nv_connector->base.eld);
623 memcpy(buf, nv_connector->base.eld,
624 min(max_bytes, ret));
629 mutex_unlock(&drm->audio.lock);
634 static const struct drm_audio_component_ops nv50_audio_component_ops = {
635 .get_eld = nv50_audio_component_get_eld,
639 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
642 struct drm_device *drm_dev = dev_get_drvdata(kdev);
643 struct nouveau_drm *drm = nouveau_drm(drm_dev);
644 struct drm_audio_component *acomp = data;
646 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
649 drm_modeset_lock_all(drm_dev);
650 acomp->ops = &nv50_audio_component_ops;
652 drm->audio.component = acomp;
653 drm_modeset_unlock_all(drm_dev);
658 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
661 struct drm_device *drm_dev = dev_get_drvdata(kdev);
662 struct nouveau_drm *drm = nouveau_drm(drm_dev);
663 struct drm_audio_component *acomp = data;
665 drm_modeset_lock_all(drm_dev);
666 drm->audio.component = NULL;
669 drm_modeset_unlock_all(drm_dev);
672 static const struct component_ops nv50_audio_component_bind_ops = {
673 .bind = nv50_audio_component_bind,
674 .unbind = nv50_audio_component_unbind,
678 nv50_audio_component_init(struct nouveau_drm *drm)
680 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
683 drm->audio.component_registered = true;
684 mutex_init(&drm->audio.lock);
688 nv50_audio_component_fini(struct nouveau_drm *drm)
690 if (!drm->audio.component_registered)
693 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
694 drm->audio.component_registered = false;
695 mutex_destroy(&drm->audio.lock);
698 /******************************************************************************
700 *****************************************************************************/
702 nv50_audio_supported(struct drm_encoder *encoder)
704 struct nv50_disp *disp = nv50_disp(encoder->dev);
706 if (disp->disp->object.oclass <= GT200_DISP ||
707 disp->disp->object.oclass == GT206_DISP)
710 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
711 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
713 switch (nv_encoder->dcb->type) {
714 case DCB_OUTPUT_TMDS:
726 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
728 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
729 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
730 struct nvif_outp *outp = &nv_encoder->outp;
732 if (!nv50_audio_supported(encoder))
735 mutex_lock(&drm->audio.lock);
736 if (nv_encoder->audio.enabled) {
737 nv_encoder->audio.enabled = false;
738 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0);
740 mutex_unlock(&drm->audio.lock);
742 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
746 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
747 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
748 struct drm_display_mode *mode)
750 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
751 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
752 struct nvif_outp *outp = &nv_encoder->outp;
754 if (!nv50_audio_supported(encoder) || !drm_detect_monitor_audio(nv_connector->edid))
757 mutex_lock(&drm->audio.lock);
759 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, nv_connector->base.eld,
760 drm_eld_size(nv_connector->base.eld));
761 nv_encoder->audio.enabled = true;
763 mutex_unlock(&drm->audio.lock);
765 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
768 /******************************************************************************
770 *****************************************************************************/
772 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
773 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
774 struct drm_display_mode *mode, bool hda)
776 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
777 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
778 struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi;
779 union hdmi_infoframe infoframe = { 0 };
780 const u8 rekey = 56; /* binary driver, and tegra, constant */
783 struct nvif_outp_infoframe_v0 infoframe;
788 max_ac_packet = mode->htotal - mode->hdisplay;
789 max_ac_packet -= rekey;
790 max_ac_packet -= 18; /* constant from tegra */
793 if (nv_encoder->i2c && hdmi->scdc.scrambling.supported) {
794 const bool high_tmds_clock_ratio = mode->clock > 340000;
797 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc);
799 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
803 scdc &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
804 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
805 scdc |= SCDC_SCRAMBLING_ENABLE;
806 if (high_tmds_clock_ratio)
807 scdc |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
809 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, scdc);
811 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
815 ret = nvif_outp_hdmi(&nv_encoder->outp, nv_crtc->index, true, max_ac_packet, rekey,
816 mode->clock, hdmi->scdc.supported, hdmi->scdc.scrambling.supported,
817 hdmi->scdc.scrambling.low_rates);
822 args.infoframe.version = 0;
823 args.infoframe.head = nv_crtc->index;
825 if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) {
826 drm_hdmi_avi_infoframe_quant_range(&infoframe.avi, &nv_connector->base, mode,
827 HDMI_QUANTIZATION_RANGE_FULL);
829 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
834 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size);
836 /* Vendor InfoFrame. */
837 memset(&args.data, 0, sizeof(args.data));
838 if (!drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi,
839 &nv_connector->base, mode))
840 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data));
844 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size);
846 nv_encoder->hdmi.enabled = true;
849 /******************************************************************************
851 *****************************************************************************/
852 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
853 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
854 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
857 struct nv50_mstm *mstm;
858 struct drm_dp_mst_port *port;
859 struct drm_connector connector;
861 struct drm_display_mode *native;
866 struct drm_encoder encoder;
868 /* head is statically assigned on msto creation */
869 struct nv50_head *head;
870 struct nv50_mstc *mstc;
877 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
879 struct nv50_msto *msto;
881 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
882 return nouveau_encoder(encoder);
884 msto = nv50_msto(encoder);
887 return msto->mstc->mstm->outp;
891 nv50_msto_cleanup(struct drm_atomic_state *state,
892 struct drm_dp_mst_topology_state *new_mst_state,
893 struct drm_dp_mst_topology_mgr *mgr,
894 struct nv50_msto *msto)
896 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
897 struct drm_dp_mst_atomic_payload *new_payload =
898 drm_atomic_get_mst_payload_state(new_mst_state, msto->mstc->port);
899 struct drm_dp_mst_topology_state *old_mst_state =
900 drm_atomic_get_old_mst_topology_state(state, mgr);
901 const struct drm_dp_mst_atomic_payload *old_payload =
902 drm_atomic_get_mst_payload_state(old_mst_state, msto->mstc->port);
903 struct nv50_mstc *mstc = msto->mstc;
904 struct nv50_mstm *mstm = mstc->mstm;
906 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
908 if (msto->disabled) {
909 if (msto->head->func->display_id) {
910 nvif_outp_dp_mst_id_put(&mstm->outp->outp, msto->display_id);
911 msto->display_id = 0;
915 msto->disabled = false;
916 drm_dp_remove_payload_part2(mgr, new_mst_state, old_payload, new_payload);
917 } else if (msto->enabled) {
918 drm_dp_add_payload_part2(mgr, state, new_payload);
919 msto->enabled = false;
924 nv50_msto_prepare(struct drm_atomic_state *state,
925 struct drm_dp_mst_topology_state *mst_state,
926 struct drm_dp_mst_topology_mgr *mgr,
927 struct nv50_msto *msto)
929 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
930 struct nv50_mstc *mstc = msto->mstc;
931 struct nv50_mstm *mstm = mstc->mstm;
932 struct drm_dp_mst_atomic_payload *payload;
935 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
937 payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port);
939 if (msto->disabled) {
940 drm_dp_remove_payload_part1(mgr, mst_state, payload);
941 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0);
945 ret = drm_dp_add_payload_part1(mgr, mst_state, payload);
949 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index,
950 payload->vc_start_slot, payload->time_slots,
952 payload->time_slots * dfixed_trunc(mst_state->pbn_div));
954 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0);
959 nv50_msto_atomic_check(struct drm_encoder *encoder,
960 struct drm_crtc_state *crtc_state,
961 struct drm_connector_state *conn_state)
963 struct drm_atomic_state *state = crtc_state->state;
964 struct drm_connector *connector = conn_state->connector;
965 struct drm_dp_mst_topology_state *mst_state;
966 struct nv50_mstc *mstc = nv50_mstc(connector);
967 struct nv50_mstm *mstm = mstc->mstm;
968 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
972 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
977 if (!drm_atomic_crtc_needs_modeset(crtc_state))
981 * When restoring duplicated states, we need to make sure that the bw
982 * remains the same and avoid recalculating it, as the connector's bpc
983 * may have changed after the state was duplicated
985 if (!state->duplicated) {
986 const int clock = crtc_state->adjusted_mode.clock;
988 asyh->or.bpc = connector->display_info.bpc;
989 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
992 mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
993 if (IS_ERR(mst_state))
994 return PTR_ERR(mst_state);
996 if (!mst_state->pbn_div.full) {
997 struct nouveau_encoder *outp = mstc->mstm->outp;
999 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr,
1000 outp->dp.link_bw, outp->dp.link_nr);
1003 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
1007 asyh->dp.tu = slots;
1013 nv50_dp_bpc_to_depth(unsigned int bpc)
1016 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
1017 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
1019 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1024 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1026 struct nv50_msto *msto = nv50_msto(encoder);
1027 struct nv50_head *head = msto->head;
1028 struct nv50_head_atom *asyh =
1029 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base));
1030 struct nv50_mstc *mstc = NULL;
1031 struct nv50_mstm *mstm = NULL;
1032 struct drm_connector *connector;
1033 struct drm_connector_list_iter conn_iter;
1036 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1037 drm_for_each_connector_iter(connector, &conn_iter) {
1038 if (connector->state->best_encoder == &msto->encoder) {
1039 mstc = nv50_mstc(connector);
1044 drm_connector_list_iter_end(&conn_iter);
1049 if (!mstm->links++) {
1050 nvif_outp_acquire_sor(&mstm->outp->outp, false /*TODO: MST audio... */);
1051 nouveau_dp_train(mstm->outp, true, 0, 0);
1054 if (head->func->display_id) {
1055 if (!WARN_ON(nvif_outp_dp_mst_id_get(&mstm->outp->outp, &msto->display_id)))
1056 head->func->display_id(head, msto->display_id);
1059 if (mstm->outp->outp.or.link & 1)
1060 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1062 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1064 mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1065 nv50_dp_bpc_to_depth(asyh->or.bpc));
1068 msto->enabled = true;
1069 mstm->modified = true;
1073 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1075 struct nv50_msto *msto = nv50_msto(encoder);
1076 struct nv50_mstc *mstc = msto->mstc;
1077 struct nv50_mstm *mstm = mstc->mstm;
1079 if (msto->head->func->display_id)
1080 msto->head->func->display_id(msto->head, 0);
1082 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1083 mstm->modified = true;
1085 mstm->disabled = true;
1086 msto->disabled = true;
1089 static const struct drm_encoder_helper_funcs
1091 .atomic_disable = nv50_msto_atomic_disable,
1092 .atomic_enable = nv50_msto_atomic_enable,
1093 .atomic_check = nv50_msto_atomic_check,
1097 nv50_msto_destroy(struct drm_encoder *encoder)
1099 struct nv50_msto *msto = nv50_msto(encoder);
1100 drm_encoder_cleanup(&msto->encoder);
1104 static const struct drm_encoder_funcs
1106 .destroy = nv50_msto_destroy,
1109 static struct nv50_msto *
1110 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1112 struct nv50_msto *msto;
1115 msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1117 return ERR_PTR(-ENOMEM);
1119 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1120 DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1123 return ERR_PTR(ret);
1126 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1127 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1132 static struct drm_encoder *
1133 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1134 struct drm_atomic_state *state)
1136 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1138 struct nv50_mstc *mstc = nv50_mstc(connector);
1139 struct drm_crtc *crtc = connector_state->crtc;
1141 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1144 return &nv50_head(crtc)->msto->encoder;
1147 static enum drm_mode_status
1148 nv50_mstc_mode_valid(struct drm_connector *connector,
1149 struct drm_display_mode *mode)
1151 struct nv50_mstc *mstc = nv50_mstc(connector);
1152 struct nouveau_encoder *outp = mstc->mstm->outp;
1154 /* TODO: calculate the PBN from the dotclock and validate against the
1155 * MSTB's max possible PBN
1158 return nv50_dp_mode_valid(outp, mode, NULL);
1162 nv50_mstc_get_modes(struct drm_connector *connector)
1164 struct nv50_mstc *mstc = nv50_mstc(connector);
1167 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1168 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1170 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1173 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1174 * to 8 to save bandwidth on the topology. In the future, we'll want
1175 * to properly fix this by dynamically selecting the highest possible
1176 * bpc that would fit in the topology
1178 if (connector->display_info.bpc)
1179 connector->display_info.bpc =
1180 clamp(connector->display_info.bpc, 6U, 8U);
1182 connector->display_info.bpc = 8;
1185 drm_mode_destroy(mstc->connector.dev, mstc->native);
1186 mstc->native = nouveau_conn_native_mode(&mstc->connector);
1191 nv50_mstc_atomic_check(struct drm_connector *connector,
1192 struct drm_atomic_state *state)
1194 struct nv50_mstc *mstc = nv50_mstc(connector);
1195 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1197 return drm_dp_atomic_release_time_slots(state, mgr, mstc->port);
1201 nv50_mstc_detect(struct drm_connector *connector,
1202 struct drm_modeset_acquire_ctx *ctx, bool force)
1204 struct nv50_mstc *mstc = nv50_mstc(connector);
1207 if (drm_connector_is_unregistered(connector))
1208 return connector_status_disconnected;
1210 ret = pm_runtime_get_sync(connector->dev->dev);
1211 if (ret < 0 && ret != -EACCES) {
1212 pm_runtime_put_autosuspend(connector->dev->dev);
1213 return connector_status_disconnected;
1216 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1218 if (ret != connector_status_connected)
1222 pm_runtime_mark_last_busy(connector->dev->dev);
1223 pm_runtime_put_autosuspend(connector->dev->dev);
1227 static const struct drm_connector_helper_funcs
1229 .get_modes = nv50_mstc_get_modes,
1230 .mode_valid = nv50_mstc_mode_valid,
1231 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1232 .atomic_check = nv50_mstc_atomic_check,
1233 .detect_ctx = nv50_mstc_detect,
1237 nv50_mstc_destroy(struct drm_connector *connector)
1239 struct nv50_mstc *mstc = nv50_mstc(connector);
1241 drm_connector_cleanup(&mstc->connector);
1242 drm_dp_mst_put_port_malloc(mstc->port);
1247 static const struct drm_connector_funcs
1249 .reset = nouveau_conn_reset,
1250 .fill_modes = drm_helper_probe_single_connector_modes,
1251 .destroy = nv50_mstc_destroy,
1252 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1253 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1254 .atomic_set_property = nouveau_conn_atomic_set_property,
1255 .atomic_get_property = nouveau_conn_atomic_get_property,
1259 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1260 const char *path, struct nv50_mstc **pmstc)
1262 struct drm_device *dev = mstm->outp->base.base.dev;
1263 struct drm_crtc *crtc;
1264 struct nv50_mstc *mstc;
1267 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1272 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1273 DRM_MODE_CONNECTOR_DisplayPort);
1280 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1282 mstc->connector.funcs->reset(&mstc->connector);
1283 nouveau_conn_attach_properties(&mstc->connector);
1285 drm_for_each_crtc(crtc, dev) {
1286 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1289 drm_connector_attach_encoder(&mstc->connector,
1290 &nv50_head(crtc)->msto->encoder);
1293 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1294 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1295 drm_connector_set_path_property(&mstc->connector, path);
1296 drm_dp_mst_get_port_malloc(port);
1301 nv50_mstm_cleanup(struct drm_atomic_state *state,
1302 struct drm_dp_mst_topology_state *mst_state,
1303 struct nv50_mstm *mstm)
1305 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1306 struct drm_encoder *encoder;
1308 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1309 drm_dp_check_act_status(&mstm->mgr);
1311 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1312 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1313 struct nv50_msto *msto = nv50_msto(encoder);
1314 struct nv50_mstc *mstc = msto->mstc;
1315 if (mstc && mstc->mstm == mstm)
1316 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto);
1320 if (mstm->disabled) {
1321 nouveau_dp_power_down(mstm->outp);
1322 nvif_outp_release(&mstm->outp->outp);
1323 mstm->disabled = false;
1326 mstm->modified = false;
1330 nv50_mstm_prepare(struct drm_atomic_state *state,
1331 struct drm_dp_mst_topology_state *mst_state,
1332 struct nv50_mstm *mstm)
1334 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1335 struct drm_encoder *encoder;
1337 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1339 /* Disable payloads first */
1340 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1341 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1342 struct nv50_msto *msto = nv50_msto(encoder);
1343 struct nv50_mstc *mstc = msto->mstc;
1344 if (mstc && mstc->mstm == mstm && msto->disabled)
1345 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1349 /* Add payloads for new heads, while also updating the start slots of any unmodified (but
1350 * active) heads that may have had their VC slots shifted left after the previous step
1352 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1353 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1354 struct nv50_msto *msto = nv50_msto(encoder);
1355 struct nv50_mstc *mstc = msto->mstc;
1356 if (mstc && mstc->mstm == mstm && !msto->disabled)
1357 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1362 static struct drm_connector *
1363 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1364 struct drm_dp_mst_port *port, const char *path)
1366 struct nv50_mstm *mstm = nv50_mstm(mgr);
1367 struct nv50_mstc *mstc;
1370 ret = nv50_mstc_new(mstm, port, path, &mstc);
1374 return &mstc->connector;
1377 static const struct drm_dp_mst_topology_cbs
1379 .add_connector = nv50_mstm_add_connector,
1383 nv50_mstm_service(struct nouveau_drm *drm,
1384 struct nouveau_connector *nv_connector,
1385 struct nv50_mstm *mstm)
1387 struct drm_dp_aux *aux = &nv_connector->aux;
1388 bool handled = true, ret = true;
1395 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1401 drm_dp_mst_hpd_irq_handle_event(&mstm->mgr, esi, ack, &handled);
1405 rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]);
1412 drm_dp_mst_hpd_irq_send_new_request(&mstm->mgr);
1416 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
1417 nv_connector->base.name, rc);
1423 nv50_mstm_remove(struct nv50_mstm *mstm)
1425 mstm->is_mst = false;
1426 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1430 nv50_mstm_detect(struct nouveau_encoder *outp)
1432 struct nv50_mstm *mstm = outp->dp.mstm;
1433 struct drm_dp_aux *aux;
1436 if (!mstm || !mstm->can_mst)
1439 aux = mstm->mgr.aux;
1441 /* Clear any leftover MST state we didn't set ourselves by first
1442 * disabling MST if it was already enabled
1444 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1448 /* And start enabling */
1449 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
1453 mstm->is_mst = true;
1458 nv50_mstm_fini(struct nouveau_encoder *outp)
1460 struct nv50_mstm *mstm = outp->dp.mstm;
1465 /* Don't change the MST state of this connector until we've finished
1466 * resuming, since we can't safely grab hpd_irq_lock in our resume
1467 * path to protect mstm->is_mst without potentially deadlocking
1469 mutex_lock(&outp->dp.hpd_irq_lock);
1470 mstm->suspended = true;
1471 mutex_unlock(&outp->dp.hpd_irq_lock);
1474 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1478 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1480 struct nv50_mstm *mstm = outp->dp.mstm;
1487 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1489 nv50_mstm_remove(mstm);
1492 mutex_lock(&outp->dp.hpd_irq_lock);
1493 mstm->suspended = false;
1494 mutex_unlock(&outp->dp.hpd_irq_lock);
1497 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1501 nv50_mstm_del(struct nv50_mstm **pmstm)
1503 struct nv50_mstm *mstm = *pmstm;
1505 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1512 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1513 int conn_base_id, struct nv50_mstm **pmstm)
1515 const int max_payloads = hweight8(outp->dcb->heads);
1516 struct drm_device *dev = outp->base.base.dev;
1517 struct nv50_mstm *mstm;
1520 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1523 mstm->mgr.cbs = &nv50_mstm;
1525 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1526 max_payloads, conn_base_id);
1533 /******************************************************************************
1535 *****************************************************************************/
1537 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1538 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1540 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1541 struct nv50_core *core = disp->core;
1544 nv_encoder->ctrl &= ~BIT(head);
1545 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1546 nv_encoder->ctrl = 0;
1548 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1549 nv_encoder->ctrl |= BIT(head);
1550 asyh->or.depth = depth;
1553 core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh);
1556 /* TODO: Should we extend this to PWM-only backlights?
1557 * As well, should we add a DRM helper for waiting for the backlight to acknowledge
1558 * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
1559 * fixed time delay from the vbios…
1562 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1564 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1565 struct nv50_head *head = nv50_head(nv_encoder->crtc);
1566 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1567 struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
1568 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
1569 struct nouveau_backlight *backlight = nv_connector->backlight;
1570 struct drm_dp_aux *aux = &nv_connector->aux;
1573 if (backlight && backlight->uses_dpcd) {
1574 ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
1576 NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
1577 nv_connector->base.base.id, nv_connector->base.name, ret);
1581 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS && nv_encoder->hdmi.enabled) {
1582 nvif_outp_hdmi(&nv_encoder->outp, head->base.index,
1583 false, 0, 0, 0, false, false, false);
1584 nv_encoder->hdmi.enabled = false;
1587 if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1588 nouveau_dp_power_down(nv_encoder);
1590 if (head->func->display_id)
1591 head->func->display_id(head, 0);
1593 nv_encoder->update(nv_encoder, head->base.index, NULL, 0, 0);
1594 nv50_audio_disable(encoder, &head->base);
1595 nv_encoder->crtc = NULL;
1598 // common/inc/displayport/displayport.h
1599 #define DP_CONFIG_WATERMARK_ADJUST 2
1600 #define DP_CONFIG_WATERMARK_LIMIT 20
1601 #define DP_CONFIG_INCREASED_WATERMARK_ADJUST 8
1602 #define DP_CONFIG_INCREASED_WATERMARK_LIMIT 22
1605 nv50_sor_dp_watermark_sst(struct nouveau_encoder *outp,
1606 struct nv50_head *head, struct nv50_head_atom *asyh)
1608 bool enhancedFraming = outp->dp.dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP;
1609 u64 minRate = outp->dp.link_bw * 1000;
1610 unsigned tuSize = 64;
1614 unsigned watermarkAdjust = DP_CONFIG_WATERMARK_ADJUST;
1615 unsigned watermarkMinimum = DP_CONFIG_WATERMARK_LIMIT;
1616 // depth is multiplied by 16 in case of DSC enable
1618 // number of link clocks per line.
1619 int vblank_symbols = 0;
1620 bool bEnableDsc = false;
1621 unsigned surfaceWidth = asyh->mode.h.blanks - asyh->mode.h.blanke;
1622 unsigned rasterWidth = asyh->mode.h.active;
1623 unsigned depth = asyh->or.bpc * 3;
1624 unsigned DSC_FACTOR = bEnableDsc ? 16 : 1;
1625 u64 pixelClockHz = asyh->mode.clock * 1000;
1626 u64 PrecisionFactor = 100000, ratioF, watermarkF;
1627 u32 numLanesPerLink = outp->dp.link_nr;
1628 u32 numSymbolsPerLine;
1630 u32 surfaceWidthPerLink;
1631 u32 PixelSteeringBits;
1632 u64 NumBlankingLinkClocks;
1635 if (outp->outp.info.dp.increased_wm) {
1636 watermarkAdjust = DP_CONFIG_INCREASED_WATERMARK_ADJUST;
1637 watermarkMinimum = DP_CONFIG_INCREASED_WATERMARK_LIMIT;
1640 if ((pixelClockHz * depth) >= (8 * minRate * outp->dp.link_nr * DSC_FACTOR))
1646 // For DSC, if (pclk * bpp) < (1/64 * orclk * 8 * lanes) then some TU may end up with
1647 // 0 active symbols. This may cause HW hang. Bug 200379426
1650 ((pixelClockHz * depth) < div_u64(8 * minRate * outp->dp.link_nr * DSC_FACTOR, 64)))
1656 // Perform the SST calculation.
1657 // For auto mode the watermark calculation does not need to track accumulated error the
1658 // formulas for manual mode will not work. So below calculation was extracted from the DTB.
1660 ratioF = div_u64((u64)pixelClockHz * depth * PrecisionFactor, DSC_FACTOR);
1662 ratioF = div_u64(ratioF, 8 * (u64) minRate * outp->dp.link_nr);
1664 if (PrecisionFactor < ratioF) // Assert if we will end up with a negative number in below
1667 watermarkF = div_u64(ratioF * tuSize * (PrecisionFactor - ratioF), PrecisionFactor);
1668 waterMark = (unsigned)(watermarkAdjust + (div_u64(2 * div_u64(depth * PrecisionFactor, 8 * numLanesPerLink * DSC_FACTOR) + watermarkF, PrecisionFactor)));
1671 // Bounds check the watermark
1673 numSymbolsPerLine = div_u64(surfaceWidth * depth, 8 * outp->dp.link_nr * DSC_FACTOR);
1675 if (WARN_ON(waterMark > 39 || waterMark > numSymbolsPerLine))
1679 // Clamp the low side
1681 if (waterMark < watermarkMinimum)
1682 waterMark = watermarkMinimum;
1684 //Bits to send BS/BE/Extra symbols due to pixel padding
1685 //Also accounts for enhanced framing.
1686 BlankingBits = 3*8*numLanesPerLink + (enhancedFraming ? 3*8*numLanesPerLink : 0);
1688 //VBID/MVID/MAUD sent 4 times all the time
1689 BlankingBits += 3*8*4;
1691 surfaceWidthPerLink = surfaceWidth;
1693 //Extra bits sent due to pixel steering
1695 div_u64_rem(surfaceWidthPerLink, numLanesPerLink, &remain);
1696 PixelSteeringBits = remain ? div_u64((numLanesPerLink - remain) * depth, DSC_FACTOR) : 0;
1698 BlankingBits += PixelSteeringBits;
1699 NumBlankingLinkClocks = div_u64((u64)BlankingBits * PrecisionFactor, (8 * numLanesPerLink));
1700 MinHBlank = (u32)(div_u64(div_u64(NumBlankingLinkClocks * pixelClockHz, minRate), PrecisionFactor));
1703 if (WARN_ON(MinHBlank > rasterWidth - surfaceWidth))
1706 // Bug 702290 - Active Width should be greater than 60
1707 if (WARN_ON(surfaceWidth <= 60))
1711 hblank_symbols = (s32)(div_u64((u64)(rasterWidth - surfaceWidth - MinHBlank) * minRate, pixelClockHz));
1713 //reduce HBlank Symbols to account for secondary data packet
1714 hblank_symbols -= 1; //Stuffer latency to send BS
1715 hblank_symbols -= 3; //SPKT latency to send data to stuffer
1717 hblank_symbols -= numLanesPerLink == 1 ? 9 : numLanesPerLink == 2 ? 6 : 3;
1719 hBlankSym = (hblank_symbols < 0) ? 0 : hblank_symbols;
1721 // Refer to dev_disp.ref for more information.
1722 // # symbols/vblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - SetRasterBlankStart.X - 40) * link_clk / pclk) - Y - 1;
1723 // where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39
1724 if (surfaceWidth < 40)
1730 vblank_symbols = (s32)((div_u64((u64)(surfaceWidth - 40) * minRate, pixelClockHz))) - 1;
1732 vblank_symbols -= numLanesPerLink == 1 ? 39 : numLanesPerLink == 2 ? 21 : 12;
1735 vBlankSym = (vblank_symbols < 0) ? 0 : vblank_symbols;
1737 return nvif_outp_dp_sst(&outp->outp, head->base.index, waterMark, hBlankSym, vBlankSym);
1741 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1743 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1744 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1745 struct nv50_head_atom *asyh =
1746 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1747 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1748 struct nv50_disp *disp = nv50_disp(encoder->dev);
1749 struct nv50_head *head = nv50_head(&nv_crtc->base);
1750 struct nvif_outp *outp = &nv_encoder->outp;
1751 struct drm_device *dev = encoder->dev;
1752 struct nouveau_drm *drm = nouveau_drm(dev);
1753 struct nouveau_connector *nv_connector;
1754 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1755 struct nouveau_backlight *backlight;
1757 struct nvbios *bios = &drm->vbios;
1758 bool lvds_dual = false, lvds_8bpc = false, hda = false;
1759 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1760 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1762 nv_connector = nv50_outp_get_new_connector(state, nv_encoder);
1763 nv_encoder->crtc = &nv_crtc->base;
1765 if ((disp->disp->object.oclass == GT214_DISP ||
1766 disp->disp->object.oclass >= GF110_DISP) &&
1767 nv_encoder->dcb->type != DCB_OUTPUT_LVDS &&
1768 drm_detect_monitor_audio(nv_connector->edid))
1771 if (!nvif_outp_acquired(outp))
1772 nvif_outp_acquire_sor(outp, hda);
1774 switch (nv_encoder->dcb->type) {
1775 case DCB_OUTPUT_TMDS:
1776 if (disp->disp->object.oclass != NV50_DISP &&
1777 drm_detect_hdmi_monitor(nv_connector->edid))
1778 nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda);
1780 if (nv_encoder->outp.or.link & 1) {
1781 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1782 /* Only enable dual-link if:
1783 * - Need to (i.e. rate > 165MHz)
1785 * - Not an HDMI monitor, since there's no dual-link
1788 if (mode->clock >= 165000 &&
1789 nv_encoder->dcb->duallink_possible &&
1790 !drm_detect_hdmi_monitor(nv_connector->edid))
1791 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1793 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1796 case DCB_OUTPUT_LVDS:
1797 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1799 if (bios->fp_no_ddc) {
1800 lvds_dual = bios->fp.dual_link;
1801 lvds_8bpc = bios->fp.if_is_24bit;
1803 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1804 if (((u8 *)nv_connector->edid)[121] == 2)
1807 if (mode->clock >= bios->fp.duallink_transition_clk) {
1812 if (bios->fp.strapless_is_24bit & 2)
1815 if (bios->fp.strapless_is_24bit & 1)
1819 if (asyh->or.bpc == 8)
1823 nvif_outp_lvds(&nv_encoder->outp, lvds_dual, lvds_8bpc);
1826 nouveau_dp_train(nv_encoder, false, mode->clock, asyh->or.bpc);
1827 nv50_sor_dp_watermark_sst(nv_encoder, head, asyh);
1828 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1830 if (nv_encoder->outp.or.link & 1)
1831 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1833 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1835 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1836 backlight = nv_connector->backlight;
1837 if (backlight && backlight->uses_dpcd)
1838 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
1839 (u16)backlight->dev->props.brightness);
1848 if (head->func->display_id)
1849 head->func->display_id(head, BIT(nv_encoder->outp.id));
1851 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1854 static const struct drm_encoder_helper_funcs
1856 .atomic_check = nv50_outp_atomic_check,
1857 .atomic_enable = nv50_sor_atomic_enable,
1858 .atomic_disable = nv50_sor_atomic_disable,
1862 nv50_sor_destroy(struct drm_encoder *encoder)
1864 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1866 nv50_mstm_del(&nv_encoder->dp.mstm);
1867 drm_encoder_cleanup(encoder);
1869 if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1870 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1872 nvif_outp_dtor(&nv_encoder->outp);
1876 static const struct drm_encoder_funcs
1878 .destroy = nv50_sor_destroy,
1882 nv50_sor_create(struct nouveau_encoder *nv_encoder)
1884 struct drm_connector *connector = &nv_encoder->conn->base;
1885 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1886 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1887 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1888 struct drm_encoder *encoder;
1889 struct dcb_output *dcbe = nv_encoder->dcb;
1890 struct nv50_disp *disp = nv50_disp(connector->dev);
1893 switch (dcbe->type) {
1894 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1895 case DCB_OUTPUT_TMDS:
1898 type = DRM_MODE_ENCODER_TMDS;
1902 nv_encoder->update = nv50_sor_update;
1904 encoder = to_drm_encoder(nv_encoder);
1905 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1906 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1907 drm_encoder_helper_add(encoder, &nv50_sor_help);
1909 drm_connector_attach_encoder(connector, encoder);
1911 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1912 nv50_outp_dump_caps(drm, nv_encoder);
1914 if (dcbe->type == DCB_OUTPUT_DP) {
1915 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1917 if (disp->disp->object.oclass < GF110_DISP) {
1918 /* HW has no support for address-only
1919 * transactions, so we're required to
1920 * use custom I2C-over-AUX code.
1922 struct nvkm_i2c_aux *aux;
1924 aux = nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1928 nv_encoder->i2c = &aux->i2c;
1930 nv_encoder->i2c = &nv_connector->aux.ddc;
1933 if (nv_connector->type != DCB_CONNECTOR_eDP && nv_encoder->outp.info.dp.mst) {
1934 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1935 16, nv_connector->base.base.id,
1936 &nv_encoder->dp.mstm);
1941 if (nv_encoder->outp.info.ddc != NVIF_OUTP_DDC_INVALID) {
1942 struct nvkm_i2c_bus *bus =
1943 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1945 nv_encoder->i2c = &bus->i2c;
1951 /******************************************************************************
1953 *****************************************************************************/
1955 nv50_pior_atomic_check(struct drm_encoder *encoder,
1956 struct drm_crtc_state *crtc_state,
1957 struct drm_connector_state *conn_state)
1959 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1962 crtc_state->adjusted_mode.clock *= 2;
1967 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1969 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1970 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1971 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1973 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
1974 nv_encoder->crtc = NULL;
1978 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1980 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1981 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1982 struct nv50_head_atom *asyh =
1983 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1984 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1987 switch (nv_crtc->index) {
1988 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1989 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1995 switch (asyh->or.bpc) {
1996 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1997 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1998 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1999 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
2002 if (!nvif_outp_acquired(&nv_encoder->outp))
2003 nvif_outp_acquire_pior(&nv_encoder->outp);
2005 switch (nv_encoder->dcb->type) {
2006 case DCB_OUTPUT_TMDS:
2007 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
2010 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
2011 nouveau_dp_train(nv_encoder, false, asyh->state.adjusted_mode.clock, 6);
2018 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
2019 nv_encoder->crtc = &nv_crtc->base;
2022 static const struct drm_encoder_helper_funcs
2024 .atomic_check = nv50_pior_atomic_check,
2025 .atomic_enable = nv50_pior_atomic_enable,
2026 .atomic_disable = nv50_pior_atomic_disable,
2030 nv50_pior_destroy(struct drm_encoder *encoder)
2032 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2034 nvif_outp_dtor(&nv_encoder->outp);
2036 drm_encoder_cleanup(encoder);
2038 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
2042 static const struct drm_encoder_funcs
2044 .destroy = nv50_pior_destroy,
2048 nv50_pior_create(struct nouveau_encoder *nv_encoder)
2050 struct drm_connector *connector = &nv_encoder->conn->base;
2051 struct drm_device *dev = connector->dev;
2052 struct nouveau_drm *drm = nouveau_drm(dev);
2053 struct nv50_disp *disp = nv50_disp(dev);
2054 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2055 struct nvkm_i2c_bus *bus = NULL;
2056 struct nvkm_i2c_aux *aux = NULL;
2057 struct i2c_adapter *ddc;
2058 struct drm_encoder *encoder;
2059 struct dcb_output *dcbe = nv_encoder->dcb;
2062 switch (dcbe->type) {
2063 case DCB_OUTPUT_TMDS:
2064 bus = nvkm_i2c_bus_find(i2c, nv_encoder->outp.info.ddc);
2065 ddc = bus ? &bus->i2c : NULL;
2066 type = DRM_MODE_ENCODER_TMDS;
2069 aux = nvkm_i2c_aux_find(i2c, nv_encoder->outp.info.dp.aux);
2070 ddc = aux ? &aux->i2c : NULL;
2071 type = DRM_MODE_ENCODER_TMDS;
2077 nv_encoder->i2c = ddc;
2079 mutex_init(&nv_encoder->dp.hpd_irq_lock);
2081 encoder = to_drm_encoder(nv_encoder);
2082 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
2083 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
2084 drm_encoder_helper_add(encoder, &nv50_pior_help);
2086 drm_connector_attach_encoder(connector, encoder);
2088 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
2089 nv50_outp_dump_caps(drm, nv_encoder);
2094 /******************************************************************************
2096 *****************************************************************************/
2099 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
2101 struct drm_dp_mst_topology_mgr *mgr;
2102 struct drm_dp_mst_topology_state *mst_state;
2103 struct nouveau_drm *drm = nouveau_drm(state->dev);
2104 struct nv50_disp *disp = nv50_disp(drm->dev);
2105 struct nv50_atom *atom = nv50_atom(state);
2106 struct nv50_core *core = disp->core;
2107 struct nv50_outp_atom *outp;
2108 struct nv50_mstm *mstm;
2111 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
2113 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
2114 mstm = nv50_mstm(mgr);
2116 nv50_mstm_prepare(state, mst_state, mstm);
2119 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
2120 core->func->update(core, interlock, true);
2121 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
2122 disp->core->chan.base.device))
2123 NV_ERROR(drm, "core notifier timeout\n");
2125 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
2126 mstm = nv50_mstm(mgr);
2128 nv50_mstm_cleanup(state, mst_state, mstm);
2131 list_for_each_entry(outp, &atom->outp, head) {
2132 if (outp->encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2133 struct nouveau_encoder *nv_encoder = nouveau_encoder(outp->encoder);
2135 if (outp->enabled) {
2136 nv50_audio_enable(outp->encoder, nouveau_crtc(nv_encoder->crtc),
2137 nv_encoder->conn, NULL, NULL);
2138 outp->enabled = outp->disabled = false;
2140 if (outp->disabled) {
2141 nvif_outp_release(&nv_encoder->outp);
2142 outp->disabled = false;
2150 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
2152 struct drm_plane_state *new_plane_state;
2153 struct drm_plane *plane;
2156 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2157 struct nv50_wndw *wndw = nv50_wndw(plane);
2158 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
2159 if (wndw->func->update)
2160 wndw->func->update(wndw, interlock);
2166 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
2168 struct drm_device *dev = state->dev;
2169 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
2170 struct drm_crtc *crtc;
2171 struct drm_plane_state *new_plane_state;
2172 struct drm_plane *plane;
2173 struct nouveau_drm *drm = nouveau_drm(dev);
2174 struct nv50_disp *disp = nv50_disp(dev);
2175 struct nv50_atom *atom = nv50_atom(state);
2176 struct nv50_core *core = disp->core;
2177 struct nv50_outp_atom *outp, *outt;
2178 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2180 bool flushed = false;
2182 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2183 nv50_crc_atomic_stop_reporting(state);
2184 drm_atomic_helper_wait_for_fences(dev, state, false);
2185 drm_atomic_helper_wait_for_dependencies(state);
2186 drm_dp_mst_atomic_wait_for_dependencies(state);
2187 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2188 drm_atomic_helper_calc_timestamping_constants(state);
2190 if (atom->lock_core)
2191 mutex_lock(&disp->mutex);
2193 /* Disable head(s). */
2194 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2195 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2196 struct nv50_head *head = nv50_head(crtc);
2198 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2199 asyh->clr.mask, asyh->set.mask);
2201 if (old_crtc_state->active && !new_crtc_state->active) {
2202 pm_runtime_put_noidle(dev->dev);
2203 drm_crtc_vblank_off(crtc);
2206 if (asyh->clr.mask) {
2207 nv50_head_flush_clr(head, asyh, atom->flush_disable);
2208 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2212 /* Disable plane(s). */
2213 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2214 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2215 struct nv50_wndw *wndw = nv50_wndw(plane);
2217 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2218 asyw->clr.mask, asyw->set.mask);
2219 if (!asyw->clr.mask)
2222 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2225 /* Disable output path(s). */
2226 list_for_each_entry(outp, &atom->outp, head) {
2227 const struct drm_encoder_helper_funcs *help;
2228 struct drm_encoder *encoder;
2230 encoder = outp->encoder;
2231 help = encoder->helper_private;
2233 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2234 outp->clr.mask, outp->set.mask);
2236 if (outp->clr.mask) {
2237 help->atomic_disable(encoder, state);
2238 outp->disabled = true;
2239 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2243 /* Flush disable. */
2244 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2245 if (atom->flush_disable) {
2246 nv50_disp_atomic_commit_wndw(state, interlock);
2247 nv50_disp_atomic_commit_core(state, interlock);
2248 memset(interlock, 0x00, sizeof(interlock));
2255 nv50_crc_atomic_release_notifier_contexts(state);
2256 nv50_crc_atomic_init_notifier_contexts(state);
2258 /* Update output path(s). */
2259 list_for_each_entry(outp, &atom->outp, head) {
2260 const struct drm_encoder_helper_funcs *help;
2261 struct drm_encoder *encoder;
2263 encoder = outp->encoder;
2264 help = encoder->helper_private;
2266 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2267 outp->set.mask, outp->clr.mask);
2269 if (outp->set.mask) {
2270 help->atomic_enable(encoder, state);
2271 outp->enabled = true;
2272 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2276 /* Update head(s). */
2277 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2278 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2279 struct nv50_head *head = nv50_head(crtc);
2281 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2282 asyh->set.mask, asyh->clr.mask);
2284 if (asyh->set.mask) {
2285 nv50_head_flush_set(head, asyh);
2286 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2289 if (new_crtc_state->active) {
2290 if (!old_crtc_state->active) {
2291 drm_crtc_vblank_on(crtc);
2292 pm_runtime_get_noresume(dev->dev);
2294 if (new_crtc_state->event)
2295 drm_crtc_vblank_get(crtc);
2299 /* Update window->head assignment.
2301 * This has to happen in an update that's not interlocked with
2302 * any window channels to avoid hitting HW error checks.
2304 *TODO: Proper handling of window ownership (Turing apparently
2305 * supports non-fixed mappings).
2307 if (core->assign_windows) {
2308 core->func->wndw.owner(core);
2309 nv50_disp_atomic_commit_core(state, interlock);
2310 core->assign_windows = false;
2311 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2314 /* Finish updating head(s)...
2316 * NVD is rather picky about both where window assignments can change,
2317 * *and* about certain core and window channel states matching.
2319 * The EFI GOP driver on newer GPUs configures window channels with a
2320 * different output format to what we do, and the core channel update
2321 * in the assign_windows case above would result in a state mismatch.
2323 * Delay some of the head update until after that point to workaround
2324 * the issue. This only affects the initial modeset.
2326 * TODO: handle this better when adding flexible window mapping
2328 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2329 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2330 struct nv50_head *head = nv50_head(crtc);
2332 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2333 asyh->set.mask, asyh->clr.mask);
2335 if (asyh->set.mask) {
2336 nv50_head_flush_set_wndw(head, asyh);
2337 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2341 /* Update plane(s). */
2342 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2343 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2344 struct nv50_wndw *wndw = nv50_wndw(plane);
2346 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2347 asyw->set.mask, asyw->clr.mask);
2348 if ( !asyw->set.mask &&
2349 (!asyw->clr.mask || atom->flush_disable))
2352 nv50_wndw_flush_set(wndw, interlock, asyw);
2356 nv50_disp_atomic_commit_wndw(state, interlock);
2358 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2359 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2360 interlock[NV50_DISP_INTERLOCK_OVLY] ||
2361 interlock[NV50_DISP_INTERLOCK_WNDW] ||
2362 !atom->state.legacy_cursor_update)
2363 nv50_disp_atomic_commit_core(state, interlock);
2365 disp->core->func->update(disp->core, interlock, false);
2368 if (atom->lock_core)
2369 mutex_unlock(&disp->mutex);
2371 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2372 list_del(&outp->head);
2376 /* Wait for HW to signal completion. */
2377 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2378 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2379 struct nv50_wndw *wndw = nv50_wndw(plane);
2380 int ret = nv50_wndw_wait_armed(wndw, asyw);
2382 NV_ERROR(drm, "%s: timeout\n", plane->name);
2385 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2386 if (new_crtc_state->event) {
2387 unsigned long flags;
2388 /* Get correct count/ts if racing with vblank irq */
2389 if (new_crtc_state->active)
2390 drm_crtc_accurate_vblank_count(crtc);
2391 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2392 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2393 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2395 new_crtc_state->event = NULL;
2396 if (new_crtc_state->active)
2397 drm_crtc_vblank_put(crtc);
2401 nv50_crc_atomic_start_reporting(state);
2403 nv50_crc_atomic_release_notifier_contexts(state);
2405 drm_atomic_helper_commit_hw_done(state);
2406 drm_atomic_helper_cleanup_planes(dev, state);
2407 drm_atomic_helper_commit_cleanup_done(state);
2408 drm_atomic_state_put(state);
2410 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2411 pm_runtime_mark_last_busy(dev->dev);
2412 pm_runtime_put_autosuspend(dev->dev);
2416 nv50_disp_atomic_commit_work(struct work_struct *work)
2418 struct drm_atomic_state *state =
2419 container_of(work, typeof(*state), commit_work);
2420 nv50_disp_atomic_commit_tail(state);
2424 nv50_disp_atomic_commit(struct drm_device *dev,
2425 struct drm_atomic_state *state, bool nonblock)
2427 struct drm_plane_state *new_plane_state;
2428 struct drm_plane *plane;
2431 ret = pm_runtime_get_sync(dev->dev);
2432 if (ret < 0 && ret != -EACCES) {
2433 pm_runtime_put_autosuspend(dev->dev);
2437 ret = drm_atomic_helper_setup_commit(state, nonblock);
2441 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2443 ret = drm_atomic_helper_prepare_planes(dev, state);
2448 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2453 ret = drm_atomic_helper_swap_state(state, true);
2457 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2458 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2459 struct nv50_wndw *wndw = nv50_wndw(plane);
2461 if (asyw->set.image)
2462 nv50_wndw_ntfy_enable(wndw, asyw);
2465 drm_atomic_state_get(state);
2468 * Grab another RPM ref for the commit tail, which will release the
2469 * ref when it's finished
2471 pm_runtime_get_noresume(dev->dev);
2474 queue_work(system_unbound_wq, &state->commit_work);
2476 nv50_disp_atomic_commit_tail(state);
2480 drm_atomic_helper_unprepare_planes(dev, state);
2482 pm_runtime_put_autosuspend(dev->dev);
2486 static struct nv50_outp_atom *
2487 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2489 struct nv50_outp_atom *outp;
2491 list_for_each_entry(outp, &atom->outp, head) {
2492 if (outp->encoder == encoder)
2496 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2498 return ERR_PTR(-ENOMEM);
2500 list_add(&outp->head, &atom->outp);
2501 outp->encoder = encoder;
2506 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2507 struct drm_connector_state *old_connector_state)
2509 struct drm_encoder *encoder = old_connector_state->best_encoder;
2510 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2511 struct drm_crtc *crtc;
2512 struct nv50_outp_atom *outp;
2514 if (!(crtc = old_connector_state->crtc))
2517 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2518 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2519 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2520 outp = nv50_disp_outp_atomic_add(atom, encoder);
2522 return PTR_ERR(outp);
2524 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST ||
2525 nouveau_encoder(outp->encoder)->dcb->type == DCB_OUTPUT_DP)
2526 atom->flush_disable = true;
2527 outp->clr.ctrl = true;
2528 atom->lock_core = true;
2535 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2536 struct drm_connector_state *connector_state)
2538 struct drm_encoder *encoder = connector_state->best_encoder;
2539 struct drm_crtc_state *new_crtc_state;
2540 struct drm_crtc *crtc;
2541 struct nv50_outp_atom *outp;
2543 if (!(crtc = connector_state->crtc))
2546 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2547 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2548 outp = nv50_disp_outp_atomic_add(atom, encoder);
2550 return PTR_ERR(outp);
2552 outp->set.ctrl = true;
2553 atom->lock_core = true;
2560 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2562 struct nv50_atom *atom = nv50_atom(state);
2563 struct nv50_core *core = nv50_disp(dev)->core;
2564 struct drm_connector_state *old_connector_state, *new_connector_state;
2565 struct drm_connector *connector;
2566 struct drm_crtc_state *new_crtc_state;
2567 struct drm_crtc *crtc;
2568 struct nv50_head *head;
2569 struct nv50_head_atom *asyh;
2572 if (core->assign_windows && core->func->head->static_wndw_map) {
2573 drm_for_each_crtc(crtc, dev) {
2574 new_crtc_state = drm_atomic_get_crtc_state(state,
2576 if (IS_ERR(new_crtc_state))
2577 return PTR_ERR(new_crtc_state);
2579 head = nv50_head(crtc);
2580 asyh = nv50_head_atom(new_crtc_state);
2581 core->func->head->static_wndw_map(head, asyh);
2585 /* We need to handle colour management on a per-plane basis. */
2586 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2587 if (new_crtc_state->color_mgmt_changed) {
2588 ret = drm_atomic_add_affected_planes(state, crtc);
2594 ret = drm_atomic_helper_check(dev, state);
2598 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2599 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2603 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2608 ret = drm_dp_mst_atomic_check(state);
2612 nv50_crc_atomic_check_outp(atom);
2618 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2620 struct nv50_atom *atom = nv50_atom(state);
2621 struct nv50_outp_atom *outp, *outt;
2623 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2624 list_del(&outp->head);
2628 drm_atomic_state_default_clear(state);
2632 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2634 struct nv50_atom *atom = nv50_atom(state);
2635 drm_atomic_state_default_release(&atom->state);
2639 static struct drm_atomic_state *
2640 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2642 struct nv50_atom *atom;
2643 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2644 drm_atomic_state_init(dev, &atom->state) < 0) {
2648 INIT_LIST_HEAD(&atom->outp);
2649 return &atom->state;
2652 static const struct drm_mode_config_funcs
2654 .fb_create = nouveau_user_framebuffer_create,
2655 .output_poll_changed = drm_fb_helper_output_poll_changed,
2656 .atomic_check = nv50_disp_atomic_check,
2657 .atomic_commit = nv50_disp_atomic_commit,
2658 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2659 .atomic_state_clear = nv50_disp_atomic_state_clear,
2660 .atomic_state_free = nv50_disp_atomic_state_free,
2663 static const struct drm_mode_config_helper_funcs
2664 nv50_disp_helper_func = {
2665 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2668 /******************************************************************************
2670 *****************************************************************************/
2673 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2675 struct nouveau_drm *drm = nouveau_drm(dev);
2676 struct drm_encoder *encoder;
2678 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2679 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2680 nv50_mstm_fini(nouveau_encoder(encoder));
2684 cancel_work_sync(&drm->hpd_work);
2688 nv50_display_read_hw_or_state(struct drm_device *dev, struct nv50_disp *disp,
2689 struct nouveau_encoder *outp)
2691 struct drm_crtc *crtc;
2692 struct drm_connector_list_iter conn_iter;
2693 struct drm_connector *conn;
2694 struct nv50_head_atom *armh;
2695 const u32 encoder_mask = drm_encoder_mask(&outp->base.base);
2696 bool found_conn = false, found_head = false;
2701 switch (outp->dcb->type) {
2702 case DCB_OUTPUT_TMDS:
2703 ret = nvif_outp_inherit_tmds(&outp->outp, &proto);
2706 ret = nvif_outp_inherit_dp(&outp->outp, &proto);
2708 case DCB_OUTPUT_LVDS:
2709 ret = nvif_outp_inherit_lvds(&outp->outp, &proto);
2711 case DCB_OUTPUT_ANALOG:
2712 ret = nvif_outp_inherit_rgb_crt(&outp->outp, &proto);
2715 drm_dbg_kms(dev, "Readback for %s not implemented yet, skipping\n",
2716 outp->base.base.name);
2717 drm_WARN_ON(dev, true);
2726 drm_for_each_crtc(crtc, dev) {
2727 if (crtc->index != head_idx)
2730 armh = nv50_head_atom(crtc->state);
2734 if (drm_WARN_ON(dev, !found_head))
2737 /* Figure out which connector is being used by this encoder */
2738 drm_connector_list_iter_begin(dev, &conn_iter);
2739 nouveau_for_each_non_mst_connector_iter(conn, &conn_iter) {
2740 if (nouveau_connector(conn)->index == outp->dcb->connector) {
2745 drm_connector_list_iter_end(&conn_iter);
2746 if (drm_WARN_ON(dev, !found_conn))
2749 armh->state.encoder_mask = encoder_mask;
2750 armh->state.connector_mask = drm_connector_mask(conn);
2751 armh->state.active = true;
2752 armh->state.enable = true;
2753 pm_runtime_get_noresume(dev->dev);
2756 outp->ctrl = NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto) | BIT(crtc->index);
2758 drm_connector_get(conn);
2759 conn->state->crtc = crtc;
2760 conn->state->best_encoder = &outp->base.base;
2763 /* Read back the currently programmed display state */
2765 nv50_display_read_hw_state(struct nouveau_drm *drm)
2767 struct drm_device *dev = drm->dev;
2768 struct drm_encoder *encoder;
2769 struct drm_modeset_acquire_ctx ctx;
2770 struct nv50_disp *disp = nv50_disp(dev);
2773 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
2775 drm_for_each_encoder(encoder, dev) {
2776 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
2779 nv50_display_read_hw_or_state(dev, disp, nouveau_encoder(encoder));
2782 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
2786 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2788 struct nv50_core *core = nv50_disp(dev)->core;
2789 struct drm_encoder *encoder;
2791 if (resume || runtime)
2792 core->func->init(core);
2794 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2795 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2796 struct nouveau_encoder *nv_encoder =
2797 nouveau_encoder(encoder);
2798 nv50_mstm_init(nv_encoder, runtime);
2803 nv50_display_read_hw_state(nouveau_drm(dev));
2809 nv50_display_destroy(struct drm_device *dev)
2811 struct nv50_disp *disp = nv50_disp(dev);
2813 nv50_audio_component_fini(nouveau_drm(dev));
2815 nvif_object_unmap(&disp->caps);
2816 nvif_object_dtor(&disp->caps);
2817 nv50_core_del(&disp->core);
2819 nouveau_bo_unmap(disp->sync);
2821 nouveau_bo_unpin(disp->sync);
2822 nouveau_bo_ref(NULL, &disp->sync);
2824 nouveau_display(dev)->priv = NULL;
2829 nv50_display_create(struct drm_device *dev)
2831 struct nouveau_drm *drm = nouveau_drm(dev);
2832 struct drm_connector *connector, *tmp;
2833 struct nv50_disp *disp;
2835 bool has_mst = false;
2837 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2841 mutex_init(&disp->mutex);
2843 nouveau_display(dev)->priv = disp;
2844 nouveau_display(dev)->dtor = nv50_display_destroy;
2845 nouveau_display(dev)->init = nv50_display_init;
2846 nouveau_display(dev)->fini = nv50_display_fini;
2847 disp->disp = &nouveau_display(dev)->disp;
2848 dev->mode_config.funcs = &nv50_disp_func;
2849 dev->mode_config.helper_private = &nv50_disp_helper_func;
2850 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2851 dev->mode_config.normalize_zpos = true;
2853 /* small shared memory area we use for notifiers and semaphores */
2854 ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
2855 NOUVEAU_GEM_DOMAIN_VRAM,
2856 0, 0x0000, NULL, NULL, &disp->sync);
2858 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2860 ret = nouveau_bo_map(disp->sync);
2862 nouveau_bo_unpin(disp->sync);
2865 nouveau_bo_ref(NULL, &disp->sync);
2871 /* allocate master evo channel */
2872 ret = nv50_core_new(drm, &disp->core);
2876 disp->core->func->init(disp->core);
2877 if (disp->core->func->caps_init) {
2878 ret = disp->core->func->caps_init(drm, disp);
2883 /* Assign the correct format modifiers */
2884 if (disp->disp->object.oclass >= TU102_DISP)
2885 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2887 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2888 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2890 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2892 /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later
2893 * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The
2894 * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to
2895 * small page allocations in prepare_fb(). When this is implemented, we should also force
2896 * large pages (128K) for ovly fbs in order to fix Kepler ovlys.
2897 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using
2900 if (disp->disp->object.oclass >= GM107_DISP) {
2901 dev->mode_config.cursor_width = 256;
2902 dev->mode_config.cursor_height = 256;
2903 } else if (disp->disp->object.oclass >= GK104_DISP) {
2904 dev->mode_config.cursor_width = 128;
2905 dev->mode_config.cursor_height = 128;
2907 dev->mode_config.cursor_width = 64;
2908 dev->mode_config.cursor_height = 64;
2911 /* create encoder/connector objects based on VBIOS DCB table */
2912 for_each_set_bit(i, &disp->disp->outp_mask, sizeof(disp->disp->outp_mask) * 8) {
2913 struct nouveau_encoder *outp;
2915 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2919 ret = nvif_outp_ctor(disp->disp, "kmsOutp", i, &outp->outp);
2925 connector = nouveau_connector_create(dev, outp->outp.info.conn);
2926 if (IS_ERR(connector)) {
2927 nvif_outp_dtor(&outp->outp);
2932 outp->base.base.possible_crtcs = outp->outp.info.heads;
2933 outp->base.base.possible_clones = 0;
2934 outp->conn = nouveau_connector(connector);
2936 outp->dcb = kzalloc(sizeof(*outp->dcb), GFP_KERNEL);
2940 switch (outp->outp.info.proto) {
2941 case NVIF_OUTP_RGB_CRT:
2942 outp->dcb->type = DCB_OUTPUT_ANALOG;
2943 outp->dcb->crtconf.maxfreq = outp->outp.info.rgb_crt.freq_max;
2945 case NVIF_OUTP_TMDS:
2946 outp->dcb->type = DCB_OUTPUT_TMDS;
2947 outp->dcb->duallink_possible = outp->outp.info.tmds.dual;
2949 case NVIF_OUTP_LVDS:
2950 outp->dcb->type = DCB_OUTPUT_LVDS;
2951 outp->dcb->lvdsconf.use_acpi_for_edid = outp->outp.info.lvds.acpi_edid;
2954 outp->dcb->type = DCB_OUTPUT_DP;
2955 outp->dcb->dpconf.link_nr = outp->outp.info.dp.link_nr;
2956 outp->dcb->dpconf.link_bw = outp->outp.info.dp.link_bw;
2957 if (outp->outp.info.dp.mst)
2965 outp->dcb->heads = outp->outp.info.heads;
2966 outp->dcb->connector = outp->outp.info.conn;
2967 outp->dcb->i2c_index = outp->outp.info.ddc;
2969 switch (outp->outp.info.type) {
2970 case NVIF_OUTP_DAC : ret = nv50_dac_create(outp); break;
2971 case NVIF_OUTP_SOR : ret = nv50_sor_create(outp); break;
2972 case NVIF_OUTP_PIOR: ret = nv50_pior_create(outp); break;
2979 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2980 i, outp->outp.info.type, outp->outp.info.proto, ret);
2984 /* cull any connectors we created that don't have an encoder */
2985 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2986 if (connector->possible_encoders)
2989 NV_WARN(drm, "%s has no encoders, removing\n",
2991 connector->funcs->destroy(connector);
2994 /* create crtc objects to represent the hw heads */
2995 for_each_set_bit(i, &disp->disp->head_mask, sizeof(disp->disp->head_mask) * 8) {
2996 struct nv50_head *head;
2998 head = nv50_head_create(dev, i);
3000 ret = PTR_ERR(head);
3005 head->msto = nv50_msto_new(dev, head, i);
3006 if (IS_ERR(head->msto)) {
3007 ret = PTR_ERR(head->msto);
3013 * FIXME: This is a hack to workaround the following
3016 * https://gitlab.gnome.org/GNOME/mutter/issues/759
3017 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
3019 * Once these issues are closed, this should be
3022 head->msto->encoder.possible_crtcs = disp->disp->head_mask;
3026 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
3027 dev->vblank_disable_immediate = true;
3029 nv50_audio_component_init(drm);
3033 nv50_display_destroy(dev);
3037 /******************************************************************************
3039 *****************************************************************************/
3041 /****************************************************************
3042 * Log2(block height) ----------------------------+ *
3043 * Page Kind ----------------------------------+ | *
3044 * Gob Height/Page Kind Generation ------+ | | *
3045 * Sector layout -------+ | | | *
3046 * Compression ------+ | | | | */
3047 const u64 disp50xx_modifiers[] = { /* | | | | | */
3048 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
3049 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
3050 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
3051 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
3052 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
3053 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
3054 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
3055 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
3056 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
3057 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
3058 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
3059 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
3060 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
3061 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
3062 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
3063 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
3064 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
3065 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
3066 DRM_FORMAT_MOD_LINEAR,
3067 DRM_FORMAT_MOD_INVALID
3070 /****************************************************************
3071 * Log2(block height) ----------------------------+ *
3072 * Page Kind ----------------------------------+ | *
3073 * Gob Height/Page Kind Generation ------+ | | *
3074 * Sector layout -------+ | | | *
3075 * Compression ------+ | | | | */
3076 const u64 disp90xx_modifiers[] = { /* | | | | | */
3077 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
3078 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
3079 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
3080 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
3081 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
3082 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
3083 DRM_FORMAT_MOD_LINEAR,
3084 DRM_FORMAT_MOD_INVALID