sound/hda/hdac_stream.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * HD-audio stream operations
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/delay.h>
   8 #include <linux/export.h>
   9 #include <linux/clocksource.h>
  10 #include <sound/compress_driver.h>
  11 #include <sound/core.h>
  12 #include <sound/pcm.h>
  13 #include <sound/hdaudio.h>
  14 #include <sound/hda_register.h>
  15 #include "trace.h"
  16
  17 /*
  18  * the hdac_stream library is intended to be used with the following
  19  * transitions. The states are not formally defined in the code but loosely
  20  * inspired by boolean variables. Note that the 'prepared' field is not used
  21  * in this library but by the callers during the hw_params/prepare transitions
  22  *
  23  *                         |
  24  *      stream_init()      |
  25  *                         v
  26  *                      +--+-------+
  27  *                      |  unused  |
  28  *                      +--+----+--+
  29  *                         |    ^
  30  *      stream_assign()    |    |    stream_release()
  31  *                         v    |
  32  *                      +--+----+--+
  33  *                      |  opened  |
  34  *                      +--+----+--+
  35  *                         |    ^
  36  *      stream_reset()     |    |
  37  *      stream_setup()     |    |    stream_cleanup()
  38  *                         v    |
  39  *                      +--+----+--+
  40  *                      | prepared |
  41  *                      +--+----+--+
  42  *                         |    ^
  43  *      stream_start()     |    |    stream_stop()
  44  *                         v    |
  45  *                      +--+----+--+
  46  *                      |  running |
  47  *                      +----------+
  48  */
  49
  50 /**
  51  * snd_hdac_get_stream_stripe_ctl - get stripe control value
  52  * @bus: HD-audio core bus
  53  * @substream: PCM substream
  54  */
  55 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
  56                                    struct snd_pcm_substream *substream)
  57 {
  58         struct snd_pcm_runtime *runtime = substream->runtime;
  59         unsigned int channels = runtime->channels,
  60                      rate = runtime->rate,
  61                      bits_per_sample = runtime->sample_bits,
  62                      max_sdo_lines, value, sdo_line;
  63
  64         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
  65         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
  66
  67         /* following is from HD audio spec */
  68         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
  69                 if (rate > 48000)
  70                         value = (channels * bits_per_sample *
  71                                         (rate / 48000)) / sdo_line;
  72                 else
  73                         value = (channels * bits_per_sample) / sdo_line;
  74
  75                 if (value >= bus->sdo_limit)
  76                         break;
  77         }
  78
  79         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
  80         return sdo_line >> 1;
  81 }
  82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
  83
  84 /**
  85  * snd_hdac_stream_init - initialize each stream (aka device)
  86  * @bus: HD-audio core bus
  87  * @azx_dev: HD-audio core stream object to initialize
  88  * @idx: stream index number
  89  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
  90  * @tag: the tag id to assign
  91  *
  92  * Assign the starting bdl address to each stream (device) and initialize.
  93  */
  94 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
  95                           int idx, int direction, int tag)
  96 {
  97         azx_dev->bus = bus;
  98         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  99         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
 100         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
 101         azx_dev->sd_int_sta_mask = 1 << idx;
 102         azx_dev->index = idx;
 103         azx_dev->direction = direction;
 104         azx_dev->stream_tag = tag;
 105         snd_hdac_dsp_lock_init(azx_dev);
 106         list_add_tail(&azx_dev->list, &bus->stream_list);
 107
 108         if (bus->spbcap) {
 109                 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +
 110                                         AZX_SPB_INTERVAL * idx +
 111                                         AZX_SPB_SPIB;
 112
 113                 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +
 114                                         AZX_SPB_INTERVAL * idx +
 115                                         AZX_SPB_MAXFIFO;
 116         }
 117
 118         if (bus->drsmcap)
 119                 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
 120                                         AZX_DRSM_INTERVAL * idx;
 121 }
 122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
 123
 124 /**
 125  * snd_hdac_stream_start - start a stream
 126  * @azx_dev: HD-audio core stream to start
 127  * @fresh_start: false = wallclock timestamp relative to period wallclock
 128  *
 129  * Start a stream, set start_wallclk and set the running flag.
 130  */
 131 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
 132 {
 133         struct hdac_bus *bus = azx_dev->bus;
 134         int stripe_ctl;
 135
 136         trace_snd_hdac_stream_start(bus, azx_dev);
 137
 138         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
 139         if (!fresh_start)
 140                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
 141
 142         /* enable SIE */
 143         snd_hdac_chip_updatel(bus, INTCTL,
 144                               1 << azx_dev->index,
 145                               1 << azx_dev->index);
 146         /* set stripe control */
 147         if (azx_dev->stripe) {
 148                 if (azx_dev->substream)
 149                         stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
 150                 else
 151                         stripe_ctl = 0;
 152                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
 153                                         stripe_ctl);
 154         }
 155         /* set DMA start and interrupt mask */
 156         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 157                                 0, SD_CTL_DMA_START | SD_INT_MASK);
 158         azx_dev->running = true;
 159 }
 160 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
 161
 162 /**
 163  * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers
 164  * @azx_dev: HD-audio core stream to stop
 165  */
 166 static void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
 167 {
 168         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 169                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
 170         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 171         if (azx_dev->stripe)
 172                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
 173         azx_dev->running = false;
 174 }
 175
 176 /**
 177  * snd_hdac_stream_stop - stop a stream
 178  * @azx_dev: HD-audio core stream to stop
 179  *
 180  * Stop a stream DMA and disable stream interrupt
 181  */
 182 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
 183 {
 184         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
 185
 186         snd_hdac_stream_clear(azx_dev);
 187         /* disable SIE */
 188         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
 189 }
 190 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
 191
 192 /**
 193  * snd_hdac_stop_streams - stop all streams
 194  * @bus: HD-audio core bus
 195  */
 196 void snd_hdac_stop_streams(struct hdac_bus *bus)
 197 {
 198         struct hdac_stream *stream;
 199
 200         list_for_each_entry(stream, &bus->stream_list, list)
 201                 snd_hdac_stream_stop(stream);
 202 }
 203 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
 204
 205 /**
 206  * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
 207  * @bus: HD-audio core bus
 208  */
 209 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
 210 {
 211
 212         if (bus->chip_init) {
 213                 snd_hdac_stop_streams(bus);
 214                 snd_hdac_bus_stop_chip(bus);
 215         }
 216 }
 217 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
 218
 219 /**
 220  * snd_hdac_stream_reset - reset a stream
 221  * @azx_dev: HD-audio core stream to reset
 222  */
 223 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
 224 {
 225         unsigned char val;
 226         int dma_run_state;
 227
 228         snd_hdac_stream_clear(azx_dev);
 229
 230         dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
 231
 232         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
 233
 234         /* wait for hardware to report that the stream entered reset */
 235         snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300);
 236
 237         if (azx_dev->bus->dma_stop_delay && dma_run_state)
 238                 udelay(azx_dev->bus->dma_stop_delay);
 239
 240         snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0);
 241
 242         /* wait for hardware to report that the stream is out of reset */
 243         snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300);
 244
 245         /* reset first position - may not be synced with hw at this time */
 246         if (azx_dev->posbuf)
 247                 *azx_dev->posbuf = 0;
 248 }
 249 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
 250
 251 /**
 252  * snd_hdac_stream_setup -  set up the SD for streaming
 253  * @azx_dev: HD-audio core stream to set up
 254  */
 255 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
 256 {
 257         struct hdac_bus *bus = azx_dev->bus;
 258         struct snd_pcm_runtime *runtime;
 259         unsigned int val;
 260
 261         if (azx_dev->substream)
 262                 runtime = azx_dev->substream->runtime;
 263         else
 264                 runtime = NULL;
 265         /* make sure the run bit is zero for SD */
 266         snd_hdac_stream_clear(azx_dev);
 267         /* program the stream_tag */
 268         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
 269         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
 270                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
 271         if (!bus->snoop)
 272                 val |= SD_CTL_TRAFFIC_PRIO;
 273         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
 274
 275         /* program the length of samples in cyclic buffer */
 276         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 277
 278         /* program the stream format */
 279         /* this value needs to be the same as the one programmed */
 280         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 281
 282         /* program the stream LVI (last valid index) of the BDL */
 283         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 284
 285         /* program the BDL address */
 286         /* lower BDL address */
 287         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
 288         /* upper BDL address */
 289         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
 290                                upper_32_bits(azx_dev->bdl.addr));
 291
 292         /* enable the position buffer */
 293         if (bus->use_posbuf && bus->posbuf.addr) {
 294                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
 295                         snd_hdac_chip_writel(bus, DPLBASE,
 296                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
 297         }
 298
 299         /* set the interrupt enable bits in the descriptor control register */
 300         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
 301
 302         azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
 303
 304         /* when LPIB delay correction gives a small negative value,
 305          * we ignore it; currently set the threshold statically to
 306          * 64 frames
 307          */
 308         if (runtime && runtime->period_size > 64)
 309                 azx_dev->delay_negative_threshold =
 310                         -frames_to_bytes(runtime, 64);
 311         else
 312                 azx_dev->delay_negative_threshold = 0;
 313
 314         /* wallclk has 24Mhz clock source */
 315         if (runtime)
 316                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
 317                                     runtime->rate) * 1000);
 318
 319         return 0;
 320 }
 321 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
 322
 323 /**
 324  * snd_hdac_stream_cleanup - cleanup a stream
 325  * @azx_dev: HD-audio core stream to clean up
 326  */
 327 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
 328 {
 329         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 330         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 331         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 332         azx_dev->bufsize = 0;
 333         azx_dev->period_bytes = 0;
 334         azx_dev->format_val = 0;
 335 }
 336 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
 337
 338 /**
 339  * snd_hdac_stream_assign - assign a stream for the PCM
 340  * @bus: HD-audio core bus
 341  * @substream: PCM substream to assign
 342  *
 343  * Look for an unused stream for the given PCM substream, assign it
 344  * and return the stream object.  If no stream is free, returns NULL.
 345  * The function tries to keep using the same stream object when it's used
 346  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
 347  * or matching entry is returned.  This is needed for some strange codecs.
 348  */
 349 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
 350                                            struct snd_pcm_substream *substream)
 351 {
 352         struct hdac_stream *azx_dev;
 353         struct hdac_stream *res = NULL;
 354
 355         /* make a non-zero unique key for the substream */
 356         int key = (substream->pcm->device << 16) | (substream->number << 2) |
 357                 (substream->stream + 1);
 358
 359         spin_lock_irq(&bus->reg_lock);
 360         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 361                 if (azx_dev->direction != substream->stream)
 362                         continue;
 363                 if (azx_dev->opened)
 364                         continue;
 365                 if (azx_dev->assigned_key == key) {
 366                         res = azx_dev;
 367                         break;
 368                 }
 369                 if (!res || bus->reverse_assign)
 370                         res = azx_dev;
 371         }
 372         if (res) {
 373                 res->opened = 1;
 374                 res->running = 0;
 375                 res->assigned_key = key;
 376                 res->substream = substream;
 377         }
 378         spin_unlock_irq(&bus->reg_lock);
 379         return res;
 380 }
 381 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
 382
 383 /**
 384  * snd_hdac_stream_release_locked - release the assigned stream
 385  * @azx_dev: HD-audio core stream to release
 386  *
 387  * Release the stream that has been assigned by snd_hdac_stream_assign().
 388  * The bus->reg_lock needs to be taken at a higher level
 389  */
 390 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev)
 391 {
 392         azx_dev->opened = 0;
 393         azx_dev->running = 0;
 394         azx_dev->substream = NULL;
 395 }
 396 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked);
 397
 398 /**
 399  * snd_hdac_stream_release - release the assigned stream
 400  * @azx_dev: HD-audio core stream to release
 401  *
 402  * Release the stream that has been assigned by snd_hdac_stream_assign().
 403  */
 404 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
 405 {
 406         struct hdac_bus *bus = azx_dev->bus;
 407
 408         spin_lock_irq(&bus->reg_lock);
 409         snd_hdac_stream_release_locked(azx_dev);
 410         spin_unlock_irq(&bus->reg_lock);
 411 }
 412 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
 413
 414 /**
 415  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
 416  * direction
 417  *
 418  * @bus: HD-audio core bus
 419  * @dir: direction for the stream to be found
 420  * @stream_tag: stream tag for stream to be found
 421  */
 422 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
 423                                         int dir, int stream_tag)
 424 {
 425         struct hdac_stream *s;
 426
 427         list_for_each_entry(s, &bus->stream_list, list) {
 428                 if (s->direction == dir && s->stream_tag == stream_tag)
 429                         return s;
 430         }
 431
 432         return NULL;
 433 }
 434 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
 435
 436 /*
 437  * set up a BDL entry
 438  */
 439 static int setup_bdle(struct hdac_bus *bus,
 440                       struct snd_dma_buffer *dmab,
 441                       struct hdac_stream *azx_dev, __le32 **bdlp,
 442                       int ofs, int size, int with_ioc)
 443 {
 444         __le32 *bdl = *bdlp;
 445
 446         while (size > 0) {
 447                 dma_addr_t addr;
 448                 int chunk;
 449
 450                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
 451                         return -EINVAL;
 452
 453                 addr = snd_sgbuf_get_addr(dmab, ofs);
 454                 /* program the address field of the BDL entry */
 455                 bdl[0] = cpu_to_le32((u32)addr);
 456                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 457                 /* program the size field of the BDL entry */
 458                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
 459                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
 460                 if (bus->align_bdle_4k) {
 461                         u32 remain = 0x1000 - (ofs & 0xfff);
 462
 463                         if (chunk > remain)
 464                                 chunk = remain;
 465                 }
 466                 bdl[2] = cpu_to_le32(chunk);
 467                 /* program the IOC to enable interrupt
 468                  * only when the whole fragment is processed
 469                  */
 470                 size -= chunk;
 471                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 472                 bdl += 4;
 473                 azx_dev->frags++;
 474                 ofs += chunk;
 475         }
 476         *bdlp = bdl;
 477         return ofs;
 478 }
 479
 480 /**
 481  * snd_hdac_stream_setup_periods - set up BDL entries
 482  * @azx_dev: HD-audio core stream to set up
 483  *
 484  * Set up the buffer descriptor table of the given stream based on the
 485  * period and buffer sizes of the assigned PCM substream.
 486  */
 487 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 488 {
 489         struct hdac_bus *bus = azx_dev->bus;
 490         struct snd_pcm_substream *substream = azx_dev->substream;
 491         struct snd_compr_stream *cstream = azx_dev->cstream;
 492         struct snd_pcm_runtime *runtime = NULL;
 493         struct snd_dma_buffer *dmab;
 494         __le32 *bdl;
 495         int i, ofs, periods, period_bytes;
 496         int pos_adj, pos_align;
 497
 498         if (substream) {
 499                 runtime = substream->runtime;
 500                 dmab = snd_pcm_get_dma_buf(substream);
 501         } else if (cstream) {
 502                 dmab = snd_pcm_get_dma_buf(cstream);
 503         } else {
 504                 WARN(1, "No substream or cstream assigned\n");
 505                 return -EINVAL;
 506         }
 507
 508         /* reset BDL address */
 509         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 510         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 511
 512         period_bytes = azx_dev->period_bytes;
 513         periods = azx_dev->bufsize / period_bytes;
 514
 515         /* program the initial BDL entries */
 516         bdl = (__le32 *)azx_dev->bdl.area;
 517         ofs = 0;
 518         azx_dev->frags = 0;
 519
 520         pos_adj = bus->bdl_pos_adj;
 521         if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {
 522                 pos_align = pos_adj;
 523                 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
 524                 if (!pos_adj)
 525                         pos_adj = pos_align;
 526                 else
 527                         pos_adj = roundup(pos_adj, pos_align);
 528                 pos_adj = frames_to_bytes(runtime, pos_adj);
 529                 if (pos_adj >= period_bytes) {
 530                         dev_warn(bus->dev, "Too big adjustment %d\n",
 531                                  pos_adj);
 532                         pos_adj = 0;
 533                 } else {
 534                         ofs = setup_bdle(bus, dmab, azx_dev,
 535                                          &bdl, ofs, pos_adj, true);
 536                         if (ofs < 0)
 537                                 goto error;
 538                 }
 539         } else
 540                 pos_adj = 0;
 541
 542         for (i = 0; i < periods; i++) {
 543                 if (i == periods - 1 && pos_adj)
 544                         ofs = setup_bdle(bus, dmab, azx_dev,
 545                                          &bdl, ofs, period_bytes - pos_adj, 0);
 546                 else
 547                         ofs = setup_bdle(bus, dmab, azx_dev,
 548                                          &bdl, ofs, period_bytes,
 549                                          !azx_dev->no_period_wakeup);
 550                 if (ofs < 0)
 551                         goto error;
 552         }
 553         return 0;
 554
 555  error:
 556         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
 557                 azx_dev->bufsize, period_bytes);
 558         return -EINVAL;
 559 }
 560 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
 561
 562 /**
 563  * snd_hdac_stream_set_params - set stream parameters
 564  * @azx_dev: HD-audio core stream for which parameters are to be set
 565  * @format_val: format value parameter
 566  *
 567  * Setup the HD-audio core stream parameters from substream of the stream
 568  * and passed format value
 569  */
 570 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
 571                                  unsigned int format_val)
 572 {
 573         struct snd_pcm_substream *substream = azx_dev->substream;
 574         struct snd_compr_stream *cstream = azx_dev->cstream;
 575         unsigned int bufsize, period_bytes;
 576         unsigned int no_period_wakeup;
 577         int err;
 578
 579         if (substream) {
 580                 bufsize = snd_pcm_lib_buffer_bytes(substream);
 581                 period_bytes = snd_pcm_lib_period_bytes(substream);
 582                 no_period_wakeup = substream->runtime->no_period_wakeup;
 583         } else if (cstream) {
 584                 bufsize = cstream->runtime->buffer_size;
 585                 period_bytes = cstream->runtime->fragment_size;
 586                 no_period_wakeup = 0;
 587         } else {
 588                 return -EINVAL;
 589         }
 590
 591         if (bufsize != azx_dev->bufsize ||
 592             period_bytes != azx_dev->period_bytes ||
 593             format_val != azx_dev->format_val ||
 594             no_period_wakeup != azx_dev->no_period_wakeup) {
 595                 azx_dev->bufsize = bufsize;
 596                 azx_dev->period_bytes = period_bytes;
 597                 azx_dev->format_val = format_val;
 598                 azx_dev->no_period_wakeup = no_period_wakeup;
 599                 err = snd_hdac_stream_setup_periods(azx_dev);
 600                 if (err < 0)
 601                         return err;
 602         }
 603         return 0;
 604 }
 605 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
 606
 607 static u64 azx_cc_read(const struct cyclecounter *cc)
 608 {
 609         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
 610
 611         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
 612 }
 613
 614 static void azx_timecounter_init(struct hdac_stream *azx_dev,
 615                                  bool force, u64 last)
 616 {
 617         struct timecounter *tc = &azx_dev->tc;
 618         struct cyclecounter *cc = &azx_dev->cc;
 619         u64 nsec;
 620
 621         cc->read = azx_cc_read;
 622         cc->mask = CLOCKSOURCE_MASK(32);
 623
 624         /*
 625          * Calculate the optimal mult/shift values. The counter wraps
 626          * around after ~178.9 seconds.
 627          */
 628         clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000,
 629                                NSEC_PER_SEC, 178);
 630
 631         nsec = 0; /* audio time is elapsed time since trigger */
 632         timecounter_init(tc, cc, nsec);
 633         if (force) {
 634                 /*
 635                  * force timecounter to use predefined value,
 636                  * used for synchronized starts
 637                  */
 638                 tc->cycle_last = last;
 639         }
 640 }
 641
 642 /**
 643  * snd_hdac_stream_timecounter_init - initialize time counter
 644  * @azx_dev: HD-audio core stream (master stream)
 645  * @streams: bit flags of streams to set up
 646  *
 647  * Initializes the time counter of streams marked by the bit flags (each
 648  * bit corresponds to the stream index).
 649  * The trigger timestamp of PCM substream assigned to the given stream is
 650  * updated accordingly, too.
 651  */
 652 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
 653                                       unsigned int streams)
 654 {
 655         struct hdac_bus *bus = azx_dev->bus;
 656         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
 657         struct hdac_stream *s;
 658         bool inited = false;
 659         u64 cycle_last = 0;
 660         int i = 0;
 661
 662         list_for_each_entry(s, &bus->stream_list, list) {
 663                 if (streams & (1 << i)) {
 664                         azx_timecounter_init(s, inited, cycle_last);
 665                         if (!inited) {
 666                                 inited = true;
 667                                 cycle_last = s->tc.cycle_last;
 668                         }
 669                 }
 670                 i++;
 671         }
 672
 673         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
 674         runtime->trigger_tstamp_latched = true;
 675 }
 676 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
 677
 678 /**
 679  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
 680  * @azx_dev: HD-audio core stream (master stream)
 681  * @set: true = set, false = clear
 682  * @streams: bit flags of streams to sync
 683  * @reg: the stream sync register address
 684  */
 685 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
 686                                   unsigned int streams, unsigned int reg)
 687 {
 688         struct hdac_bus *bus = azx_dev->bus;
 689         unsigned int val;
 690
 691         if (!reg)
 692                 reg = AZX_REG_SSYNC;
 693         val = _snd_hdac_chip_readl(bus, reg);
 694         if (set)
 695                 val |= streams;
 696         else
 697                 val &= ~streams;
 698         _snd_hdac_chip_writel(bus, reg, val);
 699 }
 700 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
 701
 702 /**
 703  * snd_hdac_stream_sync - sync with start/stop trigger operation
 704  * @azx_dev: HD-audio core stream (master stream)
 705  * @start: true = start, false = stop
 706  * @streams: bit flags of streams to sync
 707  *
 708  * For @start = true, wait until all FIFOs get ready.
 709  * For @start = false, wait until all RUN bits are cleared.
 710  */
 711 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
 712                           unsigned int streams)
 713 {
 714         struct hdac_bus *bus = azx_dev->bus;
 715         int i, nwait, timeout;
 716         struct hdac_stream *s;
 717
 718         for (timeout = 5000; timeout; timeout--) {
 719                 nwait = 0;
 720                 i = 0;
 721                 list_for_each_entry(s, &bus->stream_list, list) {
 722                         if (!(streams & (1 << i++)))
 723                                 continue;
 724
 725                         if (start) {
 726                                 /* check FIFO gets ready */
 727                                 if (!(snd_hdac_stream_readb(s, SD_STS) &
 728                                       SD_STS_FIFO_READY))
 729                                         nwait++;
 730                         } else {
 731                                 /* check RUN bit is cleared */
 732                                 if (snd_hdac_stream_readb(s, SD_CTL) &
 733                                     SD_CTL_DMA_START) {
 734                                         nwait++;
 735                                         /*
 736                                          * Perform stream reset if DMA RUN
 737                                          * bit not cleared within given timeout
 738                                          */
 739                                         if (timeout == 1)
 740                                                 snd_hdac_stream_reset(s);
 741                                 }
 742                         }
 743                 }
 744                 if (!nwait)
 745                         break;
 746                 cpu_relax();
 747         }
 748 }
 749 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
 750
 751 /**
 752  * snd_hdac_stream_spbcap_enable - enable SPIB for a stream
 753  * @bus: HD-audio core bus
 754  * @enable: flag to enable/disable SPIB
 755  * @index: stream index for which SPIB need to be enabled
 756  */
 757 void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus,
 758                                    bool enable, int index)
 759 {
 760         u32 mask = 0;
 761
 762         if (!bus->spbcap) {
 763                 dev_err(bus->dev, "Address of SPB capability is NULL\n");
 764                 return;
 765         }
 766
 767         mask |= (1 << index);
 768
 769         if (enable)
 770                 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
 771         else
 772                 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
 773 }
 774 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable);
 775
 776 /**
 777  * snd_hdac_stream_set_spib - sets the spib value of a stream
 778  * @bus: HD-audio core bus
 779  * @azx_dev: hdac_stream
 780  * @value: spib value to set
 781  */
 782 int snd_hdac_stream_set_spib(struct hdac_bus *bus,
 783                              struct hdac_stream *azx_dev, u32 value)
 784 {
 785         if (!bus->spbcap) {
 786                 dev_err(bus->dev, "Address of SPB capability is NULL\n");
 787                 return -EINVAL;
 788         }
 789
 790         writel(value, azx_dev->spib_addr);
 791
 792         return 0;
 793 }
 794 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);
 795
 796 /**
 797  * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream
 798  * @bus: HD-audio core bus
 799  * @azx_dev: hdac_stream
 800  *
 801  * Return maxfifo for the stream
 802  */
 803 int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
 804                                    struct hdac_stream *azx_dev)
 805 {
 806         if (!bus->spbcap) {
 807                 dev_err(bus->dev, "Address of SPB capability is NULL\n");
 808                 return -EINVAL;
 809         }
 810
 811         return readl(azx_dev->fifo_addr);
 812 }
 813 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo);
 814
 815 /**
 816  * snd_hdac_stream_drsm_enable - enable DMA resume for a stream
 817  * @bus: HD-audio core bus
 818  * @enable: flag to enable/disable DRSM
 819  * @index: stream index for which DRSM need to be enabled
 820  */
 821 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
 822                                  bool enable, int index)
 823 {
 824         u32 mask = 0;
 825
 826         if (!bus->drsmcap) {
 827                 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
 828                 return;
 829         }
 830
 831         mask |= (1 << index);
 832
 833         if (enable)
 834                 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
 835         else
 836                 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
 837 }
 838 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);
 839
 840 /*
 841  * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream
 842  * @azx_dev: HD-audio core stream to await RSM for
 843  *
 844  * Returns 0 on success and -ETIMEDOUT upon a timeout.
 845  */
 846 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev)
 847 {
 848         struct hdac_bus *bus = azx_dev->bus;
 849         u32 mask, reg;
 850         int ret;
 851
 852         mask = 1 << azx_dev->index;
 853
 854         ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus,
 855                                 bus->drsmcap + AZX_REG_DRSM_CTL);
 856         if (ret)
 857                 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret);
 858         return ret;
 859 }
 860 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);
 861
 862 /**
 863  * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream
 864  * @bus: HD-audio core bus
 865  * @azx_dev: hdac_stream
 866  * @value: dpib value to set
 867  */
 868 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
 869                               struct hdac_stream *azx_dev, u32 value)
 870 {
 871         if (!bus->drsmcap) {
 872                 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
 873                 return -EINVAL;
 874         }
 875
 876         writel(value, azx_dev->dpibr_addr);
 877
 878         return 0;
 879 }
 880 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);
 881
 882 /**
 883  * snd_hdac_stream_set_lpib - sets the lpib value of a stream
 884  * @azx_dev: hdac_stream
 885  * @value: lpib value to set
 886  */
 887 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value)
 888 {
 889         snd_hdac_stream_writel(azx_dev, SD_LPIB, value);
 890
 891         return 0;
 892 }
 893 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);
 894
 895 #ifdef CONFIG_SND_HDA_DSP_LOADER
 896 /**
 897  * snd_hdac_dsp_prepare - prepare for DSP loading
 898  * @azx_dev: HD-audio core stream used for DSP loading
 899  * @format: HD-audio stream format
 900  * @byte_size: data chunk byte size
 901  * @bufp: allocated buffer
 902  *
 903  * Allocate the buffer for the given size and set up the given stream for
 904  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
 905  */
 906 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
 907                          unsigned int byte_size, struct snd_dma_buffer *bufp)
 908 {
 909         struct hdac_bus *bus = azx_dev->bus;
 910         __le32 *bdl;
 911         int err;
 912
 913         snd_hdac_dsp_lock(azx_dev);
 914         spin_lock_irq(&bus->reg_lock);
 915         if (azx_dev->running || azx_dev->locked) {
 916                 spin_unlock_irq(&bus->reg_lock);
 917                 err = -EBUSY;
 918                 goto unlock;
 919         }
 920         azx_dev->locked = true;
 921         spin_unlock_irq(&bus->reg_lock);
 922
 923         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
 924                                   byte_size, bufp);
 925         if (err < 0)
 926                 goto err_alloc;
 927
 928         azx_dev->substream = NULL;
 929         azx_dev->bufsize = byte_size;
 930         azx_dev->period_bytes = byte_size;
 931         azx_dev->format_val = format;
 932
 933         snd_hdac_stream_reset(azx_dev);
 934
 935         /* reset BDL address */
 936         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 937         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 938
 939         azx_dev->frags = 0;
 940         bdl = (__le32 *)azx_dev->bdl.area;
 941         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
 942         if (err < 0)
 943                 goto error;
 944
 945         snd_hdac_stream_setup(azx_dev);
 946         snd_hdac_dsp_unlock(azx_dev);
 947         return azx_dev->stream_tag;
 948
 949  error:
 950         snd_dma_free_pages(bufp);
 951  err_alloc:
 952         spin_lock_irq(&bus->reg_lock);
 953         azx_dev->locked = false;
 954         spin_unlock_irq(&bus->reg_lock);
 955  unlock:
 956         snd_hdac_dsp_unlock(azx_dev);
 957         return err;
 958 }
 959 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
 960
 961 /**
 962  * snd_hdac_dsp_trigger - start / stop DSP loading
 963  * @azx_dev: HD-audio core stream used for DSP loading
 964  * @start: trigger start or stop
 965  */
 966 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
 967 {
 968         if (start)
 969                 snd_hdac_stream_start(azx_dev, true);
 970         else
 971                 snd_hdac_stream_stop(azx_dev);
 972 }
 973 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
 974
 975 /**
 976  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
 977  * @azx_dev: HD-audio core stream used for DSP loading
 978  * @dmab: buffer used by DSP loading
 979  */
 980 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
 981                           struct snd_dma_buffer *dmab)
 982 {
 983         struct hdac_bus *bus = azx_dev->bus;
 984
 985         if (!dmab->area || !azx_dev->locked)
 986                 return;
 987
 988         snd_hdac_dsp_lock(azx_dev);
 989         /* reset BDL address */
 990         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 991         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 992         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 993         azx_dev->bufsize = 0;
 994         azx_dev->period_bytes = 0;
 995         azx_dev->format_val = 0;
 996
 997         snd_dma_free_pages(dmab);
 998         dmab->area = NULL;
 999
1000         spin_lock_irq(&bus->reg_lock);
1001         azx_dev->locked = false;
1002         spin_unlock_irq(&bus->reg_lock);
1003         snd_hdac_dsp_unlock(azx_dev);
1004 }
1005 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1006 #endif /* CONFIG_SND_HDA_DSP_LOADER */