2 * Copyright (C) 2010-2012 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/mmu_notifier.h>
20 #include <linux/amd-iommu.h>
21 #include <linux/mm_types.h>
22 #include <linux/profile.h>
23 #include <linux/module.h>
24 #include <linux/sched.h>
25 #include <linux/sched/mm.h>
26 #include <linux/iommu.h>
27 #include <linux/wait.h>
28 #include <linux/pci.h>
29 #include <linux/gfp.h>
31 #include "amd_iommu_types.h"
32 #include "amd_iommu_proto.h"
34 MODULE_LICENSE("GPL v2");
35 MODULE_AUTHOR("Joerg Roedel <jroedel@suse.de>");
37 #define MAX_DEVICES 0x10000
38 #define PRI_QUEUE_SIZE 512
47 struct list_head list; /* For global state-list */
48 atomic_t count; /* Reference count */
49 unsigned mmu_notifier_count; /* Counting nested mmu_notifier
51 struct mm_struct *mm; /* mm_struct for the faults */
52 struct mmu_notifier mn; /* mmu_notifier handle */
53 struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */
54 struct device_state *device_state; /* Link to our device_state */
55 int pasid; /* PASID index */
56 bool invalid; /* Used during setup and
57 teardown of the pasid */
58 spinlock_t lock; /* Protect pri_queues and
60 wait_queue_head_t wq; /* To wait for count == 0 */
64 struct list_head list;
68 struct pasid_state **states;
69 struct iommu_domain *domain;
72 amd_iommu_invalid_ppr_cb inv_ppr_cb;
73 amd_iommu_invalidate_ctx inv_ctx_cb;
79 struct work_struct work;
80 struct device_state *dev_state;
81 struct pasid_state *state;
91 static LIST_HEAD(state_list);
92 static spinlock_t state_lock;
94 static struct workqueue_struct *iommu_wq;
96 static void free_pasid_states(struct device_state *dev_state);
98 static u16 device_id(struct pci_dev *pdev)
102 devid = pdev->bus->number;
103 devid = (devid << 8) | pdev->devfn;
108 static struct device_state *__get_device_state(u16 devid)
110 struct device_state *dev_state;
112 list_for_each_entry(dev_state, &state_list, list) {
113 if (dev_state->devid == devid)
120 static struct device_state *get_device_state(u16 devid)
122 struct device_state *dev_state;
125 spin_lock_irqsave(&state_lock, flags);
126 dev_state = __get_device_state(devid);
127 if (dev_state != NULL)
128 atomic_inc(&dev_state->count);
129 spin_unlock_irqrestore(&state_lock, flags);
134 static void free_device_state(struct device_state *dev_state)
136 struct iommu_group *group;
139 * First detach device from domain - No more PRI requests will arrive
140 * from that device after it is unbound from the IOMMUv2 domain.
142 group = iommu_group_get(&dev_state->pdev->dev);
146 iommu_detach_group(dev_state->domain, group);
148 iommu_group_put(group);
150 /* Everything is down now, free the IOMMUv2 domain */
151 iommu_domain_free(dev_state->domain);
153 /* Finally get rid of the device-state */
157 static void put_device_state(struct device_state *dev_state)
159 if (atomic_dec_and_test(&dev_state->count))
160 wake_up(&dev_state->wq);
163 /* Must be called under dev_state->lock */
164 static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state,
165 int pasid, bool alloc)
167 struct pasid_state **root, **ptr;
170 level = dev_state->pasid_levels;
171 root = dev_state->states;
175 index = (pasid >> (9 * level)) & 0x1ff;
185 *ptr = (void *)get_zeroed_page(GFP_ATOMIC);
190 root = (struct pasid_state **)*ptr;
197 static int set_pasid_state(struct device_state *dev_state,
198 struct pasid_state *pasid_state,
201 struct pasid_state **ptr;
205 spin_lock_irqsave(&dev_state->lock, flags);
206 ptr = __get_pasid_state_ptr(dev_state, pasid, true);
221 spin_unlock_irqrestore(&dev_state->lock, flags);
226 static void clear_pasid_state(struct device_state *dev_state, int pasid)
228 struct pasid_state **ptr;
231 spin_lock_irqsave(&dev_state->lock, flags);
232 ptr = __get_pasid_state_ptr(dev_state, pasid, true);
240 spin_unlock_irqrestore(&dev_state->lock, flags);
243 static struct pasid_state *get_pasid_state(struct device_state *dev_state,
246 struct pasid_state **ptr, *ret = NULL;
249 spin_lock_irqsave(&dev_state->lock, flags);
250 ptr = __get_pasid_state_ptr(dev_state, pasid, false);
257 atomic_inc(&ret->count);
260 spin_unlock_irqrestore(&dev_state->lock, flags);
265 static void free_pasid_state(struct pasid_state *pasid_state)
270 static void put_pasid_state(struct pasid_state *pasid_state)
272 if (atomic_dec_and_test(&pasid_state->count))
273 wake_up(&pasid_state->wq);
276 static void put_pasid_state_wait(struct pasid_state *pasid_state)
278 atomic_dec(&pasid_state->count);
279 wait_event(pasid_state->wq, !atomic_read(&pasid_state->count));
280 free_pasid_state(pasid_state);
283 static void unbind_pasid(struct pasid_state *pasid_state)
285 struct iommu_domain *domain;
287 domain = pasid_state->device_state->domain;
290 * Mark pasid_state as invalid, no more faults will we added to the
291 * work queue after this is visible everywhere.
293 pasid_state->invalid = true;
295 /* Make sure this is visible */
298 /* After this the device/pasid can't access the mm anymore */
299 amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid);
301 /* Make sure no more pending faults are in the queue */
302 flush_workqueue(iommu_wq);
305 static void free_pasid_states_level1(struct pasid_state **tbl)
309 for (i = 0; i < 512; ++i) {
313 free_page((unsigned long)tbl[i]);
317 static void free_pasid_states_level2(struct pasid_state **tbl)
319 struct pasid_state **ptr;
322 for (i = 0; i < 512; ++i) {
326 ptr = (struct pasid_state **)tbl[i];
327 free_pasid_states_level1(ptr);
331 static void free_pasid_states(struct device_state *dev_state)
333 struct pasid_state *pasid_state;
336 for (i = 0; i < dev_state->max_pasids; ++i) {
337 pasid_state = get_pasid_state(dev_state, i);
338 if (pasid_state == NULL)
341 put_pasid_state(pasid_state);
344 * This will call the mn_release function and
347 mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
349 put_pasid_state_wait(pasid_state); /* Reference taken in
350 amd_iommu_bind_pasid */
352 /* Drop reference taken in amd_iommu_bind_pasid */
353 put_device_state(dev_state);
356 if (dev_state->pasid_levels == 2)
357 free_pasid_states_level2(dev_state->states);
358 else if (dev_state->pasid_levels == 1)
359 free_pasid_states_level1(dev_state->states);
361 BUG_ON(dev_state->pasid_levels != 0);
363 free_page((unsigned long)dev_state->states);
366 static struct pasid_state *mn_to_state(struct mmu_notifier *mn)
368 return container_of(mn, struct pasid_state, mn);
371 static void __mn_flush_page(struct mmu_notifier *mn,
372 unsigned long address)
374 struct pasid_state *pasid_state;
375 struct device_state *dev_state;
377 pasid_state = mn_to_state(mn);
378 dev_state = pasid_state->device_state;
380 amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address);
383 static int mn_clear_flush_young(struct mmu_notifier *mn,
384 struct mm_struct *mm,
388 for (; start < end; start += PAGE_SIZE)
389 __mn_flush_page(mn, start);
394 static void mn_invalidate_range(struct mmu_notifier *mn,
395 struct mm_struct *mm,
396 unsigned long start, unsigned long end)
398 struct pasid_state *pasid_state;
399 struct device_state *dev_state;
401 pasid_state = mn_to_state(mn);
402 dev_state = pasid_state->device_state;
404 if ((start ^ (end - 1)) < PAGE_SIZE)
405 amd_iommu_flush_page(dev_state->domain, pasid_state->pasid,
408 amd_iommu_flush_tlb(dev_state->domain, pasid_state->pasid);
411 static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm)
413 struct pasid_state *pasid_state;
414 struct device_state *dev_state;
419 pasid_state = mn_to_state(mn);
420 dev_state = pasid_state->device_state;
421 run_inv_ctx_cb = !pasid_state->invalid;
423 if (run_inv_ctx_cb && dev_state->inv_ctx_cb)
424 dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid);
426 unbind_pasid(pasid_state);
429 static const struct mmu_notifier_ops iommu_mn = {
430 .release = mn_release,
431 .clear_flush_young = mn_clear_flush_young,
432 .invalidate_range = mn_invalidate_range,
435 static void set_pri_tag_status(struct pasid_state *pasid_state,
440 spin_lock_irqsave(&pasid_state->lock, flags);
441 pasid_state->pri[tag].status = status;
442 spin_unlock_irqrestore(&pasid_state->lock, flags);
445 static void finish_pri_tag(struct device_state *dev_state,
446 struct pasid_state *pasid_state,
451 spin_lock_irqsave(&pasid_state->lock, flags);
452 if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) &&
453 pasid_state->pri[tag].finish) {
454 amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid,
455 pasid_state->pri[tag].status, tag);
456 pasid_state->pri[tag].finish = false;
457 pasid_state->pri[tag].status = PPR_SUCCESS;
459 spin_unlock_irqrestore(&pasid_state->lock, flags);
462 static void handle_fault_error(struct fault *fault)
466 if (!fault->dev_state->inv_ppr_cb) {
467 set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
471 status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev,
476 case AMD_IOMMU_INV_PRI_RSP_SUCCESS:
477 set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS);
479 case AMD_IOMMU_INV_PRI_RSP_INVALID:
480 set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
482 case AMD_IOMMU_INV_PRI_RSP_FAIL:
483 set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE);
490 static bool access_error(struct vm_area_struct *vma, struct fault *fault)
492 unsigned long requested = 0;
494 if (fault->flags & PPR_FAULT_EXEC)
495 requested |= VM_EXEC;
497 if (fault->flags & PPR_FAULT_READ)
498 requested |= VM_READ;
500 if (fault->flags & PPR_FAULT_WRITE)
501 requested |= VM_WRITE;
503 return (requested & ~vma->vm_flags) != 0;
506 static void do_fault(struct work_struct *work)
508 struct fault *fault = container_of(work, struct fault, work);
509 struct vm_area_struct *vma;
510 int ret = VM_FAULT_ERROR;
511 unsigned int flags = 0;
512 struct mm_struct *mm;
515 mm = fault->state->mm;
516 address = fault->address;
518 if (fault->flags & PPR_FAULT_USER)
519 flags |= FAULT_FLAG_USER;
520 if (fault->flags & PPR_FAULT_WRITE)
521 flags |= FAULT_FLAG_WRITE;
522 flags |= FAULT_FLAG_REMOTE;
524 down_read(&mm->mmap_sem);
525 vma = find_extend_vma(mm, address);
526 if (!vma || address < vma->vm_start)
527 /* failed to get a vma in the right range */
530 /* Check if we have the right permissions on the vma */
531 if (access_error(vma, fault))
534 ret = handle_mm_fault(vma, address, flags);
536 up_read(&mm->mmap_sem);
538 if (ret & VM_FAULT_ERROR)
539 /* failed to service fault */
540 handle_fault_error(fault);
542 finish_pri_tag(fault->dev_state, fault->state, fault->tag);
544 put_pasid_state(fault->state);
549 static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data)
551 struct amd_iommu_fault *iommu_fault;
552 struct pasid_state *pasid_state;
553 struct device_state *dev_state;
559 struct iommu_dev_data *dev_data;
560 struct pci_dev *pdev = NULL;
563 tag = iommu_fault->tag & 0x1ff;
564 finish = (iommu_fault->tag >> 9) & 1;
566 devid = iommu_fault->device_id;
567 pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
570 dev_data = get_dev_data(&pdev->dev);
572 /* In kdump kernel pci dev is not initialized yet -> send INVALID */
574 if (translation_pre_enabled(amd_iommu_rlookup_table[devid])
575 && dev_data->defer_attach) {
576 amd_iommu_complete_ppr(pdev, iommu_fault->pasid,
581 dev_state = get_device_state(iommu_fault->device_id);
582 if (dev_state == NULL)
585 pasid_state = get_pasid_state(dev_state, iommu_fault->pasid);
586 if (pasid_state == NULL || pasid_state->invalid) {
587 /* We know the device but not the PASID -> send INVALID */
588 amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid,
593 spin_lock_irqsave(&pasid_state->lock, flags);
594 atomic_inc(&pasid_state->pri[tag].inflight);
596 pasid_state->pri[tag].finish = true;
597 spin_unlock_irqrestore(&pasid_state->lock, flags);
599 fault = kzalloc(sizeof(*fault), GFP_ATOMIC);
601 /* We are OOM - send success and let the device re-fault */
602 finish_pri_tag(dev_state, pasid_state, tag);
606 fault->dev_state = dev_state;
607 fault->address = iommu_fault->address;
608 fault->state = pasid_state;
610 fault->finish = finish;
611 fault->pasid = iommu_fault->pasid;
612 fault->flags = iommu_fault->flags;
613 INIT_WORK(&fault->work, do_fault);
615 queue_work(iommu_wq, &fault->work);
621 if (ret != NOTIFY_OK && pasid_state)
622 put_pasid_state(pasid_state);
624 put_device_state(dev_state);
630 static struct notifier_block ppr_nb = {
631 .notifier_call = ppr_notifier,
634 int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
635 struct task_struct *task)
637 struct pasid_state *pasid_state;
638 struct device_state *dev_state;
639 struct mm_struct *mm;
645 if (!amd_iommu_v2_supported())
648 devid = device_id(pdev);
649 dev_state = get_device_state(devid);
651 if (dev_state == NULL)
655 if (pasid < 0 || pasid >= dev_state->max_pasids)
659 pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL);
660 if (pasid_state == NULL)
664 atomic_set(&pasid_state->count, 1);
665 init_waitqueue_head(&pasid_state->wq);
666 spin_lock_init(&pasid_state->lock);
668 mm = get_task_mm(task);
669 pasid_state->mm = mm;
670 pasid_state->device_state = dev_state;
671 pasid_state->pasid = pasid;
672 pasid_state->invalid = true; /* Mark as valid only if we are
673 done with setting up the pasid */
674 pasid_state->mn.ops = &iommu_mn;
676 if (pasid_state->mm == NULL)
679 mmu_notifier_register(&pasid_state->mn, mm);
681 ret = set_pasid_state(dev_state, pasid_state, pasid);
685 ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid,
686 __pa(pasid_state->mm->pgd));
688 goto out_clear_state;
690 /* Now we are ready to handle faults */
691 pasid_state->invalid = false;
694 * Drop the reference to the mm_struct here. We rely on the
695 * mmu_notifier release call-back to inform us when the mm
703 clear_pasid_state(dev_state, pasid);
706 mmu_notifier_unregister(&pasid_state->mn, mm);
710 free_pasid_state(pasid_state);
713 put_device_state(dev_state);
717 EXPORT_SYMBOL(amd_iommu_bind_pasid);
719 void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid)
721 struct pasid_state *pasid_state;
722 struct device_state *dev_state;
727 if (!amd_iommu_v2_supported())
730 devid = device_id(pdev);
731 dev_state = get_device_state(devid);
732 if (dev_state == NULL)
735 if (pasid < 0 || pasid >= dev_state->max_pasids)
738 pasid_state = get_pasid_state(dev_state, pasid);
739 if (pasid_state == NULL)
742 * Drop reference taken here. We are safe because we still hold
743 * the reference taken in the amd_iommu_bind_pasid function.
745 put_pasid_state(pasid_state);
747 /* Clear the pasid state so that the pasid can be re-used */
748 clear_pasid_state(dev_state, pasid_state->pasid);
751 * Call mmu_notifier_unregister to drop our reference
754 mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
756 put_pasid_state_wait(pasid_state); /* Reference taken in
757 amd_iommu_bind_pasid */
759 /* Drop reference taken in this function */
760 put_device_state(dev_state);
762 /* Drop reference taken in amd_iommu_bind_pasid */
763 put_device_state(dev_state);
765 EXPORT_SYMBOL(amd_iommu_unbind_pasid);
767 int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
769 struct device_state *dev_state;
770 struct iommu_group *group;
777 if (!amd_iommu_v2_supported())
780 if (pasids <= 0 || pasids > (PASID_MASK + 1))
783 devid = device_id(pdev);
785 dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL);
786 if (dev_state == NULL)
789 spin_lock_init(&dev_state->lock);
790 init_waitqueue_head(&dev_state->wq);
791 dev_state->pdev = pdev;
792 dev_state->devid = devid;
795 for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9)
796 dev_state->pasid_levels += 1;
798 atomic_set(&dev_state->count, 1);
799 dev_state->max_pasids = pasids;
802 dev_state->states = (void *)get_zeroed_page(GFP_KERNEL);
803 if (dev_state->states == NULL)
804 goto out_free_dev_state;
806 dev_state->domain = iommu_domain_alloc(&pci_bus_type);
807 if (dev_state->domain == NULL)
808 goto out_free_states;
810 amd_iommu_domain_direct_map(dev_state->domain);
812 ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids);
814 goto out_free_domain;
816 group = iommu_group_get(&pdev->dev);
819 goto out_free_domain;
822 ret = iommu_attach_group(dev_state->domain, group);
826 iommu_group_put(group);
828 spin_lock_irqsave(&state_lock, flags);
830 if (__get_device_state(devid) != NULL) {
831 spin_unlock_irqrestore(&state_lock, flags);
833 goto out_free_domain;
836 list_add_tail(&dev_state->list, &state_list);
838 spin_unlock_irqrestore(&state_lock, flags);
843 iommu_group_put(group);
846 iommu_domain_free(dev_state->domain);
849 free_page((unsigned long)dev_state->states);
856 EXPORT_SYMBOL(amd_iommu_init_device);
858 void amd_iommu_free_device(struct pci_dev *pdev)
860 struct device_state *dev_state;
864 if (!amd_iommu_v2_supported())
867 devid = device_id(pdev);
869 spin_lock_irqsave(&state_lock, flags);
871 dev_state = __get_device_state(devid);
872 if (dev_state == NULL) {
873 spin_unlock_irqrestore(&state_lock, flags);
877 list_del(&dev_state->list);
879 spin_unlock_irqrestore(&state_lock, flags);
881 /* Get rid of any remaining pasid states */
882 free_pasid_states(dev_state);
884 put_device_state(dev_state);
886 * Wait until the last reference is dropped before freeing
889 wait_event(dev_state->wq, !atomic_read(&dev_state->count));
890 free_device_state(dev_state);
892 EXPORT_SYMBOL(amd_iommu_free_device);
894 int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
895 amd_iommu_invalid_ppr_cb cb)
897 struct device_state *dev_state;
902 if (!amd_iommu_v2_supported())
905 devid = device_id(pdev);
907 spin_lock_irqsave(&state_lock, flags);
910 dev_state = __get_device_state(devid);
911 if (dev_state == NULL)
914 dev_state->inv_ppr_cb = cb;
919 spin_unlock_irqrestore(&state_lock, flags);
923 EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb);
925 int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
926 amd_iommu_invalidate_ctx cb)
928 struct device_state *dev_state;
933 if (!amd_iommu_v2_supported())
936 devid = device_id(pdev);
938 spin_lock_irqsave(&state_lock, flags);
941 dev_state = __get_device_state(devid);
942 if (dev_state == NULL)
945 dev_state->inv_ctx_cb = cb;
950 spin_unlock_irqrestore(&state_lock, flags);
954 EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb);
956 static int __init amd_iommu_v2_init(void)
960 pr_info("AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>\n");
962 if (!amd_iommu_v2_supported()) {
963 pr_info("AMD IOMMUv2 functionality not available on this system\n");
965 * Load anyway to provide the symbols to other modules
966 * which may use AMD IOMMUv2 optionally.
971 spin_lock_init(&state_lock);
974 iommu_wq = alloc_workqueue("amd_iommu_v2", WQ_MEM_RECLAIM, 0);
975 if (iommu_wq == NULL)
978 amd_iommu_register_ppr_notifier(&ppr_nb);
986 static void __exit amd_iommu_v2_exit(void)
988 struct device_state *dev_state;
991 if (!amd_iommu_v2_supported())
994 amd_iommu_unregister_ppr_notifier(&ppr_nb);
996 flush_workqueue(iommu_wq);
999 * The loop below might call flush_workqueue(), so call
1000 * destroy_workqueue() after it
1002 for (i = 0; i < MAX_DEVICES; ++i) {
1003 dev_state = get_device_state(i);
1005 if (dev_state == NULL)
1010 put_device_state(dev_state);
1011 amd_iommu_free_device(dev_state->pdev);
1014 destroy_workqueue(iommu_wq);
1017 module_init(amd_iommu_v2_init);
1018 module_exit(amd_iommu_v2_exit);