1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Abramo Bagnara <abramo@alsa-project.org>
6 * Routines for control of Cirrus Logic CS461x chips
9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
10 * and the SPDIF get somewhat "distorcionated", or/and left right channel
11 * are swapped. To get around this problem when it happens, mute and unmute
12 * the SPDIF input mixer control.
13 * - On the Hercules Game Theater XP the amplifier are sometimes turned
14 * off on inadecuate moments which causes distorcions on sound.
17 * - Secondary CODEC on some soundcards
18 * - SPDIF input support for other sample rates then 48khz
19 * - Posibility to mix the SPDIF output with analog sources.
20 * - PCM channels for Center and LFE on secondary codec
22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
23 * is default configuration), no SPDIF, no secondary codec, no
24 * multi channel PCM. But known to work.
26 * FINALLY: A credit to the developers Tom and Jordan
27 * at Cirrus for have helping me out with the DSP, however we
28 * still don't have sufficient documentation and technical
29 * references to be able to implement all fancy feutures
30 * supported by the cs46xx DSP's.
31 * Benny <benny@hostmobility.com>
34 #include <linux/delay.h>
35 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/interrupt.h>
39 #include <linux/slab.h>
40 #include <linux/gameport.h>
41 #include <linux/mutex.h>
42 #include <linux/export.h>
43 #include <linux/module.h>
44 #include <linux/firmware.h>
45 #include <linux/vmalloc.h>
48 #include <sound/core.h>
49 #include <sound/control.h>
50 #include <sound/info.h>
51 #include <sound/pcm.h>
52 #include <sound/pcm_params.h>
55 #include "cs46xx_lib.h"
58 static void amp_voyetra(struct snd_cs46xx *chip, int change);
60 #ifdef CONFIG_SND_CS46XX_NEW_DSP
61 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
62 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
63 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
64 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
65 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
66 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
69 static const struct snd_pcm_ops snd_cs46xx_playback_ops;
70 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
71 static const struct snd_pcm_ops snd_cs46xx_capture_ops;
72 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
79 unsigned short result,tmp;
82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
83 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
86 chip->active_ctrl(chip, 1);
88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
89 offset = CS46XX_SECONDARY_CODEC_OFFSET;
92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
96 * 5. if DCV not cleared, break and return error
97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
113 * Setup the AC97 control registers on the CS461x to send the
114 * appropriate command to the AC97 to perform the read.
115 * ACCAD = Command Address Register = 46Ch
116 * ACCDA = Command Data Register = 470h
117 * ACCTL = Control Register = 460h
118 * set DCV - will clear when process completed
119 * set CRW - Read command
120 * set VFRM - valid frame enabled
121 * set ESYN - ASYNC generation enabled
122 * set RSTN - ARST# inactive, AC97 codec not reset
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
129 ACCTL_VFRM | ACCTL_ESYN |
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
132 ACCTL_VFRM | ACCTL_ESYN |
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
141 * Wait for the read to occur.
143 for (count = 0; count < 1000; count++) {
145 * First, we want to wait for a short time.
149 * Now, check to see if the read has completed.
150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
156 dev_err(chip->card->dev,
157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
163 * Wait for the valid status bit to go active.
165 for (count = 0; count < 100; count++) {
167 * Read the AC97 status register.
168 * ACSTS = Status Register = 464h
169 * VSTS - Valid Status
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
176 dev_err(chip->card->dev,
177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
184 * Read the data returned from the AC97 register.
185 * ACSDA = Status Data Register = 474h
188 dev_dbg(chip->card->dev,
189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
197 chip->active_ctrl(chip, -1);
201 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
204 struct snd_cs46xx *chip = ac97->private_data;
206 int codec_index = ac97->num;
208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
209 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
226 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
229 chip->active_ctrl(chip, 1);
232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
234 * 3. Write ACCTL = Control Register = 460h for initiating the write
235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
236 * 5. if DCV not cleared, break and return error
240 * Setup the AC97 control registers on the CS461x to send the
241 * appropriate command to the AC97 to perform the read.
242 * ACCAD = Command Address Register = 46Ch
243 * ACCDA = Command Data Register = 470h
244 * ACCTL = Control Register = 460h
245 * set DCV - will clear when process completed
246 * reset CRW - Write command
247 * set VFRM - valid frame enabled
248 * set ESYN - ASYNC generation enabled
249 * set RSTN - ARST# inactive, AC97 codec not reset
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
257 ACCTL_ESYN | ACCTL_RSTN);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
259 ACCTL_ESYN | ACCTL_RSTN);
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
265 for (count = 0; count < 4000; count++) {
267 * First, we want to wait for a short time.
271 * Now, check to see if the write has completed.
272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
278 dev_err(chip->card->dev,
279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
280 codec_index, reg, val);
282 chip->active_ctrl(chip, -1);
285 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
289 struct snd_cs46xx *chip = ac97->private_data;
290 int codec_index = ac97->num;
292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
293 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
301 * Chip initialization
304 int snd_cs46xx_download(struct snd_cs46xx *chip,
306 unsigned long offset,
310 unsigned int bank = offset >> 16;
311 offset = offset & 0xffff;
313 if (snd_BUG_ON((offset & 3) || (len & 3)))
315 dst = chip->region.idx[bank+1].remap_addr + offset;
318 /* writel already converts 32-bit value to right endianess */
326 static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
328 #ifdef __LITTLE_ENDIAN
329 memcpy(dst, src, len);
332 const __le32 *_src = src;
335 *_dst++ = le32_to_cpu(*_src++);
339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
341 static const char *module_names[CS46XX_DSP_MODULES] = {
342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
345 MODULE_FIRMWARE("cs46xx/cwc4630");
346 MODULE_FIRMWARE("cs46xx/cwcasync");
347 MODULE_FIRMWARE("cs46xx/cwcsnoop");
348 MODULE_FIRMWARE("cs46xx/cwcbinhack");
349 MODULE_FIRMWARE("cs46xx/cwcdma");
351 static void free_module_desc(struct dsp_module_desc *module)
355 kfree(module->module_name);
356 kfree(module->symbol_table.symbols);
357 if (module->segments) {
359 for (i = 0; i < module->nsegments; i++)
360 kfree(module->segments[i].data);
361 kfree(module->segments);
366 /* firmware binary format:
370 * char symbol_name[DSP_MAX_SYMBOL_NAME];
372 * } symbols[nsymbols];
379 * } segments[nsegments];
382 static int load_firmware(struct snd_cs46xx *chip,
383 struct dsp_module_desc **module_ret,
387 unsigned int nums, fwlen, fwsize;
389 struct dsp_module_desc *module = NULL;
390 const struct firmware *fw;
393 sprintf(fw_path, "cs46xx/%s", fw_name);
394 err = request_firmware(&fw, fw_path, &chip->pci->dev);
397 fwsize = fw->size / 4;
404 module = kzalloc(sizeof(*module), GFP_KERNEL);
407 module->module_name = kstrdup(fw_name, GFP_KERNEL);
408 if (!module->module_name)
412 fwdat = (const __le32 *)fw->data;
413 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
416 module->symbol_table.symbols =
417 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
418 if (!module->symbol_table.symbols)
420 for (i = 0; i < nums; i++) {
421 struct dsp_symbol_entry *entry =
422 &module->symbol_table.symbols[i];
423 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
425 entry->address = le32_to_cpu(fwdat[fwlen++]);
426 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
427 fwlen += DSP_MAX_SYMBOL_NAME / 4;
428 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
433 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
437 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
438 if (!module->segments)
440 for (i = 0; i < nums; i++) {
441 struct dsp_segment_desc *entry = &module->segments[i];
442 if (fwlen + 3 > fwsize)
444 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
445 entry->offset = le32_to_cpu(fwdat[fwlen++]);
446 entry->size = le32_to_cpu(fwdat[fwlen++]);
447 if (fwlen + entry->size > fwsize)
449 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
452 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
453 fwlen += entry->size;
456 *module_ret = module;
457 release_firmware(fw);
463 free_module_desc(module);
464 release_firmware(fw);
468 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
469 unsigned long offset,
473 unsigned int bank = offset >> 16;
474 offset = offset & 0xffff;
476 if (snd_BUG_ON((offset & 3) || (len & 3)))
478 dst = chip->region.idx[bank+1].remap_addr + offset;
481 /* writel already converts 32-bit value to right endianess */
489 #else /* old DSP image */
495 } memory[BA1_MEMORY_COUNT];
496 u32 map[BA1_DWORD_SIZE];
499 MODULE_FIRMWARE("cs46xx/ba1");
501 static int load_firmware(struct snd_cs46xx *chip)
503 const struct firmware *fw;
506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
509 if (fw->size != sizeof(*chip->ba1)) {
514 chip->ba1 = vmalloc(sizeof(*chip->ba1));
520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
524 for (i = 0; i < BA1_MEMORY_COUNT; i++)
525 size += chip->ba1->memory[i].size;
526 if (size > BA1_DWORD_SIZE * 4)
530 release_firmware(fw);
534 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
537 unsigned int offset = 0;
538 struct ba1_struct *ba1 = chip->ba1;
540 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
541 err = snd_cs46xx_download(chip,
543 ba1->memory[idx].offset,
544 ba1->memory[idx].size);
547 offset += ba1->memory[idx].size >> 2;
551 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
557 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
562 * Write the reset bit of the SP control register.
564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
567 * Write the control register.
569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
572 * Clear the trap registers.
574 for (idx = 0; idx < 8; idx++) {
575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
578 snd_cs46xx_poke(chip, BA1_DREG, 0);
581 * Set the frame timer to reflect the number of cycles per frame.
583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
586 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
590 * Make sure the previous FIFO write operation has completed.
592 for(i = 0; i < 50; i++){
593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
595 if( !(status & SERBST_WBSY) )
598 mdelay(retry_timeout);
601 if(status & SERBST_WBSY) {
602 dev_err(chip->card->dev,
603 "failure waiting for FIFO command to complete\n");
610 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
612 int idx, powerdown = 0;
616 * See if the devices are powered down. If so, we must power them up first
617 * or they will not respond.
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
620 if (!(tmp & CLKCR1_SWCE)) {
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
626 * We want to clear out the serial port FIFOs so we don't end up playing
627 * whatever random garbage happens to be in them. We fill the sample FIFOS
628 * with zero (silence).
630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
633 * Fill all 256 sample FIFO locations.
635 for (idx = 0; idx < 0xFF; idx++) {
637 * Make sure the previous FIFO write operation has completed.
639 if (cs46xx_wait_for_fifo(chip,1)) {
640 dev_dbg(chip->card->dev,
641 "failed waiting for FIFO at addr (%02X)\n",
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
650 * Write the serial port FIFO index.
652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
654 * Tell the serial port to load the new value into the FIFO location.
656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
659 * Now, if we powered up the devices, then power them back down again.
660 * This is kinda ugly, but should never happen.
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
666 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
671 * Set the frame timer to reflect the number of cycles per frame.
673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
675 * Turn on the run, run at frame, and DMA enable bits in the local copy of
676 * the SP control register.
678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
680 * Wait until the run at frame bit resets itself in the SP control
683 for (cnt = 0; cnt < 25; cnt++) {
685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
693 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
696 * Turn off the run, run at frame, and DMA enable bits in the local copy of
697 * the SP control register.
699 snd_cs46xx_poke(chip, BA1_SPCR, 0);
703 * Sample rate routines
706 #define GOF_PER_SEC 200
708 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
711 unsigned int tmp1, tmp2;
712 unsigned int phiIncr;
713 unsigned int correctionPerGOF, correctionPerSec;
716 * Compute the values used to drive the actual sample rate conversion.
717 * The following formulas are being computed, using inline assembly
718 * since we need to use 64 bit arithmetic to compute the values:
720 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
721 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
723 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
724 * GOF_PER_SEC * correctionPerGOF
728 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
729 * correctionPerGOF:correctionPerSec =
730 * dividend:remainder(ulOther / GOF_PER_SEC)
733 phiIncr = tmp1 / 48000;
734 tmp1 -= phiIncr * 48000;
739 tmp1 -= tmp2 * 48000;
740 correctionPerGOF = tmp1 / GOF_PER_SEC;
741 tmp1 -= correctionPerGOF * GOF_PER_SEC;
742 correctionPerSec = tmp1;
745 * Fill in the SampleRateConverter control block.
747 spin_lock_irqsave(&chip->reg_lock, flags);
748 snd_cs46xx_poke(chip, BA1_PSRC,
749 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
750 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
754 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
757 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
758 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
759 unsigned int frameGroupLength, cnt;
762 * We can only decimate by up to a factor of 1/9th the hardware rate.
763 * Correct the value if an attempt is made to stray outside that limit.
765 if ((rate * 9) < 48000)
769 * We can not capture at a rate greater than the Input Rate (48000).
770 * Return an error if an attempt is made to stray outside that limit.
776 * Compute the values used to drive the actual sample rate conversion.
777 * The following formulas are being computed, using inline assembly
778 * since we need to use 64 bit arithmetic to compute the values:
780 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
781 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
782 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
784 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
785 * GOF_PER_SEC * correctionPerGOF
786 * initialDelay = ceil((24 * Fs,in) / Fs,out)
790 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
791 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
792 * correctionPerGOF:correctionPerSec =
793 * dividend:remainder(ulOther / GOF_PER_SEC)
794 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
798 coeffIncr = tmp1 / 48000;
799 tmp1 -= coeffIncr * 48000;
802 coeffIncr += tmp1 / 48000;
803 coeffIncr ^= 0xFFFFFFFF;
806 phiIncr = tmp1 / rate;
807 tmp1 -= phiIncr * rate;
813 correctionPerGOF = tmp1 / GOF_PER_SEC;
814 tmp1 -= correctionPerGOF * GOF_PER_SEC;
815 correctionPerSec = tmp1;
816 initialDelay = DIV_ROUND_UP(48000 * 24, rate);
819 * Fill in the VariDecimate control block.
821 spin_lock_irqsave(&chip->reg_lock, flags);
822 snd_cs46xx_poke(chip, BA1_CSRC,
823 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
824 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
825 snd_cs46xx_poke(chip, BA1_CD,
826 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
827 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
831 * Figure out the frame group length for the write back task. Basically,
832 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
833 * the output sample rate.
835 frameGroupLength = 1;
836 for (cnt = 2; cnt <= 64; cnt *= 2) {
837 if (((rate / cnt) * cnt) != rate)
838 frameGroupLength *= 2;
840 if (((rate / 3) * 3) != rate) {
841 frameGroupLength *= 3;
843 for (cnt = 5; cnt <= 125; cnt *= 5) {
844 if (((rate / cnt) * cnt) != rate)
845 frameGroupLength *= 5;
849 * Fill in the WriteBack control block.
851 spin_lock_irqsave(&chip->reg_lock, flags);
852 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
853 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
854 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
855 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
856 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
857 spin_unlock_irqrestore(&chip->reg_lock, flags);
864 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
865 struct snd_pcm_indirect *rec, size_t bytes)
867 struct snd_pcm_runtime *runtime = substream->runtime;
868 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
869 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
872 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
874 struct snd_pcm_runtime *runtime = substream->runtime;
875 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
876 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
877 snd_cs46xx_pb_trans_copy);
880 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
881 struct snd_pcm_indirect *rec, size_t bytes)
883 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
884 struct snd_pcm_runtime *runtime = substream->runtime;
885 memcpy(runtime->dma_area + rec->sw_data,
886 chip->capt.hw_buf.area + rec->hw_data, bytes);
889 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
891 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
892 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
893 snd_cs46xx_cp_trans_copy);
896 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
900 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
902 if (snd_BUG_ON(!cpcm->pcm_channel))
905 #ifdef CONFIG_SND_CS46XX_NEW_DSP
906 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
908 ptr = snd_cs46xx_peek(chip, BA1_PBA);
910 ptr -= cpcm->hw_buf.addr;
911 return ptr >> cpcm->shift;
914 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
916 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
918 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
920 #ifdef CONFIG_SND_CS46XX_NEW_DSP
921 if (snd_BUG_ON(!cpcm->pcm_channel))
923 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
925 ptr = snd_cs46xx_peek(chip, BA1_PBA);
927 ptr -= cpcm->hw_buf.addr;
928 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
931 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
933 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
934 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
935 return ptr >> chip->capt.shift;
938 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
942 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
945 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
949 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
952 #ifdef CONFIG_SND_CS46XX_NEW_DSP
953 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
954 if (! cpcm->pcm_channel) {
959 case SNDRV_PCM_TRIGGER_START:
960 case SNDRV_PCM_TRIGGER_RESUME:
961 #ifdef CONFIG_SND_CS46XX_NEW_DSP
962 /* magic value to unmute PCM stream playback volume */
963 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
964 SCBVolumeCtrl) << 2, 0x80008000);
966 if (cpcm->pcm_channel->unlinked)
967 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
969 if (substream->runtime->periods != CS46XX_FRAGS)
970 snd_cs46xx_playback_transfer(substream);
972 spin_lock(&chip->reg_lock);
973 if (substream->runtime->periods != CS46XX_FRAGS)
974 snd_cs46xx_playback_transfer(substream);
976 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
978 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
980 spin_unlock(&chip->reg_lock);
983 case SNDRV_PCM_TRIGGER_STOP:
984 case SNDRV_PCM_TRIGGER_SUSPEND:
985 #ifdef CONFIG_SND_CS46XX_NEW_DSP
986 /* magic mute channel */
987 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
988 SCBVolumeCtrl) << 2, 0xffffffff);
990 if (!cpcm->pcm_channel->unlinked)
991 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
993 spin_lock(&chip->reg_lock);
995 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
997 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
999 spin_unlock(&chip->reg_lock);
1010 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1013 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1017 spin_lock(&chip->reg_lock);
1019 case SNDRV_PCM_TRIGGER_START:
1020 case SNDRV_PCM_TRIGGER_RESUME:
1021 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1023 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1025 case SNDRV_PCM_TRIGGER_STOP:
1026 case SNDRV_PCM_TRIGGER_SUSPEND:
1027 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1029 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1035 spin_unlock(&chip->reg_lock);
1040 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1041 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1045 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1046 if ( cpcm->pcm_channel == NULL) {
1047 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1048 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1049 if (cpcm->pcm_channel == NULL) {
1050 dev_err(chip->card->dev,
1051 "failed to create virtual PCM channel\n");
1054 cpcm->pcm_channel->sample_rate = sample_rate;
1056 /* if sample rate is changed */
1057 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1058 int unlinked = cpcm->pcm_channel->unlinked;
1059 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1061 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm,
1063 cpcm->pcm_channel_id);
1064 if (!cpcm->pcm_channel) {
1065 dev_err(chip->card->dev,
1066 "failed to re-create virtual PCM channel\n");
1070 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1071 cpcm->pcm_channel->sample_rate = sample_rate;
1079 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1080 struct snd_pcm_hw_params *hw_params)
1082 struct snd_pcm_runtime *runtime = substream->runtime;
1083 struct snd_cs46xx_pcm *cpcm;
1085 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1086 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1087 int sample_rate = params_rate(hw_params);
1088 int period_size = params_period_bytes(hw_params);
1090 cpcm = runtime->private_data;
1092 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1093 if (snd_BUG_ON(!sample_rate))
1096 mutex_lock(&chip->spos_mutex);
1098 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1099 mutex_unlock(&chip->spos_mutex);
1103 snd_BUG_ON(!cpcm->pcm_channel);
1104 if (!cpcm->pcm_channel) {
1105 mutex_unlock(&chip->spos_mutex);
1110 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1111 mutex_unlock(&chip->spos_mutex);
1115 dev_dbg(chip->card->dev,
1116 "period_size (%d), periods (%d) buffer_size(%d)\n",
1117 period_size, params_periods(hw_params),
1118 params_buffer_bytes(hw_params));
1121 if (params_periods(hw_params) == CS46XX_FRAGS) {
1122 if (runtime->dma_area != cpcm->hw_buf.area)
1123 snd_pcm_lib_free_pages(substream);
1124 snd_pcm_set_runtime_buffer(substream, &cpcm->hw_buf);
1127 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1128 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1129 substream->ops = &snd_cs46xx_playback_ops;
1130 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1131 substream->ops = &snd_cs46xx_playback_rear_ops;
1132 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1133 substream->ops = &snd_cs46xx_playback_clfe_ops;
1134 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1135 substream->ops = &snd_cs46xx_playback_iec958_ops;
1140 substream->ops = &snd_cs46xx_playback_ops;
1144 if (runtime->dma_area == cpcm->hw_buf.area)
1145 snd_pcm_set_runtime_buffer(substream, NULL);
1146 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1148 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1149 mutex_unlock(&chip->spos_mutex);
1154 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1155 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1156 substream->ops = &snd_cs46xx_playback_indirect_ops;
1157 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1158 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1159 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1160 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1161 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1162 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1167 substream->ops = &snd_cs46xx_playback_indirect_ops;
1172 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1173 mutex_unlock(&chip->spos_mutex);
1179 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1181 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1182 struct snd_pcm_runtime *runtime = substream->runtime;
1183 struct snd_cs46xx_pcm *cpcm;
1185 cpcm = runtime->private_data;
1187 /* if play_back open fails, then this function
1188 is called and cpcm can actually be NULL here */
1189 if (!cpcm) return -ENXIO;
1191 if (runtime->dma_area != cpcm->hw_buf.area)
1192 snd_pcm_lib_free_pages(substream);
1194 snd_pcm_set_runtime_buffer(substream, NULL);
1199 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1203 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1204 struct snd_pcm_runtime *runtime = substream->runtime;
1205 struct snd_cs46xx_pcm *cpcm;
1207 cpcm = runtime->private_data;
1209 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1210 if (snd_BUG_ON(!cpcm->pcm_channel))
1213 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1214 pfie &= ~0x0000f03f;
1217 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1218 pfie &= ~0x0000f03f;
1222 /* if to convert from stereo to mono */
1223 if (runtime->channels == 1) {
1227 /* if to convert from 8 bit to 16 bit */
1228 if (snd_pcm_format_width(runtime->format) == 8) {
1232 /* if to convert to unsigned */
1233 if (snd_pcm_format_unsigned(runtime->format))
1236 /* Never convert byte order when sample stream is 8 bit */
1237 if (snd_pcm_format_width(runtime->format) != 8) {
1238 /* convert from big endian to little endian */
1239 if (snd_pcm_format_big_endian(runtime->format))
1243 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1244 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1245 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1247 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1249 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1251 tmp |= (4 << cpcm->shift) - 1;
1252 /* playback transaction count register */
1253 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1255 /* playback format && interrupt enable */
1256 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1258 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1259 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1261 tmp |= (4 << cpcm->shift) - 1;
1262 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1263 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1264 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1270 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1271 struct snd_pcm_hw_params *hw_params)
1273 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1274 struct snd_pcm_runtime *runtime = substream->runtime;
1277 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1278 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1280 if (runtime->periods == CS46XX_FRAGS) {
1281 if (runtime->dma_area != chip->capt.hw_buf.area)
1282 snd_pcm_lib_free_pages(substream);
1283 snd_pcm_set_runtime_buffer(substream, &chip->capt.hw_buf);
1284 substream->ops = &snd_cs46xx_capture_ops;
1286 if (runtime->dma_area == chip->capt.hw_buf.area)
1287 snd_pcm_set_runtime_buffer(substream, NULL);
1288 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1291 substream->ops = &snd_cs46xx_capture_indirect_ops;
1297 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1299 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1300 struct snd_pcm_runtime *runtime = substream->runtime;
1302 if (runtime->dma_area != chip->capt.hw_buf.area)
1303 snd_pcm_lib_free_pages(substream);
1304 snd_pcm_set_runtime_buffer(substream, NULL);
1309 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1311 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1312 struct snd_pcm_runtime *runtime = substream->runtime;
1314 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1315 chip->capt.shift = 2;
1316 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1317 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1318 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1319 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1324 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1326 struct snd_cs46xx *chip = dev_id;
1328 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1329 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1332 struct snd_cs46xx_pcm *cpcm = NULL;
1336 * Read the Interrupt Status Register to clear the interrupt
1338 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1339 if ((status1 & 0x7fffffff) == 0) {
1340 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1344 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1345 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1347 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1349 if ( status1 & (1 << i) ) {
1350 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1351 if (chip->capt.substream)
1352 snd_pcm_period_elapsed(chip->capt.substream);
1354 if (ins->pcm_channels[i].active &&
1355 ins->pcm_channels[i].private_data &&
1356 !ins->pcm_channels[i].unlinked) {
1357 cpcm = ins->pcm_channels[i].private_data;
1358 snd_pcm_period_elapsed(cpcm->substream);
1363 if ( status2 & (1 << (i - 16))) {
1364 if (ins->pcm_channels[i].active &&
1365 ins->pcm_channels[i].private_data &&
1366 !ins->pcm_channels[i].unlinked) {
1367 cpcm = ins->pcm_channels[i].private_data;
1368 snd_pcm_period_elapsed(cpcm->substream);
1376 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1377 if (chip->playback_pcm->substream)
1378 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1380 if ((status1 & HISR_VC1) && chip->pcm) {
1381 if (chip->capt.substream)
1382 snd_pcm_period_elapsed(chip->capt.substream);
1386 if ((status1 & HISR_MIDI) && chip->rmidi) {
1389 spin_lock(&chip->reg_lock);
1390 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1391 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1392 if ((chip->midcr & MIDCR_RIE) == 0)
1394 snd_rawmidi_receive(chip->midi_input, &c, 1);
1396 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1397 if ((chip->midcr & MIDCR_TIE) == 0)
1399 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1400 chip->midcr &= ~MIDCR_TIE;
1401 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1404 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1406 spin_unlock(&chip->reg_lock);
1409 * EOI to the PCI part....reenables interrupts
1411 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1416 static const struct snd_pcm_hardware snd_cs46xx_playback =
1418 .info = (SNDRV_PCM_INFO_MMAP |
1419 SNDRV_PCM_INFO_INTERLEAVED |
1420 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1421 /*SNDRV_PCM_INFO_RESUME*/ |
1422 SNDRV_PCM_INFO_SYNC_APPLPTR),
1423 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1424 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1425 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1426 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1431 .buffer_bytes_max = (256 * 1024),
1432 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1433 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1434 .periods_min = CS46XX_FRAGS,
1435 .periods_max = 1024,
1439 static const struct snd_pcm_hardware snd_cs46xx_capture =
1441 .info = (SNDRV_PCM_INFO_MMAP |
1442 SNDRV_PCM_INFO_INTERLEAVED |
1443 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1444 /*SNDRV_PCM_INFO_RESUME*/ |
1445 SNDRV_PCM_INFO_SYNC_APPLPTR),
1446 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1447 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1452 .buffer_bytes_max = (256 * 1024),
1453 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1454 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1455 .periods_min = CS46XX_FRAGS,
1456 .periods_max = 1024,
1460 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1462 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1464 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1465 .count = ARRAY_SIZE(period_sizes),
1466 .list = period_sizes,
1472 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1474 kfree(runtime->private_data);
1477 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1479 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1480 struct snd_cs46xx_pcm * cpcm;
1481 struct snd_pcm_runtime *runtime = substream->runtime;
1483 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1486 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1487 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1492 runtime->hw = snd_cs46xx_playback;
1493 runtime->private_data = cpcm;
1494 runtime->private_free = snd_cs46xx_pcm_free_substream;
1496 cpcm->substream = substream;
1497 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1498 mutex_lock(&chip->spos_mutex);
1499 cpcm->pcm_channel = NULL;
1500 cpcm->pcm_channel_id = pcm_channel_id;
1503 snd_pcm_hw_constraint_list(runtime, 0,
1504 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1505 &hw_constraints_period_sizes);
1507 mutex_unlock(&chip->spos_mutex);
1509 chip->playback_pcm = cpcm; /* HACK */
1512 if (chip->accept_valid)
1513 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1514 chip->active_ctrl(chip, 1);
1519 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1521 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1522 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1525 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1526 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1528 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1529 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1532 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1534 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1535 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1538 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1540 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1542 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1544 mutex_lock(&chip->spos_mutex);
1545 cs46xx_iec958_pre_open (chip);
1546 mutex_unlock(&chip->spos_mutex);
1548 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1551 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1553 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1556 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1558 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1560 err = snd_cs46xx_playback_close(substream);
1562 mutex_lock(&chip->spos_mutex);
1563 cs46xx_iec958_post_close (chip);
1564 mutex_unlock(&chip->spos_mutex);
1570 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1572 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1574 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1575 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1577 chip->capt.substream = substream;
1578 substream->runtime->hw = snd_cs46xx_capture;
1580 if (chip->accept_valid)
1581 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1583 chip->active_ctrl(chip, 1);
1585 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1586 snd_pcm_hw_constraint_list(substream->runtime, 0,
1587 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1588 &hw_constraints_period_sizes);
1593 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1595 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1596 struct snd_pcm_runtime *runtime = substream->runtime;
1597 struct snd_cs46xx_pcm * cpcm;
1599 cpcm = runtime->private_data;
1601 /* when playback_open fails, then cpcm can be NULL */
1602 if (!cpcm) return -ENXIO;
1604 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1605 mutex_lock(&chip->spos_mutex);
1606 if (cpcm->pcm_channel) {
1607 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1608 cpcm->pcm_channel = NULL;
1610 mutex_unlock(&chip->spos_mutex);
1612 chip->playback_pcm = NULL;
1615 cpcm->substream = NULL;
1616 snd_dma_free_pages(&cpcm->hw_buf);
1617 chip->active_ctrl(chip, -1);
1622 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1624 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1626 chip->capt.substream = NULL;
1627 snd_dma_free_pages(&chip->capt.hw_buf);
1628 chip->active_ctrl(chip, -1);
1633 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1634 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1635 .open = snd_cs46xx_playback_open_rear,
1636 .close = snd_cs46xx_playback_close,
1637 .hw_params = snd_cs46xx_playback_hw_params,
1638 .hw_free = snd_cs46xx_playback_hw_free,
1639 .prepare = snd_cs46xx_playback_prepare,
1640 .trigger = snd_cs46xx_playback_trigger,
1641 .pointer = snd_cs46xx_playback_direct_pointer,
1644 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1645 .open = snd_cs46xx_playback_open_rear,
1646 .close = snd_cs46xx_playback_close,
1647 .hw_params = snd_cs46xx_playback_hw_params,
1648 .hw_free = snd_cs46xx_playback_hw_free,
1649 .prepare = snd_cs46xx_playback_prepare,
1650 .trigger = snd_cs46xx_playback_trigger,
1651 .pointer = snd_cs46xx_playback_indirect_pointer,
1652 .ack = snd_cs46xx_playback_transfer,
1655 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1656 .open = snd_cs46xx_playback_open_clfe,
1657 .close = snd_cs46xx_playback_close,
1658 .hw_params = snd_cs46xx_playback_hw_params,
1659 .hw_free = snd_cs46xx_playback_hw_free,
1660 .prepare = snd_cs46xx_playback_prepare,
1661 .trigger = snd_cs46xx_playback_trigger,
1662 .pointer = snd_cs46xx_playback_direct_pointer,
1665 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1666 .open = snd_cs46xx_playback_open_clfe,
1667 .close = snd_cs46xx_playback_close,
1668 .hw_params = snd_cs46xx_playback_hw_params,
1669 .hw_free = snd_cs46xx_playback_hw_free,
1670 .prepare = snd_cs46xx_playback_prepare,
1671 .trigger = snd_cs46xx_playback_trigger,
1672 .pointer = snd_cs46xx_playback_indirect_pointer,
1673 .ack = snd_cs46xx_playback_transfer,
1676 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1677 .open = snd_cs46xx_playback_open_iec958,
1678 .close = snd_cs46xx_playback_close_iec958,
1679 .hw_params = snd_cs46xx_playback_hw_params,
1680 .hw_free = snd_cs46xx_playback_hw_free,
1681 .prepare = snd_cs46xx_playback_prepare,
1682 .trigger = snd_cs46xx_playback_trigger,
1683 .pointer = snd_cs46xx_playback_direct_pointer,
1686 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1687 .open = snd_cs46xx_playback_open_iec958,
1688 .close = snd_cs46xx_playback_close_iec958,
1689 .hw_params = snd_cs46xx_playback_hw_params,
1690 .hw_free = snd_cs46xx_playback_hw_free,
1691 .prepare = snd_cs46xx_playback_prepare,
1692 .trigger = snd_cs46xx_playback_trigger,
1693 .pointer = snd_cs46xx_playback_indirect_pointer,
1694 .ack = snd_cs46xx_playback_transfer,
1699 static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1700 .open = snd_cs46xx_playback_open,
1701 .close = snd_cs46xx_playback_close,
1702 .hw_params = snd_cs46xx_playback_hw_params,
1703 .hw_free = snd_cs46xx_playback_hw_free,
1704 .prepare = snd_cs46xx_playback_prepare,
1705 .trigger = snd_cs46xx_playback_trigger,
1706 .pointer = snd_cs46xx_playback_direct_pointer,
1709 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1710 .open = snd_cs46xx_playback_open,
1711 .close = snd_cs46xx_playback_close,
1712 .hw_params = snd_cs46xx_playback_hw_params,
1713 .hw_free = snd_cs46xx_playback_hw_free,
1714 .prepare = snd_cs46xx_playback_prepare,
1715 .trigger = snd_cs46xx_playback_trigger,
1716 .pointer = snd_cs46xx_playback_indirect_pointer,
1717 .ack = snd_cs46xx_playback_transfer,
1720 static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1721 .open = snd_cs46xx_capture_open,
1722 .close = snd_cs46xx_capture_close,
1723 .hw_params = snd_cs46xx_capture_hw_params,
1724 .hw_free = snd_cs46xx_capture_hw_free,
1725 .prepare = snd_cs46xx_capture_prepare,
1726 .trigger = snd_cs46xx_capture_trigger,
1727 .pointer = snd_cs46xx_capture_direct_pointer,
1730 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1731 .open = snd_cs46xx_capture_open,
1732 .close = snd_cs46xx_capture_close,
1733 .hw_params = snd_cs46xx_capture_hw_params,
1734 .hw_free = snd_cs46xx_capture_hw_free,
1735 .prepare = snd_cs46xx_capture_prepare,
1736 .trigger = snd_cs46xx_capture_trigger,
1737 .pointer = snd_cs46xx_capture_indirect_pointer,
1738 .ack = snd_cs46xx_capture_transfer,
1741 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1742 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1744 #define MAX_PLAYBACK_CHANNELS 1
1747 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1749 struct snd_pcm *pcm;
1752 err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm);
1756 pcm->private_data = chip;
1758 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1759 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1762 pcm->info_flags = 0;
1763 strcpy(pcm->name, "CS46xx");
1766 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1774 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1775 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1777 struct snd_pcm *pcm;
1780 err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1784 pcm->private_data = chip;
1786 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1789 pcm->info_flags = 0;
1790 strcpy(pcm->name, "CS46xx - Rear");
1791 chip->pcm_rear = pcm;
1793 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1800 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1802 struct snd_pcm *pcm;
1805 err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1809 pcm->private_data = chip;
1811 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1814 pcm->info_flags = 0;
1815 strcpy(pcm->name, "CS46xx - Center LFE");
1816 chip->pcm_center_lfe = pcm;
1818 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1825 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1827 struct snd_pcm *pcm;
1830 err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm);
1834 pcm->private_data = chip;
1836 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1839 pcm->info_flags = 0;
1840 strcpy(pcm->name, "CS46xx - IEC958");
1841 chip->pcm_iec958 = pcm;
1843 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1854 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1856 struct snd_cs46xx *chip = ac97->private_data;
1858 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1859 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1862 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1863 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1864 chip->eapd_switch = NULL;
1867 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1870 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1871 struct snd_ctl_elem_info *uinfo)
1873 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1875 uinfo->value.integer.min = 0;
1876 uinfo->value.integer.max = 0x7fff;
1880 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1882 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1883 int reg = kcontrol->private_value;
1884 unsigned int val = snd_cs46xx_peek(chip, reg);
1885 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1886 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1890 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1892 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1893 int reg = kcontrol->private_value;
1894 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1895 (0xffff - ucontrol->value.integer.value[1]));
1896 unsigned int old = snd_cs46xx_peek(chip, reg);
1897 int change = (old != val);
1900 snd_cs46xx_poke(chip, reg, val);
1906 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1908 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1910 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1912 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1913 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1918 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1920 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1923 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1924 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1925 cs46xx_dsp_set_dac_volume(chip,
1926 ucontrol->value.integer.value[0],
1927 ucontrol->value.integer.value[1]);
1935 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1937 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1939 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1940 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1944 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1946 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1949 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1950 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1951 cs46xx_dsp_set_iec958_volume (chip,
1952 ucontrol->value.integer.value[0],
1953 ucontrol->value.integer.value[1]);
1961 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1963 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1964 struct snd_ctl_elem_value *ucontrol)
1966 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1967 int reg = kcontrol->private_value;
1969 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1970 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1972 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1977 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1978 struct snd_ctl_elem_value *ucontrol)
1980 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1983 switch (kcontrol->private_value) {
1984 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1985 mutex_lock(&chip->spos_mutex);
1986 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1987 if (ucontrol->value.integer.value[0] && !change)
1988 cs46xx_dsp_enable_spdif_out(chip);
1989 else if (change && !ucontrol->value.integer.value[0])
1990 cs46xx_dsp_disable_spdif_out(chip);
1992 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1993 mutex_unlock(&chip->spos_mutex);
1995 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1996 change = chip->dsp_spos_instance->spdif_status_in;
1997 if (ucontrol->value.integer.value[0] && !change) {
1998 cs46xx_dsp_enable_spdif_in(chip);
1999 /* restore volume */
2001 else if (change && !ucontrol->value.integer.value[0])
2002 cs46xx_dsp_disable_spdif_in(chip);
2004 res = (change != chip->dsp_spos_instance->spdif_status_in);
2008 snd_BUG(); /* should never happen ... */
2014 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2015 struct snd_ctl_elem_value *ucontrol)
2017 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2018 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2020 if (ins->adc_input != NULL)
2021 ucontrol->value.integer.value[0] = 1;
2023 ucontrol->value.integer.value[0] = 0;
2028 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2029 struct snd_ctl_elem_value *ucontrol)
2031 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2032 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2035 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2036 cs46xx_dsp_enable_adc_capture(chip);
2038 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2039 cs46xx_dsp_disable_adc_capture(chip);
2045 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2046 struct snd_ctl_elem_value *ucontrol)
2048 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2049 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2051 if (ins->pcm_input != NULL)
2052 ucontrol->value.integer.value[0] = 1;
2054 ucontrol->value.integer.value[0] = 0;
2060 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2061 struct snd_ctl_elem_value *ucontrol)
2063 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2064 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2067 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2068 cs46xx_dsp_enable_pcm_capture(chip);
2070 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2071 cs46xx_dsp_disable_pcm_capture(chip);
2078 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2079 struct snd_ctl_elem_value *ucontrol)
2081 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2083 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2085 if (val1 & EGPIODR_GPOE0)
2086 ucontrol->value.integer.value[0] = 1;
2088 ucontrol->value.integer.value[0] = 0;
2094 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2096 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2097 struct snd_ctl_elem_value *ucontrol)
2099 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2100 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2101 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2103 if (ucontrol->value.integer.value[0]) {
2104 /* optical is default */
2105 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2106 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2107 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2108 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2111 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2112 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2115 /* checking diff from the EGPIO direction register
2117 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2121 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2123 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2128 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2129 struct snd_ctl_elem_value *ucontrol)
2131 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2132 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2134 mutex_lock(&chip->spos_mutex);
2135 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2136 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2137 ucontrol->value.iec958.status[2] = 0;
2138 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2139 mutex_unlock(&chip->spos_mutex);
2144 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2145 struct snd_ctl_elem_value *ucontrol)
2147 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2148 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2152 mutex_lock(&chip->spos_mutex);
2153 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2154 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2155 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2156 /* left and right validity bit */
2157 (1 << 13) | (1 << 12);
2160 change = (unsigned int)ins->spdif_csuv_default != val;
2161 ins->spdif_csuv_default = val;
2163 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2164 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2166 mutex_unlock(&chip->spos_mutex);
2171 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2172 struct snd_ctl_elem_value *ucontrol)
2174 ucontrol->value.iec958.status[0] = 0xff;
2175 ucontrol->value.iec958.status[1] = 0xff;
2176 ucontrol->value.iec958.status[2] = 0x00;
2177 ucontrol->value.iec958.status[3] = 0xff;
2181 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2182 struct snd_ctl_elem_value *ucontrol)
2184 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2185 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2187 mutex_lock(&chip->spos_mutex);
2188 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2189 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2190 ucontrol->value.iec958.status[2] = 0;
2191 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2192 mutex_unlock(&chip->spos_mutex);
2197 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2198 struct snd_ctl_elem_value *ucontrol)
2200 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2201 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2205 mutex_lock(&chip->spos_mutex);
2206 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2207 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2208 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2209 /* left and right validity bit */
2210 (1 << 13) | (1 << 12);
2213 change = ins->spdif_csuv_stream != val;
2214 ins->spdif_csuv_stream = val;
2216 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2217 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2219 mutex_unlock(&chip->spos_mutex);
2224 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2227 static const struct snd_kcontrol_new snd_cs46xx_controls[] = {
2229 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2230 .name = "DAC Volume",
2231 .info = snd_cs46xx_vol_info,
2232 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2233 .get = snd_cs46xx_vol_get,
2234 .put = snd_cs46xx_vol_put,
2235 .private_value = BA1_PVOL,
2237 .get = snd_cs46xx_vol_dac_get,
2238 .put = snd_cs46xx_vol_dac_put,
2243 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2244 .name = "ADC Volume",
2245 .info = snd_cs46xx_vol_info,
2246 .get = snd_cs46xx_vol_get,
2247 .put = snd_cs46xx_vol_put,
2248 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2249 .private_value = BA1_CVOL,
2251 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2254 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2256 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2257 .name = "ADC Capture Switch",
2258 .info = snd_mixer_boolean_info,
2259 .get = snd_cs46xx_adc_capture_get,
2260 .put = snd_cs46xx_adc_capture_put
2263 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2264 .name = "DAC Capture Switch",
2265 .info = snd_mixer_boolean_info,
2266 .get = snd_cs46xx_pcm_capture_get,
2267 .put = snd_cs46xx_pcm_capture_put
2270 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2271 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2272 .info = snd_mixer_boolean_info,
2273 .get = snd_cs46xx_iec958_get,
2274 .put = snd_cs46xx_iec958_put,
2275 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2278 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2279 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2280 .info = snd_mixer_boolean_info,
2281 .get = snd_cs46xx_iec958_get,
2282 .put = snd_cs46xx_iec958_put,
2283 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2286 /* Input IEC958 volume does not work for the moment. (Benny) */
2288 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2289 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2290 .info = snd_cs46xx_vol_info,
2291 .get = snd_cs46xx_vol_iec958_get,
2292 .put = snd_cs46xx_vol_iec958_put,
2293 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2297 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2298 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2299 .info = snd_cs46xx_spdif_info,
2300 .get = snd_cs46xx_spdif_default_get,
2301 .put = snd_cs46xx_spdif_default_put,
2304 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2305 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2306 .info = snd_cs46xx_spdif_info,
2307 .get = snd_cs46xx_spdif_mask_get,
2308 .access = SNDRV_CTL_ELEM_ACCESS_READ
2311 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2312 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2313 .info = snd_cs46xx_spdif_info,
2314 .get = snd_cs46xx_spdif_stream_get,
2315 .put = snd_cs46xx_spdif_stream_put
2321 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2322 /* set primary cs4294 codec into Extended Audio Mode */
2323 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2324 struct snd_ctl_elem_value *ucontrol)
2326 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2328 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2329 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2333 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2334 struct snd_ctl_elem_value *ucontrol)
2336 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2337 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2338 AC97_CSR_ACMODE, 0x200,
2339 ucontrol->value.integer.value[0] ? 0 : 0x200);
2342 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2343 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2344 .name = "Duplicate Front",
2345 .info = snd_mixer_boolean_info,
2346 .get = snd_cs46xx_front_dup_get,
2347 .put = snd_cs46xx_front_dup_put,
2351 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2352 /* Only available on the Hercules Game Theater XP soundcard */
2353 static const struct snd_kcontrol_new snd_hercules_controls[] = {
2355 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2356 .name = "Optical/Coaxial SPDIF Input Switch",
2357 .info = snd_mixer_boolean_info,
2358 .get = snd_herc_spdif_select_get,
2359 .put = snd_herc_spdif_select_put,
2364 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2366 unsigned long end_time;
2369 /* reset to defaults */
2370 snd_ac97_write(ac97, AC97_RESET, 0);
2372 /* set the desired CODEC mode */
2373 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2374 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2375 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2376 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2377 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2378 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2380 snd_BUG(); /* should never happen ... */
2385 /* it's necessary to wait awhile until registers are accessible after RESET */
2386 /* because the PCM or MASTER volume registers can be modified, */
2387 /* the REC_GAIN register is used for tests */
2388 end_time = jiffies + HZ;
2390 unsigned short ext_mid;
2392 /* use preliminary reads to settle the communication */
2393 snd_ac97_read(ac97, AC97_RESET);
2394 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2395 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2397 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2398 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2401 /* test if we can write to the record gain volume register */
2402 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2403 err = snd_ac97_read(ac97, AC97_REC_GAIN);
2408 } while (time_after_eq(end_time, jiffies));
2410 dev_err(ac97->bus->card->dev,
2411 "CS46xx secondary codec doesn't respond!\n");
2415 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2418 struct snd_ac97_template ac97;
2420 memset(&ac97, 0, sizeof(ac97));
2421 ac97.private_data = chip;
2422 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2424 if (chip->amplifier_ctrl == amp_voyetra)
2425 ac97.scaps = AC97_SCAP_INV_EAPD;
2427 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2428 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2430 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2431 dev_dbg(chip->card->dev,
2432 "secondary codec not present\n");
2437 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2438 for (idx = 0; idx < 100; ++idx) {
2439 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2440 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2445 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2449 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2451 struct snd_card *card = chip->card;
2452 struct snd_ctl_elem_id id;
2455 static const struct snd_ac97_bus_ops ops = {
2456 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2457 .reset = snd_cs46xx_codec_reset,
2459 .write = snd_cs46xx_ac97_write,
2460 .read = snd_cs46xx_ac97_read,
2463 /* detect primary codec */
2464 chip->nr_ac97_codecs = 0;
2465 dev_dbg(chip->card->dev, "detecting primary codec\n");
2466 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
2470 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2472 chip->nr_ac97_codecs = 1;
2474 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2475 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2476 /* try detect a secondary codec */
2477 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2478 chip->nr_ac97_codecs = 2;
2479 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2481 /* add cs4630 mixer controls */
2482 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2483 struct snd_kcontrol *kctl;
2484 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2485 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2486 kctl->id.device = spdif_device;
2487 err = snd_ctl_add(card, kctl);
2492 /* get EAPD mixer switch (for voyetra hack) */
2493 memset(&id, 0, sizeof(id));
2494 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2495 strcpy(id.name, "External Amplifier");
2496 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2498 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2499 if (chip->nr_ac97_codecs == 1) {
2500 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2501 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2502 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2505 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2506 AC97_CSR_ACMODE, 0x200);
2509 /* do soundcard specific mixer setup */
2510 if (chip->mixer_init) {
2511 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2512 chip->mixer_init(chip);
2516 /* turn on amplifier */
2517 chip->amplifier_ctrl(chip, 1);
2526 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2528 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2530 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2533 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2535 struct snd_cs46xx *chip = substream->rmidi->private_data;
2537 chip->active_ctrl(chip, 1);
2538 spin_lock_irq(&chip->reg_lock);
2539 chip->uartm |= CS46XX_MODE_INPUT;
2540 chip->midcr |= MIDCR_RXE;
2541 chip->midi_input = substream;
2542 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2543 snd_cs46xx_midi_reset(chip);
2545 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2547 spin_unlock_irq(&chip->reg_lock);
2551 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2553 struct snd_cs46xx *chip = substream->rmidi->private_data;
2555 spin_lock_irq(&chip->reg_lock);
2556 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2557 chip->midi_input = NULL;
2558 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2559 snd_cs46xx_midi_reset(chip);
2561 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2563 chip->uartm &= ~CS46XX_MODE_INPUT;
2564 spin_unlock_irq(&chip->reg_lock);
2565 chip->active_ctrl(chip, -1);
2569 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2571 struct snd_cs46xx *chip = substream->rmidi->private_data;
2573 chip->active_ctrl(chip, 1);
2575 spin_lock_irq(&chip->reg_lock);
2576 chip->uartm |= CS46XX_MODE_OUTPUT;
2577 chip->midcr |= MIDCR_TXE;
2578 chip->midi_output = substream;
2579 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2580 snd_cs46xx_midi_reset(chip);
2582 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2584 spin_unlock_irq(&chip->reg_lock);
2588 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2590 struct snd_cs46xx *chip = substream->rmidi->private_data;
2592 spin_lock_irq(&chip->reg_lock);
2593 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2594 chip->midi_output = NULL;
2595 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2596 snd_cs46xx_midi_reset(chip);
2598 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2600 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2601 spin_unlock_irq(&chip->reg_lock);
2602 chip->active_ctrl(chip, -1);
2606 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2608 unsigned long flags;
2609 struct snd_cs46xx *chip = substream->rmidi->private_data;
2611 spin_lock_irqsave(&chip->reg_lock, flags);
2613 if ((chip->midcr & MIDCR_RIE) == 0) {
2614 chip->midcr |= MIDCR_RIE;
2615 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2618 if (chip->midcr & MIDCR_RIE) {
2619 chip->midcr &= ~MIDCR_RIE;
2620 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2623 spin_unlock_irqrestore(&chip->reg_lock, flags);
2626 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2628 unsigned long flags;
2629 struct snd_cs46xx *chip = substream->rmidi->private_data;
2632 spin_lock_irqsave(&chip->reg_lock, flags);
2634 if ((chip->midcr & MIDCR_TIE) == 0) {
2635 chip->midcr |= MIDCR_TIE;
2636 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2637 while ((chip->midcr & MIDCR_TIE) &&
2638 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2639 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2640 chip->midcr &= ~MIDCR_TIE;
2642 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2645 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2648 if (chip->midcr & MIDCR_TIE) {
2649 chip->midcr &= ~MIDCR_TIE;
2650 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2653 spin_unlock_irqrestore(&chip->reg_lock, flags);
2656 static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2658 .open = snd_cs46xx_midi_output_open,
2659 .close = snd_cs46xx_midi_output_close,
2660 .trigger = snd_cs46xx_midi_output_trigger,
2663 static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2665 .open = snd_cs46xx_midi_input_open,
2666 .close = snd_cs46xx_midi_input_close,
2667 .trigger = snd_cs46xx_midi_input_trigger,
2670 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2672 struct snd_rawmidi *rmidi;
2675 err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi);
2678 strcpy(rmidi->name, "CS46XX");
2679 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2680 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2681 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2682 rmidi->private_data = chip;
2683 chip->rmidi = rmidi;
2689 * gameport interface
2692 #if IS_REACHABLE(CONFIG_GAMEPORT)
2694 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2696 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2698 if (snd_BUG_ON(!chip))
2700 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2703 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2705 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2707 if (snd_BUG_ON(!chip))
2709 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2712 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2714 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2715 unsigned js1, js2, jst;
2717 if (snd_BUG_ON(!chip))
2720 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2721 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2722 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2724 *buttons = (~jst >> 4) & 0x0F;
2726 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2727 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2728 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2729 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2731 for(jst=0;jst<4;++jst)
2732 if(axes[jst]==0xFFFF) axes[jst] = -1;
2736 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2739 case GAMEPORT_MODE_COOKED:
2741 case GAMEPORT_MODE_RAW:
2749 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2751 struct gameport *gp;
2753 chip->gameport = gp = gameport_allocate_port();
2755 dev_err(chip->card->dev,
2756 "cannot allocate memory for gameport\n");
2760 gameport_set_name(gp, "CS46xx Gameport");
2761 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2762 gameport_set_dev_parent(gp, &chip->pci->dev);
2763 gameport_set_port_data(gp, chip);
2765 gp->open = snd_cs46xx_gameport_open;
2766 gp->read = snd_cs46xx_gameport_read;
2767 gp->trigger = snd_cs46xx_gameport_trigger;
2768 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2770 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2771 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2773 gameport_register_port(gp);
2778 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2780 if (chip->gameport) {
2781 gameport_unregister_port(chip->gameport);
2782 chip->gameport = NULL;
2786 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2787 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2788 #endif /* CONFIG_GAMEPORT */
2790 #ifdef CONFIG_SND_PROC_FS
2795 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2796 void *file_private_data,
2797 struct file *file, char __user *buf,
2798 size_t count, loff_t pos)
2800 struct snd_cs46xx_region *region = entry->private_data;
2802 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2807 static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2808 .read = snd_cs46xx_io_read,
2811 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2813 struct snd_info_entry *entry;
2816 for (idx = 0; idx < 5; idx++) {
2817 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2818 if (! snd_card_proc_new(card, region->name, &entry)) {
2819 entry->content = SNDRV_INFO_CONTENT_DATA;
2820 entry->private_data = chip;
2821 entry->c.ops = &snd_cs46xx_proc_io_ops;
2822 entry->size = region->size;
2823 entry->mode = S_IFREG | 0400;
2826 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2827 cs46xx_dsp_proc_init(card, chip);
2832 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2834 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2835 cs46xx_dsp_proc_done(chip);
2839 #else /* !CONFIG_SND_PROC_FS */
2840 #define snd_cs46xx_proc_init(card, chip)
2841 #define snd_cs46xx_proc_done(chip)
2847 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2851 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2854 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2856 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2859 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2862 * Stop playback DMA.
2864 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2865 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2870 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2871 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2874 * Reset the processor.
2876 snd_cs46xx_reset(chip);
2878 snd_cs46xx_proc_stop(chip);
2881 * Power down the PLL.
2883 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2886 * Turn off the Processor by turning off the software clock enable flag in
2887 * the clock control register.
2889 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2890 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2894 static void snd_cs46xx_free(struct snd_card *card)
2896 struct snd_cs46xx *chip = card->private_data;
2897 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2901 if (chip->active_ctrl)
2902 chip->active_ctrl(chip, 1);
2904 snd_cs46xx_remove_gameport(chip);
2906 if (chip->amplifier_ctrl)
2907 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2909 snd_cs46xx_proc_done(chip);
2911 snd_cs46xx_hw_stop(chip);
2913 if (chip->active_ctrl)
2914 chip->active_ctrl(chip, -chip->amplifier);
2916 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2917 if (chip->dsp_spos_instance) {
2918 cs46xx_dsp_spos_destroy(chip);
2919 chip->dsp_spos_instance = NULL;
2921 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2922 free_module_desc(chip->modules[idx]);
2931 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2936 * First, blast the clock control register to zero so that the PLL starts
2937 * out in a known state, and blast the master serial port control register
2938 * to zero so that the serial ports also start out in a known state.
2940 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2941 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2944 * If we are in AC97 mode, then we must set the part to a host controlled
2945 * AC-link. Otherwise, we won't be able to bring up the link.
2947 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2948 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2949 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2950 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2952 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2956 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2957 * spec) and then drive it high. This is done for non AC97 modes since
2958 * there might be logic external to the CS461x that uses the ARST# line
2961 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2962 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2963 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2966 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2967 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2968 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2972 * The first thing we do here is to enable sync generation. As soon
2973 * as we start receiving bit clock, we'll start producing the SYNC
2976 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2977 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2978 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2982 * Now wait for a short while to allow the AC97 part to start
2983 * generating bit clock (so we don't try to start the PLL without an
2989 * Set the serial port timing configuration, so that
2990 * the clock control circuit gets its clock from the correct place.
2992 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2995 * Write the selected clock control setup to the hardware. Do not turn on
2996 * SWCE yet (if requested), so that the devices clocked by the output of
2997 * PLL are not clocked until the PLL is stable.
2999 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3000 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3001 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3006 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3009 * Wait until the PLL has stabilized.
3014 * Turn on clocking of the core so that we can setup the serial ports.
3016 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3019 * Enable FIFO Host Bypass
3021 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3024 * Fill the serial port FIFOs with silence.
3026 snd_cs46xx_clear_serial_FIFOs(chip);
3029 * Set the serial port FIFO pointer to the first sample in the FIFO.
3031 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3034 * Write the serial port configuration to the part. The master
3035 * enable bit is not set until all other values have been written.
3037 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3038 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3039 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3042 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3043 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3044 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3045 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3046 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3047 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3054 * Wait for the codec ready signal from the AC97 codec.
3057 while (timeout-- > 0) {
3059 * Read the AC97 status register to see if we've seen a CODEC READY
3060 * signal from the AC97 codec.
3062 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3068 dev_err(chip->card->dev,
3069 "create - never read codec ready from AC'97\n");
3070 dev_err(chip->card->dev,
3071 "it is not probably bug, try to use CS4236 driver\n");
3074 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3077 for (count = 0; count < 150; count++) {
3078 /* First, we want to wait for a short time. */
3081 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3086 * Make sure CODEC is READY.
3088 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3089 dev_dbg(chip->card->dev,
3090 "never read card ready from secondary AC'97\n");
3095 * Assert the vaid frame signal so that we can start sending commands
3096 * to the AC97 codec.
3098 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3099 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3100 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3105 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3106 * the codec is pumping ADC data across the AC-link.
3109 while (timeout-- > 0) {
3111 * Read the input slot valid register and see if input slots 3 and
3114 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3119 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3120 dev_err(chip->card->dev,
3121 "create - never read ISV3 & ISV4 from AC'97\n");
3124 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3125 Reloading the driver may help, if there's other soundcards
3126 with the same problem I would like to know. (Benny) */
3128 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3129 dev_err(chip->card->dev,
3130 "Try reloading the ALSA driver, if you find something\n");
3131 dev_err(chip->card->dev,
3132 "broken or not working on your soundcard upon\n");
3133 dev_err(chip->card->dev,
3134 "this message please report to alsa-devel@alsa-project.org\n");
3141 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3142 * commense the transfer of digital audio data to the AC97 codec.
3145 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3149 * Power down the DAC and ADC. We will power them up (if) when we need
3152 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3155 * Turn off the Processor by turning off the software clock enable flag in
3156 * the clock control register.
3158 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3159 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3165 * start and load DSP
3168 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3172 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3174 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3176 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3178 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3181 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3184 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3187 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3193 * Reset the processor.
3195 snd_cs46xx_reset(chip);
3197 * Download the image to the processor.
3199 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3200 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3201 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3203 dev_err(chip->card->dev, "firmware load error [%s]\n",
3207 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3209 dev_err(chip->card->dev, "image download error [%s]\n",
3215 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3218 err = load_firmware(chip);
3223 err = snd_cs46xx_download_image(chip);
3225 dev_err(chip->card->dev, "image download error\n");
3230 * Stop playback DMA.
3232 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3233 chip->play_ctl = tmp & 0xffff0000;
3234 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3240 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3241 chip->capt.ctl = tmp & 0x0000ffff;
3242 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3246 snd_cs46xx_set_play_sample_rate(chip, 8000);
3247 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3249 snd_cs46xx_proc_start(chip);
3251 cs46xx_enable_stream_irqs(chip);
3253 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3254 /* set the attenuation to 0dB */
3255 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3256 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3264 * AMP control - null AMP
3267 static void amp_none(struct snd_cs46xx *chip, int change)
3271 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3272 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3275 u32 idx, valid_slots,tmp,powerdown = 0;
3276 u16 modem_power,pin_config,logic_type;
3278 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3281 * See if the devices are powered down. If so, we must power them up first
3282 * or they will not respond.
3284 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3286 if (!(tmp & CLKCR1_SWCE)) {
3287 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3292 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3295 if(chip->nr_ac97_codecs != 2) {
3296 dev_err(chip->card->dev,
3297 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3301 modem_power = snd_cs46xx_codec_read (chip,
3302 AC97_EXTENDED_MSTATUS,
3303 CS46XX_SECONDARY_CODEC_INDEX);
3304 modem_power &=0xFEFF;
3306 snd_cs46xx_codec_write(chip,
3307 AC97_EXTENDED_MSTATUS, modem_power,
3308 CS46XX_SECONDARY_CODEC_INDEX);
3311 * Set GPIO pin's 7 and 8 so that they are configured for output.
3313 pin_config = snd_cs46xx_codec_read (chip,
3315 CS46XX_SECONDARY_CODEC_INDEX);
3318 snd_cs46xx_codec_write(chip,
3319 AC97_GPIO_CFG, pin_config,
3320 CS46XX_SECONDARY_CODEC_INDEX);
3323 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3326 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3327 CS46XX_SECONDARY_CODEC_INDEX);
3330 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3331 CS46XX_SECONDARY_CODEC_INDEX);
3333 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3334 valid_slots |= 0x200;
3335 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3337 if ( cs46xx_wait_for_fifo(chip,1) ) {
3338 dev_dbg(chip->card->dev, "FIFO is busy\n");
3344 * Fill slots 12 with the correct value for the GPIO pins.
3346 for(idx = 0x90; idx <= 0x9F; idx++) {
3348 * Initialize the fifo so that bits 7 and 8 are on.
3350 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3351 * the left. 0x1800 corresponds to bits 7 and 8.
3353 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3356 * Wait for command to complete
3358 if ( cs46xx_wait_for_fifo(chip,200) ) {
3359 dev_dbg(chip->card->dev,
3360 "failed waiting for FIFO at addr (%02X)\n",
3367 * Write the serial port FIFO index.
3369 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3372 * Tell the serial port to load the new value into the FIFO location.
3374 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3377 /* wait for last command to complete */
3378 cs46xx_wait_for_fifo(chip,200);
3381 * Now, if we powered up the devices, then power them back down again.
3382 * This is kinda ugly, but should never happen.
3385 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3395 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3397 /* Manage the EAPD bit on the Crystal 4297
3398 and the Analog AD1885 */
3400 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3401 int old = chip->amplifier;
3405 chip->amplifier += change;
3406 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3407 CS46XX_PRIMARY_CODEC_INDEX);
3409 if (chip->amplifier) {
3410 /* Turn the EAPD amp on */
3413 /* Turn the EAPD amp off */
3417 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3418 CS46XX_PRIMARY_CODEC_INDEX);
3419 if (chip->eapd_switch)
3420 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3421 &chip->eapd_switch->id);
3424 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3425 if (chip->amplifier && !old) {
3426 voyetra_setup_eapd_slot(chip);
3431 static void hercules_init(struct snd_cs46xx *chip)
3433 /* default: AMP off, and SPDIF input optical */
3434 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3435 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3440 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3442 static void amp_hercules(struct snd_cs46xx *chip, int change)
3444 int old = chip->amplifier;
3445 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3446 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3448 chip->amplifier += change;
3449 if (chip->amplifier && !old) {
3450 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3452 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3453 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3454 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3455 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3456 } else if (old && !chip->amplifier) {
3457 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3458 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3459 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3463 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3465 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3467 /* Enable SPDIF out */
3468 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3469 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3472 static void hercules_mixer_init (struct snd_cs46xx *chip)
3474 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3477 struct snd_card *card = chip->card;
3480 /* set EGPIO to default */
3481 hercules_init(chip);
3483 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3485 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3486 if (chip->in_suspend)
3489 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3490 struct snd_kcontrol *kctl;
3492 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3493 err = snd_ctl_add(card, kctl);
3496 "failed to initialize Hercules mixer (%d)\n",
3510 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3512 chip->amplifier += change;
3514 if (chip->amplifier) {
3515 /* Switch the GPIO pins 7 and 8 to open drain */
3516 snd_cs46xx_codec_write(chip, 0x4C,
3517 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3518 snd_cs46xx_codec_write(chip, 0x4E,
3519 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3520 /* Now wake the AMP (this might be backwards) */
3521 snd_cs46xx_codec_write(chip, 0x54,
3522 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3524 snd_cs46xx_codec_write(chip, 0x54,
3525 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3532 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3533 * whenever we need to beat on the chip.
3535 * The original idea and code for this hack comes from David Kaiser at
3536 * Linuxcare. Perhaps one day Crystal will document their chips well
3537 * enough to make them useful.
3540 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3544 if (!chip->acpi_port)
3547 chip->amplifier += change;
3549 /* Read ACPI port */
3550 nval = control = inw(chip->acpi_port + 0x10);
3552 /* Flip CLKRUN off while running */
3553 if (! chip->amplifier)
3557 if (nval != control)
3558 outw(nval, chip->acpi_port + 0x10);
3563 * detect intel piix4
3565 static void clkrun_init(struct snd_cs46xx *chip)
3567 struct pci_dev *pdev;
3570 chip->acpi_port = 0;
3572 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3573 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3575 return; /* Not a thinkpad thats for sure */
3577 /* Find the control port */
3578 pci_read_config_byte(pdev, 0x41, &pp);
3579 chip->acpi_port = pp << 8;
3593 void (*init)(struct snd_cs46xx *);
3594 void (*amp)(struct snd_cs46xx *, int);
3595 void (*active)(struct snd_cs46xx *, int);
3596 void (*mixer_init)(struct snd_cs46xx *);
3599 static struct cs_card_type cards[] = {
3603 .name = "Genius Soundmaker 128 value",
3604 /* nothing special */
3611 .mixer_init = voyetra_mixer_init,
3616 .name = "Mitac MI6020/21",
3619 /* Hercules Game Theatre XP */
3621 .vendor = 0x14af, /* Guillemot Corporation */
3623 .name = "Hercules Game Theatre XP",
3624 .amp = amp_hercules,
3625 .mixer_init = hercules_mixer_init,
3630 .name = "Hercules Game Theatre XP",
3631 .amp = amp_hercules,
3632 .mixer_init = hercules_mixer_init,
3637 .name = "Hercules Game Theatre XP",
3638 .amp = amp_hercules,
3639 .mixer_init = hercules_mixer_init,
3645 .name = "Hercules Game Theatre XP",
3646 .amp = amp_hercules,
3647 .mixer_init = hercules_mixer_init,
3652 .name = "Hercules Game Theatre XP",
3653 .amp = amp_hercules,
3654 .mixer_init = hercules_mixer_init,
3659 .name = "Hercules Game Theatre XP",
3660 .amp = amp_hercules,
3661 .mixer_init = hercules_mixer_init,
3663 /* Herculess Fortissimo */
3667 .name = "Hercules Gamesurround Fortissimo II",
3672 .name = "Hercules Gamesurround Fortissimo III 7.1",
3678 .name = "Terratec DMX XFire 1024",
3683 .name = "Terratec SiXPack 5.1",
3685 /* Not sure if the 570 needs the clkrun hack */
3687 .vendor = PCI_VENDOR_ID_IBM,
3689 .name = "Thinkpad 570",
3690 .init = clkrun_init,
3691 .active = clkrun_hack,
3694 .vendor = PCI_VENDOR_ID_IBM,
3696 .name = "Thinkpad 600X/A20/T20",
3697 .init = clkrun_init,
3698 .active = clkrun_hack,
3701 .vendor = PCI_VENDOR_ID_IBM,
3703 .name = "Thinkpad 600E (unsupported)",
3712 #ifdef CONFIG_PM_SLEEP
3713 static const unsigned int saved_regs[] = {
3721 static int snd_cs46xx_suspend(struct device *dev)
3723 struct snd_card *card = dev_get_drvdata(dev);
3724 struct snd_cs46xx *chip = card->private_data;
3727 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3728 chip->in_suspend = 1;
3729 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3730 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3732 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3733 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3735 /* save some registers */
3736 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3737 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3739 amp_saved = chip->amplifier;
3741 chip->amplifier_ctrl(chip, -chip->amplifier);
3742 snd_cs46xx_hw_stop(chip);
3743 /* disable CLKRUN */
3744 chip->active_ctrl(chip, -chip->amplifier);
3745 chip->amplifier = amp_saved; /* restore the status */
3749 static int snd_cs46xx_resume(struct device *dev)
3751 struct snd_card *card = dev_get_drvdata(dev);
3752 struct snd_cs46xx *chip = card->private_data;
3754 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3759 amp_saved = chip->amplifier;
3760 chip->amplifier = 0;
3761 chip->active_ctrl(chip, 1); /* force to on */
3763 snd_cs46xx_chip_init(chip);
3765 snd_cs46xx_reset(chip);
3766 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3767 cs46xx_dsp_resume(chip);
3768 /* restore some registers */
3769 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3770 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3772 snd_cs46xx_download_image(chip);
3776 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3777 chip->ac97_general_purpose);
3778 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3779 chip->ac97_powerdown);
3781 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3782 chip->ac97_powerdown);
3786 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3787 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3792 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3793 chip->capt.ctl = tmp & 0x0000ffff;
3794 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3798 /* reset playback/capture */
3799 snd_cs46xx_set_play_sample_rate(chip, 8000);
3800 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3801 snd_cs46xx_proc_start(chip);
3803 cs46xx_enable_stream_irqs(chip);
3806 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3808 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3809 chip->amplifier = amp_saved;
3810 chip->in_suspend = 0;
3811 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3815 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3816 #endif /* CONFIG_PM_SLEEP */
3822 int snd_cs46xx_create(struct snd_card *card,
3823 struct pci_dev *pci,
3824 int external_amp, int thinkpad)
3826 struct snd_cs46xx *chip = card->private_data;
3828 struct snd_cs46xx_region *region;
3829 struct cs_card_type *cp;
3830 u16 ss_card, ss_vendor;
3832 /* enable PCI device */
3833 err = pcim_enable_device(pci);
3837 spin_lock_init(&chip->reg_lock);
3838 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3839 mutex_init(&chip->spos_mutex);
3845 err = pci_request_regions(pci, "CS46xx");
3848 chip->ba0_addr = pci_resource_start(pci, 0);
3849 chip->ba1_addr = pci_resource_start(pci, 1);
3850 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3851 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3852 dev_err(chip->card->dev,
3853 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3854 chip->ba0_addr, chip->ba1_addr);
3858 region = &chip->region.name.ba0;
3859 strcpy(region->name, "CS46xx_BA0");
3860 region->base = chip->ba0_addr;
3861 region->size = CS46XX_BA0_SIZE;
3863 region = &chip->region.name.data0;
3864 strcpy(region->name, "CS46xx_BA1_data0");
3865 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3866 region->size = CS46XX_BA1_DATA0_SIZE;
3868 region = &chip->region.name.data1;
3869 strcpy(region->name, "CS46xx_BA1_data1");
3870 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3871 region->size = CS46XX_BA1_DATA1_SIZE;
3873 region = &chip->region.name.pmem;
3874 strcpy(region->name, "CS46xx_BA1_pmem");
3875 region->base = chip->ba1_addr + BA1_SP_PMEM;
3876 region->size = CS46XX_BA1_PRG_SIZE;
3878 region = &chip->region.name.reg;
3879 strcpy(region->name, "CS46xx_BA1_reg");
3880 region->base = chip->ba1_addr + BA1_SP_REG;
3881 region->size = CS46XX_BA1_REG_SIZE;
3883 /* set up amp and clkrun hack */
3884 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3885 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3887 for (cp = &cards[0]; cp->name; cp++) {
3888 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3889 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3892 chip->amplifier_ctrl = cp->amp;
3893 chip->active_ctrl = cp->active;
3894 chip->mixer_init = cp->mixer_init;
3903 dev_info(chip->card->dev,
3904 "Crystal EAPD support forced on.\n");
3905 chip->amplifier_ctrl = amp_voyetra;
3909 dev_info(chip->card->dev,
3910 "Activating CLKRUN hack for Thinkpad.\n");
3911 chip->active_ctrl = clkrun_hack;
3915 if (chip->amplifier_ctrl == NULL)
3916 chip->amplifier_ctrl = amp_none;
3917 if (chip->active_ctrl == NULL)
3918 chip->active_ctrl = amp_none;
3920 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3922 pci_set_master(pci);
3924 for (idx = 0; idx < 5; idx++) {
3925 region = &chip->region.idx[idx];
3926 region->remap_addr = devm_ioremap(&pci->dev, region->base,
3928 if (region->remap_addr == NULL) {
3929 dev_err(chip->card->dev,
3930 "%s ioremap problem\n", region->name);
3935 if (devm_request_irq(&pci->dev, pci->irq, snd_cs46xx_interrupt,
3936 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3937 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3940 chip->irq = pci->irq;
3941 card->sync_irq = chip->irq;
3942 card->private_free = snd_cs46xx_free;
3944 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3945 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3946 if (!chip->dsp_spos_instance)
3950 err = snd_cs46xx_chip_init(chip);
3954 snd_cs46xx_proc_init(card, chip);
3956 #ifdef CONFIG_PM_SLEEP
3957 chip->saved_regs = devm_kmalloc_array(&pci->dev,
3958 ARRAY_SIZE(saved_regs),
3959 sizeof(*chip->saved_regs),
3961 if (!chip->saved_regs)
3965 chip->active_ctrl(chip, -1); /* disable CLKRUN */