drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc/inc/core_types.h"
  32 #include "dal_asic_id.h"
  33
  34 #include "vid.h"
  35 #include "amdgpu.h"
  36 #include "amdgpu_display.h"
  37 #include "amdgpu_ucode.h"
  38 #include "atom.h"
  39 #include "amdgpu_dm.h"
  40 #ifdef CONFIG_DRM_AMD_DC_HDCP
  41 #include "amdgpu_dm_hdcp.h"
  42 #endif
  43 #include "amdgpu_pm.h"
  44
  45 #include "amd_shared.h"
  46 #include "amdgpu_dm_irq.h"
  47 #include "dm_helpers.h"
  48 #include "amdgpu_dm_mst_types.h"
  49 #if defined(CONFIG_DEBUG_FS)
  50 #include "amdgpu_dm_debugfs.h"
  51 #endif
  52
  53 #include "ivsrcid/ivsrcid_vislands30.h"
  54
  55 #include <linux/module.h>
  56 #include <linux/moduleparam.h>
  57 #include <linux/version.h>
  58 #include <linux/types.h>
  59 #include <linux/pm_runtime.h>
  60 #include <linux/pci.h>
  61 #include <linux/firmware.h>
  62 #include <linux/component.h>
  63
  64 #include <drm/drm_atomic.h>
  65 #include <drm/drm_atomic_uapi.h>
  66 #include <drm/drm_atomic_helper.h>
  67 #include <drm/drm_dp_mst_helper.h>
  68 #include <drm/drm_fb_helper.h>
  69 #include <drm/drm_fourcc.h>
  70 #include <drm/drm_edid.h>
  71 #include <drm/drm_vblank.h>
  72 #include <drm/drm_audio_component.h>
  73 #include <drm/drm_hdcp.h>
  74
  75 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  76 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  77
  78 #include "dcn/dcn_1_0_offset.h"
  79 #include "dcn/dcn_1_0_sh_mask.h"
  80 #include "soc15_hw_ip.h"
  81 #include "vega10_ip_offset.h"
  82
  83 #include "soc15_common.h"
  84 #endif
  85
  86 #include "modules/inc/mod_freesync.h"
  87 #include "modules/power/power_helpers.h"
  88 #include "modules/inc/mod_info_packet.h"
  89
  90 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
  91 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
  92
  93 /**
  94  * DOC: overview
  95  *
  96  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
  97  * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
  98  * requests into DC requests, and DC responses into DRM responses.
  99  *
 100  * The root control structure is &struct amdgpu_display_manager.
 101  */
 102
 103 /* basic init/fini API */
 104 static int amdgpu_dm_init(struct amdgpu_device *adev);
 105 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 106
 107 /*
 108  * initializes drm_device display related structures, based on the information
 109  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 110  * drm_encoder, drm_mode_config
 111  *
 112  * Returns 0 on success
 113  */
 114 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 115 /* removes and deallocates the drm structures, created by the above function */
 116 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 117
 118 static void
 119 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
 120
 121 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 122                                 struct drm_plane *plane,
 123                                 unsigned long possible_crtcs,
 124                                 const struct dc_plane_cap *plane_cap);
 125 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 126                                struct drm_plane *plane,
 127                                uint32_t link_index);
 128 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 129                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 130                                     uint32_t link_index,
 131                                     struct amdgpu_encoder *amdgpu_encoder);
 132 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 133                                   struct amdgpu_encoder *aencoder,
 134                                   uint32_t link_index);
 135
 136 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 137
 138 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 139                                    struct drm_atomic_state *state,
 140                                    bool nonblock);
 141
 142 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 143
 144 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 145                                   struct drm_atomic_state *state);
 146
 147 static void handle_cursor_update(struct drm_plane *plane,
 148                                  struct drm_plane_state *old_plane_state);
 149
 150 /*
 151  * dm_vblank_get_counter
 152  *
 153  * @brief
 154  * Get counter for number of vertical blanks
 155  *
 156  * @param
 157  * struct amdgpu_device *adev - [in] desired amdgpu device
 158  * int disp_idx - [in] which CRTC to get the counter from
 159  *
 160  * @return
 161  * Counter for vertical blanks
 162  */
 163 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 164 {
 165         if (crtc >= adev->mode_info.num_crtc)
 166                 return 0;
 167         else {
 168                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 169                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 170                                 acrtc->base.state);
 171
 172
 173                 if (acrtc_state->stream == NULL) {
 174                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 175                                   crtc);
 176                         return 0;
 177                 }
 178
 179                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 180         }
 181 }
 182
 183 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 184                                   u32 *vbl, u32 *position)
 185 {
 186         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 187
 188         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 189                 return -EINVAL;
 190         else {
 191                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 192                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 193                                                 acrtc->base.state);
 194
 195                 if (acrtc_state->stream ==  NULL) {
 196                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 197                                   crtc);
 198                         return 0;
 199                 }
 200
 201                 /*
 202                  * TODO rework base driver to use values directly.
 203                  * for now parse it back into reg-format
 204                  */
 205                 dc_stream_get_scanoutpos(acrtc_state->stream,
 206                                          &v_blank_start,
 207                                          &v_blank_end,
 208                                          &h_position,
 209                                          &v_position);
 210
 211                 *position = v_position | (h_position << 16);
 212                 *vbl = v_blank_start | (v_blank_end << 16);
 213         }
 214
 215         return 0;
 216 }
 217
 218 static bool dm_is_idle(void *handle)
 219 {
 220         /* XXX todo */
 221         return true;
 222 }
 223
 224 static int dm_wait_for_idle(void *handle)
 225 {
 226         /* XXX todo */
 227         return 0;
 228 }
 229
 230 static bool dm_check_soft_reset(void *handle)
 231 {
 232         return false;
 233 }
 234
 235 static int dm_soft_reset(void *handle)
 236 {
 237         /* XXX todo */
 238         return 0;
 239 }
 240
 241 static struct amdgpu_crtc *
 242 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 243                      int otg_inst)
 244 {
 245         struct drm_device *dev = adev->ddev;
 246         struct drm_crtc *crtc;
 247         struct amdgpu_crtc *amdgpu_crtc;
 248
 249         if (otg_inst == -1) {
 250                 WARN_ON(1);
 251                 return adev->mode_info.crtcs[0];
 252         }
 253
 254         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 255                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 256
 257                 if (amdgpu_crtc->otg_inst == otg_inst)
 258                         return amdgpu_crtc;
 259         }
 260
 261         return NULL;
 262 }
 263
 264 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
 265 {
 266         return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
 267                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 268 }
 269
 270 /**
 271  * dm_pflip_high_irq() - Handle pageflip interrupt
 272  * @interrupt_params: ignored
 273  *
 274  * Handles the pageflip interrupt by notifying all interested parties
 275  * that the pageflip has been completed.
 276  */
 277 static void dm_pflip_high_irq(void *interrupt_params)
 278 {
 279         struct amdgpu_crtc *amdgpu_crtc;
 280         struct common_irq_params *irq_params = interrupt_params;
 281         struct amdgpu_device *adev = irq_params->adev;
 282         unsigned long flags;
 283         struct drm_pending_vblank_event *e;
 284         struct dm_crtc_state *acrtc_state;
 285         uint32_t vpos, hpos, v_blank_start, v_blank_end;
 286         bool vrr_active;
 287
 288         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 289
 290         /* IRQ could occur when in initial stage */
 291         /* TODO work and BO cleanup */
 292         if (amdgpu_crtc == NULL) {
 293                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 294                 return;
 295         }
 296
 297         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 298
 299         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 300                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 301                                                  amdgpu_crtc->pflip_status,
 302                                                  AMDGPU_FLIP_SUBMITTED,
 303                                                  amdgpu_crtc->crtc_id,
 304                                                  amdgpu_crtc);
 305                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 306                 return;
 307         }
 308
 309         /* page flip completed. */
 310         e = amdgpu_crtc->event;
 311         amdgpu_crtc->event = NULL;
 312
 313         if (!e)
 314                 WARN_ON(1);
 315
 316         acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
 317         vrr_active = amdgpu_dm_vrr_active(acrtc_state);
 318
 319         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 320         if (!vrr_active ||
 321             !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
 322                                       &v_blank_end, &hpos, &vpos) ||
 323             (vpos < v_blank_start)) {
 324                 /* Update to correct count and vblank timestamp if racing with
 325                  * vblank irq. This also updates to the correct vblank timestamp
 326                  * even in VRR mode, as scanout is past the front-porch atm.
 327                  */
 328                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 329
 330                 /* Wake up userspace by sending the pageflip event with proper
 331                  * count and timestamp of vblank of flip completion.
 332                  */
 333                 if (e) {
 334                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 335
 336                         /* Event sent, so done with vblank for this flip */
 337                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 338                 }
 339         } else if (e) {
 340                 /* VRR active and inside front-porch: vblank count and
 341                  * timestamp for pageflip event will only be up to date after
 342                  * drm_crtc_handle_vblank() has been executed from late vblank
 343                  * irq handler after start of back-porch (vline 0). We queue the
 344                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 345                  * updated timestamp and count, once it runs after us.
 346                  *
 347                  * We need to open-code this instead of using the helper
 348                  * drm_crtc_arm_vblank_event(), as that helper would
 349                  * call drm_crtc_accurate_vblank_count(), which we must
 350                  * not call in VRR mode while we are in front-porch!
 351                  */
 352
 353                 /* sequence will be replaced by real count during send-out. */
 354                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 355                 e->pipe = amdgpu_crtc->crtc_id;
 356
 357                 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
 358                 e = NULL;
 359         }
 360
 361         /* Keep track of vblank of this flip for flip throttling. We use the
 362          * cooked hw counter, as that one incremented at start of this vblank
 363          * of pageflip completion, so last_flip_vblank is the forbidden count
 364          * for queueing new pageflips if vsync + VRR is enabled.
 365          */
 366         amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
 367                                                         amdgpu_crtc->crtc_id);
 368
 369         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 370         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 371
 372         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 373                          amdgpu_crtc->crtc_id, amdgpu_crtc,
 374                          vrr_active, (int) !e);
 375 }
 376
 377 static void dm_vupdate_high_irq(void *interrupt_params)
 378 {
 379         struct common_irq_params *irq_params = interrupt_params;
 380         struct amdgpu_device *adev = irq_params->adev;
 381         struct amdgpu_crtc *acrtc;
 382         struct dm_crtc_state *acrtc_state;
 383         unsigned long flags;
 384
 385         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 386
 387         if (acrtc) {
 388                 acrtc_state = to_dm_crtc_state(acrtc->base.state);
 389
 390                 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 391                                  amdgpu_dm_vrr_active(acrtc_state));
 392
 393                 /* Core vblank handling is done here after end of front-porch in
 394                  * vrr mode, as vblank timestamping will give valid results
 395                  * while now done after front-porch. This will also deliver
 396                  * page-flip completion events that have been queued to us
 397                  * if a pageflip happened inside front-porch.
 398                  */
 399                 if (amdgpu_dm_vrr_active(acrtc_state)) {
 400                         drm_crtc_handle_vblank(&acrtc->base);
 401
 402                         /* BTR processing for pre-DCE12 ASICs */
 403                         if (acrtc_state->stream &&
 404                             adev->family < AMDGPU_FAMILY_AI) {
 405                                 spin_lock_irqsave(&adev->ddev->event_lock, flags);
 406                                 mod_freesync_handle_v_update(
 407                                     adev->dm.freesync_module,
 408                                     acrtc_state->stream,
 409                                     &acrtc_state->vrr_params);
 410
 411                                 dc_stream_adjust_vmin_vmax(
 412                                     adev->dm.dc,
 413                                     acrtc_state->stream,
 414                                     &acrtc_state->vrr_params.adjust);
 415                                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 416                         }
 417                 }
 418         }
 419 }
 420
 421 /**
 422  * dm_crtc_high_irq() - Handles CRTC interrupt
 423  * @interrupt_params: ignored
 424  *
 425  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 426  * event handler.
 427  */
 428 static void dm_crtc_high_irq(void *interrupt_params)
 429 {
 430         struct common_irq_params *irq_params = interrupt_params;
 431         struct amdgpu_device *adev = irq_params->adev;
 432         struct amdgpu_crtc *acrtc;
 433         struct dm_crtc_state *acrtc_state;
 434         unsigned long flags;
 435
 436         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 437
 438         if (acrtc) {
 439                 acrtc_state = to_dm_crtc_state(acrtc->base.state);
 440
 441                 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 442                                  amdgpu_dm_vrr_active(acrtc_state));
 443
 444                 /* Core vblank handling at start of front-porch is only possible
 445                  * in non-vrr mode, as only there vblank timestamping will give
 446                  * valid results while done in front-porch. Otherwise defer it
 447                  * to dm_vupdate_high_irq after end of front-porch.
 448                  */
 449                 if (!amdgpu_dm_vrr_active(acrtc_state))
 450                         drm_crtc_handle_vblank(&acrtc->base);
 451
 452                 /* Following stuff must happen at start of vblank, for crc
 453                  * computation and below-the-range btr support in vrr mode.
 454                  */
 455                 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 456
 457                 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
 458                     acrtc_state->vrr_params.supported &&
 459                     acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
 460                         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 461                         mod_freesync_handle_v_update(
 462                                 adev->dm.freesync_module,
 463                                 acrtc_state->stream,
 464                                 &acrtc_state->vrr_params);
 465
 466                         dc_stream_adjust_vmin_vmax(
 467                                 adev->dm.dc,
 468                                 acrtc_state->stream,
 469                                 &acrtc_state->vrr_params.adjust);
 470                         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 471                 }
 472         }
 473 }
 474
 475 static int dm_set_clockgating_state(void *handle,
 476                   enum amd_clockgating_state state)
 477 {
 478         return 0;
 479 }
 480
 481 static int dm_set_powergating_state(void *handle,
 482                   enum amd_powergating_state state)
 483 {
 484         return 0;
 485 }
 486
 487 /* Prototypes of private functions */
 488 static int dm_early_init(void* handle);
 489
 490 /* Allocate memory for FBC compressed data  */
 491 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 492 {
 493         struct drm_device *dev = connector->dev;
 494         struct amdgpu_device *adev = dev->dev_private;
 495         struct dm_comressor_info *compressor = &adev->dm.compressor;
 496         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 497         struct drm_display_mode *mode;
 498         unsigned long max_size = 0;
 499
 500         if (adev->dm.dc->fbc_compressor == NULL)
 501                 return;
 502
 503         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 504                 return;
 505
 506         if (compressor->bo_ptr)
 507                 return;
 508
 509
 510         list_for_each_entry(mode, &connector->modes, head) {
 511                 if (max_size < mode->htotal * mode->vtotal)
 512                         max_size = mode->htotal * mode->vtotal;
 513         }
 514
 515         if (max_size) {
 516                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 517                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 518                             &compressor->gpu_addr, &compressor->cpu_addr);
 519
 520                 if (r)
 521                         DRM_ERROR("DM: Failed to initialize FBC\n");
 522                 else {
 523                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 524                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 525                 }
 526
 527         }
 528
 529 }
 530
 531 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 532                                           int pipe, bool *enabled,
 533                                           unsigned char *buf, int max_bytes)
 534 {
 535         struct drm_device *dev = dev_get_drvdata(kdev);
 536         struct amdgpu_device *adev = dev->dev_private;
 537         struct drm_connector *connector;
 538         struct drm_connector_list_iter conn_iter;
 539         struct amdgpu_dm_connector *aconnector;
 540         int ret = 0;
 541
 542         *enabled = false;
 543
 544         mutex_lock(&adev->dm.audio_lock);
 545
 546         drm_connector_list_iter_begin(dev, &conn_iter);
 547         drm_for_each_connector_iter(connector, &conn_iter) {
 548                 aconnector = to_amdgpu_dm_connector(connector);
 549                 if (aconnector->audio_inst != port)
 550                         continue;
 551
 552                 *enabled = true;
 553                 ret = drm_eld_size(connector->eld);
 554                 memcpy(buf, connector->eld, min(max_bytes, ret));
 555
 556                 break;
 557         }
 558         drm_connector_list_iter_end(&conn_iter);
 559
 560         mutex_unlock(&adev->dm.audio_lock);
 561
 562         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 563
 564         return ret;
 565 }
 566
 567 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 568         .get_eld = amdgpu_dm_audio_component_get_eld,
 569 };
 570
 571 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 572                                        struct device *hda_kdev, void *data)
 573 {
 574         struct drm_device *dev = dev_get_drvdata(kdev);
 575         struct amdgpu_device *adev = dev->dev_private;
 576         struct drm_audio_component *acomp = data;
 577
 578         acomp->ops = &amdgpu_dm_audio_component_ops;
 579         acomp->dev = kdev;
 580         adev->dm.audio_component = acomp;
 581
 582         return 0;
 583 }
 584
 585 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 586                                           struct device *hda_kdev, void *data)
 587 {
 588         struct drm_device *dev = dev_get_drvdata(kdev);
 589         struct amdgpu_device *adev = dev->dev_private;
 590         struct drm_audio_component *acomp = data;
 591
 592         acomp->ops = NULL;
 593         acomp->dev = NULL;
 594         adev->dm.audio_component = NULL;
 595 }
 596
 597 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 598         .bind   = amdgpu_dm_audio_component_bind,
 599         .unbind = amdgpu_dm_audio_component_unbind,
 600 };
 601
 602 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 603 {
 604         int i, ret;
 605
 606         if (!amdgpu_audio)
 607                 return 0;
 608
 609         adev->mode_info.audio.enabled = true;
 610
 611         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 612
 613         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 614                 adev->mode_info.audio.pin[i].channels = -1;
 615                 adev->mode_info.audio.pin[i].rate = -1;
 616                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
 617                 adev->mode_info.audio.pin[i].status_bits = 0;
 618                 adev->mode_info.audio.pin[i].category_code = 0;
 619                 adev->mode_info.audio.pin[i].connected = false;
 620                 adev->mode_info.audio.pin[i].id =
 621                         adev->dm.dc->res_pool->audios[i]->inst;
 622                 adev->mode_info.audio.pin[i].offset = 0;
 623         }
 624
 625         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 626         if (ret < 0)
 627                 return ret;
 628
 629         adev->dm.audio_registered = true;
 630
 631         return 0;
 632 }
 633
 634 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
 635 {
 636         if (!amdgpu_audio)
 637                 return;
 638
 639         if (!adev->mode_info.audio.enabled)
 640                 return;
 641
 642         if (adev->dm.audio_registered) {
 643                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 644                 adev->dm.audio_registered = false;
 645         }
 646
 647         /* TODO: Disable audio? */
 648
 649         adev->mode_info.audio.enabled = false;
 650 }
 651
 652 void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
 653 {
 654         struct drm_audio_component *acomp = adev->dm.audio_component;
 655
 656         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
 657                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
 658
 659                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 660                                                  pin, -1);
 661         }
 662 }
 663
 664 static int amdgpu_dm_init(struct amdgpu_device *adev)
 665 {
 666         struct dc_init_data init_data;
 667 #ifdef CONFIG_DRM_AMD_DC_HDCP
 668         struct dc_callback_init init_params;
 669 #endif
 670
 671         adev->dm.ddev = adev->ddev;
 672         adev->dm.adev = adev;
 673
 674         /* Zero all the fields */
 675         memset(&init_data, 0, sizeof(init_data));
 676 #ifdef CONFIG_DRM_AMD_DC_HDCP
 677         memset(&init_params, 0, sizeof(init_params));
 678 #endif
 679
 680         mutex_init(&adev->dm.dc_lock);
 681         mutex_init(&adev->dm.audio_lock);
 682
 683         if(amdgpu_dm_irq_init(adev)) {
 684                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 685                 goto error;
 686         }
 687
 688         init_data.asic_id.chip_family = adev->family;
 689
 690         init_data.asic_id.pci_revision_id = adev->rev_id;
 691         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 692
 693         init_data.asic_id.vram_width = adev->gmc.vram_width;
 694         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 695         init_data.asic_id.atombios_base_address =
 696                 adev->mode_info.atom_context->bios;
 697
 698         init_data.driver = adev;
 699
 700         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 701
 702         if (!adev->dm.cgs_device) {
 703                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 704                 goto error;
 705         }
 706
 707         init_data.cgs_device = adev->dm.cgs_device;
 708
 709         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 710
 711         /*
 712          * TODO debug why this doesn't work on Raven
 713          */
 714         if (adev->flags & AMD_IS_APU &&
 715             adev->asic_type >= CHIP_CARRIZO &&
 716             adev->asic_type <= CHIP_RAVEN)
 717                 init_data.flags.gpu_vm_support = true;
 718
 719         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
 720                 init_data.flags.fbc_support = true;
 721
 722         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
 723                 init_data.flags.multi_mon_pp_mclk_switch = true;
 724
 725         init_data.flags.power_down_display_on_boot = true;
 726
 727 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 728         init_data.soc_bounding_box = adev->dm.soc_bounding_box;
 729 #endif
 730
 731         /* Display Core create. */
 732         adev->dm.dc = dc_create(&init_data);
 733
 734         if (adev->dm.dc) {
 735                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 736         } else {
 737                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 738                 goto error;
 739         }
 740
 741         dc_hardware_init(adev->dm.dc);
 742
 743         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 744         if (!adev->dm.freesync_module) {
 745                 DRM_ERROR(
 746                 "amdgpu: failed to initialize freesync_module.\n");
 747         } else
 748                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 749                                 adev->dm.freesync_module);
 750
 751         amdgpu_dm_init_color_mod();
 752
 753 #ifdef CONFIG_DRM_AMD_DC_HDCP
 754         if (adev->asic_type >= CHIP_RAVEN) {
 755                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc);
 756
 757                 if (!adev->dm.hdcp_workqueue)
 758                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
 759                 else
 760                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
 761
 762                 dc_init_callbacks(adev->dm.dc, &init_params);
 763         }
 764 #endif
 765         if (amdgpu_dm_initialize_drm_device(adev)) {
 766                 DRM_ERROR(
 767                 "amdgpu: failed to initialize sw for display support.\n");
 768                 goto error;
 769         }
 770
 771         /* Update the actual used number of crtc */
 772         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 773
 774         /* TODO: Add_display_info? */
 775
 776         /* TODO use dynamic cursor width */
 777         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 778         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 779
 780         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 781                 DRM_ERROR(
 782                 "amdgpu: failed to initialize sw for display support.\n");
 783                 goto error;
 784         }
 785
 786 #if defined(CONFIG_DEBUG_FS)
 787         if (dtn_debugfs_init(adev))
 788                 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
 789 #endif
 790
 791         DRM_DEBUG_DRIVER("KMS initialized.\n");
 792
 793         return 0;
 794 error:
 795         amdgpu_dm_fini(adev);
 796
 797         return -EINVAL;
 798 }
 799
 800 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 801 {
 802         amdgpu_dm_audio_fini(adev);
 803
 804         amdgpu_dm_destroy_drm_device(&adev->dm);
 805
 806 #ifdef CONFIG_DRM_AMD_DC_HDCP
 807         if (adev->dm.hdcp_workqueue) {
 808                 hdcp_destroy(adev->dm.hdcp_workqueue);
 809                 adev->dm.hdcp_workqueue = NULL;
 810         }
 811
 812         if (adev->dm.dc)
 813                 dc_deinit_callbacks(adev->dm.dc);
 814 #endif
 815
 816         /* DC Destroy TODO: Replace destroy DAL */
 817         if (adev->dm.dc)
 818                 dc_destroy(&adev->dm.dc);
 819         /*
 820          * TODO: pageflip, vlank interrupt
 821          *
 822          * amdgpu_dm_irq_fini(adev);
 823          */
 824
 825         if (adev->dm.cgs_device) {
 826                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 827                 adev->dm.cgs_device = NULL;
 828         }
 829         if (adev->dm.freesync_module) {
 830                 mod_freesync_destroy(adev->dm.freesync_module);
 831                 adev->dm.freesync_module = NULL;
 832         }
 833
 834         mutex_destroy(&adev->dm.audio_lock);
 835         mutex_destroy(&adev->dm.dc_lock);
 836
 837         return;
 838 }
 839
 840 static int load_dmcu_fw(struct amdgpu_device *adev)
 841 {
 842         const char *fw_name_dmcu = NULL;
 843         int r;
 844         const struct dmcu_firmware_header_v1_0 *hdr;
 845
 846         switch(adev->asic_type) {
 847         case CHIP_BONAIRE:
 848         case CHIP_HAWAII:
 849         case CHIP_KAVERI:
 850         case CHIP_KABINI:
 851         case CHIP_MULLINS:
 852         case CHIP_TONGA:
 853         case CHIP_FIJI:
 854         case CHIP_CARRIZO:
 855         case CHIP_STONEY:
 856         case CHIP_POLARIS11:
 857         case CHIP_POLARIS10:
 858         case CHIP_POLARIS12:
 859         case CHIP_VEGAM:
 860         case CHIP_VEGA10:
 861         case CHIP_VEGA12:
 862         case CHIP_VEGA20:
 863         case CHIP_NAVI10:
 864         case CHIP_NAVI14:
 865         case CHIP_NAVI12:
 866         case CHIP_RENOIR:
 867                 return 0;
 868         case CHIP_RAVEN:
 869                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
 870                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 871                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
 872                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 873                 else
 874                         return 0;
 875                 break;
 876         default:
 877                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
 878                 return -EINVAL;
 879         }
 880
 881         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 882                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
 883                 return 0;
 884         }
 885
 886         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
 887         if (r == -ENOENT) {
 888                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
 889                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
 890                 adev->dm.fw_dmcu = NULL;
 891                 return 0;
 892         }
 893         if (r) {
 894                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
 895                         fw_name_dmcu);
 896                 return r;
 897         }
 898
 899         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
 900         if (r) {
 901                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
 902                         fw_name_dmcu);
 903                 release_firmware(adev->dm.fw_dmcu);
 904                 adev->dm.fw_dmcu = NULL;
 905                 return r;
 906         }
 907
 908         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
 909         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
 910         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
 911         adev->firmware.fw_size +=
 912                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 913
 914         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
 915         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
 916         adev->firmware.fw_size +=
 917                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 918
 919         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
 920
 921         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
 922
 923         return 0;
 924 }
 925
 926 static int dm_sw_init(void *handle)
 927 {
 928         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 929
 930         return load_dmcu_fw(adev);
 931 }
 932
 933 static int dm_sw_fini(void *handle)
 934 {
 935         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 936
 937         if(adev->dm.fw_dmcu) {
 938                 release_firmware(adev->dm.fw_dmcu);
 939                 adev->dm.fw_dmcu = NULL;
 940         }
 941
 942         return 0;
 943 }
 944
 945 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 946 {
 947         struct amdgpu_dm_connector *aconnector;
 948         struct drm_connector *connector;
 949         struct drm_connector_list_iter iter;
 950         int ret = 0;
 951
 952         drm_connector_list_iter_begin(dev, &iter);
 953         drm_for_each_connector_iter(connector, &iter) {
 954                 aconnector = to_amdgpu_dm_connector(connector);
 955                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
 956                     aconnector->mst_mgr.aux) {
 957                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 958                                          aconnector,
 959                                          aconnector->base.base.id);
 960
 961                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 962                         if (ret < 0) {
 963                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 964                                 aconnector->dc_link->type =
 965                                         dc_connection_single;
 966                                 break;
 967                         }
 968                 }
 969         }
 970         drm_connector_list_iter_end(&iter);
 971
 972         return ret;
 973 }
 974
 975 static int dm_late_init(void *handle)
 976 {
 977         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 978
 979         struct dmcu_iram_parameters params;
 980         unsigned int linear_lut[16];
 981         int i;
 982         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
 983         bool ret = false;
 984
 985         for (i = 0; i < 16; i++)
 986                 linear_lut[i] = 0xFFFF * i / 15;
 987
 988         params.set = 0;
 989         params.backlight_ramping_start = 0xCCCC;
 990         params.backlight_ramping_reduction = 0xCCCCCCCC;
 991         params.backlight_lut_array_size = 16;
 992         params.backlight_lut_array = linear_lut;
 993
 994         /* Min backlight level after ABM reduction,  Don't allow below 1%
 995          * 0xFFFF x 0.01 = 0x28F
 996          */
 997         params.min_abm_backlight = 0x28F;
 998
 999         /* todo will enable for navi10 */
1000         if (adev->asic_type <= CHIP_RAVEN) {
1001                 ret = dmcu_load_iram(dmcu, params);
1002
1003                 if (!ret)
1004                         return -EINVAL;
1005         }
1006
1007         return detect_mst_link_for_all_connectors(adev->ddev);
1008 }
1009
1010 static void s3_handle_mst(struct drm_device *dev, bool suspend)
1011 {
1012         struct amdgpu_dm_connector *aconnector;
1013         struct drm_connector *connector;
1014         struct drm_connector_list_iter iter;
1015         struct drm_dp_mst_topology_mgr *mgr;
1016         int ret;
1017         bool need_hotplug = false;
1018
1019         drm_connector_list_iter_begin(dev, &iter);
1020         drm_for_each_connector_iter(connector, &iter) {
1021                 aconnector = to_amdgpu_dm_connector(connector);
1022                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
1023                     aconnector->mst_port)
1024                         continue;
1025
1026                 mgr = &aconnector->mst_mgr;
1027
1028                 if (suspend) {
1029                         drm_dp_mst_topology_mgr_suspend(mgr);
1030                 } else {
1031                         ret = drm_dp_mst_topology_mgr_resume(mgr);
1032                         if (ret < 0) {
1033                                 drm_dp_mst_topology_mgr_set_mst(mgr, false);
1034                                 need_hotplug = true;
1035                         }
1036                 }
1037         }
1038         drm_connector_list_iter_end(&iter);
1039
1040         if (need_hotplug)
1041                 drm_kms_helper_hotplug_event(dev);
1042 }
1043
1044 /**
1045  * dm_hw_init() - Initialize DC device
1046  * @handle: The base driver device containing the amdgpu_dm device.
1047  *
1048  * Initialize the &struct amdgpu_display_manager device. This involves calling
1049  * the initializers of each DM component, then populating the struct with them.
1050  *
1051  * Although the function implies hardware initialization, both hardware and
1052  * software are initialized here. Splitting them out to their relevant init
1053  * hooks is a future TODO item.
1054  *
1055  * Some notable things that are initialized here:
1056  *
1057  * - Display Core, both software and hardware
1058  * - DC modules that we need (freesync and color management)
1059  * - DRM software states
1060  * - Interrupt sources and handlers
1061  * - Vblank support
1062  * - Debug FS entries, if enabled
1063  */
1064 static int dm_hw_init(void *handle)
1065 {
1066         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1067         /* Create DAL display manager */
1068         amdgpu_dm_init(adev);
1069         amdgpu_dm_hpd_init(adev);
1070
1071         return 0;
1072 }
1073
1074 /**
1075  * dm_hw_fini() - Teardown DC device
1076  * @handle: The base driver device containing the amdgpu_dm device.
1077  *
1078  * Teardown components within &struct amdgpu_display_manager that require
1079  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1080  * were loaded. Also flush IRQ workqueues and disable them.
1081  */
1082 static int dm_hw_fini(void *handle)
1083 {
1084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086         amdgpu_dm_hpd_fini(adev);
1087
1088         amdgpu_dm_irq_fini(adev);
1089         amdgpu_dm_fini(adev);
1090         return 0;
1091 }
1092
1093 static int dm_suspend(void *handle)
1094 {
1095         struct amdgpu_device *adev = handle;
1096         struct amdgpu_display_manager *dm = &adev->dm;
1097         int ret = 0;
1098
1099         WARN_ON(adev->dm.cached_state);
1100         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
1101
1102         s3_handle_mst(adev->ddev, true);
1103
1104         amdgpu_dm_irq_suspend(adev);
1105
1106
1107         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1108
1109         return ret;
1110 }
1111
1112 static struct amdgpu_dm_connector *
1113 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1114                                              struct drm_crtc *crtc)
1115 {
1116         uint32_t i;
1117         struct drm_connector_state *new_con_state;
1118         struct drm_connector *connector;
1119         struct drm_crtc *crtc_from_state;
1120
1121         for_each_new_connector_in_state(state, connector, new_con_state, i) {
1122                 crtc_from_state = new_con_state->crtc;
1123
1124                 if (crtc_from_state == crtc)
1125                         return to_amdgpu_dm_connector(connector);
1126         }
1127
1128         return NULL;
1129 }
1130
1131 static void emulated_link_detect(struct dc_link *link)
1132 {
1133         struct dc_sink_init_data sink_init_data = { 0 };
1134         struct display_sink_capability sink_caps = { 0 };
1135         enum dc_edid_status edid_status;
1136         struct dc_context *dc_ctx = link->ctx;
1137         struct dc_sink *sink = NULL;
1138         struct dc_sink *prev_sink = NULL;
1139
1140         link->type = dc_connection_none;
1141         prev_sink = link->local_sink;
1142
1143         if (prev_sink != NULL)
1144                 dc_sink_retain(prev_sink);
1145
1146         switch (link->connector_signal) {
1147         case SIGNAL_TYPE_HDMI_TYPE_A: {
1148                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1149                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1150                 break;
1151         }
1152
1153         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1154                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1155                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1156                 break;
1157         }
1158
1159         case SIGNAL_TYPE_DVI_DUAL_LINK: {
1160                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1161                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1162                 break;
1163         }
1164
1165         case SIGNAL_TYPE_LVDS: {
1166                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1167                 sink_caps.signal = SIGNAL_TYPE_LVDS;
1168                 break;
1169         }
1170
1171         case SIGNAL_TYPE_EDP: {
1172                 sink_caps.transaction_type =
1173                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1174                 sink_caps.signal = SIGNAL_TYPE_EDP;
1175                 break;
1176         }
1177
1178         case SIGNAL_TYPE_DISPLAY_PORT: {
1179                 sink_caps.transaction_type =
1180                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1181                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1182                 break;
1183         }
1184
1185         default:
1186                 DC_ERROR("Invalid connector type! signal:%d\n",
1187                         link->connector_signal);
1188                 return;
1189         }
1190
1191         sink_init_data.link = link;
1192         sink_init_data.sink_signal = sink_caps.signal;
1193
1194         sink = dc_sink_create(&sink_init_data);
1195         if (!sink) {
1196                 DC_ERROR("Failed to create sink!\n");
1197                 return;
1198         }
1199
1200         /* dc_sink_create returns a new reference */
1201         link->local_sink = sink;
1202
1203         edid_status = dm_helpers_read_local_edid(
1204                         link->ctx,
1205                         link,
1206                         sink);
1207
1208         if (edid_status != EDID_OK)
1209                 DC_ERROR("Failed to read EDID");
1210
1211 }
1212
1213 static int dm_resume(void *handle)
1214 {
1215         struct amdgpu_device *adev = handle;
1216         struct drm_device *ddev = adev->ddev;
1217         struct amdgpu_display_manager *dm = &adev->dm;
1218         struct amdgpu_dm_connector *aconnector;
1219         struct drm_connector *connector;
1220         struct drm_connector_list_iter iter;
1221         struct drm_crtc *crtc;
1222         struct drm_crtc_state *new_crtc_state;
1223         struct dm_crtc_state *dm_new_crtc_state;
1224         struct drm_plane *plane;
1225         struct drm_plane_state *new_plane_state;
1226         struct dm_plane_state *dm_new_plane_state;
1227         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
1228         enum dc_connection_type new_connection_type = dc_connection_none;
1229         int i;
1230
1231         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1232         dc_release_state(dm_state->context);
1233         dm_state->context = dc_create_state(dm->dc);
1234         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1235         dc_resource_state_construct(dm->dc, dm_state->context);
1236
1237         /* power on hardware */
1238         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1239
1240         /* program HPD filter */
1241         dc_resume(dm->dc);
1242
1243         /*
1244          * early enable HPD Rx IRQ, should be done before set mode as short
1245          * pulse interrupts are used for MST
1246          */
1247         amdgpu_dm_irq_resume_early(adev);
1248
1249         /* On resume we need to  rewrite the MSTM control bits to enable MST*/
1250         s3_handle_mst(ddev, false);
1251
1252         /* Do detection*/
1253         drm_connector_list_iter_begin(ddev, &iter);
1254         drm_for_each_connector_iter(connector, &iter) {
1255                 aconnector = to_amdgpu_dm_connector(connector);
1256
1257                 /*
1258                  * this is the case when traversing through already created
1259                  * MST connectors, should be skipped
1260                  */
1261                 if (aconnector->mst_port)
1262                         continue;
1263
1264                 mutex_lock(&aconnector->hpd_lock);
1265                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1266                         DRM_ERROR("KMS: Failed to detect connector\n");
1267
1268                 if (aconnector->base.force && new_connection_type == dc_connection_none)
1269                         emulated_link_detect(aconnector->dc_link);
1270                 else
1271                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1272
1273                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1274                         aconnector->fake_enable = false;
1275
1276                 if (aconnector->dc_sink)
1277                         dc_sink_release(aconnector->dc_sink);
1278                 aconnector->dc_sink = NULL;
1279                 amdgpu_dm_update_connector_after_detect(aconnector);
1280                 mutex_unlock(&aconnector->hpd_lock);
1281         }
1282         drm_connector_list_iter_end(&iter);
1283
1284         /* Force mode set in atomic commit */
1285         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
1286                 new_crtc_state->active_changed = true;
1287
1288         /*
1289          * atomic_check is expected to create the dc states. We need to release
1290          * them here, since they were duplicated as part of the suspend
1291          * procedure.
1292          */
1293         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
1294                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1295                 if (dm_new_crtc_state->stream) {
1296                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1297                         dc_stream_release(dm_new_crtc_state->stream);
1298                         dm_new_crtc_state->stream = NULL;
1299                 }
1300         }
1301
1302         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
1303                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1304                 if (dm_new_plane_state->dc_state) {
1305                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1306                         dc_plane_state_release(dm_new_plane_state->dc_state);
1307                         dm_new_plane_state->dc_state = NULL;
1308                 }
1309         }
1310
1311         drm_atomic_helper_resume(ddev, dm->cached_state);
1312
1313         dm->cached_state = NULL;
1314
1315         amdgpu_dm_irq_resume_late(adev);
1316
1317         return 0;
1318 }
1319
1320 /**
1321  * DOC: DM Lifecycle
1322  *
1323  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1324  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1325  * the base driver's device list to be initialized and torn down accordingly.
1326  *
1327  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1328  */
1329
1330 static const struct amd_ip_funcs amdgpu_dm_funcs = {
1331         .name = "dm",
1332         .early_init = dm_early_init,
1333         .late_init = dm_late_init,
1334         .sw_init = dm_sw_init,
1335         .sw_fini = dm_sw_fini,
1336         .hw_init = dm_hw_init,
1337         .hw_fini = dm_hw_fini,
1338         .suspend = dm_suspend,
1339         .resume = dm_resume,
1340         .is_idle = dm_is_idle,
1341         .wait_for_idle = dm_wait_for_idle,
1342         .check_soft_reset = dm_check_soft_reset,
1343         .soft_reset = dm_soft_reset,
1344         .set_clockgating_state = dm_set_clockgating_state,
1345         .set_powergating_state = dm_set_powergating_state,
1346 };
1347
1348 const struct amdgpu_ip_block_version dm_ip_block =
1349 {
1350         .type = AMD_IP_BLOCK_TYPE_DCE,
1351         .major = 1,
1352         .minor = 0,
1353         .rev = 0,
1354         .funcs = &amdgpu_dm_funcs,
1355 };
1356
1357
1358 /**
1359  * DOC: atomic
1360  *
1361  * *WIP*
1362  */
1363
1364 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1365         .fb_create = amdgpu_display_user_framebuffer_create,
1366         .output_poll_changed = drm_fb_helper_output_poll_changed,
1367         .atomic_check = amdgpu_dm_atomic_check,
1368         .atomic_commit = amdgpu_dm_atomic_commit,
1369 };
1370
1371 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1372         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1373 };
1374
1375 static void
1376 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1377 {
1378         struct drm_connector *connector = &aconnector->base;
1379         struct drm_device *dev = connector->dev;
1380         struct dc_sink *sink;
1381
1382         /* MST handled by drm_mst framework */
1383         if (aconnector->mst_mgr.mst_state == true)
1384                 return;
1385
1386
1387         sink = aconnector->dc_link->local_sink;
1388         if (sink)
1389                 dc_sink_retain(sink);
1390
1391         /*
1392          * Edid mgmt connector gets first update only in mode_valid hook and then
1393          * the connector sink is set to either fake or physical sink depends on link status.
1394          * Skip if already done during boot.
1395          */
1396         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1397                         && aconnector->dc_em_sink) {
1398
1399                 /*
1400                  * For S3 resume with headless use eml_sink to fake stream
1401                  * because on resume connector->sink is set to NULL
1402                  */
1403                 mutex_lock(&dev->mode_config.mutex);
1404
1405                 if (sink) {
1406                         if (aconnector->dc_sink) {
1407                                 amdgpu_dm_update_freesync_caps(connector, NULL);
1408                                 /*
1409                                  * retain and release below are used to
1410                                  * bump up refcount for sink because the link doesn't point
1411                                  * to it anymore after disconnect, so on next crtc to connector
1412                                  * reshuffle by UMD we will get into unwanted dc_sink release
1413                                  */
1414                                 dc_sink_release(aconnector->dc_sink);
1415                         }
1416                         aconnector->dc_sink = sink;
1417                         dc_sink_retain(aconnector->dc_sink);
1418                         amdgpu_dm_update_freesync_caps(connector,
1419                                         aconnector->edid);
1420                 } else {
1421                         amdgpu_dm_update_freesync_caps(connector, NULL);
1422                         if (!aconnector->dc_sink) {
1423                                 aconnector->dc_sink = aconnector->dc_em_sink;
1424                                 dc_sink_retain(aconnector->dc_sink);
1425                         }
1426                 }
1427
1428                 mutex_unlock(&dev->mode_config.mutex);
1429
1430                 if (sink)
1431                         dc_sink_release(sink);
1432                 return;
1433         }
1434
1435         /*
1436          * TODO: temporary guard to look for proper fix
1437          * if this sink is MST sink, we should not do anything
1438          */
1439         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1440                 dc_sink_release(sink);
1441                 return;
1442         }
1443
1444         if (aconnector->dc_sink == sink) {
1445                 /*
1446                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
1447                  * Do nothing!!
1448                  */
1449                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1450                                 aconnector->connector_id);
1451                 if (sink)
1452                         dc_sink_release(sink);
1453                 return;
1454         }
1455
1456         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1457                 aconnector->connector_id, aconnector->dc_sink, sink);
1458
1459         mutex_lock(&dev->mode_config.mutex);
1460
1461         /*
1462          * 1. Update status of the drm connector
1463          * 2. Send an event and let userspace tell us what to do
1464          */
1465         if (sink) {
1466                 /*
1467                  * TODO: check if we still need the S3 mode update workaround.
1468                  * If yes, put it here.
1469                  */
1470                 if (aconnector->dc_sink)
1471                         amdgpu_dm_update_freesync_caps(connector, NULL);
1472
1473                 aconnector->dc_sink = sink;
1474                 dc_sink_retain(aconnector->dc_sink);
1475                 if (sink->dc_edid.length == 0) {
1476                         aconnector->edid = NULL;
1477                         drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1478                 } else {
1479                         aconnector->edid =
1480                                 (struct edid *) sink->dc_edid.raw_edid;
1481
1482
1483                         drm_connector_update_edid_property(connector,
1484                                         aconnector->edid);
1485                         drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1486                                             aconnector->edid);
1487                 }
1488                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1489
1490         } else {
1491                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1492                 amdgpu_dm_update_freesync_caps(connector, NULL);
1493                 drm_connector_update_edid_property(connector, NULL);
1494                 aconnector->num_modes = 0;
1495                 dc_sink_release(aconnector->dc_sink);
1496                 aconnector->dc_sink = NULL;
1497                 aconnector->edid = NULL;
1498 #ifdef CONFIG_DRM_AMD_DC_HDCP
1499                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
1500                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
1501                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
1502 #endif
1503         }
1504
1505         mutex_unlock(&dev->mode_config.mutex);
1506
1507         if (sink)
1508                 dc_sink_release(sink);
1509 }
1510
1511 static void handle_hpd_irq(void *param)
1512 {
1513         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1514         struct drm_connector *connector = &aconnector->base;
1515         struct drm_device *dev = connector->dev;
1516         enum dc_connection_type new_connection_type = dc_connection_none;
1517 #ifdef CONFIG_DRM_AMD_DC_HDCP
1518         struct amdgpu_device *adev = dev->dev_private;
1519 #endif
1520
1521         /*
1522          * In case of failure or MST no need to update connector status or notify the OS
1523          * since (for MST case) MST does this in its own context.
1524          */
1525         mutex_lock(&aconnector->hpd_lock);
1526
1527 #ifdef CONFIG_DRM_AMD_DC_HDCP
1528         if (adev->asic_type >= CHIP_RAVEN)
1529                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
1530 #endif
1531         if (aconnector->fake_enable)
1532                 aconnector->fake_enable = false;
1533
1534         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1535                 DRM_ERROR("KMS: Failed to detect connector\n");
1536
1537         if (aconnector->base.force && new_connection_type == dc_connection_none) {
1538                 emulated_link_detect(aconnector->dc_link);
1539
1540
1541                 drm_modeset_lock_all(dev);
1542                 dm_restore_drm_connector_state(dev, connector);
1543                 drm_modeset_unlock_all(dev);
1544
1545                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1546                         drm_kms_helper_hotplug_event(dev);
1547
1548         } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1549                 amdgpu_dm_update_connector_after_detect(aconnector);
1550
1551
1552                 drm_modeset_lock_all(dev);
1553                 dm_restore_drm_connector_state(dev, connector);
1554                 drm_modeset_unlock_all(dev);
1555
1556                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1557                         drm_kms_helper_hotplug_event(dev);
1558         }
1559         mutex_unlock(&aconnector->hpd_lock);
1560
1561 }
1562
1563 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1564 {
1565         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1566         uint8_t dret;
1567         bool new_irq_handled = false;
1568         int dpcd_addr;
1569         int dpcd_bytes_to_read;
1570
1571         const int max_process_count = 30;
1572         int process_count = 0;
1573
1574         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1575
1576         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1577                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1578                 /* DPCD 0x200 - 0x201 for downstream IRQ */
1579                 dpcd_addr = DP_SINK_COUNT;
1580         } else {
1581                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1582                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1583                 dpcd_addr = DP_SINK_COUNT_ESI;
1584         }
1585
1586         dret = drm_dp_dpcd_read(
1587                 &aconnector->dm_dp_aux.aux,
1588                 dpcd_addr,
1589                 esi,
1590                 dpcd_bytes_to_read);
1591
1592         while (dret == dpcd_bytes_to_read &&
1593                 process_count < max_process_count) {
1594                 uint8_t retry;
1595                 dret = 0;
1596
1597                 process_count++;
1598
1599                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1600                 /* handle HPD short pulse irq */
1601                 if (aconnector->mst_mgr.mst_state)
1602                         drm_dp_mst_hpd_irq(
1603                                 &aconnector->mst_mgr,
1604                                 esi,
1605                                 &new_irq_handled);
1606
1607                 if (new_irq_handled) {
1608                         /* ACK at DPCD to notify down stream */
1609                         const int ack_dpcd_bytes_to_write =
1610                                 dpcd_bytes_to_read - 1;
1611
1612                         for (retry = 0; retry < 3; retry++) {
1613                                 uint8_t wret;
1614
1615                                 wret = drm_dp_dpcd_write(
1616                                         &aconnector->dm_dp_aux.aux,
1617                                         dpcd_addr + 1,
1618                                         &esi[1],
1619                                         ack_dpcd_bytes_to_write);
1620                                 if (wret == ack_dpcd_bytes_to_write)
1621                                         break;
1622                         }
1623
1624                         /* check if there is new irq to be handled */
1625                         dret = drm_dp_dpcd_read(
1626                                 &aconnector->dm_dp_aux.aux,
1627                                 dpcd_addr,
1628                                 esi,
1629                                 dpcd_bytes_to_read);
1630
1631                         new_irq_handled = false;
1632                 } else {
1633                         break;
1634                 }
1635         }
1636
1637         if (process_count == max_process_count)
1638                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1639 }
1640
1641 static void handle_hpd_rx_irq(void *param)
1642 {
1643         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1644         struct drm_connector *connector = &aconnector->base;
1645         struct drm_device *dev = connector->dev;
1646         struct dc_link *dc_link = aconnector->dc_link;
1647         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1648         enum dc_connection_type new_connection_type = dc_connection_none;
1649 #ifdef CONFIG_DRM_AMD_DC_HDCP
1650         union hpd_irq_data hpd_irq_data;
1651         struct amdgpu_device *adev = dev->dev_private;
1652
1653         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
1654 #endif
1655
1656         /*
1657          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1658          * conflict, after implement i2c helper, this mutex should be
1659          * retired.
1660          */
1661         if (dc_link->type != dc_connection_mst_branch)
1662                 mutex_lock(&aconnector->hpd_lock);
1663
1664
1665 #ifdef CONFIG_DRM_AMD_DC_HDCP
1666         if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL) &&
1667 #else
1668         if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1669 #endif
1670                         !is_mst_root_connector) {
1671                 /* Downstream Port status changed. */
1672                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1673                         DRM_ERROR("KMS: Failed to detect connector\n");
1674
1675                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1676                         emulated_link_detect(dc_link);
1677
1678                         if (aconnector->fake_enable)
1679                                 aconnector->fake_enable = false;
1680
1681                         amdgpu_dm_update_connector_after_detect(aconnector);
1682
1683
1684                         drm_modeset_lock_all(dev);
1685                         dm_restore_drm_connector_state(dev, connector);
1686                         drm_modeset_unlock_all(dev);
1687
1688                         drm_kms_helper_hotplug_event(dev);
1689                 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1690
1691                         if (aconnector->fake_enable)
1692                                 aconnector->fake_enable = false;
1693
1694                         amdgpu_dm_update_connector_after_detect(aconnector);
1695
1696
1697                         drm_modeset_lock_all(dev);
1698                         dm_restore_drm_connector_state(dev, connector);
1699                         drm_modeset_unlock_all(dev);
1700
1701                         drm_kms_helper_hotplug_event(dev);
1702                 }
1703         }
1704 #ifdef CONFIG_DRM_AMD_DC_HDCP
1705         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ)
1706                 hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
1707 #endif
1708         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1709             (dc_link->type == dc_connection_mst_branch))
1710                 dm_handle_hpd_rx_irq(aconnector);
1711
1712         if (dc_link->type != dc_connection_mst_branch) {
1713                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1714                 mutex_unlock(&aconnector->hpd_lock);
1715         }
1716 }
1717
1718 static void register_hpd_handlers(struct amdgpu_device *adev)
1719 {
1720         struct drm_device *dev = adev->ddev;
1721         struct drm_connector *connector;
1722         struct amdgpu_dm_connector *aconnector;
1723         const struct dc_link *dc_link;
1724         struct dc_interrupt_params int_params = {0};
1725
1726         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1727         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1728
1729         list_for_each_entry(connector,
1730                         &dev->mode_config.connector_list, head) {
1731
1732                 aconnector = to_amdgpu_dm_connector(connector);
1733                 dc_link = aconnector->dc_link;
1734
1735                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1736                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1737                         int_params.irq_source = dc_link->irq_source_hpd;
1738
1739                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1740                                         handle_hpd_irq,
1741                                         (void *) aconnector);
1742                 }
1743
1744                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1745
1746                         /* Also register for DP short pulse (hpd_rx). */
1747                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1748                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1749
1750                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1751                                         handle_hpd_rx_irq,
1752                                         (void *) aconnector);
1753                 }
1754         }
1755 }
1756
1757 /* Register IRQ sources and initialize IRQ callbacks */
1758 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1759 {
1760         struct dc *dc = adev->dm.dc;
1761         struct common_irq_params *c_irq_params;
1762         struct dc_interrupt_params int_params = {0};
1763         int r;
1764         int i;
1765         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1766
1767         if (adev->asic_type >= CHIP_VEGA10)
1768                 client_id = SOC15_IH_CLIENTID_DCE;
1769
1770         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1771         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1772
1773         /*
1774          * Actions of amdgpu_irq_add_id():
1775          * 1. Register a set() function with base driver.
1776          *    Base driver will call set() function to enable/disable an
1777          *    interrupt in DC hardware.
1778          * 2. Register amdgpu_dm_irq_handler().
1779          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1780          *    coming from DC hardware.
1781          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1782          *    for acknowledging and handling. */
1783
1784         /* Use VBLANK interrupt */
1785         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1786                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1787                 if (r) {
1788                         DRM_ERROR("Failed to add crtc irq id!\n");
1789                         return r;
1790                 }
1791
1792                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1793                 int_params.irq_source =
1794                         dc_interrupt_to_irq_source(dc, i, 0);
1795
1796                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1797
1798                 c_irq_params->adev = adev;
1799                 c_irq_params->irq_src = int_params.irq_source;
1800
1801                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1802                                 dm_crtc_high_irq, c_irq_params);
1803         }
1804
1805         /* Use VUPDATE interrupt */
1806         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1807                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1808                 if (r) {
1809                         DRM_ERROR("Failed to add vupdate irq id!\n");
1810                         return r;
1811                 }
1812
1813                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1814                 int_params.irq_source =
1815                         dc_interrupt_to_irq_source(dc, i, 0);
1816
1817                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1818
1819                 c_irq_params->adev = adev;
1820                 c_irq_params->irq_src = int_params.irq_source;
1821
1822                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1823                                 dm_vupdate_high_irq, c_irq_params);
1824         }
1825
1826         /* Use GRPH_PFLIP interrupt */
1827         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1828                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1829                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1830                 if (r) {
1831                         DRM_ERROR("Failed to add page flip irq id!\n");
1832                         return r;
1833                 }
1834
1835                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1836                 int_params.irq_source =
1837                         dc_interrupt_to_irq_source(dc, i, 0);
1838
1839                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1840
1841                 c_irq_params->adev = adev;
1842                 c_irq_params->irq_src = int_params.irq_source;
1843
1844                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1845                                 dm_pflip_high_irq, c_irq_params);
1846
1847         }
1848
1849         /* HPD */
1850         r = amdgpu_irq_add_id(adev, client_id,
1851                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1852         if (r) {
1853                 DRM_ERROR("Failed to add hpd irq id!\n");
1854                 return r;
1855         }
1856
1857         register_hpd_handlers(adev);
1858
1859         return 0;
1860 }
1861
1862 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1863 /* Register IRQ sources and initialize IRQ callbacks */
1864 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1865 {
1866         struct dc *dc = adev->dm.dc;
1867         struct common_irq_params *c_irq_params;
1868         struct dc_interrupt_params int_params = {0};
1869         int r;
1870         int i;
1871
1872         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1873         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1874
1875         /*
1876          * Actions of amdgpu_irq_add_id():
1877          * 1. Register a set() function with base driver.
1878          *    Base driver will call set() function to enable/disable an
1879          *    interrupt in DC hardware.
1880          * 2. Register amdgpu_dm_irq_handler().
1881          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1882          *    coming from DC hardware.
1883          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1884          *    for acknowledging and handling.
1885          */
1886
1887         /* Use VSTARTUP interrupt */
1888         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1889                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1890                         i++) {
1891                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1892
1893                 if (r) {
1894                         DRM_ERROR("Failed to add crtc irq id!\n");
1895                         return r;
1896                 }
1897
1898                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1899                 int_params.irq_source =
1900                         dc_interrupt_to_irq_source(dc, i, 0);
1901
1902                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1903
1904                 c_irq_params->adev = adev;
1905                 c_irq_params->irq_src = int_params.irq_source;
1906
1907                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1908                                 dm_crtc_high_irq, c_irq_params);
1909         }
1910
1911         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1912          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1913          * to trigger at end of each vblank, regardless of state of the lock,
1914          * matching DCE behaviour.
1915          */
1916         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1917              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1918              i++) {
1919                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1920
1921                 if (r) {
1922                         DRM_ERROR("Failed to add vupdate irq id!\n");
1923                         return r;
1924                 }
1925
1926                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1927                 int_params.irq_source =
1928                         dc_interrupt_to_irq_source(dc, i, 0);
1929
1930                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1931
1932                 c_irq_params->adev = adev;
1933                 c_irq_params->irq_src = int_params.irq_source;
1934
1935                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1936                                 dm_vupdate_high_irq, c_irq_params);
1937         }
1938
1939         /* Use GRPH_PFLIP interrupt */
1940         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1941                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1942                         i++) {
1943                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1944                 if (r) {
1945                         DRM_ERROR("Failed to add page flip irq id!\n");
1946                         return r;
1947                 }
1948
1949                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1950                 int_params.irq_source =
1951                         dc_interrupt_to_irq_source(dc, i, 0);
1952
1953                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1954
1955                 c_irq_params->adev = adev;
1956                 c_irq_params->irq_src = int_params.irq_source;
1957
1958                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1959                                 dm_pflip_high_irq, c_irq_params);
1960
1961         }
1962
1963         /* HPD */
1964         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1965                         &adev->hpd_irq);
1966         if (r) {
1967                 DRM_ERROR("Failed to add hpd irq id!\n");
1968                 return r;
1969         }
1970
1971         register_hpd_handlers(adev);
1972
1973         return 0;
1974 }
1975 #endif
1976
1977 /*
1978  * Acquires the lock for the atomic state object and returns
1979  * the new atomic state.
1980  *
1981  * This should only be called during atomic check.
1982  */
1983 static int dm_atomic_get_state(struct drm_atomic_state *state,
1984                                struct dm_atomic_state **dm_state)
1985 {
1986         struct drm_device *dev = state->dev;
1987         struct amdgpu_device *adev = dev->dev_private;
1988         struct amdgpu_display_manager *dm = &adev->dm;
1989         struct drm_private_state *priv_state;
1990
1991         if (*dm_state)
1992                 return 0;
1993
1994         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1995         if (IS_ERR(priv_state))
1996                 return PTR_ERR(priv_state);
1997
1998         *dm_state = to_dm_atomic_state(priv_state);
1999
2000         return 0;
2001 }
2002
2003 struct dm_atomic_state *
2004 dm_atomic_get_new_state(struct drm_atomic_state *state)
2005 {
2006         struct drm_device *dev = state->dev;
2007         struct amdgpu_device *adev = dev->dev_private;
2008         struct amdgpu_display_manager *dm = &adev->dm;
2009         struct drm_private_obj *obj;
2010         struct drm_private_state *new_obj_state;
2011         int i;
2012
2013         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
2014                 if (obj->funcs == dm->atomic_obj.funcs)
2015                         return to_dm_atomic_state(new_obj_state);
2016         }
2017
2018         return NULL;
2019 }
2020
2021 struct dm_atomic_state *
2022 dm_atomic_get_old_state(struct drm_atomic_state *state)
2023 {
2024         struct drm_device *dev = state->dev;
2025         struct amdgpu_device *adev = dev->dev_private;
2026         struct amdgpu_display_manager *dm = &adev->dm;
2027         struct drm_private_obj *obj;
2028         struct drm_private_state *old_obj_state;
2029         int i;
2030
2031         for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
2032                 if (obj->funcs == dm->atomic_obj.funcs)
2033                         return to_dm_atomic_state(old_obj_state);
2034         }
2035
2036         return NULL;
2037 }
2038
2039 static struct drm_private_state *
2040 dm_atomic_duplicate_state(struct drm_private_obj *obj)
2041 {
2042         struct dm_atomic_state *old_state, *new_state;
2043
2044         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
2045         if (!new_state)
2046                 return NULL;
2047
2048         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
2049
2050         old_state = to_dm_atomic_state(obj->state);
2051
2052         if (old_state && old_state->context)
2053                 new_state->context = dc_copy_state(old_state->context);
2054
2055         if (!new_state->context) {
2056                 kfree(new_state);
2057                 return NULL;
2058         }
2059
2060         return &new_state->base;
2061 }
2062
2063 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
2064                                     struct drm_private_state *state)
2065 {
2066         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
2067
2068         if (dm_state && dm_state->context)
2069                 dc_release_state(dm_state->context);
2070
2071         kfree(dm_state);
2072 }
2073
2074 static struct drm_private_state_funcs dm_atomic_state_funcs = {
2075         .atomic_duplicate_state = dm_atomic_duplicate_state,
2076         .atomic_destroy_state = dm_atomic_destroy_state,
2077 };
2078
2079 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
2080 {
2081         struct dm_atomic_state *state;
2082         int r;
2083
2084         adev->mode_info.mode_config_initialized = true;
2085
2086         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
2087         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
2088
2089         adev->ddev->mode_config.max_width = 16384;
2090         adev->ddev->mode_config.max_height = 16384;
2091
2092         adev->ddev->mode_config.preferred_depth = 24;
2093         adev->ddev->mode_config.prefer_shadow = 1;
2094         /* indicates support for immediate flip */
2095         adev->ddev->mode_config.async_page_flip = true;
2096
2097         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2098
2099         state = kzalloc(sizeof(*state), GFP_KERNEL);
2100         if (!state)
2101                 return -ENOMEM;
2102
2103         state->context = dc_create_state(adev->dm.dc);
2104         if (!state->context) {
2105                 kfree(state);
2106                 return -ENOMEM;
2107         }
2108
2109         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
2110
2111         drm_atomic_private_obj_init(adev->ddev,
2112                                     &adev->dm.atomic_obj,
2113                                     &state->base,
2114                                     &dm_atomic_state_funcs);
2115
2116         r = amdgpu_display_modeset_create_props(adev);
2117         if (r)
2118                 return r;
2119
2120         r = amdgpu_dm_audio_init(adev);
2121         if (r)
2122                 return r;
2123
2124         return 0;
2125 }
2126
2127 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2128 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2129
2130 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2131         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2132
2133 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
2134 {
2135 #if defined(CONFIG_ACPI)
2136         struct amdgpu_dm_backlight_caps caps;
2137
2138         if (dm->backlight_caps.caps_valid)
2139                 return;
2140
2141         amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
2142         if (caps.caps_valid) {
2143                 dm->backlight_caps.min_input_signal = caps.min_input_signal;
2144                 dm->backlight_caps.max_input_signal = caps.max_input_signal;
2145                 dm->backlight_caps.caps_valid = true;
2146         } else {
2147                 dm->backlight_caps.min_input_signal =
2148                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2149                 dm->backlight_caps.max_input_signal =
2150                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2151         }
2152 #else
2153         dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2154         dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2155 #endif
2156 }
2157
2158 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
2159 {
2160         struct amdgpu_display_manager *dm = bl_get_data(bd);
2161         struct amdgpu_dm_backlight_caps caps;
2162         uint32_t brightness = bd->props.brightness;
2163
2164         amdgpu_dm_update_backlight_caps(dm);
2165         caps = dm->backlight_caps;
2166         /*
2167          * The brightness input is in the range 0-255
2168          * It needs to be rescaled to be between the
2169          * requested min and max input signal
2170          *
2171          * It also needs to be scaled up by 0x101 to
2172          * match the DC interface which has a range of
2173          * 0 to 0xffff
2174          */
2175         brightness =
2176                 brightness
2177                 * 0x101
2178                 * (caps.max_input_signal - caps.min_input_signal)
2179                 / AMDGPU_MAX_BL_LEVEL
2180                 + caps.min_input_signal * 0x101;
2181
2182         if (dc_link_set_backlight_level(dm->backlight_link,
2183                         brightness, 0))
2184                 return 0;
2185         else
2186                 return 1;
2187 }
2188
2189 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
2190 {
2191         struct amdgpu_display_manager *dm = bl_get_data(bd);
2192         int ret = dc_link_get_backlight_level(dm->backlight_link);
2193
2194         if (ret == DC_ERROR_UNEXPECTED)
2195                 return bd->props.brightness;
2196         return ret;
2197 }
2198
2199 static const struct backlight_ops amdgpu_dm_backlight_ops = {
2200         .options = BL_CORE_SUSPENDRESUME,
2201         .get_brightness = amdgpu_dm_backlight_get_brightness,
2202         .update_status  = amdgpu_dm_backlight_update_status,
2203 };
2204
2205 static void
2206 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
2207 {
2208         char bl_name[16];
2209         struct backlight_properties props = { 0 };
2210
2211         amdgpu_dm_update_backlight_caps(dm);
2212
2213         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
2214         props.brightness = AMDGPU_MAX_BL_LEVEL;
2215         props.type = BACKLIGHT_RAW;
2216
2217         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
2218                         dm->adev->ddev->primary->index);
2219
2220         dm->backlight_dev = backlight_device_register(bl_name,
2221                         dm->adev->ddev->dev,
2222                         dm,
2223                         &amdgpu_dm_backlight_ops,
2224                         &props);
2225
2226         if (IS_ERR(dm->backlight_dev))
2227                 DRM_ERROR("DM: Backlight registration failed!\n");
2228         else
2229                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
2230 }
2231
2232 #endif
2233
2234 static int initialize_plane(struct amdgpu_display_manager *dm,
2235                             struct amdgpu_mode_info *mode_info, int plane_id,
2236                             enum drm_plane_type plane_type,
2237                             const struct dc_plane_cap *plane_cap)
2238 {
2239         struct drm_plane *plane;
2240         unsigned long possible_crtcs;
2241         int ret = 0;
2242
2243         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
2244         if (!plane) {
2245                 DRM_ERROR("KMS: Failed to allocate plane\n");
2246                 return -ENOMEM;
2247         }
2248         plane->type = plane_type;
2249
2250         /*
2251          * HACK: IGT tests expect that the primary plane for a CRTC
2252          * can only have one possible CRTC. Only expose support for
2253          * any CRTC if they're not going to be used as a primary plane
2254          * for a CRTC - like overlay or underlay planes.
2255          */
2256         possible_crtcs = 1 << plane_id;
2257         if (plane_id >= dm->dc->caps.max_streams)
2258                 possible_crtcs = 0xff;
2259
2260         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
2261
2262         if (ret) {
2263                 DRM_ERROR("KMS: Failed to initialize plane\n");
2264                 kfree(plane);
2265                 return ret;
2266         }
2267
2268         if (mode_info)
2269                 mode_info->planes[plane_id] = plane;
2270
2271         return ret;
2272 }
2273
2274
2275 static void register_backlight_device(struct amdgpu_display_manager *dm,
2276                                       struct dc_link *link)
2277 {
2278 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2279         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2280
2281         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2282             link->type != dc_connection_none) {
2283                 /*
2284                  * Event if registration failed, we should continue with
2285                  * DM initialization because not having a backlight control
2286                  * is better then a black screen.
2287                  */
2288                 amdgpu_dm_register_backlight_device(dm);
2289
2290                 if (dm->backlight_dev)
2291                         dm->backlight_link = link;
2292         }
2293 #endif
2294 }
2295
2296
2297 /*
2298  * In this architecture, the association
2299  * connector -> encoder -> crtc
2300  * id not really requried. The crtc and connector will hold the
2301  * display_index as an abstraction to use with DAL component
2302  *
2303  * Returns 0 on success
2304  */
2305 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2306 {
2307         struct amdgpu_display_manager *dm = &adev->dm;
2308         int32_t i;
2309         struct amdgpu_dm_connector *aconnector = NULL;
2310         struct amdgpu_encoder *aencoder = NULL;
2311         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2312         uint32_t link_cnt;
2313         int32_t primary_planes;
2314         enum dc_connection_type new_connection_type = dc_connection_none;
2315         const struct dc_plane_cap *plane;
2316
2317         link_cnt = dm->dc->caps.max_links;
2318         if (amdgpu_dm_mode_config_init(dm->adev)) {
2319                 DRM_ERROR("DM: Failed to initialize mode config\n");
2320                 return -EINVAL;
2321         }
2322
2323         /* There is one primary plane per CRTC */
2324         primary_planes = dm->dc->caps.max_streams;
2325         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
2326
2327         /*
2328          * Initialize primary planes, implicit planes for legacy IOCTLS.
2329          * Order is reversed to match iteration order in atomic check.
2330          */
2331         for (i = (primary_planes - 1); i >= 0; i--) {
2332                 plane = &dm->dc->caps.planes[i];
2333
2334                 if (initialize_plane(dm, mode_info, i,
2335                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
2336                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
2337                         goto fail;
2338                 }
2339         }
2340
2341         /*
2342          * Initialize overlay planes, index starting after primary planes.
2343          * These planes have a higher DRM index than the primary planes since
2344          * they should be considered as having a higher z-order.
2345          * Order is reversed to match iteration order in atomic check.
2346          *
2347          * Only support DCN for now, and only expose one so we don't encourage
2348          * userspace to use up all the pipes.
2349          */
2350         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2351                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2352
2353                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2354                         continue;
2355
2356                 if (!plane->blends_with_above || !plane->blends_with_below)
2357                         continue;
2358
2359                 if (!plane->pixel_format_support.argb8888)
2360                         continue;
2361
2362                 if (initialize_plane(dm, NULL, primary_planes + i,
2363                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
2364                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
2365                         goto fail;
2366                 }
2367
2368                 /* Only create one overlay plane. */
2369                 break;
2370         }
2371
2372         for (i = 0; i < dm->dc->caps.max_streams; i++)
2373                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
2374                         DRM_ERROR("KMS: Failed to initialize crtc\n");
2375                         goto fail;
2376                 }
2377
2378         dm->display_indexes_num = dm->dc->caps.max_streams;
2379
2380         /* loops over all connectors on the board */
2381         for (i = 0; i < link_cnt; i++) {
2382                 struct dc_link *link = NULL;
2383
2384                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2385                         DRM_ERROR(
2386                                 "KMS: Cannot support more than %d display indexes\n",
2387                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
2388                         continue;
2389                 }
2390
2391                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2392                 if (!aconnector)
2393                         goto fail;
2394
2395                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
2396                 if (!aencoder)
2397                         goto fail;
2398
2399                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2400                         DRM_ERROR("KMS: Failed to initialize encoder\n");
2401                         goto fail;
2402                 }
2403
2404                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2405                         DRM_ERROR("KMS: Failed to initialize connector\n");
2406                         goto fail;
2407                 }
2408
2409                 link = dc_get_link_at_index(dm->dc, i);
2410
2411                 if (!dc_link_detect_sink(link, &new_connection_type))
2412                         DRM_ERROR("KMS: Failed to detect connector\n");
2413
2414                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2415                         emulated_link_detect(link);
2416                         amdgpu_dm_update_connector_after_detect(aconnector);
2417
2418                 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
2419                         amdgpu_dm_update_connector_after_detect(aconnector);
2420                         register_backlight_device(dm, link);
2421                 }
2422
2423
2424         }
2425
2426         /* Software is initialized. Now we can register interrupt handlers. */
2427         switch (adev->asic_type) {
2428         case CHIP_BONAIRE:
2429         case CHIP_HAWAII:
2430         case CHIP_KAVERI:
2431         case CHIP_KABINI:
2432         case CHIP_MULLINS:
2433         case CHIP_TONGA:
2434         case CHIP_FIJI:
2435         case CHIP_CARRIZO:
2436         case CHIP_STONEY:
2437         case CHIP_POLARIS11:
2438         case CHIP_POLARIS10:
2439         case CHIP_POLARIS12:
2440         case CHIP_VEGAM:
2441         case CHIP_VEGA10:
2442         case CHIP_VEGA12:
2443         case CHIP_VEGA20:
2444                 if (dce110_register_irq_handlers(dm->adev)) {
2445                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2446                         goto fail;
2447                 }
2448                 break;
2449 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2450         case CHIP_RAVEN:
2451 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2452         case CHIP_NAVI12:
2453         case CHIP_NAVI10:
2454         case CHIP_NAVI14:
2455 #endif
2456 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2457         case CHIP_RENOIR:
2458 #endif
2459                 if (dcn10_register_irq_handlers(dm->adev)) {
2460                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2461                         goto fail;
2462                 }
2463                 break;
2464 #endif
2465         default:
2466                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2467                 goto fail;
2468         }
2469
2470         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2471                 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2472
2473         return 0;
2474 fail:
2475         kfree(aencoder);
2476         kfree(aconnector);
2477
2478         return -EINVAL;
2479 }
2480
2481 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2482 {
2483         drm_mode_config_cleanup(dm->ddev);
2484         drm_atomic_private_obj_fini(&dm->atomic_obj);
2485         return;
2486 }
2487
2488 /******************************************************************************
2489  * amdgpu_display_funcs functions
2490  *****************************************************************************/
2491
2492 /*
2493  * dm_bandwidth_update - program display watermarks
2494  *
2495  * @adev: amdgpu_device pointer
2496  *
2497  * Calculate and program the display watermarks and line buffer allocation.
2498  */
2499 static void dm_bandwidth_update(struct amdgpu_device *adev)
2500 {
2501         /* TODO: implement later */
2502 }
2503
2504 static const struct amdgpu_display_funcs dm_display_funcs = {
2505         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2506         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2507         .backlight_set_level = NULL, /* never called for DC */
2508         .backlight_get_level = NULL, /* never called for DC */
2509         .hpd_sense = NULL,/* called unconditionally */
2510         .hpd_set_polarity = NULL, /* called unconditionally */
2511         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2512         .page_flip_get_scanoutpos =
2513                 dm_crtc_get_scanoutpos,/* called unconditionally */
2514         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2515         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2516 };
2517
2518 #if defined(CONFIG_DEBUG_KERNEL_DC)
2519
2520 static ssize_t s3_debug_store(struct device *device,
2521                               struct device_attribute *attr,
2522                               const char *buf,
2523                               size_t count)
2524 {
2525         int ret;
2526         int s3_state;
2527         struct drm_device *drm_dev = dev_get_drvdata(device);
2528         struct amdgpu_device *adev = drm_dev->dev_private;
2529
2530         ret = kstrtoint(buf, 0, &s3_state);
2531
2532         if (ret == 0) {
2533                 if (s3_state) {
2534                         dm_resume(adev);
2535                         drm_kms_helper_hotplug_event(adev->ddev);
2536                 } else
2537                         dm_suspend(adev);
2538         }
2539
2540         return ret == 0 ? count : 0;
2541 }
2542
2543 DEVICE_ATTR_WO(s3_debug);
2544
2545 #endif
2546
2547 static int dm_early_init(void *handle)
2548 {
2549         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2550
2551         switch (adev->asic_type) {
2552         case CHIP_BONAIRE:
2553         case CHIP_HAWAII:
2554                 adev->mode_info.num_crtc = 6;
2555                 adev->mode_info.num_hpd = 6;
2556                 adev->mode_info.num_dig = 6;
2557                 break;
2558         case CHIP_KAVERI:
2559                 adev->mode_info.num_crtc = 4;
2560                 adev->mode_info.num_hpd = 6;
2561                 adev->mode_info.num_dig = 7;
2562                 break;
2563         case CHIP_KABINI:
2564         case CHIP_MULLINS:
2565                 adev->mode_info.num_crtc = 2;
2566                 adev->mode_info.num_hpd = 6;
2567                 adev->mode_info.num_dig = 6;
2568                 break;
2569         case CHIP_FIJI:
2570         case CHIP_TONGA:
2571                 adev->mode_info.num_crtc = 6;
2572                 adev->mode_info.num_hpd = 6;
2573                 adev->mode_info.num_dig = 7;
2574                 break;
2575         case CHIP_CARRIZO:
2576                 adev->mode_info.num_crtc = 3;
2577                 adev->mode_info.num_hpd = 6;
2578                 adev->mode_info.num_dig = 9;
2579                 break;
2580         case CHIP_STONEY:
2581                 adev->mode_info.num_crtc = 2;
2582                 adev->mode_info.num_hpd = 6;
2583                 adev->mode_info.num_dig = 9;
2584                 break;
2585         case CHIP_POLARIS11:
2586         case CHIP_POLARIS12:
2587                 adev->mode_info.num_crtc = 5;
2588                 adev->mode_info.num_hpd = 5;
2589                 adev->mode_info.num_dig = 5;
2590                 break;
2591         case CHIP_POLARIS10:
2592         case CHIP_VEGAM:
2593                 adev->mode_info.num_crtc = 6;
2594                 adev->mode_info.num_hpd = 6;
2595                 adev->mode_info.num_dig = 6;
2596                 break;
2597         case CHIP_VEGA10:
2598         case CHIP_VEGA12:
2599         case CHIP_VEGA20:
2600                 adev->mode_info.num_crtc = 6;
2601                 adev->mode_info.num_hpd = 6;
2602                 adev->mode_info.num_dig = 6;
2603                 break;
2604 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2605         case CHIP_RAVEN:
2606                 adev->mode_info.num_crtc = 4;
2607                 adev->mode_info.num_hpd = 4;
2608                 adev->mode_info.num_dig = 4;
2609                 break;
2610 #endif
2611 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2612         case CHIP_NAVI10:
2613         case CHIP_NAVI12:
2614                 adev->mode_info.num_crtc = 6;
2615                 adev->mode_info.num_hpd = 6;
2616                 adev->mode_info.num_dig = 6;
2617                 break;
2618         case CHIP_NAVI14:
2619                 adev->mode_info.num_crtc = 5;
2620                 adev->mode_info.num_hpd = 5;
2621                 adev->mode_info.num_dig = 5;
2622                 break;
2623 #endif
2624 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2625         case CHIP_RENOIR:
2626                 adev->mode_info.num_crtc = 4;
2627                 adev->mode_info.num_hpd = 4;
2628                 adev->mode_info.num_dig = 4;
2629                 break;
2630 #endif
2631         default:
2632                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2633                 return -EINVAL;
2634         }
2635
2636         amdgpu_dm_set_irq_funcs(adev);
2637
2638         if (adev->mode_info.funcs == NULL)
2639                 adev->mode_info.funcs = &dm_display_funcs;
2640
2641         /*
2642          * Note: Do NOT change adev->audio_endpt_rreg and
2643          * adev->audio_endpt_wreg because they are initialised in
2644          * amdgpu_device_init()
2645          */
2646 #if defined(CONFIG_DEBUG_KERNEL_DC)
2647         device_create_file(
2648                 adev->ddev->dev,
2649                 &dev_attr_s3_debug);
2650 #endif
2651
2652         return 0;
2653 }
2654
2655 static bool modeset_required(struct drm_crtc_state *crtc_state,
2656                              struct dc_stream_state *new_stream,
2657                              struct dc_stream_state *old_stream)
2658 {
2659         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2660                 return false;
2661
2662         if (!crtc_state->enable)
2663                 return false;
2664
2665         return crtc_state->active;
2666 }
2667
2668 static bool modereset_required(struct drm_crtc_state *crtc_state)
2669 {
2670         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2671                 return false;
2672
2673         return !crtc_state->enable || !crtc_state->active;
2674 }
2675
2676 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2677 {
2678         drm_encoder_cleanup(encoder);
2679         kfree(encoder);
2680 }
2681
2682 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2683         .destroy = amdgpu_dm_encoder_destroy,
2684 };
2685
2686
2687 static int fill_dc_scaling_info(const struct drm_plane_state *state,
2688                                 struct dc_scaling_info *scaling_info)
2689 {
2690         int scale_w, scale_h;
2691
2692         memset(scaling_info, 0, sizeof(*scaling_info));
2693
2694         /* Source is fixed 16.16 but we ignore mantissa for now... */
2695         scaling_info->src_rect.x = state->src_x >> 16;
2696         scaling_info->src_rect.y = state->src_y >> 16;
2697
2698         scaling_info->src_rect.width = state->src_w >> 16;
2699         if (scaling_info->src_rect.width == 0)
2700                 return -EINVAL;
2701
2702         scaling_info->src_rect.height = state->src_h >> 16;
2703         if (scaling_info->src_rect.height == 0)
2704                 return -EINVAL;
2705
2706         scaling_info->dst_rect.x = state->crtc_x;
2707         scaling_info->dst_rect.y = state->crtc_y;
2708
2709         if (state->crtc_w == 0)
2710                 return -EINVAL;
2711
2712         scaling_info->dst_rect.width = state->crtc_w;
2713
2714         if (state->crtc_h == 0)
2715                 return -EINVAL;
2716
2717         scaling_info->dst_rect.height = state->crtc_h;
2718
2719         /* DRM doesn't specify clipping on destination output. */
2720         scaling_info->clip_rect = scaling_info->dst_rect;
2721
2722         /* TODO: Validate scaling per-format with DC plane caps */
2723         scale_w = scaling_info->dst_rect.width * 1000 /
2724                   scaling_info->src_rect.width;
2725
2726         if (scale_w < 250 || scale_w > 16000)
2727                 return -EINVAL;
2728
2729         scale_h = scaling_info->dst_rect.height * 1000 /
2730                   scaling_info->src_rect.height;
2731
2732         if (scale_h < 250 || scale_h > 16000)
2733                 return -EINVAL;
2734
2735         /*
2736          * The "scaling_quality" can be ignored for now, quality = 0 has DC
2737          * assume reasonable defaults based on the format.
2738          */
2739
2740         return 0;
2741 }
2742
2743 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2744                        uint64_t *tiling_flags)
2745 {
2746         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2747         int r = amdgpu_bo_reserve(rbo, false);
2748
2749         if (unlikely(r)) {
2750                 /* Don't show error message when returning -ERESTARTSYS */
2751                 if (r != -ERESTARTSYS)
2752                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
2753                 return r;
2754         }
2755
2756         if (tiling_flags)
2757                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2758
2759         amdgpu_bo_unreserve(rbo);
2760
2761         return r;
2762 }
2763
2764 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2765 {
2766         uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2767
2768         return offset ? (address + offset * 256) : 0;
2769 }
2770
2771 static int
2772 fill_plane_dcc_attributes(struct amdgpu_device *adev,
2773                           const struct amdgpu_framebuffer *afb,
2774                           const enum surface_pixel_format format,
2775                           const enum dc_rotation_angle rotation,
2776                           const struct plane_size *plane_size,
2777                           const union dc_tiling_info *tiling_info,
2778                           const uint64_t info,
2779                           struct dc_plane_dcc_param *dcc,
2780                           struct dc_plane_address *address)
2781 {
2782         struct dc *dc = adev->dm.dc;
2783         struct dc_dcc_surface_param input;
2784         struct dc_surface_dcc_cap output;
2785         uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2786         uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2787         uint64_t dcc_address;
2788
2789         memset(&input, 0, sizeof(input));
2790         memset(&output, 0, sizeof(output));
2791
2792         if (!offset)
2793                 return 0;
2794
2795         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2796                 return 0;
2797
2798         if (!dc->cap_funcs.get_dcc_compression_cap)
2799                 return -EINVAL;
2800
2801         input.format = format;
2802         input.surface_size.width = plane_size->surface_size.width;
2803         input.surface_size.height = plane_size->surface_size.height;
2804         input.swizzle_mode = tiling_info->gfx9.swizzle;
2805
2806         if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
2807                 input.scan = SCAN_DIRECTION_HORIZONTAL;
2808         else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
2809                 input.scan = SCAN_DIRECTION_VERTICAL;
2810
2811         if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2812                 return -EINVAL;
2813
2814         if (!output.capable)
2815                 return -EINVAL;
2816
2817         if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2818                 return -EINVAL;
2819
2820         dcc->enable = 1;
2821         dcc->meta_pitch =
2822                 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2823         dcc->independent_64b_blks = i64b;
2824
2825         dcc_address = get_dcc_address(afb->address, info);
2826         address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2827         address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
2828
2829         return 0;
2830 }
2831
2832 static int
2833 fill_plane_buffer_attributes(struct amdgpu_device *adev,
2834                              const struct amdgpu_framebuffer *afb,
2835                              const enum surface_pixel_format format,
2836                              const enum dc_rotation_angle rotation,
2837                              const uint64_t tiling_flags,
2838                              union dc_tiling_info *tiling_info,
2839                              struct plane_size *plane_size,
2840                              struct dc_plane_dcc_param *dcc,
2841                              struct dc_plane_address *address)
2842 {
2843         const struct drm_framebuffer *fb = &afb->base;
2844         int ret;
2845
2846         memset(tiling_info, 0, sizeof(*tiling_info));
2847         memset(plane_size, 0, sizeof(*plane_size));
2848         memset(dcc, 0, sizeof(*dcc));
2849         memset(address, 0, sizeof(*address));
2850
2851         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2852                 plane_size->surface_size.x = 0;
2853                 plane_size->surface_size.y = 0;
2854                 plane_size->surface_size.width = fb->width;
2855                 plane_size->surface_size.height = fb->height;
2856                 plane_size->surface_pitch =
2857                         fb->pitches[0] / fb->format->cpp[0];
2858
2859                 address->type = PLN_ADDR_TYPE_GRAPHICS;
2860                 address->grph.addr.low_part = lower_32_bits(afb->address);
2861                 address->grph.addr.high_part = upper_32_bits(afb->address);
2862         } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
2863                 uint64_t chroma_addr = afb->address + fb->offsets[1];
2864
2865                 plane_size->surface_size.x = 0;
2866                 plane_size->surface_size.y = 0;
2867                 plane_size->surface_size.width = fb->width;
2868                 plane_size->surface_size.height = fb->height;
2869                 plane_size->surface_pitch =
2870                         fb->pitches[0] / fb->format->cpp[0];
2871
2872                 plane_size->chroma_size.x = 0;
2873                 plane_size->chroma_size.y = 0;
2874                 /* TODO: set these based on surface format */
2875                 plane_size->chroma_size.width = fb->width / 2;
2876                 plane_size->chroma_size.height = fb->height / 2;
2877
2878                 plane_size->chroma_pitch =
2879                         fb->pitches[1] / fb->format->cpp[1];
2880
2881                 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2882                 address->video_progressive.luma_addr.low_part =
2883                         lower_32_bits(afb->address);
2884                 address->video_progressive.luma_addr.high_part =
2885                         upper_32_bits(afb->address);
2886                 address->video_progressive.chroma_addr.low_part =
2887                         lower_32_bits(chroma_addr);
2888                 address->video_progressive.chroma_addr.high_part =
2889                         upper_32_bits(chroma_addr);
2890         }
2891
2892         /* Fill GFX8 params */
2893         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2894                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2895
2896                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2897                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2898                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2899                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2900                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2901
2902                 /* XXX fix me for VI */
2903                 tiling_info->gfx8.num_banks = num_banks;
2904                 tiling_info->gfx8.array_mode =
2905                                 DC_ARRAY_2D_TILED_THIN1;
2906                 tiling_info->gfx8.tile_split = tile_split;
2907                 tiling_info->gfx8.bank_width = bankw;
2908                 tiling_info->gfx8.bank_height = bankh;
2909                 tiling_info->gfx8.tile_aspect = mtaspect;
2910                 tiling_info->gfx8.tile_mode =
2911                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2912         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2913                         == DC_ARRAY_1D_TILED_THIN1) {
2914                 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2915         }
2916
2917         tiling_info->gfx8.pipe_config =
2918                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2919
2920         if (adev->asic_type == CHIP_VEGA10 ||
2921             adev->asic_type == CHIP_VEGA12 ||
2922             adev->asic_type == CHIP_VEGA20 ||
2923 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2924             adev->asic_type == CHIP_NAVI10 ||
2925             adev->asic_type == CHIP_NAVI14 ||
2926             adev->asic_type == CHIP_NAVI12 ||
2927 #endif
2928 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2929             adev->asic_type == CHIP_RENOIR ||
2930 #endif
2931             adev->asic_type == CHIP_RAVEN) {
2932                 /* Fill GFX9 params */
2933                 tiling_info->gfx9.num_pipes =
2934                         adev->gfx.config.gb_addr_config_fields.num_pipes;
2935                 tiling_info->gfx9.num_banks =
2936                         adev->gfx.config.gb_addr_config_fields.num_banks;
2937                 tiling_info->gfx9.pipe_interleave =
2938                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2939                 tiling_info->gfx9.num_shader_engines =
2940                         adev->gfx.config.gb_addr_config_fields.num_se;
2941                 tiling_info->gfx9.max_compressed_frags =
2942                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2943                 tiling_info->gfx9.num_rb_per_se =
2944                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2945                 tiling_info->gfx9.swizzle =
2946                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2947                 tiling_info->gfx9.shaderEnable = 1;
2948
2949                 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
2950                                                 plane_size, tiling_info,
2951                                                 tiling_flags, dcc, address);
2952                 if (ret)
2953                         return ret;
2954         }
2955
2956         return 0;
2957 }
2958
2959 static void
2960 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
2961                                bool *per_pixel_alpha, bool *global_alpha,
2962                                int *global_alpha_value)
2963 {
2964         *per_pixel_alpha = false;
2965         *global_alpha = false;
2966         *global_alpha_value = 0xff;
2967
2968         if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2969                 return;
2970
2971         if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2972                 static const uint32_t alpha_formats[] = {
2973                         DRM_FORMAT_ARGB8888,
2974                         DRM_FORMAT_RGBA8888,
2975                         DRM_FORMAT_ABGR8888,
2976                 };
2977                 uint32_t format = plane_state->fb->format->format;
2978                 unsigned int i;
2979
2980                 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2981                         if (format == alpha_formats[i]) {
2982                                 *per_pixel_alpha = true;
2983                                 break;
2984                         }
2985                 }
2986         }
2987
2988         if (plane_state->alpha < 0xffff) {
2989                 *global_alpha = true;
2990                 *global_alpha_value = plane_state->alpha >> 8;
2991         }
2992 }
2993
2994 static int
2995 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
2996                             const enum surface_pixel_format format,
2997                             enum dc_color_space *color_space)
2998 {
2999         bool full_range;
3000
3001         *color_space = COLOR_SPACE_SRGB;
3002
3003         /* DRM color properties only affect non-RGB formats. */
3004         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
3005                 return 0;
3006
3007         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
3008
3009         switch (plane_state->color_encoding) {
3010         case DRM_COLOR_YCBCR_BT601:
3011                 if (full_range)
3012                         *color_space = COLOR_SPACE_YCBCR601;
3013                 else
3014                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
3015                 break;
3016
3017         case DRM_COLOR_YCBCR_BT709:
3018                 if (full_range)
3019                         *color_space = COLOR_SPACE_YCBCR709;
3020                 else
3021                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
3022                 break;
3023
3024         case DRM_COLOR_YCBCR_BT2020:
3025                 if (full_range)
3026                         *color_space = COLOR_SPACE_2020_YCBCR;
3027                 else
3028                         return -EINVAL;
3029                 break;
3030
3031         default:
3032                 return -EINVAL;
3033         }
3034
3035         return 0;
3036 }
3037
3038 static int
3039 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
3040                             const struct drm_plane_state *plane_state,
3041                             const uint64_t tiling_flags,
3042                             struct dc_plane_info *plane_info,
3043                             struct dc_plane_address *address)
3044 {
3045         const struct drm_framebuffer *fb = plane_state->fb;
3046         const struct amdgpu_framebuffer *afb =
3047                 to_amdgpu_framebuffer(plane_state->fb);
3048         struct drm_format_name_buf format_name;
3049         int ret;
3050
3051         memset(plane_info, 0, sizeof(*plane_info));
3052
3053         switch (fb->format->format) {
3054         case DRM_FORMAT_C8:
3055                 plane_info->format =
3056                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
3057                 break;
3058         case DRM_FORMAT_RGB565:
3059                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
3060                 break;
3061         case DRM_FORMAT_XRGB8888:
3062         case DRM_FORMAT_ARGB8888:
3063                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
3064                 break;
3065         case DRM_FORMAT_XRGB2101010:
3066         case DRM_FORMAT_ARGB2101010:
3067                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
3068                 break;
3069         case DRM_FORMAT_XBGR2101010:
3070         case DRM_FORMAT_ABGR2101010:
3071                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
3072                 break;
3073         case DRM_FORMAT_XBGR8888:
3074         case DRM_FORMAT_ABGR8888:
3075                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
3076                 break;
3077         case DRM_FORMAT_NV21:
3078                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
3079                 break;
3080         case DRM_FORMAT_NV12:
3081                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
3082                 break;
3083         default:
3084                 DRM_ERROR(
3085                         "Unsupported screen format %s\n",
3086                         drm_get_format_name(fb->format->format, &format_name));
3087                 return -EINVAL;
3088         }
3089
3090         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
3091         case DRM_MODE_ROTATE_0:
3092                 plane_info->rotation = ROTATION_ANGLE_0;
3093                 break;
3094         case DRM_MODE_ROTATE_90:
3095                 plane_info->rotation = ROTATION_ANGLE_90;
3096                 break;
3097         case DRM_MODE_ROTATE_180:
3098                 plane_info->rotation = ROTATION_ANGLE_180;
3099                 break;
3100         case DRM_MODE_ROTATE_270:
3101                 plane_info->rotation = ROTATION_ANGLE_270;
3102                 break;
3103         default:
3104                 plane_info->rotation = ROTATION_ANGLE_0;
3105                 break;
3106         }
3107
3108         plane_info->visible = true;
3109         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
3110
3111         plane_info->layer_index = 0;
3112
3113         ret = fill_plane_color_attributes(plane_state, plane_info->format,
3114                                           &plane_info->color_space);
3115         if (ret)
3116                 return ret;
3117
3118         ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
3119                                            plane_info->rotation, tiling_flags,
3120                                            &plane_info->tiling_info,
3121                                            &plane_info->plane_size,
3122                                            &plane_info->dcc, address);
3123         if (ret)
3124                 return ret;
3125
3126         fill_blending_from_plane_state(
3127                 plane_state, &plane_info->per_pixel_alpha,
3128                 &plane_info->global_alpha, &plane_info->global_alpha_value);
3129
3130         return 0;
3131 }
3132
3133 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
3134                                     struct dc_plane_state *dc_plane_state,
3135                                     struct drm_plane_state *plane_state,
3136                                     struct drm_crtc_state *crtc_state)
3137 {
3138         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
3139         const struct amdgpu_framebuffer *amdgpu_fb =
3140                 to_amdgpu_framebuffer(plane_state->fb);
3141         struct dc_scaling_info scaling_info;
3142         struct dc_plane_info plane_info;
3143         uint64_t tiling_flags;
3144         int ret;
3145
3146         ret = fill_dc_scaling_info(plane_state, &scaling_info);
3147         if (ret)
3148                 return ret;
3149
3150         dc_plane_state->src_rect = scaling_info.src_rect;
3151         dc_plane_state->dst_rect = scaling_info.dst_rect;
3152         dc_plane_state->clip_rect = scaling_info.clip_rect;
3153         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
3154
3155         ret = get_fb_info(amdgpu_fb, &tiling_flags);
3156         if (ret)
3157                 return ret;
3158
3159         ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3160                                           &plane_info,
3161                                           &dc_plane_state->address);
3162         if (ret)
3163                 return ret;
3164
3165         dc_plane_state->format = plane_info.format;
3166         dc_plane_state->color_space = plane_info.color_space;
3167         dc_plane_state->format = plane_info.format;
3168         dc_plane_state->plane_size = plane_info.plane_size;
3169         dc_plane_state->rotation = plane_info.rotation;
3170         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
3171         dc_plane_state->stereo_format = plane_info.stereo_format;
3172         dc_plane_state->tiling_info = plane_info.tiling_info;
3173         dc_plane_state->visible = plane_info.visible;
3174         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
3175         dc_plane_state->global_alpha = plane_info.global_alpha;
3176         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
3177         dc_plane_state->dcc = plane_info.dcc;
3178         dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
3179
3180         /*
3181          * Always set input transfer function, since plane state is refreshed
3182          * every time.
3183          */
3184         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
3185         if (ret)
3186                 return ret;
3187
3188         return 0;
3189 }
3190
3191 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
3192                                            const struct dm_connector_state *dm_state,
3193                                            struct dc_stream_state *stream)
3194 {
3195         enum amdgpu_rmx_type rmx_type;
3196
3197         struct rect src = { 0 }; /* viewport in composition space*/
3198         struct rect dst = { 0 }; /* stream addressable area */
3199
3200         /* no mode. nothing to be done */
3201         if (!mode)
3202                 return;
3203
3204         /* Full screen scaling by default */
3205         src.width = mode->hdisplay;
3206         src.height = mode->vdisplay;
3207         dst.width = stream->timing.h_addressable;
3208         dst.height = stream->timing.v_addressable;
3209
3210         if (dm_state) {
3211                 rmx_type = dm_state->scaling;
3212                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
3213                         if (src.width * dst.height <
3214                                         src.height * dst.width) {
3215                                 /* height needs less upscaling/more downscaling */
3216                                 dst.width = src.width *
3217                                                 dst.height / src.height;
3218                         } else {
3219                                 /* width needs less upscaling/more downscaling */
3220                                 dst.height = src.height *
3221                                                 dst.width / src.width;
3222                         }
3223                 } else if (rmx_type == RMX_CENTER) {
3224                         dst = src;
3225                 }
3226
3227                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
3228                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
3229
3230                 if (dm_state->underscan_enable) {
3231                         dst.x += dm_state->underscan_hborder / 2;
3232                         dst.y += dm_state->underscan_vborder / 2;
3233                         dst.width -= dm_state->underscan_hborder;
3234                         dst.height -= dm_state->underscan_vborder;
3235                 }
3236         }
3237
3238         stream->src = src;
3239         stream->dst = dst;
3240
3241         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
3242                         dst.x, dst.y, dst.width, dst.height);
3243
3244 }
3245
3246 static enum dc_color_depth
3247 convert_color_depth_from_display_info(const struct drm_connector *connector,
3248                                       const struct drm_connector_state *state)
3249 {
3250         uint8_t bpc = (uint8_t)connector->display_info.bpc;
3251
3252         /* Assume 8 bpc by default if no bpc is specified. */
3253         bpc = bpc ? bpc : 8;
3254
3255         if (!state)
3256                 state = connector->state;
3257
3258         if (state) {
3259                 /*
3260                  * Cap display bpc based on the user requested value.
3261                  *
3262                  * The value for state->max_bpc may not correctly updated
3263                  * depending on when the connector gets added to the state
3264                  * or if this was called outside of atomic check, so it
3265                  * can't be used directly.
3266                  */
3267                 bpc = min(bpc, state->max_requested_bpc);
3268
3269                 /* Round down to the nearest even number. */
3270                 bpc = bpc - (bpc & 1);
3271         }
3272
3273         switch (bpc) {
3274         case 0:
3275                 /*
3276                  * Temporary Work around, DRM doesn't parse color depth for
3277                  * EDID revision before 1.4
3278                  * TODO: Fix edid parsing
3279                  */
3280                 return COLOR_DEPTH_888;
3281         case 6:
3282                 return COLOR_DEPTH_666;
3283         case 8:
3284                 return COLOR_DEPTH_888;
3285         case 10:
3286                 return COLOR_DEPTH_101010;
3287         case 12:
3288                 return COLOR_DEPTH_121212;
3289         case 14:
3290                 return COLOR_DEPTH_141414;
3291         case 16:
3292                 return COLOR_DEPTH_161616;
3293         default:
3294                 return COLOR_DEPTH_UNDEFINED;
3295         }
3296 }
3297
3298 static enum dc_aspect_ratio
3299 get_aspect_ratio(const struct drm_display_mode *mode_in)
3300 {
3301         /* 1-1 mapping, since both enums follow the HDMI spec. */
3302         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
3303 }
3304
3305 static enum dc_color_space
3306 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
3307 {
3308         enum dc_color_space color_space = COLOR_SPACE_SRGB;
3309
3310         switch (dc_crtc_timing->pixel_encoding) {
3311         case PIXEL_ENCODING_YCBCR422:
3312         case PIXEL_ENCODING_YCBCR444:
3313         case PIXEL_ENCODING_YCBCR420:
3314         {
3315                 /*
3316                  * 27030khz is the separation point between HDTV and SDTV
3317                  * according to HDMI spec, we use YCbCr709 and YCbCr601
3318                  * respectively
3319                  */
3320                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
3321                         if (dc_crtc_timing->flags.Y_ONLY)
3322                                 color_space =
3323                                         COLOR_SPACE_YCBCR709_LIMITED;
3324                         else
3325                                 color_space = COLOR_SPACE_YCBCR709;
3326                 } else {
3327                         if (dc_crtc_timing->flags.Y_ONLY)
3328                                 color_space =
3329                                         COLOR_SPACE_YCBCR601_LIMITED;
3330                         else
3331                                 color_space = COLOR_SPACE_YCBCR601;
3332                 }
3333
3334         }
3335         break;
3336         case PIXEL_ENCODING_RGB:
3337                 color_space = COLOR_SPACE_SRGB;
3338                 break;
3339
3340         default:
3341                 WARN_ON(1);
3342                 break;
3343         }
3344
3345         return color_space;
3346 }
3347
3348 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
3349 {
3350         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3351                 return;
3352
3353         timing_out->display_color_depth--;
3354 }
3355
3356 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
3357                                                 const struct drm_display_info *info)
3358 {
3359         int normalized_clk;
3360         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3361                 return;
3362         do {
3363                 normalized_clk = timing_out->pix_clk_100hz / 10;
3364                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3365                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3366                         normalized_clk /= 2;
3367                 /* Adjusting pix clock following on HDMI spec based on colour depth */
3368                 switch (timing_out->display_color_depth) {
3369                 case COLOR_DEPTH_101010:
3370                         normalized_clk = (normalized_clk * 30) / 24;
3371                         break;
3372                 case COLOR_DEPTH_121212:
3373                         normalized_clk = (normalized_clk * 36) / 24;
3374                         break;
3375                 case COLOR_DEPTH_161616:
3376                         normalized_clk = (normalized_clk * 48) / 24;
3377                         break;
3378                 default:
3379                         return;
3380                 }
3381                 if (normalized_clk <= info->max_tmds_clock)
3382                         return;
3383                 reduce_mode_colour_depth(timing_out);
3384
3385         } while (timing_out->display_color_depth > COLOR_DEPTH_888);
3386
3387 }
3388
3389 static void fill_stream_properties_from_drm_display_mode(
3390         struct dc_stream_state *stream,
3391         const struct drm_display_mode *mode_in,
3392         const struct drm_connector *connector,
3393         const struct drm_connector_state *connector_state,
3394         const struct dc_stream_state *old_stream)
3395 {
3396         struct dc_crtc_timing *timing_out = &stream->timing;
3397         const struct drm_display_info *info = &connector->display_info;
3398         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3399         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
3400
3401         timing_out->h_border_left = 0;
3402         timing_out->h_border_right = 0;
3403         timing_out->v_border_top = 0;
3404         timing_out->v_border_bottom = 0;
3405         /* TODO: un-hardcode */
3406         if (drm_mode_is_420_only(info, mode_in)
3407                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3408                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3409         else if (drm_mode_is_420_also(info, mode_in)
3410                         && aconnector->force_yuv420_output)
3411                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3412         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
3413                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3414                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3415         else
3416                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3417
3418         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3419         timing_out->display_color_depth = convert_color_depth_from_display_info(
3420                 connector, connector_state);
3421         timing_out->scan_type = SCANNING_TYPE_NODATA;
3422         timing_out->hdmi_vic = 0;
3423
3424         if(old_stream) {
3425                 timing_out->vic = old_stream->timing.vic;
3426                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3427                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3428         } else {
3429                 timing_out->vic = drm_match_cea_mode(mode_in);
3430                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3431                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3432                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3433                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3434         }
3435
3436         timing_out->h_addressable = mode_in->crtc_hdisplay;
3437         timing_out->h_total = mode_in->crtc_htotal;
3438         timing_out->h_sync_width =
3439                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3440         timing_out->h_front_porch =
3441                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3442         timing_out->v_total = mode_in->crtc_vtotal;
3443         timing_out->v_addressable = mode_in->crtc_vdisplay;
3444         timing_out->v_front_porch =
3445                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3446         timing_out->v_sync_width =
3447                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
3448         timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
3449         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
3450
3451         stream->output_color_space = get_output_color_space(timing_out);
3452
3453         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3454         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
3455         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3456                 adjust_colour_depth_from_display_info(timing_out, info);
3457 }
3458
3459 static void fill_audio_info(struct audio_info *audio_info,
3460                             const struct drm_connector *drm_connector,
3461                             const struct dc_sink *dc_sink)
3462 {
3463         int i = 0;
3464         int cea_revision = 0;
3465         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3466
3467         audio_info->manufacture_id = edid_caps->manufacturer_id;
3468         audio_info->product_id = edid_caps->product_id;
3469
3470         cea_revision = drm_connector->display_info.cea_rev;
3471
3472         strscpy(audio_info->display_name,
3473                 edid_caps->display_name,
3474                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
3475
3476         if (cea_revision >= 3) {
3477                 audio_info->mode_count = edid_caps->audio_mode_count;
3478
3479                 for (i = 0; i < audio_info->mode_count; ++i) {
3480                         audio_info->modes[i].format_code =
3481                                         (enum audio_format_code)
3482                                         (edid_caps->audio_modes[i].format_code);
3483                         audio_info->modes[i].channel_count =
3484                                         edid_caps->audio_modes[i].channel_count;
3485                         audio_info->modes[i].sample_rates.all =
3486                                         edid_caps->audio_modes[i].sample_rate;
3487                         audio_info->modes[i].sample_size =
3488                                         edid_caps->audio_modes[i].sample_size;
3489                 }
3490         }
3491
3492         audio_info->flags.all = edid_caps->speaker_flags;
3493
3494         /* TODO: We only check for the progressive mode, check for interlace mode too */
3495         if (drm_connector->latency_present[0]) {
3496                 audio_info->video_latency = drm_connector->video_latency[0];
3497                 audio_info->audio_latency = drm_connector->audio_latency[0];
3498         }
3499
3500         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3501
3502 }
3503
3504 static void
3505 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3506                                       struct drm_display_mode *dst_mode)
3507 {
3508         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3509         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3510         dst_mode->crtc_clock = src_mode->crtc_clock;
3511         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3512         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
3513         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
3514         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3515         dst_mode->crtc_htotal = src_mode->crtc_htotal;
3516         dst_mode->crtc_hskew = src_mode->crtc_hskew;
3517         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3518         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3519         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3520         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3521         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3522 }
3523
3524 static void
3525 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3526                                         const struct drm_display_mode *native_mode,
3527                                         bool scale_enabled)
3528 {
3529         if (scale_enabled) {
3530                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3531         } else if (native_mode->clock == drm_mode->clock &&
3532                         native_mode->htotal == drm_mode->htotal &&
3533                         native_mode->vtotal == drm_mode->vtotal) {
3534                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3535         } else {
3536                 /* no scaling nor amdgpu inserted, no need to patch */
3537         }
3538 }
3539
3540 static struct dc_sink *
3541 create_fake_sink(struct amdgpu_dm_connector *aconnector)
3542 {
3543         struct dc_sink_init_data sink_init_data = { 0 };
3544         struct dc_sink *sink = NULL;
3545         sink_init_data.link = aconnector->dc_link;
3546         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3547
3548         sink = dc_sink_create(&sink_init_data);
3549         if (!sink) {
3550                 DRM_ERROR("Failed to create sink!\n");
3551                 return NULL;
3552         }
3553         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
3554
3555         return sink;
3556 }
3557
3558 static void set_multisync_trigger_params(
3559                 struct dc_stream_state *stream)
3560 {
3561         if (stream->triggered_crtc_reset.enabled) {
3562                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3563                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3564         }
3565 }
3566
3567 static void set_master_stream(struct dc_stream_state *stream_set[],
3568                               int stream_count)
3569 {
3570         int j, highest_rfr = 0, master_stream = 0;
3571
3572         for (j = 0;  j < stream_count; j++) {
3573                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3574                         int refresh_rate = 0;
3575
3576                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
3577                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3578                         if (refresh_rate > highest_rfr) {
3579                                 highest_rfr = refresh_rate;
3580                                 master_stream = j;
3581                         }
3582                 }
3583         }
3584         for (j = 0;  j < stream_count; j++) {
3585                 if (stream_set[j])
3586                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3587         }
3588 }
3589
3590 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3591 {
3592         int i = 0;
3593
3594         if (context->stream_count < 2)
3595                 return;
3596         for (i = 0; i < context->stream_count ; i++) {
3597                 if (!context->streams[i])
3598                         continue;
3599                 /*
3600                  * TODO: add a function to read AMD VSDB bits and set
3601                  * crtc_sync_master.multi_sync_enabled flag
3602                  * For now it's set to false
3603                  */
3604                 set_multisync_trigger_params(context->streams[i]);
3605         }
3606         set_master_stream(context->streams, context->stream_count);
3607 }
3608
3609 static struct dc_stream_state *
3610 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3611                        const struct drm_display_mode *drm_mode,
3612                        const struct dm_connector_state *dm_state,
3613                        const struct dc_stream_state *old_stream)
3614 {
3615         struct drm_display_mode *preferred_mode = NULL;
3616         struct drm_connector *drm_connector;
3617         const struct drm_connector_state *con_state =
3618                 dm_state ? &dm_state->base : NULL;
3619         struct dc_stream_state *stream = NULL;
3620         struct drm_display_mode mode = *drm_mode;
3621         bool native_mode_found = false;
3622         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3623         int mode_refresh;
3624         int preferred_refresh = 0;
3625 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3626         struct dsc_dec_dpcd_caps dsc_caps;
3627         uint32_t link_bandwidth_kbps;
3628 #endif
3629
3630         struct dc_sink *sink = NULL;
3631         if (aconnector == NULL) {
3632                 DRM_ERROR("aconnector is NULL!\n");
3633                 return stream;
3634         }
3635
3636         drm_connector = &aconnector->base;
3637
3638         if (!aconnector->dc_sink) {
3639                 sink = create_fake_sink(aconnector);
3640                 if (!sink)
3641                         return stream;
3642         } else {
3643                 sink = aconnector->dc_sink;
3644                 dc_sink_retain(sink);
3645         }
3646
3647         stream = dc_create_stream_for_sink(sink);
3648
3649         if (stream == NULL) {
3650                 DRM_ERROR("Failed to create stream for sink!\n");
3651                 goto finish;
3652         }
3653
3654         stream->dm_stream_context = aconnector;
3655
3656         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3657                 /* Search for preferred mode */
3658                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3659                         native_mode_found = true;
3660                         break;
3661                 }
3662         }
3663         if (!native_mode_found)
3664                 preferred_mode = list_first_entry_or_null(
3665                                 &aconnector->base.modes,
3666                                 struct drm_display_mode,
3667                                 head);
3668
3669         mode_refresh = drm_mode_vrefresh(&mode);
3670
3671         if (preferred_mode == NULL) {
3672                 /*
3673                  * This may not be an error, the use case is when we have no
3674                  * usermode calls to reset and set mode upon hotplug. In this
3675                  * case, we call set mode ourselves to restore the previous mode
3676                  * and the modelist may not be filled in in time.
3677                  */
3678                 DRM_DEBUG_DRIVER("No preferred mode found\n");
3679         } else {
3680                 decide_crtc_timing_for_drm_display_mode(
3681                                 &mode, preferred_mode,
3682                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
3683                 preferred_refresh = drm_mode_vrefresh(preferred_mode);
3684         }
3685
3686         if (!dm_state)
3687                 drm_mode_set_crtcinfo(&mode, 0);
3688
3689         /*
3690         * If scaling is enabled and refresh rate didn't change
3691         * we copy the vic and polarities of the old timings
3692         */
3693         if (!scale || mode_refresh != preferred_refresh)
3694                 fill_stream_properties_from_drm_display_mode(stream,
3695                         &mode, &aconnector->base, con_state, NULL);
3696         else
3697                 fill_stream_properties_from_drm_display_mode(stream,
3698                         &mode, &aconnector->base, con_state, old_stream);
3699
3700 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3701         stream->timing.flags.DSC = 0;
3702
3703         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3704                 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3705                                       aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
3706                                       &dsc_caps);
3707                 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
3708                                                              dc_link_get_link_cap(aconnector->dc_link));
3709
3710                 if (dsc_caps.is_dsc_supported)
3711                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
3712                                                   &dsc_caps,
3713                                                   aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
3714                                                   link_bandwidth_kbps,
3715                                                   &stream->timing,
3716                                                   &stream->timing.dsc_cfg))
3717                                 stream->timing.flags.DSC = 1;
3718         }
3719 #endif
3720
3721         update_stream_scaling_settings(&mode, dm_state, stream);
3722
3723         fill_audio_info(
3724                 &stream->audio_info,
3725                 drm_connector,
3726                 sink);
3727
3728         update_stream_signal(stream, sink);
3729
3730 finish:
3731         dc_sink_release(sink);
3732
3733         return stream;
3734 }
3735
3736 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
3737 {
3738         drm_crtc_cleanup(crtc);
3739         kfree(crtc);
3740 }
3741
3742 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3743                                   struct drm_crtc_state *state)
3744 {
3745         struct dm_crtc_state *cur = to_dm_crtc_state(state);
3746
3747         /* TODO Destroy dc_stream objects are stream object is flattened */
3748         if (cur->stream)
3749                 dc_stream_release(cur->stream);
3750
3751
3752         __drm_atomic_helper_crtc_destroy_state(state);
3753
3754
3755         kfree(state);
3756 }
3757
3758 static void dm_crtc_reset_state(struct drm_crtc *crtc)
3759 {
3760         struct dm_crtc_state *state;
3761
3762         if (crtc->state)
3763                 dm_crtc_destroy_state(crtc, crtc->state);
3764
3765         state = kzalloc(sizeof(*state), GFP_KERNEL);
3766         if (WARN_ON(!state))
3767                 return;
3768
3769         crtc->state = &state->base;
3770         crtc->state->crtc = crtc;
3771
3772 }
3773
3774 static struct drm_crtc_state *
3775 dm_crtc_duplicate_state(struct drm_crtc *crtc)
3776 {
3777         struct dm_crtc_state *state, *cur;
3778
3779         cur = to_dm_crtc_state(crtc->state);
3780
3781         if (WARN_ON(!crtc->state))
3782                 return NULL;
3783
3784         state = kzalloc(sizeof(*state), GFP_KERNEL);
3785         if (!state)
3786                 return NULL;
3787
3788         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3789
3790         if (cur->stream) {
3791                 state->stream = cur->stream;
3792                 dc_stream_retain(state->stream);
3793         }
3794
3795         state->active_planes = cur->active_planes;
3796         state->interrupts_enabled = cur->interrupts_enabled;
3797         state->vrr_params = cur->vrr_params;
3798         state->vrr_infopacket = cur->vrr_infopacket;
3799         state->abm_level = cur->abm_level;
3800         state->vrr_supported = cur->vrr_supported;
3801         state->freesync_config = cur->freesync_config;
3802         state->crc_src = cur->crc_src;
3803         state->cm_has_degamma = cur->cm_has_degamma;
3804         state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
3805
3806         /* TODO Duplicate dc_stream after objects are stream object is flattened */
3807
3808         return &state->base;
3809 }
3810
3811 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3812 {
3813         enum dc_irq_source irq_source;
3814         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3815         struct amdgpu_device *adev = crtc->dev->dev_private;
3816         int rc;
3817
3818         irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3819
3820         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3821
3822         DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3823                          acrtc->crtc_id, enable ? "en" : "dis", rc);
3824         return rc;
3825 }
3826
3827 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3828 {
3829         enum dc_irq_source irq_source;
3830         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3831         struct amdgpu_device *adev = crtc->dev->dev_private;
3832         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3833         int rc = 0;
3834
3835         if (enable) {
3836                 /* vblank irq on -> Only need vupdate irq in vrr mode */
3837                 if (amdgpu_dm_vrr_active(acrtc_state))
3838                         rc = dm_set_vupdate_irq(crtc, true);
3839         } else {
3840                 /* vblank irq off -> vupdate irq off */
3841                 rc = dm_set_vupdate_irq(crtc, false);
3842         }
3843
3844         if (rc)
3845                 return rc;
3846
3847         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3848         return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3849 }
3850
3851 static int dm_enable_vblank(struct drm_crtc *crtc)
3852 {
3853         return dm_set_vblank(crtc, true);
3854 }
3855
3856 static void dm_disable_vblank(struct drm_crtc *crtc)
3857 {
3858         dm_set_vblank(crtc, false);
3859 }
3860
3861 /* Implemented only the options currently availible for the driver */
3862 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3863         .reset = dm_crtc_reset_state,
3864         .destroy = amdgpu_dm_crtc_destroy,
3865         .gamma_set = drm_atomic_helper_legacy_gamma_set,
3866         .set_config = drm_atomic_helper_set_config,
3867         .page_flip = drm_atomic_helper_page_flip,
3868         .atomic_duplicate_state = dm_crtc_duplicate_state,
3869         .atomic_destroy_state = dm_crtc_destroy_state,
3870         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3871         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
3872         .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
3873         .enable_vblank = dm_enable_vblank,
3874         .disable_vblank = dm_disable_vblank,
3875 };
3876
3877 static enum drm_connector_status
3878 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3879 {
3880         bool connected;
3881         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3882
3883         /*
3884          * Notes:
3885          * 1. This interface is NOT called in context of HPD irq.
3886          * 2. This interface *is called* in context of user-mode ioctl. Which
3887          * makes it a bad place for *any* MST-related activity.
3888          */
3889
3890         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3891             !aconnector->fake_enable)
3892                 connected = (aconnector->dc_sink != NULL);
3893         else
3894                 connected = (aconnector->base.force == DRM_FORCE_ON);
3895
3896         return (connected ? connector_status_connected :
3897                         connector_status_disconnected);
3898 }
3899
3900 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3901                                             struct drm_connector_state *connector_state,
3902                                             struct drm_property *property,
3903                                             uint64_t val)
3904 {
3905         struct drm_device *dev = connector->dev;
3906         struct amdgpu_device *adev = dev->dev_private;
3907         struct dm_connector_state *dm_old_state =
3908                 to_dm_connector_state(connector->state);
3909         struct dm_connector_state *dm_new_state =
3910                 to_dm_connector_state(connector_state);
3911
3912         int ret = -EINVAL;
3913
3914         if (property == dev->mode_config.scaling_mode_property) {
3915                 enum amdgpu_rmx_type rmx_type;
3916
3917                 switch (val) {
3918                 case DRM_MODE_SCALE_CENTER:
3919                         rmx_type = RMX_CENTER;
3920                         break;
3921                 case DRM_MODE_SCALE_ASPECT:
3922                         rmx_type = RMX_ASPECT;
3923                         break;
3924                 case DRM_MODE_SCALE_FULLSCREEN:
3925                         rmx_type = RMX_FULL;
3926                         break;
3927                 case DRM_MODE_SCALE_NONE:
3928                 default:
3929                         rmx_type = RMX_OFF;
3930                         break;
3931                 }
3932
3933                 if (dm_old_state->scaling == rmx_type)
3934                         return 0;
3935
3936                 dm_new_state->scaling = rmx_type;
3937                 ret = 0;
3938         } else if (property == adev->mode_info.underscan_hborder_property) {
3939                 dm_new_state->underscan_hborder = val;
3940                 ret = 0;
3941         } else if (property == adev->mode_info.underscan_vborder_property) {
3942                 dm_new_state->underscan_vborder = val;
3943                 ret = 0;
3944         } else if (property == adev->mode_info.underscan_property) {
3945                 dm_new_state->underscan_enable = val;
3946                 ret = 0;
3947         } else if (property == adev->mode_info.abm_level_property) {
3948                 dm_new_state->abm_level = val;
3949                 ret = 0;
3950         }
3951
3952         return ret;
3953 }
3954
3955 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3956                                             const struct drm_connector_state *state,
3957                                             struct drm_property *property,
3958                                             uint64_t *val)
3959 {
3960         struct drm_device *dev = connector->dev;
3961         struct amdgpu_device *adev = dev->dev_private;
3962         struct dm_connector_state *dm_state =
3963                 to_dm_connector_state(state);
3964         int ret = -EINVAL;
3965
3966         if (property == dev->mode_config.scaling_mode_property) {
3967                 switch (dm_state->scaling) {
3968                 case RMX_CENTER:
3969                         *val = DRM_MODE_SCALE_CENTER;
3970                         break;
3971                 case RMX_ASPECT:
3972                         *val = DRM_MODE_SCALE_ASPECT;
3973                         break;
3974                 case RMX_FULL:
3975                         *val = DRM_MODE_SCALE_FULLSCREEN;
3976                         break;
3977                 case RMX_OFF:
3978                 default:
3979                         *val = DRM_MODE_SCALE_NONE;
3980                         break;
3981                 }
3982                 ret = 0;
3983         } else if (property == adev->mode_info.underscan_hborder_property) {
3984                 *val = dm_state->underscan_hborder;
3985                 ret = 0;
3986         } else if (property == adev->mode_info.underscan_vborder_property) {
3987                 *val = dm_state->underscan_vborder;
3988                 ret = 0;
3989         } else if (property == adev->mode_info.underscan_property) {
3990                 *val = dm_state->underscan_enable;
3991                 ret = 0;
3992         } else if (property == adev->mode_info.abm_level_property) {
3993                 *val = dm_state->abm_level;
3994                 ret = 0;
3995         }
3996
3997         return ret;
3998 }
3999
4000 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
4001 {
4002         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
4003
4004         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
4005 }
4006
4007 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
4008 {
4009         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4010         const struct dc_link *link = aconnector->dc_link;
4011         struct amdgpu_device *adev = connector->dev->dev_private;
4012         struct amdgpu_display_manager *dm = &adev->dm;
4013
4014 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
4015         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
4016
4017         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4018             link->type != dc_connection_none &&
4019             dm->backlight_dev) {
4020                 backlight_device_unregister(dm->backlight_dev);
4021                 dm->backlight_dev = NULL;
4022         }
4023 #endif
4024
4025         if (aconnector->dc_em_sink)
4026                 dc_sink_release(aconnector->dc_em_sink);
4027         aconnector->dc_em_sink = NULL;
4028         if (aconnector->dc_sink)
4029                 dc_sink_release(aconnector->dc_sink);
4030         aconnector->dc_sink = NULL;
4031
4032         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
4033         drm_connector_unregister(connector);
4034         drm_connector_cleanup(connector);
4035         if (aconnector->i2c) {
4036                 i2c_del_adapter(&aconnector->i2c->base);
4037                 kfree(aconnector->i2c);
4038         }
4039
4040         kfree(connector);
4041 }
4042
4043 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
4044 {
4045         struct dm_connector_state *state =
4046                 to_dm_connector_state(connector->state);
4047
4048         if (connector->state)
4049                 __drm_atomic_helper_connector_destroy_state(connector->state);
4050
4051         kfree(state);
4052
4053         state = kzalloc(sizeof(*state), GFP_KERNEL);
4054
4055         if (state) {
4056                 state->scaling = RMX_OFF;
4057                 state->underscan_enable = false;
4058                 state->underscan_hborder = 0;
4059                 state->underscan_vborder = 0;
4060                 state->base.max_requested_bpc = 8;
4061
4062                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4063                         state->abm_level = amdgpu_dm_abm_level;
4064
4065                 __drm_atomic_helper_connector_reset(connector, &state->base);
4066         }
4067 }
4068
4069 struct drm_connector_state *
4070 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
4071 {
4072         struct dm_connector_state *state =
4073                 to_dm_connector_state(connector->state);
4074
4075         struct dm_connector_state *new_state =
4076                         kmemdup(state, sizeof(*state), GFP_KERNEL);
4077
4078         if (!new_state)
4079                 return NULL;
4080
4081         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
4082
4083         new_state->freesync_capable = state->freesync_capable;
4084         new_state->abm_level = state->abm_level;
4085         new_state->scaling = state->scaling;
4086         new_state->underscan_enable = state->underscan_enable;
4087         new_state->underscan_hborder = state->underscan_hborder;
4088         new_state->underscan_vborder = state->underscan_vborder;
4089
4090         return &new_state->base;
4091 }
4092
4093 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
4094         .reset = amdgpu_dm_connector_funcs_reset,
4095         .detect = amdgpu_dm_connector_detect,
4096         .fill_modes = drm_helper_probe_single_connector_modes,
4097         .destroy = amdgpu_dm_connector_destroy,
4098         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
4099         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4100         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
4101         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
4102         .early_unregister = amdgpu_dm_connector_unregister
4103 };
4104
4105 static int get_modes(struct drm_connector *connector)
4106 {
4107         return amdgpu_dm_connector_get_modes(connector);
4108 }
4109
4110 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
4111 {
4112         struct dc_sink_init_data init_params = {
4113                         .link = aconnector->dc_link,
4114                         .sink_signal = SIGNAL_TYPE_VIRTUAL
4115         };
4116         struct edid *edid;
4117
4118         if (!aconnector->base.edid_blob_ptr) {
4119                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
4120                                 aconnector->base.name);
4121
4122                 aconnector->base.force = DRM_FORCE_OFF;
4123                 aconnector->base.override_edid = false;
4124                 return;
4125         }
4126
4127         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
4128
4129         aconnector->edid = edid;
4130
4131         aconnector->dc_em_sink = dc_link_add_remote_sink(
4132                 aconnector->dc_link,
4133                 (uint8_t *)edid,
4134                 (edid->extensions + 1) * EDID_LENGTH,
4135                 &init_params);
4136
4137         if (aconnector->base.force == DRM_FORCE_ON) {
4138                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
4139                 aconnector->dc_link->local_sink :
4140                 aconnector->dc_em_sink;
4141                 dc_sink_retain(aconnector->dc_sink);
4142         }
4143 }
4144
4145 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
4146 {
4147         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
4148
4149         /*
4150          * In case of headless boot with force on for DP managed connector
4151          * Those settings have to be != 0 to get initial modeset
4152          */
4153         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4154                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
4155                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
4156         }
4157
4158
4159         aconnector->base.override_edid = true;
4160         create_eml_sink(aconnector);
4161 }
4162
4163 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
4164                                    struct drm_display_mode *mode)
4165 {
4166         int result = MODE_ERROR;
4167         struct dc_sink *dc_sink;
4168         struct amdgpu_device *adev = connector->dev->dev_private;
4169         /* TODO: Unhardcode stream count */
4170         struct dc_stream_state *stream;
4171         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4172         enum dc_status dc_result = DC_OK;
4173
4174         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
4175                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
4176                 return result;
4177
4178         /*
4179          * Only run this the first time mode_valid is called to initilialize
4180          * EDID mgmt
4181          */
4182         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
4183                 !aconnector->dc_em_sink)
4184                 handle_edid_mgmt(aconnector);
4185
4186         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
4187
4188         if (dc_sink == NULL) {
4189                 DRM_ERROR("dc_sink is NULL!\n");
4190                 goto fail;
4191         }
4192
4193         stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
4194         if (stream == NULL) {
4195                 DRM_ERROR("Failed to create stream for sink!\n");
4196                 goto fail;
4197         }
4198
4199         dc_result = dc_validate_stream(adev->dm.dc, stream);
4200
4201         if (dc_result == DC_OK)
4202                 result = MODE_OK;
4203         else
4204                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
4205                               mode->vdisplay,
4206                               mode->hdisplay,
4207                               mode->clock,
4208                               dc_result);
4209
4210         dc_stream_release(stream);
4211
4212 fail:
4213         /* TODO: error handling*/
4214         return result;
4215 }
4216
4217 static int fill_hdr_info_packet(const struct drm_connector_state *state,
4218                                 struct dc_info_packet *out)
4219 {
4220         struct hdmi_drm_infoframe frame;
4221         unsigned char buf[30]; /* 26 + 4 */
4222         ssize_t len;
4223         int ret, i;
4224
4225         memset(out, 0, sizeof(*out));
4226
4227         if (!state->hdr_output_metadata)
4228                 return 0;
4229
4230         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
4231         if (ret)
4232                 return ret;
4233
4234         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
4235         if (len < 0)
4236                 return (int)len;
4237
4238         /* Static metadata is a fixed 26 bytes + 4 byte header. */
4239         if (len != 30)
4240                 return -EINVAL;
4241
4242         /* Prepare the infopacket for DC. */
4243         switch (state->connector->connector_type) {
4244         case DRM_MODE_CONNECTOR_HDMIA:
4245                 out->hb0 = 0x87; /* type */
4246                 out->hb1 = 0x01; /* version */
4247                 out->hb2 = 0x1A; /* length */
4248                 out->sb[0] = buf[3]; /* checksum */
4249                 i = 1;
4250                 break;
4251
4252         case DRM_MODE_CONNECTOR_DisplayPort:
4253         case DRM_MODE_CONNECTOR_eDP:
4254                 out->hb0 = 0x00; /* sdp id, zero */
4255                 out->hb1 = 0x87; /* type */
4256                 out->hb2 = 0x1D; /* payload len - 1 */
4257                 out->hb3 = (0x13 << 2); /* sdp version */
4258                 out->sb[0] = 0x01; /* version */
4259                 out->sb[1] = 0x1A; /* length */
4260                 i = 2;
4261                 break;
4262
4263         default:
4264                 return -EINVAL;
4265         }
4266
4267         memcpy(&out->sb[i], &buf[4], 26);
4268         out->valid = true;
4269
4270         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
4271                        sizeof(out->sb), false);
4272
4273         return 0;
4274 }
4275
4276 static bool
4277 is_hdr_metadata_different(const struct drm_connector_state *old_state,
4278                           const struct drm_connector_state *new_state)
4279 {
4280         struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
4281         struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
4282
4283         if (old_blob != new_blob) {
4284                 if (old_blob && new_blob &&
4285                     old_blob->length == new_blob->length)
4286                         return memcmp(old_blob->data, new_blob->data,
4287                                       old_blob->length);
4288
4289                 return true;
4290         }
4291
4292         return false;
4293 }
4294
4295 static int
4296 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
4297                                  struct drm_atomic_state *state)
4298 {
4299         struct drm_connector_state *new_con_state =
4300                 drm_atomic_get_new_connector_state(state, conn);
4301         struct drm_connector_state *old_con_state =
4302                 drm_atomic_get_old_connector_state(state, conn);
4303         struct drm_crtc *crtc = new_con_state->crtc;
4304         struct drm_crtc_state *new_crtc_state;
4305         int ret;
4306
4307         if (!crtc)
4308                 return 0;
4309
4310         if (is_hdr_metadata_different(old_con_state, new_con_state)) {
4311                 struct dc_info_packet hdr_infopacket;
4312
4313                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
4314                 if (ret)
4315                         return ret;
4316
4317                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
4318                 if (IS_ERR(new_crtc_state))
4319                         return PTR_ERR(new_crtc_state);
4320
4321                 /*
4322                  * DC considers the stream backends changed if the
4323                  * static metadata changes. Forcing the modeset also
4324                  * gives a simple way for userspace to switch from
4325                  * 8bpc to 10bpc when setting the metadata to enter
4326                  * or exit HDR.
4327                  *
4328                  * Changing the static metadata after it's been
4329                  * set is permissible, however. So only force a
4330                  * modeset if we're entering or exiting HDR.
4331                  */
4332                 new_crtc_state->mode_changed =
4333                         !old_con_state->hdr_output_metadata ||
4334                         !new_con_state->hdr_output_metadata;
4335         }
4336
4337         return 0;
4338 }
4339
4340 static const struct drm_connector_helper_funcs
4341 amdgpu_dm_connector_helper_funcs = {
4342         /*
4343          * If hotplugging a second bigger display in FB Con mode, bigger resolution
4344          * modes will be filtered by drm_mode_validate_size(), and those modes
4345          * are missing after user start lightdm. So we need to renew modes list.
4346          * in get_modes call back, not just return the modes count
4347          */
4348         .get_modes = get_modes,
4349         .mode_valid = amdgpu_dm_connector_mode_valid,
4350         .atomic_check = amdgpu_dm_connector_atomic_check,
4351 };
4352
4353 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4354 {
4355 }
4356
4357 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4358 {
4359         struct drm_device *dev = new_crtc_state->crtc->dev;
4360         struct drm_plane *plane;
4361
4362         drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4363                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4364                         return true;
4365         }
4366
4367         return false;
4368 }
4369
4370 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
4371 {
4372         struct drm_atomic_state *state = new_crtc_state->state;
4373         struct drm_plane *plane;
4374         int num_active = 0;
4375
4376         drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4377                 struct drm_plane_state *new_plane_state;
4378
4379                 /* Cursor planes are "fake". */
4380                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4381                         continue;
4382
4383                 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4384
4385                 if (!new_plane_state) {
4386                         /*
4387                          * The plane is enable on the CRTC and hasn't changed
4388                          * state. This means that it previously passed
4389                          * validation and is therefore enabled.
4390                          */
4391                         num_active += 1;
4392                         continue;
4393                 }
4394
4395                 /* We need a framebuffer to be considered enabled. */
4396                 num_active += (new_plane_state->fb != NULL);
4397         }
4398
4399         return num_active;
4400 }
4401
4402 /*
4403  * Sets whether interrupts should be enabled on a specific CRTC.
4404  * We require that the stream be enabled and that there exist active
4405  * DC planes on the stream.
4406  */
4407 static void
4408 dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4409                                struct drm_crtc_state *new_crtc_state)
4410 {
4411         struct dm_crtc_state *dm_new_crtc_state =
4412                 to_dm_crtc_state(new_crtc_state);
4413
4414         dm_new_crtc_state->active_planes = 0;
4415         dm_new_crtc_state->interrupts_enabled = false;
4416
4417         if (!dm_new_crtc_state->stream)
4418                 return;
4419
4420         dm_new_crtc_state->active_planes =
4421                 count_crtc_active_planes(new_crtc_state);
4422
4423         dm_new_crtc_state->interrupts_enabled =
4424                 dm_new_crtc_state->active_planes > 0;
4425 }
4426
4427 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4428                                        struct drm_crtc_state *state)
4429 {
4430         struct amdgpu_device *adev = crtc->dev->dev_private;
4431         struct dc *dc = adev->dm.dc;
4432         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4433         int ret = -EINVAL;
4434
4435         /*
4436          * Update interrupt state for the CRTC. This needs to happen whenever
4437          * the CRTC has changed or whenever any of its planes have changed.
4438          * Atomic check satisfies both of these requirements since the CRTC
4439          * is added to the state by DRM during drm_atomic_helper_check_planes.
4440          */
4441         dm_update_crtc_interrupt_state(crtc, state);
4442
4443         if (unlikely(!dm_crtc_state->stream &&
4444                      modeset_required(state, NULL, dm_crtc_state->stream))) {
4445                 WARN_ON(1);
4446                 return ret;
4447         }
4448
4449         /* In some use cases, like reset, no stream is attached */
4450         if (!dm_crtc_state->stream)
4451                 return 0;
4452
4453         /*
4454          * We want at least one hardware plane enabled to use
4455          * the stream with a cursor enabled.
4456          */
4457         if (state->enable && state->active &&
4458             does_crtc_have_active_cursor(state) &&
4459             dm_crtc_state->active_planes == 0)
4460                 return -EINVAL;
4461
4462         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
4463                 return 0;
4464
4465         return ret;
4466 }
4467
4468 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4469                                       const struct drm_display_mode *mode,
4470                                       struct drm_display_mode *adjusted_mode)
4471 {
4472         return true;
4473 }
4474
4475 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4476         .disable = dm_crtc_helper_disable,
4477         .atomic_check = dm_crtc_helper_atomic_check,
4478         .mode_fixup = dm_crtc_helper_mode_fixup
4479 };
4480
4481 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4482 {
4483
4484 }
4485
4486 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4487                                           struct drm_crtc_state *crtc_state,
4488                                           struct drm_connector_state *conn_state)
4489 {
4490         return 0;
4491 }
4492
4493 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4494         .disable = dm_encoder_helper_disable,
4495         .atomic_check = dm_encoder_helper_atomic_check
4496 };
4497
4498 static void dm_drm_plane_reset(struct drm_plane *plane)
4499 {
4500         struct dm_plane_state *amdgpu_state = NULL;
4501
4502         if (plane->state)
4503                 plane->funcs->atomic_destroy_state(plane, plane->state);
4504
4505         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
4506         WARN_ON(amdgpu_state == NULL);
4507
4508         if (amdgpu_state)
4509                 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
4510 }
4511
4512 static struct drm_plane_state *
4513 dm_drm_plane_duplicate_state(struct drm_plane *plane)
4514 {
4515         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4516
4517         old_dm_plane_state = to_dm_plane_state(plane->state);
4518         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4519         if (!dm_plane_state)
4520                 return NULL;
4521
4522         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4523
4524         if (old_dm_plane_state->dc_state) {
4525                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4526                 dc_plane_state_retain(dm_plane_state->dc_state);
4527         }
4528
4529         return &dm_plane_state->base;
4530 }
4531
4532 void dm_drm_plane_destroy_state(struct drm_plane *plane,
4533                                 struct drm_plane_state *state)
4534 {
4535         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4536
4537         if (dm_plane_state->dc_state)
4538                 dc_plane_state_release(dm_plane_state->dc_state);
4539
4540         drm_atomic_helper_plane_destroy_state(plane, state);
4541 }
4542
4543 static const struct drm_plane_funcs dm_plane_funcs = {
4544         .update_plane   = drm_atomic_helper_update_plane,
4545         .disable_plane  = drm_atomic_helper_disable_plane,
4546         .destroy        = drm_primary_helper_destroy,
4547         .reset = dm_drm_plane_reset,
4548         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
4549         .atomic_destroy_state = dm_drm_plane_destroy_state,
4550 };
4551
4552 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
4553                                       struct drm_plane_state *new_state)
4554 {
4555         struct amdgpu_framebuffer *afb;
4556         struct drm_gem_object *obj;
4557         struct amdgpu_device *adev;
4558         struct amdgpu_bo *rbo;
4559         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
4560         struct list_head list;
4561         struct ttm_validate_buffer tv;
4562         struct ww_acquire_ctx ticket;
4563         uint64_t tiling_flags;
4564         uint32_t domain;
4565         int r;
4566
4567         dm_plane_state_old = to_dm_plane_state(plane->state);
4568         dm_plane_state_new = to_dm_plane_state(new_state);
4569
4570         if (!new_state->fb) {
4571                 DRM_DEBUG_DRIVER("No FB bound\n");
4572                 return 0;
4573         }
4574
4575         afb = to_amdgpu_framebuffer(new_state->fb);
4576         obj = new_state->fb->obj[0];
4577         rbo = gem_to_amdgpu_bo(obj);
4578         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
4579         INIT_LIST_HEAD(&list);
4580
4581         tv.bo = &rbo->tbo;
4582         tv.num_shared = 1;
4583         list_add(&tv.head, &list);
4584
4585         r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true);
4586         if (r) {
4587                 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
4588                 return r;
4589         }
4590
4591         if (plane->type != DRM_PLANE_TYPE_CURSOR)
4592                 domain = amdgpu_display_supported_domains(adev, rbo->flags);
4593         else
4594                 domain = AMDGPU_GEM_DOMAIN_VRAM;
4595
4596         r = amdgpu_bo_pin(rbo, domain);
4597         if (unlikely(r != 0)) {
4598                 if (r != -ERESTARTSYS)
4599                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
4600                 ttm_eu_backoff_reservation(&ticket, &list);
4601                 return r;
4602         }
4603
4604         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
4605         if (unlikely(r != 0)) {
4606                 amdgpu_bo_unpin(rbo);
4607                 ttm_eu_backoff_reservation(&ticket, &list);
4608                 DRM_ERROR("%p bind failed\n", rbo);
4609                 return r;
4610         }
4611
4612         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
4613
4614         ttm_eu_backoff_reservation(&ticket, &list);
4615
4616         afb->address = amdgpu_bo_gpu_offset(rbo);
4617
4618         amdgpu_bo_ref(rbo);
4619
4620         if (dm_plane_state_new->dc_state &&
4621                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4622                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
4623
4624                 fill_plane_buffer_attributes(
4625                         adev, afb, plane_state->format, plane_state->rotation,
4626                         tiling_flags, &plane_state->tiling_info,
4627                         &plane_state->plane_size, &plane_state->dcc,
4628                         &plane_state->address);
4629         }
4630
4631         return 0;
4632 }
4633
4634 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4635                                        struct drm_plane_state *old_state)
4636 {
4637         struct amdgpu_bo *rbo;
4638         int r;
4639
4640         if (!old_state->fb)
4641                 return;
4642
4643         rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
4644         r = amdgpu_bo_reserve(rbo, false);
4645         if (unlikely(r)) {
4646                 DRM_ERROR("failed to reserve rbo before unpin\n");
4647                 return;
4648         }
4649
4650         amdgpu_bo_unpin(rbo);
4651         amdgpu_bo_unreserve(rbo);
4652         amdgpu_bo_unref(&rbo);
4653 }
4654
4655 static int dm_plane_atomic_check(struct drm_plane *plane,
4656                                  struct drm_plane_state *state)
4657 {
4658         struct amdgpu_device *adev = plane->dev->dev_private;
4659         struct dc *dc = adev->dm.dc;
4660         struct dm_plane_state *dm_plane_state;
4661         struct dc_scaling_info scaling_info;
4662         int ret;
4663
4664         dm_plane_state = to_dm_plane_state(state);
4665
4666         if (!dm_plane_state->dc_state)
4667                 return 0;
4668
4669         ret = fill_dc_scaling_info(state, &scaling_info);
4670         if (ret)
4671                 return ret;
4672
4673         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
4674                 return 0;
4675
4676         return -EINVAL;
4677 }
4678
4679 static int dm_plane_atomic_async_check(struct drm_plane *plane,
4680                                        struct drm_plane_state *new_plane_state)
4681 {
4682         /* Only support async updates on cursor planes. */
4683         if (plane->type != DRM_PLANE_TYPE_CURSOR)
4684                 return -EINVAL;
4685
4686         return 0;
4687 }
4688
4689 static void dm_plane_atomic_async_update(struct drm_plane *plane,
4690                                          struct drm_plane_state *new_state)
4691 {
4692         struct drm_plane_state *old_state =
4693                 drm_atomic_get_old_plane_state(new_state->state, plane);
4694
4695         swap(plane->state->fb, new_state->fb);
4696
4697         plane->state->src_x = new_state->src_x;
4698         plane->state->src_y = new_state->src_y;
4699         plane->state->src_w = new_state->src_w;
4700         plane->state->src_h = new_state->src_h;
4701         plane->state->crtc_x = new_state->crtc_x;
4702         plane->state->crtc_y = new_state->crtc_y;
4703         plane->state->crtc_w = new_state->crtc_w;
4704         plane->state->crtc_h = new_state->crtc_h;
4705
4706         handle_cursor_update(plane, old_state);
4707 }
4708
4709 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4710         .prepare_fb = dm_plane_helper_prepare_fb,
4711         .cleanup_fb = dm_plane_helper_cleanup_fb,
4712         .atomic_check = dm_plane_atomic_check,
4713         .atomic_async_check = dm_plane_atomic_async_check,
4714         .atomic_async_update = dm_plane_atomic_async_update
4715 };
4716
4717 /*
4718  * TODO: these are currently initialized to rgb formats only.
4719  * For future use cases we should either initialize them dynamically based on
4720  * plane capabilities, or initialize this array to all formats, so internal drm
4721  * check will succeed, and let DC implement proper check
4722  */
4723 static const uint32_t rgb_formats[] = {
4724         DRM_FORMAT_XRGB8888,
4725         DRM_FORMAT_ARGB8888,
4726         DRM_FORMAT_RGBA8888,
4727         DRM_FORMAT_XRGB2101010,
4728         DRM_FORMAT_XBGR2101010,
4729         DRM_FORMAT_ARGB2101010,
4730         DRM_FORMAT_ABGR2101010,
4731         DRM_FORMAT_XBGR8888,
4732         DRM_FORMAT_ABGR8888,
4733         DRM_FORMAT_RGB565,
4734 };
4735
4736 static const uint32_t overlay_formats[] = {
4737         DRM_FORMAT_XRGB8888,
4738         DRM_FORMAT_ARGB8888,
4739         DRM_FORMAT_RGBA8888,
4740         DRM_FORMAT_XBGR8888,
4741         DRM_FORMAT_ABGR8888,
4742         DRM_FORMAT_RGB565
4743 };
4744
4745 static const u32 cursor_formats[] = {
4746         DRM_FORMAT_ARGB8888
4747 };
4748
4749 static int get_plane_formats(const struct drm_plane *plane,
4750                              const struct dc_plane_cap *plane_cap,
4751                              uint32_t *formats, int max_formats)
4752 {
4753         int i, num_formats = 0;
4754
4755         /*
4756          * TODO: Query support for each group of formats directly from
4757          * DC plane caps. This will require adding more formats to the
4758          * caps list.
4759          */
4760
4761         switch (plane->type) {
4762         case DRM_PLANE_TYPE_PRIMARY:
4763                 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4764                         if (num_formats >= max_formats)
4765                                 break;
4766
4767                         formats[num_formats++] = rgb_formats[i];
4768                 }
4769
4770                 if (plane_cap && plane_cap->pixel_format_support.nv12)
4771                         formats[num_formats++] = DRM_FORMAT_NV12;
4772                 break;
4773
4774         case DRM_PLANE_TYPE_OVERLAY:
4775                 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4776                         if (num_formats >= max_formats)
4777                                 break;
4778
4779                         formats[num_formats++] = overlay_formats[i];
4780                 }
4781                 break;
4782
4783         case DRM_PLANE_TYPE_CURSOR:
4784                 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4785                         if (num_formats >= max_formats)
4786                                 break;
4787
4788                         formats[num_formats++] = cursor_formats[i];
4789                 }
4790                 break;
4791         }
4792
4793         return num_formats;
4794 }
4795
4796 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4797                                 struct drm_plane *plane,
4798                                 unsigned long possible_crtcs,
4799                                 const struct dc_plane_cap *plane_cap)
4800 {
4801         uint32_t formats[32];
4802         int num_formats;
4803         int res = -EPERM;
4804
4805         num_formats = get_plane_formats(plane, plane_cap, formats,
4806                                         ARRAY_SIZE(formats));
4807
4808         res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4809                                        &dm_plane_funcs, formats, num_formats,
4810                                        NULL, plane->type, NULL);
4811         if (res)
4812                 return res;
4813
4814         if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4815             plane_cap && plane_cap->per_pixel_alpha) {
4816                 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4817                                           BIT(DRM_MODE_BLEND_PREMULTI);
4818
4819                 drm_plane_create_alpha_property(plane);
4820                 drm_plane_create_blend_mode_property(plane, blend_caps);
4821         }
4822
4823         if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
4824             plane_cap && plane_cap->pixel_format_support.nv12) {
4825                 /* This only affects YUV formats. */
4826                 drm_plane_create_color_properties(
4827                         plane,
4828                         BIT(DRM_COLOR_YCBCR_BT601) |
4829                         BIT(DRM_COLOR_YCBCR_BT709),
4830                         BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4831                         BIT(DRM_COLOR_YCBCR_FULL_RANGE),
4832                         DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
4833         }
4834
4835         drm_plane_helper_add(plane, &dm_plane_helper_funcs);
4836
4837         /* Create (reset) the plane state */
4838         if (plane->funcs->reset)
4839                 plane->funcs->reset(plane);
4840
4841         return 0;
4842 }
4843
4844 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4845                                struct drm_plane *plane,
4846                                uint32_t crtc_index)
4847 {
4848         struct amdgpu_crtc *acrtc = NULL;
4849         struct drm_plane *cursor_plane;
4850
4851         int res = -ENOMEM;
4852
4853         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
4854         if (!cursor_plane)
4855                 goto fail;
4856
4857         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
4858         res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
4859
4860         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4861         if (!acrtc)
4862                 goto fail;
4863
4864         res = drm_crtc_init_with_planes(
4865                         dm->ddev,
4866                         &acrtc->base,
4867                         plane,
4868                         cursor_plane,
4869                         &amdgpu_dm_crtc_funcs, NULL);
4870
4871         if (res)
4872                 goto fail;
4873
4874         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
4875
4876         /* Create (reset) the plane state */
4877         if (acrtc->base.funcs->reset)
4878                 acrtc->base.funcs->reset(&acrtc->base);
4879
4880         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
4881         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4882
4883         acrtc->crtc_id = crtc_index;
4884         acrtc->base.enabled = false;
4885         acrtc->otg_inst = -1;
4886
4887         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
4888         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
4889                                    true, MAX_COLOR_LUT_ENTRIES);
4890         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
4891
4892         return 0;
4893
4894 fail:
4895         kfree(acrtc);
4896         kfree(cursor_plane);
4897         return res;
4898 }
4899
4900
4901 static int to_drm_connector_type(enum signal_type st)
4902 {
4903         switch (st) {
4904         case SIGNAL_TYPE_HDMI_TYPE_A:
4905                 return DRM_MODE_CONNECTOR_HDMIA;
4906         case SIGNAL_TYPE_EDP:
4907                 return DRM_MODE_CONNECTOR_eDP;
4908         case SIGNAL_TYPE_LVDS:
4909                 return DRM_MODE_CONNECTOR_LVDS;
4910         case SIGNAL_TYPE_RGB:
4911                 return DRM_MODE_CONNECTOR_VGA;
4912         case SIGNAL_TYPE_DISPLAY_PORT:
4913         case SIGNAL_TYPE_DISPLAY_PORT_MST:
4914                 return DRM_MODE_CONNECTOR_DisplayPort;
4915         case SIGNAL_TYPE_DVI_DUAL_LINK:
4916         case SIGNAL_TYPE_DVI_SINGLE_LINK:
4917                 return DRM_MODE_CONNECTOR_DVID;
4918         case SIGNAL_TYPE_VIRTUAL:
4919                 return DRM_MODE_CONNECTOR_VIRTUAL;
4920
4921         default:
4922                 return DRM_MODE_CONNECTOR_Unknown;
4923         }
4924 }
4925
4926 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
4927 {
4928         struct drm_encoder *encoder;
4929
4930         /* There is only one encoder per connector */
4931         drm_connector_for_each_possible_encoder(connector, encoder)
4932                 return encoder;
4933
4934         return NULL;
4935 }
4936
4937 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
4938 {
4939         struct drm_encoder *encoder;
4940         struct amdgpu_encoder *amdgpu_encoder;
4941
4942         encoder = amdgpu_dm_connector_to_encoder(connector);
4943
4944         if (encoder == NULL)
4945                 return;
4946
4947         amdgpu_encoder = to_amdgpu_encoder(encoder);
4948
4949         amdgpu_encoder->native_mode.clock = 0;
4950
4951         if (!list_empty(&connector->probed_modes)) {
4952                 struct drm_display_mode *preferred_mode = NULL;
4953
4954                 list_for_each_entry(preferred_mode,
4955                                     &connector->probed_modes,
4956                                     head) {
4957                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
4958                                 amdgpu_encoder->native_mode = *preferred_mode;
4959
4960                         break;
4961                 }
4962
4963         }
4964 }
4965
4966 static struct drm_display_mode *
4967 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4968                              char *name,
4969                              int hdisplay, int vdisplay)
4970 {
4971         struct drm_device *dev = encoder->dev;
4972         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4973         struct drm_display_mode *mode = NULL;
4974         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4975
4976         mode = drm_mode_duplicate(dev, native_mode);
4977
4978         if (mode == NULL)
4979                 return NULL;
4980
4981         mode->hdisplay = hdisplay;
4982         mode->vdisplay = vdisplay;
4983         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
4984         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
4985
4986         return mode;
4987
4988 }
4989
4990 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
4991                                                  struct drm_connector *connector)
4992 {
4993         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4994         struct drm_display_mode *mode = NULL;
4995         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4996         struct amdgpu_dm_connector *amdgpu_dm_connector =
4997                                 to_amdgpu_dm_connector(connector);
4998         int i;
4999         int n;
5000         struct mode_size {
5001                 char name[DRM_DISPLAY_MODE_LEN];
5002                 int w;
5003                 int h;
5004         } common_modes[] = {
5005                 {  "640x480",  640,  480},
5006                 {  "800x600",  800,  600},
5007                 { "1024x768", 1024,  768},
5008                 { "1280x720", 1280,  720},
5009                 { "1280x800", 1280,  800},
5010                 {"1280x1024", 1280, 1024},
5011                 { "1440x900", 1440,  900},
5012                 {"1680x1050", 1680, 1050},
5013                 {"1600x1200", 1600, 1200},
5014                 {"1920x1080", 1920, 1080},
5015                 {"1920x1200", 1920, 1200}
5016         };
5017
5018         n = ARRAY_SIZE(common_modes);
5019
5020         for (i = 0; i < n; i++) {
5021                 struct drm_display_mode *curmode = NULL;
5022                 bool mode_existed = false;
5023
5024                 if (common_modes[i].w > native_mode->hdisplay ||
5025                     common_modes[i].h > native_mode->vdisplay ||
5026                    (common_modes[i].w == native_mode->hdisplay &&
5027                     common_modes[i].h == native_mode->vdisplay))
5028                         continue;
5029
5030                 list_for_each_entry(curmode, &connector->probed_modes, head) {
5031                         if (common_modes[i].w == curmode->hdisplay &&
5032                             common_modes[i].h == curmode->vdisplay) {
5033                                 mode_existed = true;
5034                                 break;
5035                         }
5036                 }
5037
5038                 if (mode_existed)
5039                         continue;
5040
5041                 mode = amdgpu_dm_create_common_mode(encoder,
5042                                 common_modes[i].name, common_modes[i].w,
5043                                 common_modes[i].h);
5044                 drm_mode_probed_add(connector, mode);
5045                 amdgpu_dm_connector->num_modes++;
5046         }
5047 }
5048
5049 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
5050                                               struct edid *edid)
5051 {
5052         struct amdgpu_dm_connector *amdgpu_dm_connector =
5053                         to_amdgpu_dm_connector(connector);
5054
5055         if (edid) {
5056                 /* empty probed_modes */
5057                 INIT_LIST_HEAD(&connector->probed_modes);
5058                 amdgpu_dm_connector->num_modes =
5059                                 drm_add_edid_modes(connector, edid);
5060
5061                 /* sorting the probed modes before calling function
5062                  * amdgpu_dm_get_native_mode() since EDID can have
5063                  * more than one preferred mode. The modes that are
5064                  * later in the probed mode list could be of higher
5065                  * and preferred resolution. For example, 3840x2160
5066                  * resolution in base EDID preferred timing and 4096x2160
5067                  * preferred resolution in DID extension block later.
5068                  */
5069                 drm_mode_sort(&connector->probed_modes);
5070                 amdgpu_dm_get_native_mode(connector);
5071         } else {
5072                 amdgpu_dm_connector->num_modes = 0;
5073         }
5074 }
5075
5076 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
5077 {
5078         struct amdgpu_dm_connector *amdgpu_dm_connector =
5079                         to_amdgpu_dm_connector(connector);
5080         struct drm_encoder *encoder;
5081         struct edid *edid = amdgpu_dm_connector->edid;
5082
5083         encoder = amdgpu_dm_connector_to_encoder(connector);
5084
5085         if (!edid || !drm_edid_is_valid(edid)) {
5086                 amdgpu_dm_connector->num_modes =
5087                                 drm_add_modes_noedid(connector, 640, 480);
5088         } else {
5089                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
5090                 amdgpu_dm_connector_add_common_modes(encoder, connector);
5091         }
5092         amdgpu_dm_fbc_init(connector);
5093
5094         return amdgpu_dm_connector->num_modes;
5095 }
5096
5097 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
5098                                      struct amdgpu_dm_connector *aconnector,
5099                                      int connector_type,
5100                                      struct dc_link *link,
5101                                      int link_index)
5102 {
5103         struct amdgpu_device *adev = dm->ddev->dev_private;
5104
5105         /*
5106          * Some of the properties below require access to state, like bpc.
5107          * Allocate some default initial connector state with our reset helper.
5108          */
5109         if (aconnector->base.funcs->reset)
5110                 aconnector->base.funcs->reset(&aconnector->base);
5111
5112         aconnector->connector_id = link_index;
5113         aconnector->dc_link = link;
5114         aconnector->base.interlace_allowed = false;
5115         aconnector->base.doublescan_allowed = false;
5116         aconnector->base.stereo_allowed = false;
5117         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
5118         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
5119         aconnector->audio_inst = -1;
5120         mutex_init(&aconnector->hpd_lock);
5121
5122         /*
5123          * configure support HPD hot plug connector_>polled default value is 0
5124          * which means HPD hot plug not supported
5125          */
5126         switch (connector_type) {
5127         case DRM_MODE_CONNECTOR_HDMIA:
5128                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5129                 aconnector->base.ycbcr_420_allowed =
5130                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
5131                 break;
5132         case DRM_MODE_CONNECTOR_DisplayPort:
5133                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5134                 aconnector->base.ycbcr_420_allowed =
5135                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
5136                 break;
5137         case DRM_MODE_CONNECTOR_DVID:
5138                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5139                 break;
5140         default:
5141                 break;
5142         }
5143
5144         drm_object_attach_property(&aconnector->base.base,
5145                                 dm->ddev->mode_config.scaling_mode_property,
5146                                 DRM_MODE_SCALE_NONE);
5147
5148         drm_object_attach_property(&aconnector->base.base,
5149                                 adev->mode_info.underscan_property,
5150                                 UNDERSCAN_OFF);
5151         drm_object_attach_property(&aconnector->base.base,
5152                                 adev->mode_info.underscan_hborder_property,
5153                                 0);
5154         drm_object_attach_property(&aconnector->base.base,
5155                                 adev->mode_info.underscan_vborder_property,
5156                                 0);
5157
5158         drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
5159
5160         /* This defaults to the max in the range, but we want 8bpc. */
5161         aconnector->base.state->max_bpc = 8;
5162         aconnector->base.state->max_requested_bpc = 8;
5163
5164         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5165             dc_is_dmcu_initialized(adev->dm.dc)) {
5166                 drm_object_attach_property(&aconnector->base.base,
5167                                 adev->mode_info.abm_level_property, 0);
5168         }
5169
5170         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
5171             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5172             connector_type == DRM_MODE_CONNECTOR_eDP) {
5173                 drm_object_attach_property(
5174                         &aconnector->base.base,
5175                         dm->ddev->mode_config.hdr_output_metadata_property, 0);
5176
5177                 drm_connector_attach_vrr_capable_property(
5178                         &aconnector->base);
5179 #ifdef CONFIG_DRM_AMD_DC_HDCP
5180                 if (adev->asic_type >= CHIP_RAVEN)
5181                         drm_connector_attach_content_protection_property(&aconnector->base, false);
5182 #endif
5183         }
5184 }
5185
5186 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
5187                               struct i2c_msg *msgs, int num)
5188 {
5189         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
5190         struct ddc_service *ddc_service = i2c->ddc_service;
5191         struct i2c_command cmd;
5192         int i;
5193         int result = -EIO;
5194
5195         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
5196
5197         if (!cmd.payloads)
5198                 return result;
5199
5200         cmd.number_of_payloads = num;
5201         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
5202         cmd.speed = 100;
5203
5204         for (i = 0; i < num; i++) {
5205                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
5206                 cmd.payloads[i].address = msgs[i].addr;
5207                 cmd.payloads[i].length = msgs[i].len;
5208                 cmd.payloads[i].data = msgs[i].buf;
5209         }
5210
5211         if (dc_submit_i2c(
5212                         ddc_service->ctx->dc,
5213                         ddc_service->ddc_pin->hw_info.ddc_channel,
5214                         &cmd))
5215                 result = num;
5216
5217         kfree(cmd.payloads);
5218         return result;
5219 }
5220
5221 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
5222 {
5223         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
5224 }
5225
5226 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
5227         .master_xfer = amdgpu_dm_i2c_xfer,
5228         .functionality = amdgpu_dm_i2c_func,
5229 };
5230
5231 static struct amdgpu_i2c_adapter *
5232 create_i2c(struct ddc_service *ddc_service,
5233            int link_index,
5234            int *res)
5235 {
5236         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
5237         struct amdgpu_i2c_adapter *i2c;
5238
5239         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
5240         if (!i2c)
5241                 return NULL;
5242         i2c->base.owner = THIS_MODULE;
5243         i2c->base.class = I2C_CLASS_DDC;
5244         i2c->base.dev.parent = &adev->pdev->dev;
5245         i2c->base.algo = &amdgpu_dm_i2c_algo;
5246         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
5247         i2c_set_adapdata(&i2c->base, i2c);
5248         i2c->ddc_service = ddc_service;
5249         i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
5250
5251         return i2c;
5252 }
5253
5254
5255 /*
5256  * Note: this function assumes that dc_link_detect() was called for the
5257  * dc_link which will be represented by this aconnector.
5258  */
5259 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
5260                                     struct amdgpu_dm_connector *aconnector,
5261                                     uint32_t link_index,
5262                                     struct amdgpu_encoder *aencoder)
5263 {
5264         int res = 0;
5265         int connector_type;
5266         struct dc *dc = dm->dc;
5267         struct dc_link *link = dc_get_link_at_index(dc, link_index);
5268         struct amdgpu_i2c_adapter *i2c;
5269
5270         link->priv = aconnector;
5271
5272         DRM_DEBUG_DRIVER("%s()\n", __func__);
5273
5274         i2c = create_i2c(link->ddc, link->link_index, &res);
5275         if (!i2c) {
5276                 DRM_ERROR("Failed to create i2c adapter data\n");
5277                 return -ENOMEM;
5278         }
5279
5280         aconnector->i2c = i2c;
5281         res = i2c_add_adapter(&i2c->base);
5282
5283         if (res) {
5284                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
5285                 goto out_free;
5286         }
5287
5288         connector_type = to_drm_connector_type(link->connector_signal);
5289
5290         res = drm_connector_init(
5291                         dm->ddev,
5292                         &aconnector->base,
5293                         &amdgpu_dm_connector_funcs,
5294                         connector_type);
5295
5296         if (res) {
5297                 DRM_ERROR("connector_init failed\n");
5298                 aconnector->connector_id = -1;
5299                 goto out_free;
5300         }
5301
5302         drm_connector_helper_add(
5303                         &aconnector->base,
5304                         &amdgpu_dm_connector_helper_funcs);
5305
5306         amdgpu_dm_connector_init_helper(
5307                 dm,
5308                 aconnector,
5309                 connector_type,
5310                 link,
5311                 link_index);
5312
5313         drm_connector_attach_encoder(
5314                 &aconnector->base, &aencoder->base);
5315
5316         drm_connector_register(&aconnector->base);
5317 #if defined(CONFIG_DEBUG_FS)
5318         connector_debugfs_init(aconnector);
5319         aconnector->debugfs_dpcd_address = 0;
5320         aconnector->debugfs_dpcd_size = 0;
5321 #endif
5322
5323         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
5324                 || connector_type == DRM_MODE_CONNECTOR_eDP)
5325                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
5326
5327 out_free:
5328         if (res) {
5329                 kfree(i2c);
5330                 aconnector->i2c = NULL;
5331         }
5332         return res;
5333 }
5334
5335 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
5336 {
5337         switch (adev->mode_info.num_crtc) {
5338         case 1:
5339                 return 0x1;
5340         case 2:
5341                 return 0x3;
5342         case 3:
5343                 return 0x7;
5344         case 4:
5345                 return 0xf;
5346         case 5:
5347                 return 0x1f;
5348         case 6:
5349         default:
5350                 return 0x3f;
5351         }
5352 }
5353
5354 static int amdgpu_dm_encoder_init(struct drm_device *dev,
5355                                   struct amdgpu_encoder *aencoder,
5356                                   uint32_t link_index)
5357 {
5358         struct amdgpu_device *adev = dev->dev_private;
5359
5360         int res = drm_encoder_init(dev,
5361                                    &aencoder->base,
5362                                    &amdgpu_dm_encoder_funcs,
5363                                    DRM_MODE_ENCODER_TMDS,
5364                                    NULL);
5365
5366         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
5367
5368         if (!res)
5369                 aencoder->encoder_id = link_index;
5370         else
5371                 aencoder->encoder_id = -1;
5372
5373         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
5374
5375         return res;
5376 }
5377
5378 static void manage_dm_interrupts(struct amdgpu_device *adev,
5379                                  struct amdgpu_crtc *acrtc,
5380                                  bool enable)
5381 {
5382         /*
5383          * this is not correct translation but will work as soon as VBLANK
5384          * constant is the same as PFLIP
5385          */
5386         int irq_type =
5387                 amdgpu_display_crtc_idx_to_irq_type(
5388                         adev,
5389                         acrtc->crtc_id);
5390
5391         if (enable) {
5392                 drm_crtc_vblank_on(&acrtc->base);
5393                 amdgpu_irq_get(
5394                         adev,
5395                         &adev->pageflip_irq,
5396                         irq_type);
5397         } else {
5398
5399                 amdgpu_irq_put(
5400                         adev,
5401                         &adev->pageflip_irq,
5402                         irq_type);
5403                 drm_crtc_vblank_off(&acrtc->base);
5404         }
5405 }
5406
5407 static bool
5408 is_scaling_state_different(const struct dm_connector_state *dm_state,
5409                            const struct dm_connector_state *old_dm_state)
5410 {
5411         if (dm_state->scaling != old_dm_state->scaling)
5412                 return true;
5413         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
5414                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
5415                         return true;
5416         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
5417                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
5418                         return true;
5419         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
5420                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
5421                 return true;
5422         return false;
5423 }
5424
5425 #ifdef CONFIG_DRM_AMD_DC_HDCP
5426 static bool is_content_protection_different(struct drm_connector_state *state,
5427                                             const struct drm_connector_state *old_state,
5428                                             const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
5429 {
5430         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5431
5432         /* CP is being re enabled, ignore this */
5433         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
5434             state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
5435                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
5436                 return false;
5437         }
5438
5439         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */
5440         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
5441             state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
5442                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
5443
5444         /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
5445          * hot-plug, headless s3, dpms
5446          */
5447         if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && connector->dpms == DRM_MODE_DPMS_ON &&
5448             aconnector->dc_sink != NULL)
5449                 return true;
5450
5451         if (old_state->content_protection == state->content_protection)
5452                 return false;
5453
5454         if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
5455                 return true;
5456
5457         return false;
5458 }
5459
5460 static void update_content_protection(struct drm_connector_state *state, const struct drm_connector *connector,
5461                                       struct hdcp_workqueue *hdcp_w)
5462 {
5463         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5464
5465         if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
5466                 hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, aconnector);
5467         else if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
5468                 hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, aconnector->base.index);
5469
5470 }
5471 #endif
5472 static void remove_stream(struct amdgpu_device *adev,
5473                           struct amdgpu_crtc *acrtc,
5474                           struct dc_stream_state *stream)
5475 {
5476         /* this is the update mode case */
5477
5478         acrtc->otg_inst = -1;
5479         acrtc->enabled = false;
5480 }
5481
5482 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
5483                                struct dc_cursor_position *position)
5484 {
5485         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5486         int x, y;
5487         int xorigin = 0, yorigin = 0;
5488
5489         position->enable = false;
5490         position->x = 0;
5491         position->y = 0;
5492
5493         if (!crtc || !plane->state->fb)
5494                 return 0;
5495
5496         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
5497             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
5498                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
5499                           __func__,
5500                           plane->state->crtc_w,
5501                           plane->state->crtc_h);
5502                 return -EINVAL;
5503         }
5504
5505         x = plane->state->crtc_x;
5506         y = plane->state->crtc_y;
5507
5508         if (x <= -amdgpu_crtc->max_cursor_width ||
5509             y <= -amdgpu_crtc->max_cursor_height)
5510                 return 0;
5511
5512         if (crtc->primary->state) {
5513                 /* avivo cursor are offset into the total surface */
5514                 x += crtc->primary->state->src_x >> 16;
5515                 y += crtc->primary->state->src_y >> 16;
5516         }
5517
5518         if (x < 0) {
5519                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
5520                 x = 0;
5521         }
5522         if (y < 0) {
5523                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
5524                 y = 0;
5525         }
5526         position->enable = true;
5527         position->x = x;
5528         position->y = y;
5529         position->x_hotspot = xorigin;
5530         position->y_hotspot = yorigin;
5531
5532         return 0;
5533 }
5534
5535 static void handle_cursor_update(struct drm_plane *plane,
5536                                  struct drm_plane_state *old_plane_state)
5537 {
5538         struct amdgpu_device *adev = plane->dev->dev_private;
5539         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
5540         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
5541         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
5542         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5543         uint64_t address = afb ? afb->address : 0;
5544         struct dc_cursor_position position;
5545         struct dc_cursor_attributes attributes;
5546         int ret;
5547
5548         if (!plane->state->fb && !old_plane_state->fb)
5549                 return;
5550
5551         DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
5552                          __func__,
5553                          amdgpu_crtc->crtc_id,
5554                          plane->state->crtc_w,
5555                          plane->state->crtc_h);
5556
5557         ret = get_cursor_position(plane, crtc, &position);
5558         if (ret)
5559                 return;
5560
5561         if (!position.enable) {
5562                 /* turn off cursor */
5563                 if (crtc_state && crtc_state->stream) {
5564                         mutex_lock(&adev->dm.dc_lock);
5565                         dc_stream_set_cursor_position(crtc_state->stream,
5566                                                       &position);
5567                         mutex_unlock(&adev->dm.dc_lock);
5568                 }
5569                 return;
5570         }
5571
5572         amdgpu_crtc->cursor_width = plane->state->crtc_w;
5573         amdgpu_crtc->cursor_height = plane->state->crtc_h;
5574
5575         memset(&attributes, 0, sizeof(attributes));
5576         attributes.address.high_part = upper_32_bits(address);
5577         attributes.address.low_part  = lower_32_bits(address);
5578         attributes.width             = plane->state->crtc_w;
5579         attributes.height            = plane->state->crtc_h;
5580         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
5581         attributes.rotation_angle    = 0;
5582         attributes.attribute_flags.value = 0;
5583
5584         attributes.pitch = attributes.width;
5585
5586         if (crtc_state->stream) {
5587                 mutex_lock(&adev->dm.dc_lock);
5588                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
5589                                                          &attributes))
5590                         DRM_ERROR("DC failed to set cursor attributes\n");
5591
5592                 if (!dc_stream_set_cursor_position(crtc_state->stream,
5593                                                    &position))
5594                         DRM_ERROR("DC failed to set cursor position\n");
5595                 mutex_unlock(&adev->dm.dc_lock);
5596         }
5597 }
5598
5599 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
5600 {
5601
5602         assert_spin_locked(&acrtc->base.dev->event_lock);
5603         WARN_ON(acrtc->event);
5604
5605         acrtc->event = acrtc->base.state->event;
5606
5607         /* Set the flip status */
5608         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
5609
5610         /* Mark this event as consumed */
5611         acrtc->base.state->event = NULL;
5612
5613         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
5614                                                  acrtc->crtc_id);
5615 }
5616
5617 static void update_freesync_state_on_stream(
5618         struct amdgpu_display_manager *dm,
5619         struct dm_crtc_state *new_crtc_state,
5620         struct dc_stream_state *new_stream,
5621         struct dc_plane_state *surface,
5622         u32 flip_timestamp_in_us)
5623 {
5624         struct mod_vrr_params vrr_params;
5625         struct dc_info_packet vrr_infopacket = {0};
5626         struct amdgpu_device *adev = dm->adev;
5627         unsigned long flags;
5628
5629         if (!new_stream)
5630                 return;
5631
5632         /*
5633          * TODO: Determine why min/max totals and vrefresh can be 0 here.
5634          * For now it's sufficient to just guard against these conditions.
5635          */
5636
5637         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5638                 return;
5639
5640         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5641         vrr_params = new_crtc_state->vrr_params;
5642
5643         if (surface) {
5644                 mod_freesync_handle_preflip(
5645                         dm->freesync_module,
5646                         surface,
5647                         new_stream,
5648                         flip_timestamp_in_us,
5649                         &vrr_params);
5650
5651                 if (adev->family < AMDGPU_FAMILY_AI &&
5652                     amdgpu_dm_vrr_active(new_crtc_state)) {
5653                         mod_freesync_handle_v_update(dm->freesync_module,
5654                                                      new_stream, &vrr_params);
5655
5656                         /* Need to call this before the frame ends. */
5657                         dc_stream_adjust_vmin_vmax(dm->dc,
5658                                                    new_crtc_state->stream,
5659                                                    &vrr_params.adjust);
5660                 }
5661         }
5662
5663         mod_freesync_build_vrr_infopacket(
5664                 dm->freesync_module,
5665                 new_stream,
5666                 &vrr_params,
5667                 PACKET_TYPE_VRR,
5668                 TRANSFER_FUNC_UNKNOWN,
5669                 &vrr_infopacket);
5670
5671         new_crtc_state->freesync_timing_changed |=
5672                 (memcmp(&new_crtc_state->vrr_params.adjust,
5673                         &vrr_params.adjust,
5674                         sizeof(vrr_params.adjust)) != 0);
5675
5676         new_crtc_state->freesync_vrr_info_changed |=
5677                 (memcmp(&new_crtc_state->vrr_infopacket,
5678                         &vrr_infopacket,
5679                         sizeof(vrr_infopacket)) != 0);
5680
5681         new_crtc_state->vrr_params = vrr_params;
5682         new_crtc_state->vrr_infopacket = vrr_infopacket;
5683
5684         new_stream->adjust = new_crtc_state->vrr_params.adjust;
5685         new_stream->vrr_infopacket = vrr_infopacket;
5686
5687         if (new_crtc_state->freesync_vrr_info_changed)
5688                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
5689                               new_crtc_state->base.crtc->base.id,
5690                               (int)new_crtc_state->base.vrr_enabled,
5691                               (int)vrr_params.state);
5692
5693         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5694 }
5695
5696 static void pre_update_freesync_state_on_stream(
5697         struct amdgpu_display_manager *dm,
5698         struct dm_crtc_state *new_crtc_state)
5699 {
5700         struct dc_stream_state *new_stream = new_crtc_state->stream;
5701         struct mod_vrr_params vrr_params;
5702         struct mod_freesync_config config = new_crtc_state->freesync_config;
5703         struct amdgpu_device *adev = dm->adev;
5704         unsigned long flags;
5705
5706         if (!new_stream)
5707                 return;
5708
5709         /*
5710          * TODO: Determine why min/max totals and vrefresh can be 0 here.
5711          * For now it's sufficient to just guard against these conditions.
5712          */
5713         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5714                 return;
5715
5716         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5717         vrr_params = new_crtc_state->vrr_params;
5718
5719         if (new_crtc_state->vrr_supported &&
5720             config.min_refresh_in_uhz &&
5721             config.max_refresh_in_uhz) {
5722                 config.state = new_crtc_state->base.vrr_enabled ?
5723                         VRR_STATE_ACTIVE_VARIABLE :
5724                         VRR_STATE_INACTIVE;
5725         } else {
5726                 config.state = VRR_STATE_UNSUPPORTED;
5727         }
5728
5729         mod_freesync_build_vrr_params(dm->freesync_module,
5730                                       new_stream,
5731                                       &config, &vrr_params);
5732
5733         new_crtc_state->freesync_timing_changed |=
5734                 (memcmp(&new_crtc_state->vrr_params.adjust,
5735                         &vrr_params.adjust,
5736                         sizeof(vrr_params.adjust)) != 0);
5737
5738         new_crtc_state->vrr_params = vrr_params;
5739         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5740 }
5741
5742 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
5743                                             struct dm_crtc_state *new_state)
5744 {
5745         bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
5746         bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
5747
5748         if (!old_vrr_active && new_vrr_active) {
5749                 /* Transition VRR inactive -> active:
5750                  * While VRR is active, we must not disable vblank irq, as a
5751                  * reenable after disable would compute bogus vblank/pflip
5752                  * timestamps if it likely happened inside display front-porch.
5753                  *
5754                  * We also need vupdate irq for the actual core vblank handling
5755                  * at end of vblank.
5756                  */
5757                 dm_set_vupdate_irq(new_state->base.crtc, true);
5758                 drm_crtc_vblank_get(new_state->base.crtc);
5759                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
5760                                  __func__, new_state->base.crtc->base.id);
5761         } else if (old_vrr_active && !new_vrr_active) {
5762                 /* Transition VRR active -> inactive:
5763                  * Allow vblank irq disable again for fixed refresh rate.
5764                  */
5765                 dm_set_vupdate_irq(new_state->base.crtc, false);
5766                 drm_crtc_vblank_put(new_state->base.crtc);
5767                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
5768                                  __func__, new_state->base.crtc->base.id);
5769         }
5770 }
5771
5772 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
5773 {
5774         struct drm_plane *plane;
5775         struct drm_plane_state *old_plane_state, *new_plane_state;
5776         int i;
5777
5778         /*
5779          * TODO: Make this per-stream so we don't issue redundant updates for
5780          * commits with multiple streams.
5781          */
5782         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
5783                                        new_plane_state, i)
5784                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5785                         handle_cursor_update(plane, old_plane_state);
5786 }
5787
5788 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
5789                                     struct dc_state *dc_state,
5790                                     struct drm_device *dev,
5791                                     struct amdgpu_display_manager *dm,
5792                                     struct drm_crtc *pcrtc,
5793                                     bool wait_for_vblank)
5794 {
5795         uint32_t i;
5796         uint64_t timestamp_ns;
5797         struct drm_plane *plane;
5798         struct drm_plane_state *old_plane_state, *new_plane_state;
5799         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
5800         struct drm_crtc_state *new_pcrtc_state =
5801                         drm_atomic_get_new_crtc_state(state, pcrtc);
5802         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
5803         struct dm_crtc_state *dm_old_crtc_state =
5804                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
5805         int planes_count = 0, vpos, hpos;
5806         long r;
5807         unsigned long flags;
5808         struct amdgpu_bo *abo;
5809         uint64_t tiling_flags;
5810         uint32_t target_vblank, last_flip_vblank;
5811         bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
5812         bool pflip_present = false;
5813         struct {
5814                 struct dc_surface_update surface_updates[MAX_SURFACES];
5815                 struct dc_plane_info plane_infos[MAX_SURFACES];
5816                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
5817                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
5818                 struct dc_stream_update stream_update;
5819         } *bundle;
5820
5821         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
5822
5823         if (!bundle) {
5824                 dm_error("Failed to allocate update bundle\n");
5825                 goto cleanup;
5826         }
5827
5828         /*
5829          * Disable the cursor first if we're disabling all the planes.
5830          * It'll remain on the screen after the planes are re-enabled
5831          * if we don't.
5832          */
5833         if (acrtc_state->active_planes == 0)
5834                 amdgpu_dm_commit_cursors(state);
5835
5836         /* update planes when needed */
5837         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
5838                 struct drm_crtc *crtc = new_plane_state->crtc;
5839                 struct drm_crtc_state *new_crtc_state;
5840                 struct drm_framebuffer *fb = new_plane_state->fb;
5841                 bool plane_needs_flip;
5842                 struct dc_plane_state *dc_plane;
5843                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
5844
5845                 /* Cursor plane is handled after stream updates */
5846                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5847                         continue;
5848
5849                 if (!fb || !crtc || pcrtc != crtc)
5850                         continue;
5851
5852                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
5853                 if (!new_crtc_state->active)
5854                         continue;
5855
5856                 dc_plane = dm_new_plane_state->dc_state;
5857
5858                 bundle->surface_updates[planes_count].surface = dc_plane;
5859                 if (new_pcrtc_state->color_mgmt_changed) {
5860                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
5861                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
5862                 }
5863
5864                 fill_dc_scaling_info(new_plane_state,
5865                                      &bundle->scaling_infos[planes_count]);
5866
5867                 bundle->surface_updates[planes_count].scaling_info =
5868                         &bundle->scaling_infos[planes_count];
5869
5870                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
5871
5872                 pflip_present = pflip_present || plane_needs_flip;
5873
5874                 if (!plane_needs_flip) {
5875                         planes_count += 1;
5876                         continue;
5877                 }
5878
5879                 abo = gem_to_amdgpu_bo(fb->obj[0]);
5880
5881                 /*
5882                  * Wait for all fences on this FB. Do limited wait to avoid
5883                  * deadlock during GPU reset when this fence will not signal
5884                  * but we hold reservation lock for the BO.
5885                  */
5886                 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
5887                                                         false,
5888                                                         msecs_to_jiffies(5000));
5889                 if (unlikely(r <= 0))
5890                         DRM_ERROR("Waiting for fences timed out!");
5891
5892                 /*
5893                  * TODO This might fail and hence better not used, wait
5894                  * explicitly on fences instead
5895                  * and in general should be called for
5896                  * blocking commit to as per framework helpers
5897                  */
5898                 r = amdgpu_bo_reserve(abo, true);
5899                 if (unlikely(r != 0))
5900                         DRM_ERROR("failed to reserve buffer before flip\n");
5901
5902                 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
5903
5904                 amdgpu_bo_unreserve(abo);
5905
5906                 fill_dc_plane_info_and_addr(
5907                         dm->adev, new_plane_state, tiling_flags,
5908                         &bundle->plane_infos[planes_count],
5909                         &bundle->flip_addrs[planes_count].address);
5910
5911                 bundle->surface_updates[planes_count].plane_info =
5912                         &bundle->plane_infos[planes_count];
5913
5914                 /*
5915                  * Only allow immediate flips for fast updates that don't
5916                  * change FB pitch, DCC state, rotation or mirroing.
5917                  */
5918                 bundle->flip_addrs[planes_count].flip_immediate =
5919                         crtc->state->async_flip &&
5920                         acrtc_state->update_type == UPDATE_TYPE_FAST;
5921
5922                 timestamp_ns = ktime_get_ns();
5923                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
5924                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
5925                 bundle->surface_updates[planes_count].surface = dc_plane;
5926
5927                 if (!bundle->surface_updates[planes_count].surface) {
5928                         DRM_ERROR("No surface for CRTC: id=%d\n",
5929                                         acrtc_attach->crtc_id);
5930                         continue;
5931                 }
5932
5933                 if (plane == pcrtc->primary)
5934                         update_freesync_state_on_stream(
5935                                 dm,
5936                                 acrtc_state,
5937                                 acrtc_state->stream,
5938                                 dc_plane,
5939                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
5940
5941                 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
5942                                  __func__,
5943                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
5944                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
5945
5946                 planes_count += 1;
5947
5948         }
5949
5950         if (pflip_present) {
5951                 if (!vrr_active) {
5952                         /* Use old throttling in non-vrr fixed refresh rate mode
5953                          * to keep flip scheduling based on target vblank counts
5954                          * working in a backwards compatible way, e.g., for
5955                          * clients using the GLX_OML_sync_control extension or
5956                          * DRI3/Present extension with defined target_msc.
5957                          */
5958                         last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
5959                 }
5960                 else {
5961                         /* For variable refresh rate mode only:
5962                          * Get vblank of last completed flip to avoid > 1 vrr
5963                          * flips per video frame by use of throttling, but allow
5964                          * flip programming anywhere in the possibly large
5965                          * variable vrr vblank interval for fine-grained flip
5966                          * timing control and more opportunity to avoid stutter
5967                          * on late submission of flips.
5968                          */
5969                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5970                         last_flip_vblank = acrtc_attach->last_flip_vblank;
5971                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5972                 }
5973
5974                 target_vblank = last_flip_vblank + wait_for_vblank;
5975
5976                 /*
5977                  * Wait until we're out of the vertical blank period before the one
5978                  * targeted by the flip
5979                  */
5980                 while ((acrtc_attach->enabled &&
5981                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
5982                                                             0, &vpos, &hpos, NULL,
5983                                                             NULL, &pcrtc->hwmode)
5984                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
5985                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
5986                         (int)(target_vblank -
5987                           amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
5988                         usleep_range(1000, 1100);
5989                 }
5990
5991                 if (acrtc_attach->base.state->event) {
5992                         drm_crtc_vblank_get(pcrtc);
5993
5994                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5995
5996                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
5997                         prepare_flip_isr(acrtc_attach);
5998
5999                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6000                 }
6001
6002                 if (acrtc_state->stream) {
6003                         if (acrtc_state->freesync_vrr_info_changed)
6004                                 bundle->stream_update.vrr_infopacket =
6005                                         &acrtc_state->stream->vrr_infopacket;
6006                 }
6007         }
6008
6009         /* Update the planes if changed or disable if we don't have any. */
6010         if ((planes_count || acrtc_state->active_planes == 0) &&
6011                 acrtc_state->stream) {
6012                 bundle->stream_update.stream = acrtc_state->stream;
6013                 if (new_pcrtc_state->mode_changed) {
6014                         bundle->stream_update.src = acrtc_state->stream->src;
6015                         bundle->stream_update.dst = acrtc_state->stream->dst;
6016                 }
6017
6018                 if (new_pcrtc_state->color_mgmt_changed) {
6019                         /*
6020                          * TODO: This isn't fully correct since we've actually
6021                          * already modified the stream in place.
6022                          */
6023                         bundle->stream_update.gamut_remap =
6024                                 &acrtc_state->stream->gamut_remap_matrix;
6025                         bundle->stream_update.output_csc_transform =
6026                                 &acrtc_state->stream->csc_color_matrix;
6027                         bundle->stream_update.out_transfer_func =
6028                                 acrtc_state->stream->out_transfer_func;
6029                 }
6030
6031                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
6032                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
6033                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
6034
6035                 /*
6036                  * If FreeSync state on the stream has changed then we need to
6037                  * re-adjust the min/max bounds now that DC doesn't handle this
6038                  * as part of commit.
6039                  */
6040                 if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
6041                     amdgpu_dm_vrr_active(acrtc_state)) {
6042                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6043                         dc_stream_adjust_vmin_vmax(
6044                                 dm->dc, acrtc_state->stream,
6045                                 &acrtc_state->vrr_params.adjust);
6046                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6047                 }
6048
6049                 mutex_lock(&dm->dc_lock);
6050                 dc_commit_updates_for_stream(dm->dc,
6051                                                      bundle->surface_updates,
6052                                                      planes_count,
6053                                                      acrtc_state->stream,
6054                                                      &bundle->stream_update,
6055                                                      dc_state);
6056                 mutex_unlock(&dm->dc_lock);
6057         }
6058
6059         /*
6060          * Update cursor state *after* programming all the planes.
6061          * This avoids redundant programming in the case where we're going
6062          * to be disabling a single plane - those pipes are being disabled.
6063          */
6064         if (acrtc_state->active_planes)
6065                 amdgpu_dm_commit_cursors(state);
6066
6067 cleanup:
6068         kfree(bundle);
6069 }
6070
6071 static void amdgpu_dm_commit_audio(struct drm_device *dev,
6072                                    struct drm_atomic_state *state)
6073 {
6074         struct amdgpu_device *adev = dev->dev_private;
6075         struct amdgpu_dm_connector *aconnector;
6076         struct drm_connector *connector;
6077         struct drm_connector_state *old_con_state, *new_con_state;
6078         struct drm_crtc_state *new_crtc_state;
6079         struct dm_crtc_state *new_dm_crtc_state;
6080         const struct dc_stream_status *status;
6081         int i, inst;
6082
6083         /* Notify device removals. */
6084         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6085                 if (old_con_state->crtc != new_con_state->crtc) {
6086                         /* CRTC changes require notification. */
6087                         goto notify;
6088                 }
6089
6090                 if (!new_con_state->crtc)
6091                         continue;
6092
6093                 new_crtc_state = drm_atomic_get_new_crtc_state(
6094                         state, new_con_state->crtc);
6095
6096                 if (!new_crtc_state)
6097                         continue;
6098
6099                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6100                         continue;
6101
6102         notify:
6103                 aconnector = to_amdgpu_dm_connector(connector);
6104
6105                 mutex_lock(&adev->dm.audio_lock);
6106                 inst = aconnector->audio_inst;
6107                 aconnector->audio_inst = -1;
6108                 mutex_unlock(&adev->dm.audio_lock);
6109
6110                 amdgpu_dm_audio_eld_notify(adev, inst);
6111         }
6112
6113         /* Notify audio device additions. */
6114         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6115                 if (!new_con_state->crtc)
6116                         continue;
6117
6118                 new_crtc_state = drm_atomic_get_new_crtc_state(
6119                         state, new_con_state->crtc);
6120
6121                 if (!new_crtc_state)
6122                         continue;
6123
6124                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6125                         continue;
6126
6127                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6128                 if (!new_dm_crtc_state->stream)
6129                         continue;
6130
6131                 status = dc_stream_get_status(new_dm_crtc_state->stream);
6132                 if (!status)
6133                         continue;
6134
6135                 aconnector = to_amdgpu_dm_connector(connector);
6136
6137                 mutex_lock(&adev->dm.audio_lock);
6138                 inst = status->audio_inst;
6139                 aconnector->audio_inst = inst;
6140                 mutex_unlock(&adev->dm.audio_lock);
6141
6142                 amdgpu_dm_audio_eld_notify(adev, inst);
6143         }
6144 }
6145
6146 /*
6147  * Enable interrupts on CRTCs that are newly active, undergone
6148  * a modeset, or have active planes again.
6149  *
6150  * Done in two passes, based on the for_modeset flag:
6151  * Pass 1: For CRTCs going through modeset
6152  * Pass 2: For CRTCs going from 0 to n active planes
6153  *
6154  * Interrupts can only be enabled after the planes are programmed,
6155  * so this requires a two-pass approach since we don't want to
6156  * just defer the interrupts until after commit planes every time.
6157  */
6158 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
6159                                              struct drm_atomic_state *state,
6160                                              bool for_modeset)
6161 {
6162         struct amdgpu_device *adev = dev->dev_private;
6163         struct drm_crtc *crtc;
6164         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6165         int i;
6166 #ifdef CONFIG_DEBUG_FS
6167         enum amdgpu_dm_pipe_crc_source source;
6168 #endif
6169
6170         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6171                                       new_crtc_state, i) {
6172                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6173                 struct dm_crtc_state *dm_new_crtc_state =
6174                         to_dm_crtc_state(new_crtc_state);
6175                 struct dm_crtc_state *dm_old_crtc_state =
6176                         to_dm_crtc_state(old_crtc_state);
6177                 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
6178                 bool run_pass;
6179
6180                 run_pass = (for_modeset && modeset) ||
6181                            (!for_modeset && !modeset &&
6182                             !dm_old_crtc_state->interrupts_enabled);
6183
6184                 if (!run_pass)
6185                         continue;
6186
6187                 if (!dm_new_crtc_state->interrupts_enabled)
6188                         continue;
6189
6190                 manage_dm_interrupts(adev, acrtc, true);
6191
6192 #ifdef CONFIG_DEBUG_FS
6193                 /* The stream has changed so CRC capture needs to re-enabled. */
6194                 source = dm_new_crtc_state->crc_src;
6195                 if (amdgpu_dm_is_valid_crc_source(source)) {
6196                         amdgpu_dm_crtc_configure_crc_source(
6197                                 crtc, dm_new_crtc_state,
6198                                 dm_new_crtc_state->crc_src);
6199                 }
6200 #endif
6201         }
6202 }
6203
6204 /*
6205  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
6206  * @crtc_state: the DRM CRTC state
6207  * @stream_state: the DC stream state.
6208  *
6209  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
6210  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
6211  */
6212 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
6213                                                 struct dc_stream_state *stream_state)
6214 {
6215         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
6216 }
6217
6218 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
6219                                    struct drm_atomic_state *state,
6220                                    bool nonblock)
6221 {
6222         struct drm_crtc *crtc;
6223         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6224         struct amdgpu_device *adev = dev->dev_private;
6225         int i;
6226
6227         /*
6228          * We evade vblank and pflip interrupts on CRTCs that are undergoing
6229          * a modeset, being disabled, or have no active planes.
6230          *
6231          * It's done in atomic commit rather than commit tail for now since
6232          * some of these interrupt handlers access the current CRTC state and
6233          * potentially the stream pointer itself.
6234          *
6235          * Since the atomic state is swapped within atomic commit and not within
6236          * commit tail this would leave to new state (that hasn't been committed yet)
6237          * being accesssed from within the handlers.
6238          *
6239          * TODO: Fix this so we can do this in commit tail and not have to block
6240          * in atomic check.
6241          */
6242         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6243                 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6244                 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6245                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6246
6247                 if (dm_old_crtc_state->interrupts_enabled &&
6248                     (!dm_new_crtc_state->interrupts_enabled ||
6249                      drm_atomic_crtc_needs_modeset(new_crtc_state)))
6250                         manage_dm_interrupts(adev, acrtc, false);
6251         }
6252         /*
6253          * Add check here for SoC's that support hardware cursor plane, to
6254          * unset legacy_cursor_update
6255          */
6256
6257         return drm_atomic_helper_commit(dev, state, nonblock);
6258
6259         /*TODO Handle EINTR, reenable IRQ*/
6260 }
6261
6262 /**
6263  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
6264  * @state: The atomic state to commit
6265  *
6266  * This will tell DC to commit the constructed DC state from atomic_check,
6267  * programming the hardware. Any failures here implies a hardware failure, since
6268  * atomic check should have filtered anything non-kosher.
6269  */
6270 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
6271 {
6272         struct drm_device *dev = state->dev;
6273         struct amdgpu_device *adev = dev->dev_private;
6274         struct amdgpu_display_manager *dm = &adev->dm;
6275         struct dm_atomic_state *dm_state;
6276         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
6277         uint32_t i, j;
6278         struct drm_crtc *crtc;
6279         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6280         unsigned long flags;
6281         bool wait_for_vblank = true;
6282         struct drm_connector *connector;
6283         struct drm_connector_state *old_con_state, *new_con_state;
6284         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6285         int crtc_disable_count = 0;
6286
6287         drm_atomic_helper_update_legacy_modeset_state(dev, state);
6288
6289         dm_state = dm_atomic_get_new_state(state);
6290         if (dm_state && dm_state->context) {
6291                 dc_state = dm_state->context;
6292         } else {
6293                 /* No state changes, retain current state. */
6294                 dc_state_temp = dc_create_state(dm->dc);
6295                 ASSERT(dc_state_temp);
6296                 dc_state = dc_state_temp;
6297                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
6298         }
6299
6300         /* update changed items */
6301         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6302                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6303
6304                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6305                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6306
6307                 DRM_DEBUG_DRIVER(
6308                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6309                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6310                         "connectors_changed:%d\n",
6311                         acrtc->crtc_id,
6312                         new_crtc_state->enable,
6313                         new_crtc_state->active,
6314                         new_crtc_state->planes_changed,
6315                         new_crtc_state->mode_changed,
6316                         new_crtc_state->active_changed,
6317                         new_crtc_state->connectors_changed);
6318
6319                 /* Copy all transient state flags into dc state */
6320                 if (dm_new_crtc_state->stream) {
6321                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
6322                                                             dm_new_crtc_state->stream);
6323                 }
6324
6325                 /* handles headless hotplug case, updating new_state and
6326                  * aconnector as needed
6327                  */
6328
6329                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
6330
6331                         DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
6332
6333                         if (!dm_new_crtc_state->stream) {
6334                                 /*
6335                                  * this could happen because of issues with
6336                                  * userspace notifications delivery.
6337                                  * In this case userspace tries to set mode on
6338                                  * display which is disconnected in fact.
6339                                  * dc_sink is NULL in this case on aconnector.
6340                                  * We expect reset mode will come soon.
6341                                  *
6342                                  * This can also happen when unplug is done
6343                                  * during resume sequence ended
6344                                  *
6345                                  * In this case, we want to pretend we still
6346                                  * have a sink to keep the pipe running so that
6347                                  * hw state is consistent with the sw state
6348                                  */
6349                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6350                                                 __func__, acrtc->base.base.id);
6351                                 continue;
6352                         }
6353
6354                         if (dm_old_crtc_state->stream)
6355                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6356
6357                         pm_runtime_get_noresume(dev->dev);
6358
6359                         acrtc->enabled = true;
6360                         acrtc->hw_mode = new_crtc_state->mode;
6361                         crtc->hwmode = new_crtc_state->mode;
6362                 } else if (modereset_required(new_crtc_state)) {
6363                         DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
6364
6365                         /* i.e. reset mode */
6366                         if (dm_old_crtc_state->stream)
6367                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6368                 }
6369         } /* for_each_crtc_in_state() */
6370
6371         if (dc_state) {
6372                 dm_enable_per_frame_crtc_master_sync(dc_state);
6373                 mutex_lock(&dm->dc_lock);
6374                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
6375                 mutex_unlock(&dm->dc_lock);
6376         }
6377
6378         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
6379                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6380
6381                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6382
6383                 if (dm_new_crtc_state->stream != NULL) {
6384                         const struct dc_stream_status *status =
6385                                         dc_stream_get_status(dm_new_crtc_state->stream);
6386
6387                         if (!status)
6388                                 status = dc_stream_get_status_from_state(dc_state,
6389                                                                          dm_new_crtc_state->stream);
6390
6391                         if (!status)
6392                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
6393                         else
6394                                 acrtc->otg_inst = status->primary_otg_inst;
6395                 }
6396         }
6397 #ifdef CONFIG_DRM_AMD_DC_HDCP
6398         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6399                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6400                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6401                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6402
6403                 new_crtc_state = NULL;
6404
6405                 if (acrtc)
6406                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6407
6408                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6409
6410                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
6411                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
6412                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
6413                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
6414                         continue;
6415                 }
6416
6417                 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
6418                         update_content_protection(new_con_state, connector, adev->dm.hdcp_workqueue);
6419         }
6420 #endif
6421
6422         /* Handle connector state changes */
6423         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6424                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6425                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6426                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6427                 struct dc_surface_update dummy_updates[MAX_SURFACES];
6428                 struct dc_stream_update stream_update;
6429                 struct dc_info_packet hdr_packet;
6430                 struct dc_stream_status *status = NULL;
6431                 bool abm_changed, hdr_changed, scaling_changed;
6432
6433                 memset(&dummy_updates, 0, sizeof(dummy_updates));
6434                 memset(&stream_update, 0, sizeof(stream_update));
6435
6436                 if (acrtc) {
6437                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6438                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
6439                 }
6440
6441                 /* Skip any modesets/resets */
6442                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
6443                         continue;
6444
6445                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6446                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6447
6448                 scaling_changed = is_scaling_state_different(dm_new_con_state,
6449                                                              dm_old_con_state);
6450
6451                 abm_changed = dm_new_crtc_state->abm_level !=
6452                               dm_old_crtc_state->abm_level;
6453
6454                 hdr_changed =
6455                         is_hdr_metadata_different(old_con_state, new_con_state);
6456
6457                 if (!scaling_changed && !abm_changed && !hdr_changed)
6458                         continue;
6459
6460                 stream_update.stream = dm_new_crtc_state->stream;
6461                 if (scaling_changed) {
6462                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
6463                                         dm_new_con_state, dm_new_crtc_state->stream);
6464
6465                         stream_update.src = dm_new_crtc_state->stream->src;
6466                         stream_update.dst = dm_new_crtc_state->stream->dst;
6467                 }
6468
6469                 if (abm_changed) {
6470                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
6471
6472                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
6473                 }
6474
6475                 if (hdr_changed) {
6476                         fill_hdr_info_packet(new_con_state, &hdr_packet);
6477                         stream_update.hdr_static_metadata = &hdr_packet;
6478                 }
6479
6480                 status = dc_stream_get_status(dm_new_crtc_state->stream);
6481                 WARN_ON(!status);
6482                 WARN_ON(!status->plane_count);
6483
6484                 /*
6485                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
6486                  * Here we create an empty update on each plane.
6487                  * To fix this, DC should permit updating only stream properties.
6488                  */
6489                 for (j = 0; j < status->plane_count; j++)
6490                         dummy_updates[j].surface = status->plane_states[0];
6491
6492
6493                 mutex_lock(&dm->dc_lock);
6494                 dc_commit_updates_for_stream(dm->dc,
6495                                                      dummy_updates,
6496                                                      status->plane_count,
6497                                                      dm_new_crtc_state->stream,
6498                                                      &stream_update,
6499                                                      dc_state);
6500                 mutex_unlock(&dm->dc_lock);
6501         }
6502
6503         /* Count number of newly disabled CRTCs for dropping PM refs later. */
6504         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6505                                       new_crtc_state, i) {
6506                 if (old_crtc_state->active && !new_crtc_state->active)
6507                         crtc_disable_count++;
6508
6509                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6510                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6511
6512                 /* Update freesync active state. */
6513                 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
6514
6515                 /* Handle vrr on->off / off->on transitions */
6516                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
6517                                                 dm_new_crtc_state);
6518         }
6519
6520         /* Enable interrupts for CRTCs going through a modeset. */
6521         amdgpu_dm_enable_crtc_interrupts(dev, state, true);
6522
6523         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
6524                 if (new_crtc_state->async_flip)
6525                         wait_for_vblank = false;
6526
6527         /* update planes when needed per crtc*/
6528         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
6529                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6530
6531                 if (dm_new_crtc_state->stream)
6532                         amdgpu_dm_commit_planes(state, dc_state, dev,
6533                                                 dm, crtc, wait_for_vblank);
6534         }
6535
6536         /* Enable interrupts for CRTCs going from 0 to n active planes. */
6537         amdgpu_dm_enable_crtc_interrupts(dev, state, false);
6538
6539         /* Update audio instances for each connector. */
6540         amdgpu_dm_commit_audio(dev, state);
6541
6542         /*
6543          * send vblank event on all events not handled in flip and
6544          * mark consumed event for drm_atomic_helper_commit_hw_done
6545          */
6546         spin_lock_irqsave(&adev->ddev->event_lock, flags);
6547         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
6548
6549                 if (new_crtc_state->event)
6550                         drm_send_event_locked(dev, &new_crtc_state->event->base);
6551
6552                 new_crtc_state->event = NULL;
6553         }
6554         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6555
6556         /* Signal HW programming completion */
6557         drm_atomic_helper_commit_hw_done(state);
6558
6559         if (wait_for_vblank)
6560                 drm_atomic_helper_wait_for_flip_done(dev, state);
6561
6562         drm_atomic_helper_cleanup_planes(dev, state);
6563
6564         /*
6565          * Finally, drop a runtime PM reference for each newly disabled CRTC,
6566          * so we can put the GPU into runtime suspend if we're not driving any
6567          * displays anymore
6568          */
6569         for (i = 0; i < crtc_disable_count; i++)
6570                 pm_runtime_put_autosuspend(dev->dev);
6571         pm_runtime_mark_last_busy(dev->dev);
6572
6573         if (dc_state_temp)
6574                 dc_release_state(dc_state_temp);
6575 }
6576
6577
6578 static int dm_force_atomic_commit(struct drm_connector *connector)
6579 {
6580         int ret = 0;
6581         struct drm_device *ddev = connector->dev;
6582         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
6583         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
6584         struct drm_plane *plane = disconnected_acrtc->base.primary;
6585         struct drm_connector_state *conn_state;
6586         struct drm_crtc_state *crtc_state;
6587         struct drm_plane_state *plane_state;
6588
6589         if (!state)
6590                 return -ENOMEM;
6591
6592         state->acquire_ctx = ddev->mode_config.acquire_ctx;
6593
6594         /* Construct an atomic state to restore previous display setting */
6595
6596         /*
6597          * Attach connectors to drm_atomic_state
6598          */
6599         conn_state = drm_atomic_get_connector_state(state, connector);
6600
6601         ret = PTR_ERR_OR_ZERO(conn_state);
6602         if (ret)
6603                 goto err;
6604
6605         /* Attach crtc to drm_atomic_state*/
6606         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
6607
6608         ret = PTR_ERR_OR_ZERO(crtc_state);
6609         if (ret)
6610                 goto err;
6611
6612         /* force a restore */
6613         crtc_state->mode_changed = true;
6614
6615         /* Attach plane to drm_atomic_state */
6616         plane_state = drm_atomic_get_plane_state(state, plane);
6617
6618         ret = PTR_ERR_OR_ZERO(plane_state);
6619         if (ret)
6620                 goto err;
6621
6622
6623         /* Call commit internally with the state we just constructed */
6624         ret = drm_atomic_commit(state);
6625         if (!ret)
6626                 return 0;
6627
6628 err:
6629         DRM_ERROR("Restoring old state failed with %i\n", ret);
6630         drm_atomic_state_put(state);
6631
6632         return ret;
6633 }
6634
6635 /*
6636  * This function handles all cases when set mode does not come upon hotplug.
6637  * This includes when a display is unplugged then plugged back into the
6638  * same port and when running without usermode desktop manager supprot
6639  */
6640 void dm_restore_drm_connector_state(struct drm_device *dev,
6641                                     struct drm_connector *connector)
6642 {
6643         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6644         struct amdgpu_crtc *disconnected_acrtc;
6645         struct dm_crtc_state *acrtc_state;
6646
6647         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
6648                 return;
6649
6650         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
6651         if (!disconnected_acrtc)
6652                 return;
6653
6654         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
6655         if (!acrtc_state->stream)
6656                 return;
6657
6658         /*
6659          * If the previous sink is not released and different from the current,
6660          * we deduce we are in a state where we can not rely on usermode call
6661          * to turn on the display, so we do it here
6662          */
6663         if (acrtc_state->stream->sink != aconnector->dc_sink)
6664                 dm_force_atomic_commit(&aconnector->base);
6665 }
6666
6667 /*
6668  * Grabs all modesetting locks to serialize against any blocking commits,
6669  * Waits for completion of all non blocking commits.
6670  */
6671 static int do_aquire_global_lock(struct drm_device *dev,
6672                                  struct drm_atomic_state *state)
6673 {
6674         struct drm_crtc *crtc;
6675         struct drm_crtc_commit *commit;
6676         long ret;
6677
6678         /*
6679          * Adding all modeset locks to aquire_ctx will
6680          * ensure that when the framework release it the
6681          * extra locks we are locking here will get released to
6682          */
6683         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
6684         if (ret)
6685                 return ret;
6686
6687         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6688                 spin_lock(&crtc->commit_lock);
6689                 commit = list_first_entry_or_null(&crtc->commit_list,
6690                                 struct drm_crtc_commit, commit_entry);
6691                 if (commit)
6692                         drm_crtc_commit_get(commit);
6693                 spin_unlock(&crtc->commit_lock);
6694
6695                 if (!commit)
6696                         continue;
6697
6698                 /*
6699                  * Make sure all pending HW programming completed and
6700                  * page flips done
6701                  */
6702                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
6703
6704                 if (ret > 0)
6705                         ret = wait_for_completion_interruptible_timeout(
6706                                         &commit->flip_done, 10*HZ);
6707
6708                 if (ret == 0)
6709                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
6710                                   "timed out\n", crtc->base.id, crtc->name);
6711
6712                 drm_crtc_commit_put(commit);
6713         }
6714
6715         return ret < 0 ? ret : 0;
6716 }
6717
6718 static void get_freesync_config_for_crtc(
6719         struct dm_crtc_state *new_crtc_state,
6720         struct dm_connector_state *new_con_state)
6721 {
6722         struct mod_freesync_config config = {0};
6723         struct amdgpu_dm_connector *aconnector =
6724                         to_amdgpu_dm_connector(new_con_state->base.connector);
6725         struct drm_display_mode *mode = &new_crtc_state->base.mode;
6726         int vrefresh = drm_mode_vrefresh(mode);
6727
6728         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
6729                                         vrefresh >= aconnector->min_vfreq &&
6730                                         vrefresh <= aconnector->max_vfreq;
6731
6732         if (new_crtc_state->vrr_supported) {
6733                 new_crtc_state->stream->ignore_msa_timing_param = true;
6734                 config.state = new_crtc_state->base.vrr_enabled ?
6735                                 VRR_STATE_ACTIVE_VARIABLE :
6736                                 VRR_STATE_INACTIVE;
6737                 config.min_refresh_in_uhz =
6738                                 aconnector->min_vfreq * 1000000;
6739                 config.max_refresh_in_uhz =
6740                                 aconnector->max_vfreq * 1000000;
6741                 config.vsif_supported = true;
6742                 config.btr = true;
6743         }
6744
6745         new_crtc_state->freesync_config = config;
6746 }
6747
6748 static void reset_freesync_config_for_crtc(
6749         struct dm_crtc_state *new_crtc_state)
6750 {
6751         new_crtc_state->vrr_supported = false;
6752
6753         memset(&new_crtc_state->vrr_params, 0,
6754                sizeof(new_crtc_state->vrr_params));
6755         memset(&new_crtc_state->vrr_infopacket, 0,
6756                sizeof(new_crtc_state->vrr_infopacket));
6757 }
6758
6759 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
6760                                 struct drm_atomic_state *state,
6761                                 struct drm_crtc *crtc,
6762                                 struct drm_crtc_state *old_crtc_state,
6763                                 struct drm_crtc_state *new_crtc_state,
6764                                 bool enable,
6765                                 bool *lock_and_validation_needed)
6766 {
6767         struct dm_atomic_state *dm_state = NULL;
6768         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6769         struct dc_stream_state *new_stream;
6770         int ret = 0;
6771
6772         /*
6773          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
6774          * update changed items
6775          */
6776         struct amdgpu_crtc *acrtc = NULL;
6777         struct amdgpu_dm_connector *aconnector = NULL;
6778         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
6779         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
6780
6781         new_stream = NULL;
6782
6783         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6784         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6785         acrtc = to_amdgpu_crtc(crtc);
6786         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
6787
6788         /* TODO This hack should go away */
6789         if (aconnector && enable) {
6790                 /* Make sure fake sink is created in plug-in scenario */
6791                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
6792                                                             &aconnector->base);
6793                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
6794                                                             &aconnector->base);
6795
6796                 if (IS_ERR(drm_new_conn_state)) {
6797                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
6798                         goto fail;
6799                 }
6800
6801                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
6802                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
6803
6804                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6805                         goto skip_modeset;
6806
6807                 new_stream = create_stream_for_sink(aconnector,
6808                                                      &new_crtc_state->mode,
6809                                                     dm_new_conn_state,
6810                                                     dm_old_crtc_state->stream);
6811
6812                 /*
6813                  * we can have no stream on ACTION_SET if a display
6814                  * was disconnected during S3, in this case it is not an
6815                  * error, the OS will be updated after detection, and
6816                  * will do the right thing on next atomic commit
6817                  */
6818
6819                 if (!new_stream) {
6820                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6821                                         __func__, acrtc->base.base.id);
6822                         ret = -ENOMEM;
6823                         goto fail;
6824                 }
6825
6826                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6827
6828                 ret = fill_hdr_info_packet(drm_new_conn_state,
6829                                            &new_stream->hdr_static_metadata);
6830                 if (ret)
6831                         goto fail;
6832
6833                 /*
6834                  * If we already removed the old stream from the context
6835                  * (and set the new stream to NULL) then we can't reuse
6836                  * the old stream even if the stream and scaling are unchanged.
6837                  * We'll hit the BUG_ON and black screen.
6838                  *
6839                  * TODO: Refactor this function to allow this check to work
6840                  * in all conditions.
6841                  */
6842                 if (dm_new_crtc_state->stream &&
6843                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
6844                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
6845                         new_crtc_state->mode_changed = false;
6846                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
6847                                          new_crtc_state->mode_changed);
6848                 }
6849         }
6850
6851         /* mode_changed flag may get updated above, need to check again */
6852         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6853                 goto skip_modeset;
6854
6855         DRM_DEBUG_DRIVER(
6856                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6857                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6858                 "connectors_changed:%d\n",
6859                 acrtc->crtc_id,
6860                 new_crtc_state->enable,
6861                 new_crtc_state->active,
6862                 new_crtc_state->planes_changed,
6863                 new_crtc_state->mode_changed,
6864                 new_crtc_state->active_changed,
6865                 new_crtc_state->connectors_changed);
6866
6867         /* Remove stream for any changed/disabled CRTC */
6868         if (!enable) {
6869
6870                 if (!dm_old_crtc_state->stream)
6871                         goto skip_modeset;
6872
6873                 ret = dm_atomic_get_state(state, &dm_state);
6874                 if (ret)
6875                         goto fail;
6876
6877                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
6878                                 crtc->base.id);
6879
6880                 /* i.e. reset mode */
6881                 if (dc_remove_stream_from_ctx(
6882                                 dm->dc,
6883                                 dm_state->context,
6884                                 dm_old_crtc_state->stream) != DC_OK) {
6885                         ret = -EINVAL;
6886                         goto fail;
6887                 }
6888
6889                 dc_stream_release(dm_old_crtc_state->stream);
6890                 dm_new_crtc_state->stream = NULL;
6891
6892                 reset_freesync_config_for_crtc(dm_new_crtc_state);
6893
6894                 *lock_and_validation_needed = true;
6895
6896         } else {/* Add stream for any updated/enabled CRTC */
6897                 /*
6898                  * Quick fix to prevent NULL pointer on new_stream when
6899                  * added MST connectors not found in existing crtc_state in the chained mode
6900                  * TODO: need to dig out the root cause of that
6901                  */
6902                 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
6903                         goto skip_modeset;
6904
6905                 if (modereset_required(new_crtc_state))
6906                         goto skip_modeset;
6907
6908                 if (modeset_required(new_crtc_state, new_stream,
6909                                      dm_old_crtc_state->stream)) {
6910
6911                         WARN_ON(dm_new_crtc_state->stream);
6912
6913                         ret = dm_atomic_get_state(state, &dm_state);
6914                         if (ret)
6915                                 goto fail;
6916
6917                         dm_new_crtc_state->stream = new_stream;
6918
6919                         dc_stream_retain(new_stream);
6920
6921                         DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
6922                                                 crtc->base.id);
6923
6924                         if (dc_add_stream_to_ctx(
6925                                         dm->dc,
6926                                         dm_state->context,
6927                                         dm_new_crtc_state->stream) != DC_OK) {
6928                                 ret = -EINVAL;
6929                                 goto fail;
6930                         }
6931
6932                         *lock_and_validation_needed = true;
6933                 }
6934         }
6935
6936 skip_modeset:
6937         /* Release extra reference */
6938         if (new_stream)
6939                  dc_stream_release(new_stream);
6940
6941         /*
6942          * We want to do dc stream updates that do not require a
6943          * full modeset below.
6944          */
6945         if (!(enable && aconnector && new_crtc_state->enable &&
6946               new_crtc_state->active))
6947                 return 0;
6948         /*
6949          * Given above conditions, the dc state cannot be NULL because:
6950          * 1. We're in the process of enabling CRTCs (just been added
6951          *    to the dc context, or already is on the context)
6952          * 2. Has a valid connector attached, and
6953          * 3. Is currently active and enabled.
6954          * => The dc stream state currently exists.
6955          */
6956         BUG_ON(dm_new_crtc_state->stream == NULL);
6957
6958         /* Scaling or underscan settings */
6959         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
6960                 update_stream_scaling_settings(
6961                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
6962
6963         /* ABM settings */
6964         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6965
6966         /*
6967          * Color management settings. We also update color properties
6968          * when a modeset is needed, to ensure it gets reprogrammed.
6969          */
6970         if (dm_new_crtc_state->base.color_mgmt_changed ||
6971             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
6972                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
6973                 if (ret)
6974                         goto fail;
6975         }
6976
6977         /* Update Freesync settings. */
6978         get_freesync_config_for_crtc(dm_new_crtc_state,
6979                                      dm_new_conn_state);
6980
6981         return ret;
6982
6983 fail:
6984         if (new_stream)
6985                 dc_stream_release(new_stream);
6986         return ret;
6987 }
6988
6989 static bool should_reset_plane(struct drm_atomic_state *state,
6990                                struct drm_plane *plane,
6991                                struct drm_plane_state *old_plane_state,
6992                                struct drm_plane_state *new_plane_state)
6993 {
6994         struct drm_plane *other;
6995         struct drm_plane_state *old_other_state, *new_other_state;
6996         struct drm_crtc_state *new_crtc_state;
6997         int i;
6998
6999         /*
7000          * TODO: Remove this hack once the checks below are sufficient
7001          * enough to determine when we need to reset all the planes on
7002          * the stream.
7003          */
7004         if (state->allow_modeset)
7005                 return true;
7006
7007         /* Exit early if we know that we're adding or removing the plane. */
7008         if (old_plane_state->crtc != new_plane_state->crtc)
7009                 return true;
7010
7011         /* old crtc == new_crtc == NULL, plane not in context. */
7012         if (!new_plane_state->crtc)
7013                 return false;
7014
7015         new_crtc_state =
7016                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
7017
7018         if (!new_crtc_state)
7019                 return true;
7020
7021         /* CRTC Degamma changes currently require us to recreate planes. */
7022         if (new_crtc_state->color_mgmt_changed)
7023                 return true;
7024
7025         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
7026                 return true;
7027
7028         /*
7029          * If there are any new primary or overlay planes being added or
7030          * removed then the z-order can potentially change. To ensure
7031          * correct z-order and pipe acquisition the current DC architecture
7032          * requires us to remove and recreate all existing planes.
7033          *
7034          * TODO: Come up with a more elegant solution for this.
7035          */
7036         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
7037                 if (other->type == DRM_PLANE_TYPE_CURSOR)
7038                         continue;
7039
7040                 if (old_other_state->crtc != new_plane_state->crtc &&
7041                     new_other_state->crtc != new_plane_state->crtc)
7042                         continue;
7043
7044                 if (old_other_state->crtc != new_other_state->crtc)
7045                         return true;
7046
7047                 /* TODO: Remove this once we can handle fast format changes. */
7048                 if (old_other_state->fb && new_other_state->fb &&
7049                     old_other_state->fb->format != new_other_state->fb->format)
7050                         return true;
7051         }
7052
7053         return false;
7054 }
7055
7056 static int dm_update_plane_state(struct dc *dc,
7057                                  struct drm_atomic_state *state,
7058                                  struct drm_plane *plane,
7059                                  struct drm_plane_state *old_plane_state,
7060                                  struct drm_plane_state *new_plane_state,
7061                                  bool enable,
7062                                  bool *lock_and_validation_needed)
7063 {
7064
7065         struct dm_atomic_state *dm_state = NULL;
7066         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
7067         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7068         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
7069         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
7070         bool needs_reset;
7071         int ret = 0;
7072
7073
7074         new_plane_crtc = new_plane_state->crtc;
7075         old_plane_crtc = old_plane_state->crtc;
7076         dm_new_plane_state = to_dm_plane_state(new_plane_state);
7077         dm_old_plane_state = to_dm_plane_state(old_plane_state);
7078
7079         /*TODO Implement atomic check for cursor plane */
7080         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7081                 return 0;
7082
7083         needs_reset = should_reset_plane(state, plane, old_plane_state,
7084                                          new_plane_state);
7085
7086         /* Remove any changed/removed planes */
7087         if (!enable) {
7088                 if (!needs_reset)
7089                         return 0;
7090
7091                 if (!old_plane_crtc)
7092                         return 0;
7093
7094                 old_crtc_state = drm_atomic_get_old_crtc_state(
7095                                 state, old_plane_crtc);
7096                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7097
7098                 if (!dm_old_crtc_state->stream)
7099                         return 0;
7100
7101                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
7102                                 plane->base.id, old_plane_crtc->base.id);
7103
7104                 ret = dm_atomic_get_state(state, &dm_state);
7105                 if (ret)
7106                         return ret;
7107
7108                 if (!dc_remove_plane_from_context(
7109                                 dc,
7110                                 dm_old_crtc_state->stream,
7111                                 dm_old_plane_state->dc_state,
7112                                 dm_state->context)) {
7113
7114                         ret = EINVAL;
7115                         return ret;
7116                 }
7117
7118
7119                 dc_plane_state_release(dm_old_plane_state->dc_state);
7120                 dm_new_plane_state->dc_state = NULL;
7121
7122                 *lock_and_validation_needed = true;
7123
7124         } else { /* Add new planes */
7125                 struct dc_plane_state *dc_new_plane_state;
7126
7127                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
7128                         return 0;
7129
7130                 if (!new_plane_crtc)
7131                         return 0;
7132
7133                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
7134                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7135
7136                 if (!dm_new_crtc_state->stream)
7137                         return 0;
7138
7139                 if (!needs_reset)
7140                         return 0;
7141
7142                 WARN_ON(dm_new_plane_state->dc_state);
7143
7144                 dc_new_plane_state = dc_create_plane_state(dc);
7145                 if (!dc_new_plane_state)
7146                         return -ENOMEM;
7147
7148                 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
7149                                 plane->base.id, new_plane_crtc->base.id);
7150
7151                 ret = fill_dc_plane_attributes(
7152                         new_plane_crtc->dev->dev_private,
7153                         dc_new_plane_state,
7154                         new_plane_state,
7155                         new_crtc_state);
7156                 if (ret) {
7157                         dc_plane_state_release(dc_new_plane_state);
7158                         return ret;
7159                 }
7160
7161                 ret = dm_atomic_get_state(state, &dm_state);
7162                 if (ret) {
7163                         dc_plane_state_release(dc_new_plane_state);
7164                         return ret;
7165                 }
7166
7167                 /*
7168                  * Any atomic check errors that occur after this will
7169                  * not need a release. The plane state will be attached
7170                  * to the stream, and therefore part of the atomic
7171                  * state. It'll be released when the atomic state is
7172                  * cleaned.
7173                  */
7174                 if (!dc_add_plane_to_context(
7175                                 dc,
7176                                 dm_new_crtc_state->stream,
7177                                 dc_new_plane_state,
7178                                 dm_state->context)) {
7179
7180                         dc_plane_state_release(dc_new_plane_state);
7181                         return -EINVAL;
7182                 }
7183
7184                 dm_new_plane_state->dc_state = dc_new_plane_state;
7185
7186                 /* Tell DC to do a full surface update every time there
7187                  * is a plane change. Inefficient, but works for now.
7188                  */
7189                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
7190
7191                 *lock_and_validation_needed = true;
7192         }
7193
7194
7195         return ret;
7196 }
7197
7198 static int
7199 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
7200                                     struct drm_atomic_state *state,
7201                                     enum surface_update_type *out_type)
7202 {
7203         struct dc *dc = dm->dc;
7204         struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
7205         int i, j, num_plane, ret = 0;
7206         struct drm_plane_state *old_plane_state, *new_plane_state;
7207         struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
7208         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
7209         struct drm_plane *plane;
7210
7211         struct drm_crtc *crtc;
7212         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
7213         struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
7214         struct dc_stream_status *status = NULL;
7215
7216         struct dc_surface_update *updates;
7217         enum surface_update_type update_type = UPDATE_TYPE_FAST;
7218
7219         updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
7220
7221         if (!updates) {
7222                 DRM_ERROR("Failed to allocate plane updates\n");
7223                 /* Set type to FULL to avoid crashing in DC*/
7224                 update_type = UPDATE_TYPE_FULL;
7225                 goto cleanup;
7226         }
7227
7228         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7229                 struct dc_scaling_info scaling_info;
7230                 struct dc_stream_update stream_update;
7231
7232                 memset(&stream_update, 0, sizeof(stream_update));
7233
7234                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7235                 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
7236                 num_plane = 0;
7237
7238                 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
7239                         update_type = UPDATE_TYPE_FULL;
7240                         goto cleanup;
7241                 }
7242
7243                 if (!new_dm_crtc_state->stream)
7244                         continue;
7245
7246                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
7247                         const struct amdgpu_framebuffer *amdgpu_fb =
7248                                 to_amdgpu_framebuffer(new_plane_state->fb);
7249                         struct dc_plane_info plane_info;
7250                         struct dc_flip_addrs flip_addr;
7251                         uint64_t tiling_flags;
7252
7253                         new_plane_crtc = new_plane_state->crtc;
7254                         old_plane_crtc = old_plane_state->crtc;
7255                         new_dm_plane_state = to_dm_plane_state(new_plane_state);
7256                         old_dm_plane_state = to_dm_plane_state(old_plane_state);
7257
7258                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7259                                 continue;
7260
7261                         if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
7262                                 update_type = UPDATE_TYPE_FULL;
7263                                 goto cleanup;
7264                         }
7265
7266                         if (crtc != new_plane_crtc)
7267                                 continue;
7268
7269                         updates[num_plane].surface = new_dm_plane_state->dc_state;
7270
7271                         if (new_crtc_state->mode_changed) {
7272                                 stream_update.dst = new_dm_crtc_state->stream->dst;
7273                                 stream_update.src = new_dm_crtc_state->stream->src;
7274                         }
7275
7276                         if (new_crtc_state->color_mgmt_changed) {
7277                                 updates[num_plane].gamma =
7278                                                 new_dm_plane_state->dc_state->gamma_correction;
7279                                 updates[num_plane].in_transfer_func =
7280                                                 new_dm_plane_state->dc_state->in_transfer_func;
7281                                 stream_update.gamut_remap =
7282                                                 &new_dm_crtc_state->stream->gamut_remap_matrix;
7283                                 stream_update.output_csc_transform =
7284                                                 &new_dm_crtc_state->stream->csc_color_matrix;
7285                                 stream_update.out_transfer_func =
7286                                                 new_dm_crtc_state->stream->out_transfer_func;
7287                         }
7288
7289                         ret = fill_dc_scaling_info(new_plane_state,
7290                                                    &scaling_info);
7291                         if (ret)
7292                                 goto cleanup;
7293
7294                         updates[num_plane].scaling_info = &scaling_info;
7295
7296                         if (amdgpu_fb) {
7297                                 ret = get_fb_info(amdgpu_fb, &tiling_flags);
7298                                 if (ret)
7299                                         goto cleanup;
7300
7301                                 memset(&flip_addr, 0, sizeof(flip_addr));
7302
7303                                 ret = fill_dc_plane_info_and_addr(
7304                                         dm->adev, new_plane_state, tiling_flags,
7305                                         &plane_info,
7306                                         &flip_addr.address);
7307                                 if (ret)
7308                                         goto cleanup;
7309
7310                                 updates[num_plane].plane_info = &plane_info;
7311                                 updates[num_plane].flip_addr = &flip_addr;
7312                         }
7313
7314                         num_plane++;
7315                 }
7316
7317                 if (num_plane == 0)
7318                         continue;
7319
7320                 ret = dm_atomic_get_state(state, &dm_state);
7321                 if (ret)
7322                         goto cleanup;
7323
7324                 old_dm_state = dm_atomic_get_old_state(state);
7325                 if (!old_dm_state) {
7326                         ret = -EINVAL;
7327                         goto cleanup;
7328                 }
7329
7330                 status = dc_stream_get_status_from_state(old_dm_state->context,
7331                                                          new_dm_crtc_state->stream);
7332                 stream_update.stream = new_dm_crtc_state->stream;
7333                 /*
7334                  * TODO: DC modifies the surface during this call so we need
7335                  * to lock here - find a way to do this without locking.
7336                  */
7337                 mutex_lock(&dm->dc_lock);
7338                 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
7339                                                                   &stream_update, status);
7340                 mutex_unlock(&dm->dc_lock);
7341
7342                 if (update_type > UPDATE_TYPE_MED) {
7343                         update_type = UPDATE_TYPE_FULL;
7344                         goto cleanup;
7345                 }
7346         }
7347
7348 cleanup:
7349         kfree(updates);
7350
7351         *out_type = update_type;
7352         return ret;
7353 }
7354
7355 /**
7356  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
7357  * @dev: The DRM device
7358  * @state: The atomic state to commit
7359  *
7360  * Validate that the given atomic state is programmable by DC into hardware.
7361  * This involves constructing a &struct dc_state reflecting the new hardware
7362  * state we wish to commit, then querying DC to see if it is programmable. It's
7363  * important not to modify the existing DC state. Otherwise, atomic_check
7364  * may unexpectedly commit hardware changes.
7365  *
7366  * When validating the DC state, it's important that the right locks are
7367  * acquired. For full updates case which removes/adds/updates streams on one
7368  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
7369  * that any such full update commit will wait for completion of any outstanding
7370  * flip using DRMs synchronization events. See
7371  * dm_determine_update_type_for_commit()
7372  *
7373  * Note that DM adds the affected connectors for all CRTCs in state, when that
7374  * might not seem necessary. This is because DC stream creation requires the
7375  * DC sink, which is tied to the DRM connector state. Cleaning this up should
7376  * be possible but non-trivial - a possible TODO item.
7377  *
7378  * Return: -Error code if validation failed.
7379  */
7380 static int amdgpu_dm_atomic_check(struct drm_device *dev,
7381                                   struct drm_atomic_state *state)
7382 {
7383         struct amdgpu_device *adev = dev->dev_private;
7384         struct dm_atomic_state *dm_state = NULL;
7385         struct dc *dc = adev->dm.dc;
7386         struct drm_connector *connector;
7387         struct drm_connector_state *old_con_state, *new_con_state;
7388         struct drm_crtc *crtc;
7389         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7390         struct drm_plane *plane;
7391         struct drm_plane_state *old_plane_state, *new_plane_state;
7392         enum surface_update_type update_type = UPDATE_TYPE_FAST;
7393         enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
7394
7395         int ret, i;
7396
7397         /*
7398          * This bool will be set for true for any modeset/reset
7399          * or plane update which implies non fast surface update.
7400          */
7401         bool lock_and_validation_needed = false;
7402
7403         ret = drm_atomic_helper_check_modeset(dev, state);
7404         if (ret)
7405                 goto fail;
7406
7407         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7408                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
7409                     !new_crtc_state->color_mgmt_changed &&
7410                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
7411                         continue;
7412
7413                 if (!new_crtc_state->enable)
7414                         continue;
7415
7416                 ret = drm_atomic_add_affected_connectors(state, crtc);
7417                 if (ret)
7418                         return ret;
7419
7420                 ret = drm_atomic_add_affected_planes(state, crtc);
7421                 if (ret)
7422                         goto fail;
7423         }
7424
7425         /*
7426          * Add all primary and overlay planes on the CRTC to the state
7427          * whenever a plane is enabled to maintain correct z-ordering
7428          * and to enable fast surface updates.
7429          */
7430         drm_for_each_crtc(crtc, dev) {
7431                 bool modified = false;
7432
7433                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7434                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7435                                 continue;
7436
7437                         if (new_plane_state->crtc == crtc ||
7438                             old_plane_state->crtc == crtc) {
7439                                 modified = true;
7440                                 break;
7441                         }
7442                 }
7443
7444                 if (!modified)
7445                         continue;
7446
7447                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
7448                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7449                                 continue;
7450
7451                         new_plane_state =
7452                                 drm_atomic_get_plane_state(state, plane);
7453
7454                         if (IS_ERR(new_plane_state)) {
7455                                 ret = PTR_ERR(new_plane_state);
7456                                 goto fail;
7457                         }
7458                 }
7459         }
7460
7461         /* Remove exiting planes if they are modified */
7462         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7463                 ret = dm_update_plane_state(dc, state, plane,
7464                                             old_plane_state,
7465                                             new_plane_state,
7466                                             false,
7467                                             &lock_and_validation_needed);
7468                 if (ret)
7469                         goto fail;
7470         }
7471
7472         /* Disable all crtcs which require disable */
7473         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7474                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7475                                            old_crtc_state,
7476                                            new_crtc_state,
7477                                            false,
7478                                            &lock_and_validation_needed);
7479                 if (ret)
7480                         goto fail;
7481         }
7482
7483         /* Enable all crtcs which require enable */
7484         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7485                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7486                                            old_crtc_state,
7487                                            new_crtc_state,
7488                                            true,
7489                                            &lock_and_validation_needed);
7490                 if (ret)
7491                         goto fail;
7492         }
7493
7494         /* Add new/modified planes */
7495         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7496                 ret = dm_update_plane_state(dc, state, plane,
7497                                             old_plane_state,
7498                                             new_plane_state,
7499                                             true,
7500                                             &lock_and_validation_needed);
7501                 if (ret)
7502                         goto fail;
7503         }
7504
7505         /* Run this here since we want to validate the streams we created */
7506         ret = drm_atomic_helper_check_planes(dev, state);
7507         if (ret)
7508                 goto fail;
7509
7510         if (state->legacy_cursor_update) {
7511                 /*
7512                  * This is a fast cursor update coming from the plane update
7513                  * helper, check if it can be done asynchronously for better
7514                  * performance.
7515                  */
7516                 state->async_update =
7517                         !drm_atomic_helper_async_check(dev, state);
7518
7519                 /*
7520                  * Skip the remaining global validation if this is an async
7521                  * update. Cursor updates can be done without affecting
7522                  * state or bandwidth calcs and this avoids the performance
7523                  * penalty of locking the private state object and
7524                  * allocating a new dc_state.
7525                  */
7526                 if (state->async_update)
7527                         return 0;
7528         }
7529
7530         /* Check scaling and underscan changes*/
7531         /* TODO Removed scaling changes validation due to inability to commit
7532          * new stream into context w\o causing full reset. Need to
7533          * decide how to handle.
7534          */
7535         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
7536                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
7537                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
7538                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
7539
7540                 /* Skip any modesets/resets */
7541                 if (!acrtc || drm_atomic_crtc_needs_modeset(
7542                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
7543                         continue;
7544
7545                 /* Skip any thing not scale or underscan changes */
7546                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
7547                         continue;
7548
7549                 overall_update_type = UPDATE_TYPE_FULL;
7550                 lock_and_validation_needed = true;
7551         }
7552
7553         ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
7554         if (ret)
7555                 goto fail;
7556
7557         if (overall_update_type < update_type)
7558                 overall_update_type = update_type;
7559
7560         /*
7561          * lock_and_validation_needed was an old way to determine if we need to set
7562          * the global lock. Leaving it in to check if we broke any corner cases
7563          * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
7564          * lock_and_validation_needed false = UPDATE_TYPE_FAST
7565          */
7566         if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
7567                 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
7568
7569         if (overall_update_type > UPDATE_TYPE_FAST) {
7570                 ret = dm_atomic_get_state(state, &dm_state);
7571                 if (ret)
7572                         goto fail;
7573
7574                 ret = do_aquire_global_lock(dev, state);
7575                 if (ret)
7576                         goto fail;
7577
7578                 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
7579                         ret = -EINVAL;
7580                         goto fail;
7581                 }
7582         } else {
7583                 /*
7584                  * The commit is a fast update. Fast updates shouldn't change
7585                  * the DC context, affect global validation, and can have their
7586                  * commit work done in parallel with other commits not touching
7587                  * the same resource. If we have a new DC context as part of
7588                  * the DM atomic state from validation we need to free it and
7589                  * retain the existing one instead.
7590                  */
7591                 struct dm_atomic_state *new_dm_state, *old_dm_state;
7592
7593                 new_dm_state = dm_atomic_get_new_state(state);
7594                 old_dm_state = dm_atomic_get_old_state(state);
7595
7596                 if (new_dm_state && old_dm_state) {
7597                         if (new_dm_state->context)
7598                                 dc_release_state(new_dm_state->context);
7599
7600                         new_dm_state->context = old_dm_state->context;
7601
7602                         if (old_dm_state->context)
7603                                 dc_retain_state(old_dm_state->context);
7604                 }
7605         }
7606
7607         /* Store the overall update type for use later in atomic check. */
7608         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
7609                 struct dm_crtc_state *dm_new_crtc_state =
7610                         to_dm_crtc_state(new_crtc_state);
7611
7612                 dm_new_crtc_state->update_type = (int)overall_update_type;
7613         }
7614
7615         /* Must be success */
7616         WARN_ON(ret);
7617         return ret;
7618
7619 fail:
7620         if (ret == -EDEADLK)
7621                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
7622         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
7623                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
7624         else
7625                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
7626
7627         return ret;
7628 }
7629
7630 static bool is_dp_capable_without_timing_msa(struct dc *dc,
7631                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
7632 {
7633         uint8_t dpcd_data;
7634         bool capable = false;
7635
7636         if (amdgpu_dm_connector->dc_link &&
7637                 dm_helpers_dp_read_dpcd(
7638                                 NULL,
7639                                 amdgpu_dm_connector->dc_link,
7640                                 DP_DOWN_STREAM_PORT_COUNT,
7641                                 &dpcd_data,
7642                                 sizeof(dpcd_data))) {
7643                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
7644         }
7645
7646         return capable;
7647 }
7648 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
7649                                         struct edid *edid)
7650 {
7651         int i;
7652         bool edid_check_required;
7653         struct detailed_timing *timing;
7654         struct detailed_non_pixel *data;
7655         struct detailed_data_monitor_range *range;
7656         struct amdgpu_dm_connector *amdgpu_dm_connector =
7657                         to_amdgpu_dm_connector(connector);
7658         struct dm_connector_state *dm_con_state = NULL;
7659
7660         struct drm_device *dev = connector->dev;
7661         struct amdgpu_device *adev = dev->dev_private;
7662         bool freesync_capable = false;
7663
7664         if (!connector->state) {
7665                 DRM_ERROR("%s - Connector has no state", __func__);
7666                 goto update;
7667         }
7668
7669         if (!edid) {
7670                 dm_con_state = to_dm_connector_state(connector->state);
7671
7672                 amdgpu_dm_connector->min_vfreq = 0;
7673                 amdgpu_dm_connector->max_vfreq = 0;
7674                 amdgpu_dm_connector->pixel_clock_mhz = 0;
7675
7676                 goto update;
7677         }
7678
7679         dm_con_state = to_dm_connector_state(connector->state);
7680
7681         edid_check_required = false;
7682         if (!amdgpu_dm_connector->dc_sink) {
7683                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
7684                 goto update;
7685         }
7686         if (!adev->dm.freesync_module)
7687                 goto update;
7688         /*
7689          * if edid non zero restrict freesync only for dp and edp
7690          */
7691         if (edid) {
7692                 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
7693                         || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
7694                         edid_check_required = is_dp_capable_without_timing_msa(
7695                                                 adev->dm.dc,
7696                                                 amdgpu_dm_connector);
7697                 }
7698         }
7699         if (edid_check_required == true && (edid->version > 1 ||
7700            (edid->version == 1 && edid->revision > 1))) {
7701                 for (i = 0; i < 4; i++) {
7702
7703                         timing  = &edid->detailed_timings[i];
7704                         data    = &timing->data.other_data;
7705                         range   = &data->data.range;
7706                         /*
7707                          * Check if monitor has continuous frequency mode
7708                          */
7709                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
7710                                 continue;
7711                         /*
7712                          * Check for flag range limits only. If flag == 1 then
7713                          * no additional timing information provided.
7714                          * Default GTF, GTF Secondary curve and CVT are not
7715                          * supported
7716                          */
7717                         if (range->flags != 1)
7718                                 continue;
7719
7720                         amdgpu_dm_connector->min_vfreq = range->min_vfreq;
7721                         amdgpu_dm_connector->max_vfreq = range->max_vfreq;
7722                         amdgpu_dm_connector->pixel_clock_mhz =
7723                                 range->pixel_clock_mhz * 10;
7724                         break;
7725                 }
7726
7727                 if (amdgpu_dm_connector->max_vfreq -
7728                     amdgpu_dm_connector->min_vfreq > 10) {
7729
7730                         freesync_capable = true;
7731                 }
7732         }
7733
7734 update:
7735         if (dm_con_state)
7736                 dm_con_state->freesync_capable = freesync_capable;
7737
7738         if (connector->vrr_capable_property)
7739                 drm_connector_set_vrr_capable_property(connector,
7740                                                        freesync_capable);
7741 }
7742