2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct i915_gpu_error *error)
94 #define EXIT_COND (!i915_reset_in_progress(error) || \
95 i915_terminally_wedged(error))
100 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
101 * userspace. If it takes that long something really bad is going on and
102 * we should simply try to bail out and fail as gracefully as possible.
104 ret = wait_event_interruptible_timeout(error->reset_queue,
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret < 0) {
118 int i915_mutex_lock_interruptible(struct drm_device *dev)
120 struct drm_i915_private *dev_priv = dev->dev_private;
123 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
127 ret = mutex_lock_interruptible(&dev->struct_mutex);
131 WARN_ON(i915_verify_lists(dev));
136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
138 return obj->gtt_space && !obj->active;
142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
143 struct drm_file *file)
145 struct drm_i915_private *dev_priv = dev->dev_private;
146 struct drm_i915_gem_init *args = data;
148 if (drm_core_check_feature(dev, DRIVER_MODESET))
151 if (args->gtt_start >= args->gtt_end ||
152 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
155 /* GEM with user mode setting was never supported on ilk and later. */
156 if (INTEL_INFO(dev)->gen >= 5)
159 mutex_lock(&dev->struct_mutex);
160 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
162 dev_priv->gtt.mappable_end = args->gtt_end;
163 mutex_unlock(&dev->struct_mutex);
169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_get_aperture *args = data;
174 struct drm_i915_gem_object *obj;
178 mutex_lock(&dev->struct_mutex);
179 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
181 pinned += obj->gtt_space->size;
182 mutex_unlock(&dev->struct_mutex);
184 args->aper_size = dev_priv->gtt.total;
185 args->aper_available_size = args->aper_size - pinned;
190 void *i915_gem_object_alloc(struct drm_device *dev)
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
198 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
199 kmem_cache_free(dev_priv->slab, obj);
203 i915_gem_create(struct drm_file *file,
204 struct drm_device *dev,
208 struct drm_i915_gem_object *obj;
212 size = roundup(size, PAGE_SIZE);
216 /* Allocate the new object */
217 obj = i915_gem_alloc_object(dev, size);
221 ret = drm_gem_handle_create(file, &obj->base, &handle);
223 drm_gem_object_release(&obj->base);
224 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
225 i915_gem_object_free(obj);
229 /* drop reference from allocate - handle holds it now */
230 drm_gem_object_unreference(&obj->base);
231 trace_i915_gem_object_create(obj);
238 i915_gem_dumb_create(struct drm_file *file,
239 struct drm_device *dev,
240 struct drm_mode_create_dumb *args)
242 /* have to work out size/pitch and return them */
243 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
244 args->size = args->pitch * args->height;
245 return i915_gem_create(file, dev,
246 args->size, &args->handle);
249 int i915_gem_dumb_destroy(struct drm_file *file,
250 struct drm_device *dev,
253 return drm_gem_handle_delete(file, handle);
257 * Creates a new mm object and returns a handle to it.
260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
261 struct drm_file *file)
263 struct drm_i915_gem_create *args = data;
265 return i915_gem_create(file, dev,
266 args->size, &args->handle);
270 __copy_to_user_swizzled(char __user *cpu_vaddr,
271 const char *gpu_vaddr, int gpu_offset,
274 int ret, cpu_offset = 0;
277 int cacheline_end = ALIGN(gpu_offset + 1, 64);
278 int this_length = min(cacheline_end - gpu_offset, length);
279 int swizzled_gpu_offset = gpu_offset ^ 64;
281 ret = __copy_to_user(cpu_vaddr + cpu_offset,
282 gpu_vaddr + swizzled_gpu_offset,
287 cpu_offset += this_length;
288 gpu_offset += this_length;
289 length -= this_length;
296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
297 const char __user *cpu_vaddr,
300 int ret, cpu_offset = 0;
303 int cacheline_end = ALIGN(gpu_offset + 1, 64);
304 int this_length = min(cacheline_end - gpu_offset, length);
305 int swizzled_gpu_offset = gpu_offset ^ 64;
307 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
308 cpu_vaddr + cpu_offset,
313 cpu_offset += this_length;
314 gpu_offset += this_length;
315 length -= this_length;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
326 char __user *user_data,
327 bool page_do_bit17_swizzling, bool needs_clflush)
332 if (unlikely(page_do_bit17_swizzling))
335 vaddr = kmap_atomic(page);
337 drm_clflush_virt_range(vaddr + shmem_page_offset,
339 ret = __copy_to_user_inatomic(user_data,
340 vaddr + shmem_page_offset,
342 kunmap_atomic(vaddr);
344 return ret ? -EFAULT : 0;
348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
351 if (unlikely(swizzled)) {
352 unsigned long start = (unsigned long) addr;
353 unsigned long end = (unsigned long) addr + length;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start = round_down(start, 128);
360 end = round_up(end, 128);
362 drm_clflush_virt_range((void *)start, end - start);
364 drm_clflush_virt_range(addr, length);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
373 char __user *user_data,
374 bool page_do_bit17_swizzling, bool needs_clflush)
381 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
383 page_do_bit17_swizzling);
385 if (page_do_bit17_swizzling)
386 ret = __copy_to_user_swizzled(user_data,
387 vaddr, shmem_page_offset,
390 ret = __copy_to_user(user_data,
391 vaddr + shmem_page_offset,
395 return ret ? - EFAULT : 0;
399 i915_gem_shmem_pread(struct drm_device *dev,
400 struct drm_i915_gem_object *obj,
401 struct drm_i915_gem_pread *args,
402 struct drm_file *file)
404 char __user *user_data;
407 int shmem_page_offset, page_length, ret = 0;
408 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
410 int needs_clflush = 0;
411 struct sg_page_iter sg_iter;
413 user_data = to_user_ptr(args->data_ptr);
416 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
418 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
419 /* If we're not in the cpu read domain, set ourself into the gtt
420 * read domain and manually flush cachelines (if required). This
421 * optimizes for the case when the gpu will dirty the data
422 * anyway again before the next pread happens. */
423 if (obj->cache_level == I915_CACHE_NONE)
425 if (obj->gtt_space) {
426 ret = i915_gem_object_set_to_gtt_domain(obj, false);
432 ret = i915_gem_object_get_pages(obj);
436 i915_gem_object_pin_pages(obj);
438 offset = args->offset;
440 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
441 offset >> PAGE_SHIFT) {
442 struct page *page = sg_page_iter_page(&sg_iter);
447 /* Operation in this page
449 * shmem_page_offset = offset within page in shmem file
450 * page_length = bytes to copy for this page
452 shmem_page_offset = offset_in_page(offset);
453 page_length = remain;
454 if ((shmem_page_offset + page_length) > PAGE_SIZE)
455 page_length = PAGE_SIZE - shmem_page_offset;
457 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
458 (page_to_phys(page) & (1 << 17)) != 0;
460 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
461 user_data, page_do_bit17_swizzling,
466 mutex_unlock(&dev->struct_mutex);
469 ret = fault_in_multipages_writeable(user_data, remain);
470 /* Userspace is tricking us, but we've already clobbered
471 * its pages with the prefault and promised to write the
472 * data up to the first fault. Hence ignore any errors
473 * and just continue. */
478 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
479 user_data, page_do_bit17_swizzling,
482 mutex_lock(&dev->struct_mutex);
485 mark_page_accessed(page);
490 remain -= page_length;
491 user_data += page_length;
492 offset += page_length;
496 i915_gem_object_unpin_pages(obj);
502 * Reads data from the object referenced by handle.
504 * On error, the contents of *data are undefined.
507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
508 struct drm_file *file)
510 struct drm_i915_gem_pread *args = data;
511 struct drm_i915_gem_object *obj;
517 if (!access_ok(VERIFY_WRITE,
518 to_user_ptr(args->data_ptr),
522 ret = i915_mutex_lock_interruptible(dev);
526 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
527 if (&obj->base == NULL) {
532 /* Bounds check source. */
533 if (args->offset > obj->base.size ||
534 args->size > obj->base.size - args->offset) {
539 /* prime objects have no backing filp to GEM pread/pwrite
542 if (!obj->base.filp) {
547 trace_i915_gem_object_pread(obj, args->offset, args->size);
549 ret = i915_gem_shmem_pread(dev, obj, args, file);
552 drm_gem_object_unreference(&obj->base);
554 mutex_unlock(&dev->struct_mutex);
558 /* This is the fast write path which cannot handle
559 * page faults in the source data
563 fast_user_write(struct io_mapping *mapping,
564 loff_t page_base, int page_offset,
565 char __user *user_data,
568 void __iomem *vaddr_atomic;
570 unsigned long unwritten;
572 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
573 /* We can use the cpu mem copy function because this is X86. */
574 vaddr = (void __force*)vaddr_atomic + page_offset;
575 unwritten = __copy_from_user_inatomic_nocache(vaddr,
577 io_mapping_unmap_atomic(vaddr_atomic);
582 * This is the fast pwrite path, where we copy the data directly from the
583 * user into the GTT, uncached.
586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
587 struct drm_i915_gem_object *obj,
588 struct drm_i915_gem_pwrite *args,
589 struct drm_file *file)
591 drm_i915_private_t *dev_priv = dev->dev_private;
593 loff_t offset, page_base;
594 char __user *user_data;
595 int page_offset, page_length, ret;
597 ret = i915_gem_object_pin(obj, 0, true, true);
601 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 ret = i915_gem_object_put_fence(obj);
609 user_data = to_user_ptr(args->data_ptr);
612 offset = obj->gtt_offset + args->offset;
615 /* Operation in this page
617 * page_base = page offset within aperture
618 * page_offset = offset within page
619 * page_length = bytes to copy for this page
621 page_base = offset & PAGE_MASK;
622 page_offset = offset_in_page(offset);
623 page_length = remain;
624 if ((page_offset + remain) > PAGE_SIZE)
625 page_length = PAGE_SIZE - page_offset;
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
631 if (fast_user_write(dev_priv->gtt.mappable, page_base,
632 page_offset, user_data, page_length)) {
637 remain -= page_length;
638 user_data += page_length;
639 offset += page_length;
643 i915_gem_object_unpin(obj);
648 /* Per-page copy function for the shmem pwrite fastpath.
649 * Flushes invalid cachelines before writing to the target if
650 * needs_clflush_before is set and flushes out any written cachelines after
651 * writing if needs_clflush is set. */
653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
654 char __user *user_data,
655 bool page_do_bit17_swizzling,
656 bool needs_clflush_before,
657 bool needs_clflush_after)
662 if (unlikely(page_do_bit17_swizzling))
665 vaddr = kmap_atomic(page);
666 if (needs_clflush_before)
667 drm_clflush_virt_range(vaddr + shmem_page_offset,
669 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
672 if (needs_clflush_after)
673 drm_clflush_virt_range(vaddr + shmem_page_offset,
675 kunmap_atomic(vaddr);
677 return ret ? -EFAULT : 0;
680 /* Only difference to the fast-path function is that this can handle bit17
681 * and uses non-atomic copy and kmap functions. */
683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
684 char __user *user_data,
685 bool page_do_bit17_swizzling,
686 bool needs_clflush_before,
687 bool needs_clflush_after)
693 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
694 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
696 page_do_bit17_swizzling);
697 if (page_do_bit17_swizzling)
698 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
702 ret = __copy_from_user(vaddr + shmem_page_offset,
705 if (needs_clflush_after)
706 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
708 page_do_bit17_swizzling);
711 return ret ? -EFAULT : 0;
715 i915_gem_shmem_pwrite(struct drm_device *dev,
716 struct drm_i915_gem_object *obj,
717 struct drm_i915_gem_pwrite *args,
718 struct drm_file *file)
722 char __user *user_data;
723 int shmem_page_offset, page_length, ret = 0;
724 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
725 int hit_slowpath = 0;
726 int needs_clflush_after = 0;
727 int needs_clflush_before = 0;
728 struct sg_page_iter sg_iter;
730 user_data = to_user_ptr(args->data_ptr);
733 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
735 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
736 /* If we're not in the cpu write domain, set ourself into the gtt
737 * write domain and manually flush cachelines (if required). This
738 * optimizes for the case when the gpu will use the data
739 * right away and we therefore have to clflush anyway. */
740 if (obj->cache_level == I915_CACHE_NONE)
741 needs_clflush_after = 1;
742 if (obj->gtt_space) {
743 ret = i915_gem_object_set_to_gtt_domain(obj, true);
748 /* Same trick applies for invalidate partially written cachelines before
750 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
751 && obj->cache_level == I915_CACHE_NONE)
752 needs_clflush_before = 1;
754 ret = i915_gem_object_get_pages(obj);
758 i915_gem_object_pin_pages(obj);
760 offset = args->offset;
763 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
764 offset >> PAGE_SHIFT) {
765 struct page *page = sg_page_iter_page(&sg_iter);
766 int partial_cacheline_write;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset = offset_in_page(offset);
778 page_length = remain;
779 if ((shmem_page_offset + page_length) > PAGE_SIZE)
780 page_length = PAGE_SIZE - shmem_page_offset;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write = needs_clflush_before &&
786 ((shmem_page_offset | page_length)
787 & (boot_cpu_data.x86_clflush_size - 1));
789 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
790 (page_to_phys(page) & (1 << 17)) != 0;
792 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
793 user_data, page_do_bit17_swizzling,
794 partial_cacheline_write,
795 needs_clflush_after);
800 mutex_unlock(&dev->struct_mutex);
801 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
802 user_data, page_do_bit17_swizzling,
803 partial_cacheline_write,
804 needs_clflush_after);
806 mutex_lock(&dev->struct_mutex);
809 set_page_dirty(page);
810 mark_page_accessed(page);
815 remain -= page_length;
816 user_data += page_length;
817 offset += page_length;
821 i915_gem_object_unpin_pages(obj);
825 * Fixup: Flush cpu caches in case we didn't flush the dirty
826 * cachelines in-line while writing and the object moved
827 * out of the cpu write domain while we've dropped the lock.
829 if (!needs_clflush_after &&
830 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
831 i915_gem_clflush_object(obj);
832 i915_gem_chipset_flush(dev);
836 if (needs_clflush_after)
837 i915_gem_chipset_flush(dev);
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file)
851 struct drm_i915_gem_pwrite *args = data;
852 struct drm_i915_gem_object *obj;
858 if (!access_ok(VERIFY_READ,
859 to_user_ptr(args->data_ptr),
863 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
868 ret = i915_mutex_lock_interruptible(dev);
872 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
873 if (&obj->base == NULL) {
878 /* Bounds check destination. */
879 if (args->offset > obj->base.size ||
880 args->size > obj->base.size - args->offset) {
885 /* prime objects have no backing filp to GEM pread/pwrite
888 if (!obj->base.filp) {
893 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
896 /* We can only do the GTT pwrite on untiled buffers, as otherwise
897 * it would end up going through the fenced access, and we'll get
898 * different detiling behavior between reading and writing.
899 * pread/pwrite currently are reading and writing from the CPU
900 * perspective, requiring manual detiling by the client.
903 ret = i915_gem_phys_pwrite(dev, obj, args, file);
907 if (obj->cache_level == I915_CACHE_NONE &&
908 obj->tiling_mode == I915_TILING_NONE &&
909 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
910 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
911 /* Note that the gtt paths might fail with non-page-backed user
912 * pointers (e.g. gtt mappings when moving data between
913 * textures). Fallback to the shmem path in that case. */
916 if (ret == -EFAULT || ret == -ENOSPC)
917 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
920 drm_gem_object_unreference(&obj->base);
922 mutex_unlock(&dev->struct_mutex);
927 i915_gem_check_wedge(struct i915_gpu_error *error,
930 if (i915_reset_in_progress(error)) {
931 /* Non-interruptible callers can't handle -EAGAIN, hence return
932 * -EIO unconditionally for these. */
936 /* Recovery complete, but the reset failed ... */
937 if (i915_terminally_wedged(error))
947 * Compare seqno against outstanding lazy request. Emit a request if they are
951 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
955 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
958 if (seqno == ring->outstanding_lazy_request)
959 ret = i915_add_request(ring, NULL);
965 * __wait_seqno - wait until execution of seqno has finished
966 * @ring: the ring expected to report seqno
968 * @reset_counter: reset sequence associated with the given seqno
969 * @interruptible: do an interruptible wait (normally yes)
970 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
972 * Note: It is of utmost importance that the passed in seqno and reset_counter
973 * values have been read by the caller in an smp safe manner. Where read-side
974 * locks are involved, it is sufficient to read the reset_counter before
975 * unlocking the lock that protects the seqno. For lockless tricks, the
976 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
979 * Returns 0 if the seqno was found within the alloted time. Else returns the
980 * errno with remaining time filled in timeout argument.
982 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
983 unsigned reset_counter,
984 bool interruptible, struct timespec *timeout)
986 drm_i915_private_t *dev_priv = ring->dev->dev_private;
987 struct timespec before, now, wait_time={1,0};
988 unsigned long timeout_jiffies;
990 bool wait_forever = true;
993 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
996 trace_i915_gem_request_wait_begin(ring, seqno);
998 if (timeout != NULL) {
999 wait_time = *timeout;
1000 wait_forever = false;
1003 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1005 if (WARN_ON(!ring->irq_get(ring)))
1008 /* Record current time in case interrupted by signal, or wedged * */
1009 getrawmonotonic(&before);
1012 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013 i915_reset_in_progress(&dev_priv->gpu_error) || \
1014 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1017 end = wait_event_interruptible_timeout(ring->irq_queue,
1021 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1024 /* We need to check whether any gpu reset happened in between
1025 * the caller grabbing the seqno and now ... */
1026 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1029 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1031 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1034 } while (end == 0 && wait_forever);
1036 getrawmonotonic(&now);
1038 ring->irq_put(ring);
1039 trace_i915_gem_request_wait_end(ring, seqno);
1043 struct timespec sleep_time = timespec_sub(now, before);
1044 *timeout = timespec_sub(*timeout, sleep_time);
1045 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1046 set_normalized_timespec(timeout, 0, 0);
1051 case -EAGAIN: /* Wedged */
1052 case -ERESTARTSYS: /* Signal */
1054 case 0: /* Timeout */
1056 default: /* Completed */
1057 WARN_ON(end < 0); /* We're not aware of other errors */
1063 * Waits for a sequence number to be signaled, and cleans up the
1064 * request and object lists appropriately for that event.
1067 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1069 struct drm_device *dev = ring->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 bool interruptible = dev_priv->mm.interruptible;
1074 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1077 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1081 ret = i915_gem_check_olr(ring, seqno);
1085 return __wait_seqno(ring, seqno,
1086 atomic_read(&dev_priv->gpu_error.reset_counter),
1087 interruptible, NULL);
1091 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1092 struct intel_ring_buffer *ring)
1094 i915_gem_retire_requests_ring(ring);
1096 /* Manually manage the write flush as we may have not yet
1097 * retired the buffer.
1099 * Note that the last_write_seqno is always the earlier of
1100 * the two (read/write) seqno, so if we haved successfully waited,
1101 * we know we have passed the last write.
1103 obj->last_write_seqno = 0;
1104 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1110 * Ensures that all rendering to the object has completed and the object is
1111 * safe to unbind from the GTT or access from the CPU.
1113 static __must_check int
1114 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1117 struct intel_ring_buffer *ring = obj->ring;
1121 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1125 ret = i915_wait_seqno(ring, seqno);
1129 return i915_gem_object_wait_rendering__tail(obj, ring);
1132 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1133 * as the object state may change during this call.
1135 static __must_check int
1136 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1139 struct drm_device *dev = obj->base.dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 struct intel_ring_buffer *ring = obj->ring;
1142 unsigned reset_counter;
1146 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1147 BUG_ON(!dev_priv->mm.interruptible);
1149 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1153 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1157 ret = i915_gem_check_olr(ring, seqno);
1161 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1162 mutex_unlock(&dev->struct_mutex);
1163 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1164 mutex_lock(&dev->struct_mutex);
1168 return i915_gem_object_wait_rendering__tail(obj, ring);
1172 * Called when user space prepares to use an object with the CPU, either
1173 * through the mmap ioctl's mapping or a GTT mapping.
1176 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1177 struct drm_file *file)
1179 struct drm_i915_gem_set_domain *args = data;
1180 struct drm_i915_gem_object *obj;
1181 uint32_t read_domains = args->read_domains;
1182 uint32_t write_domain = args->write_domain;
1185 /* Only handle setting domains to types used by the CPU. */
1186 if (write_domain & I915_GEM_GPU_DOMAINS)
1189 if (read_domains & I915_GEM_GPU_DOMAINS)
1192 /* Having something in the write domain implies it's in the read
1193 * domain, and only that read domain. Enforce that in the request.
1195 if (write_domain != 0 && read_domains != write_domain)
1198 ret = i915_mutex_lock_interruptible(dev);
1202 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1203 if (&obj->base == NULL) {
1208 /* Try to flush the object off the GPU without holding the lock.
1209 * We will repeat the flush holding the lock in the normal manner
1210 * to catch cases where we are gazumped.
1212 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1216 if (read_domains & I915_GEM_DOMAIN_GTT) {
1217 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1219 /* Silently promote "you're not bound, there was nothing to do"
1220 * to success, since the client was just asking us to
1221 * make sure everything was done.
1226 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1230 drm_gem_object_unreference(&obj->base);
1232 mutex_unlock(&dev->struct_mutex);
1237 * Called when user space has done writes to this buffer
1240 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1241 struct drm_file *file)
1243 struct drm_i915_gem_sw_finish *args = data;
1244 struct drm_i915_gem_object *obj;
1247 ret = i915_mutex_lock_interruptible(dev);
1251 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1252 if (&obj->base == NULL) {
1257 /* Pinned buffers may be scanout, so flush the cache */
1259 i915_gem_object_flush_cpu_write_domain(obj);
1261 drm_gem_object_unreference(&obj->base);
1263 mutex_unlock(&dev->struct_mutex);
1268 * Maps the contents of an object, returning the address it is mapped
1271 * While the mapping holds a reference on the contents of the object, it doesn't
1272 * imply a ref on the object itself.
1275 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1276 struct drm_file *file)
1278 struct drm_i915_gem_mmap *args = data;
1279 struct drm_gem_object *obj;
1282 obj = drm_gem_object_lookup(dev, file, args->handle);
1286 /* prime objects have no backing filp to GEM mmap
1290 drm_gem_object_unreference_unlocked(obj);
1294 addr = vm_mmap(obj->filp, 0, args->size,
1295 PROT_READ | PROT_WRITE, MAP_SHARED,
1297 drm_gem_object_unreference_unlocked(obj);
1298 if (IS_ERR((void *)addr))
1301 args->addr_ptr = (uint64_t) addr;
1307 * i915_gem_fault - fault a page into the GTT
1308 * vma: VMA in question
1311 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1312 * from userspace. The fault handler takes care of binding the object to
1313 * the GTT (if needed), allocating and programming a fence register (again,
1314 * only if needed based on whether the old reg is still valid or the object
1315 * is tiled) and inserting a new PTE into the faulting process.
1317 * Note that the faulting process may involve evicting existing objects
1318 * from the GTT and/or fence registers to make room. So performance may
1319 * suffer if the GTT working set is large or there are few fence registers
1322 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1324 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1325 struct drm_device *dev = obj->base.dev;
1326 drm_i915_private_t *dev_priv = dev->dev_private;
1327 pgoff_t page_offset;
1330 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1332 /* We don't use vmf->pgoff since that has the fake offset */
1333 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1336 ret = i915_mutex_lock_interruptible(dev);
1340 trace_i915_gem_object_fault(obj, page_offset, true, write);
1342 /* Access to snoopable pages through the GTT is incoherent. */
1343 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1348 /* Now bind it into the GTT if needed */
1349 ret = i915_gem_object_pin(obj, 0, true, false);
1353 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1357 ret = i915_gem_object_get_fence(obj);
1361 obj->fault_mappable = true;
1363 pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
1366 /* Finally, remap it using the new GTT offset */
1367 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1369 i915_gem_object_unpin(obj);
1371 mutex_unlock(&dev->struct_mutex);
1375 /* If this -EIO is due to a gpu hang, give the reset code a
1376 * chance to clean up the mess. Otherwise return the proper
1378 if (i915_terminally_wedged(&dev_priv->gpu_error))
1379 return VM_FAULT_SIGBUS;
1381 /* Give the error handler a chance to run and move the
1382 * objects off the GPU active list. Next time we service the
1383 * fault, we should be able to transition the page into the
1384 * GTT without touching the GPU (and so avoid further
1385 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1386 * with coherency, just lost writes.
1394 * EBUSY is ok: this just means that another thread
1395 * already did the job.
1397 return VM_FAULT_NOPAGE;
1399 return VM_FAULT_OOM;
1401 return VM_FAULT_SIGBUS;
1403 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1404 return VM_FAULT_SIGBUS;
1409 * i915_gem_release_mmap - remove physical page mappings
1410 * @obj: obj in question
1412 * Preserve the reservation of the mmapping with the DRM core code, but
1413 * relinquish ownership of the pages back to the system.
1415 * It is vital that we remove the page mapping if we have mapped a tiled
1416 * object through the GTT and then lose the fence register due to
1417 * resource pressure. Similarly if the object has been moved out of the
1418 * aperture, than pages mapped into userspace must be revoked. Removing the
1419 * mapping will then trigger a page fault on the next user access, allowing
1420 * fixup by i915_gem_fault().
1423 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1425 if (!obj->fault_mappable)
1428 if (obj->base.dev->dev_mapping)
1429 unmap_mapping_range(obj->base.dev->dev_mapping,
1430 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1433 obj->fault_mappable = false;
1437 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1441 if (INTEL_INFO(dev)->gen >= 4 ||
1442 tiling_mode == I915_TILING_NONE)
1445 /* Previous chips need a power-of-two fence region when tiling */
1446 if (INTEL_INFO(dev)->gen == 3)
1447 gtt_size = 1024*1024;
1449 gtt_size = 512*1024;
1451 while (gtt_size < size)
1458 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1459 * @obj: object to check
1461 * Return the required GTT alignment for an object, taking into account
1462 * potential fence register mapping.
1465 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1466 int tiling_mode, bool fenced)
1469 * Minimum alignment is 4k (GTT page size), but might be greater
1470 * if a fence register is needed for the object.
1472 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1473 tiling_mode == I915_TILING_NONE)
1477 * Previous chips need to be aligned to the size of the smallest
1478 * fence register that can contain the object.
1480 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1483 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1485 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1488 if (obj->base.map_list.map)
1491 dev_priv->mm.shrinker_no_lock_stealing = true;
1493 ret = drm_gem_create_mmap_offset(&obj->base);
1497 /* Badly fragmented mmap space? The only way we can recover
1498 * space is by destroying unwanted objects. We can't randomly release
1499 * mmap_offsets as userspace expects them to be persistent for the
1500 * lifetime of the objects. The closest we can is to release the
1501 * offsets on purgeable objects by truncating it and marking it purged,
1502 * which prevents userspace from ever using that object again.
1504 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1505 ret = drm_gem_create_mmap_offset(&obj->base);
1509 i915_gem_shrink_all(dev_priv);
1510 ret = drm_gem_create_mmap_offset(&obj->base);
1512 dev_priv->mm.shrinker_no_lock_stealing = false;
1517 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1519 if (!obj->base.map_list.map)
1522 drm_gem_free_mmap_offset(&obj->base);
1526 i915_gem_mmap_gtt(struct drm_file *file,
1527 struct drm_device *dev,
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 struct drm_i915_gem_object *obj;
1535 ret = i915_mutex_lock_interruptible(dev);
1539 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1540 if (&obj->base == NULL) {
1545 if (obj->base.size > dev_priv->gtt.mappable_end) {
1550 if (obj->madv != I915_MADV_WILLNEED) {
1551 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1556 ret = i915_gem_object_create_mmap_offset(obj);
1560 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1563 drm_gem_object_unreference(&obj->base);
1565 mutex_unlock(&dev->struct_mutex);
1570 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1572 * @data: GTT mapping ioctl data
1573 * @file: GEM object info
1575 * Simply returns the fake offset to userspace so it can mmap it.
1576 * The mmap call will end up in drm_gem_mmap(), which will set things
1577 * up so we can get faults in the handler above.
1579 * The fault handler will take care of binding the object into the GTT
1580 * (since it may have been evicted to make room for something), allocating
1581 * a fence register, and mapping the appropriate aperture address into
1585 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1586 struct drm_file *file)
1588 struct drm_i915_gem_mmap_gtt *args = data;
1590 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1593 /* Immediately discard the backing storage */
1595 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1597 struct inode *inode;
1599 i915_gem_object_free_mmap_offset(obj);
1601 if (obj->base.filp == NULL)
1604 /* Our goal here is to return as much of the memory as
1605 * is possible back to the system as we are called from OOM.
1606 * To do this we must instruct the shmfs to drop all of its
1607 * backing pages, *now*.
1609 inode = file_inode(obj->base.filp);
1610 shmem_truncate_range(inode, 0, (loff_t)-1);
1612 obj->madv = __I915_MADV_PURGED;
1616 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1618 return obj->madv == I915_MADV_DONTNEED;
1622 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1624 struct sg_page_iter sg_iter;
1627 BUG_ON(obj->madv == __I915_MADV_PURGED);
1629 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1631 /* In the event of a disaster, abandon all caches and
1632 * hope for the best.
1634 WARN_ON(ret != -EIO);
1635 i915_gem_clflush_object(obj);
1636 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1639 if (i915_gem_object_needs_bit17_swizzle(obj))
1640 i915_gem_object_save_bit_17_swizzle(obj);
1642 if (obj->madv == I915_MADV_DONTNEED)
1645 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1646 struct page *page = sg_page_iter_page(&sg_iter);
1649 set_page_dirty(page);
1651 if (obj->madv == I915_MADV_WILLNEED)
1652 mark_page_accessed(page);
1654 page_cache_release(page);
1658 sg_free_table(obj->pages);
1663 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1665 const struct drm_i915_gem_object_ops *ops = obj->ops;
1667 if (obj->pages == NULL)
1670 BUG_ON(obj->gtt_space);
1672 if (obj->pages_pin_count)
1675 /* ->put_pages might need to allocate memory for the bit17 swizzle
1676 * array, hence protect them from being reaped by removing them from gtt
1678 list_del(&obj->global_list);
1680 ops->put_pages(obj);
1683 if (i915_gem_object_is_purgeable(obj))
1684 i915_gem_object_truncate(obj);
1690 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1691 bool purgeable_only)
1693 struct drm_i915_gem_object *obj, *next;
1696 list_for_each_entry_safe(obj, next,
1697 &dev_priv->mm.unbound_list,
1699 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1700 i915_gem_object_put_pages(obj) == 0) {
1701 count += obj->base.size >> PAGE_SHIFT;
1702 if (count >= target)
1707 list_for_each_entry_safe(obj, next,
1708 &dev_priv->mm.inactive_list,
1710 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1711 i915_gem_object_unbind(obj) == 0 &&
1712 i915_gem_object_put_pages(obj) == 0) {
1713 count += obj->base.size >> PAGE_SHIFT;
1714 if (count >= target)
1723 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1725 return __i915_gem_shrink(dev_priv, target, true);
1729 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1731 struct drm_i915_gem_object *obj, *next;
1733 i915_gem_evict_everything(dev_priv->dev);
1735 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1737 i915_gem_object_put_pages(obj);
1741 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1743 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1745 struct address_space *mapping;
1746 struct sg_table *st;
1747 struct scatterlist *sg;
1748 struct sg_page_iter sg_iter;
1750 unsigned long last_pfn = 0; /* suppress gcc warning */
1753 /* Assert that the object is not currently in any GPU domain. As it
1754 * wasn't in the GTT, there shouldn't be any way it could have been in
1757 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1758 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1760 st = kmalloc(sizeof(*st), GFP_KERNEL);
1764 page_count = obj->base.size / PAGE_SIZE;
1765 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1771 /* Get the list of pages out of our struct file. They'll be pinned
1772 * at this point until we release them.
1774 * Fail silently without starting the shrinker
1776 mapping = file_inode(obj->base.filp)->i_mapping;
1777 gfp = mapping_gfp_mask(mapping);
1778 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1779 gfp &= ~(__GFP_IO | __GFP_WAIT);
1782 for (i = 0; i < page_count; i++) {
1783 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1785 i915_gem_purge(dev_priv, page_count);
1786 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1789 /* We've tried hard to allocate the memory by reaping
1790 * our own buffer, now let the real VM do its job and
1791 * go down in flames if truly OOM.
1793 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1794 gfp |= __GFP_IO | __GFP_WAIT;
1796 i915_gem_shrink_all(dev_priv);
1797 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1801 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1802 gfp &= ~(__GFP_IO | __GFP_WAIT);
1804 #ifdef CONFIG_SWIOTLB
1805 if (swiotlb_nr_tbl()) {
1807 sg_set_page(sg, page, PAGE_SIZE, 0);
1812 if (!i || page_to_pfn(page) != last_pfn + 1) {
1816 sg_set_page(sg, page, PAGE_SIZE, 0);
1818 sg->length += PAGE_SIZE;
1820 last_pfn = page_to_pfn(page);
1822 #ifdef CONFIG_SWIOTLB
1823 if (!swiotlb_nr_tbl())
1828 if (i915_gem_object_needs_bit17_swizzle(obj))
1829 i915_gem_object_do_bit_17_swizzle(obj);
1835 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1836 page_cache_release(sg_page_iter_page(&sg_iter));
1839 return PTR_ERR(page);
1842 /* Ensure that the associated pages are gathered from the backing storage
1843 * and pinned into our object. i915_gem_object_get_pages() may be called
1844 * multiple times before they are released by a single call to
1845 * i915_gem_object_put_pages() - once the pages are no longer referenced
1846 * either as a result of memory pressure (reaping pages under the shrinker)
1847 * or as the object is itself released.
1850 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1852 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1853 const struct drm_i915_gem_object_ops *ops = obj->ops;
1859 if (obj->madv != I915_MADV_WILLNEED) {
1860 DRM_ERROR("Attempting to obtain a purgeable object\n");
1864 BUG_ON(obj->pages_pin_count);
1866 ret = ops->get_pages(obj);
1870 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1875 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1876 struct intel_ring_buffer *ring)
1878 struct drm_device *dev = obj->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 u32 seqno = intel_ring_get_seqno(ring);
1882 BUG_ON(ring == NULL);
1883 if (obj->ring != ring && obj->last_write_seqno) {
1884 /* Keep the seqno relative to the current ring */
1885 obj->last_write_seqno = seqno;
1889 /* Add a reference if we're newly entering the active list. */
1891 drm_gem_object_reference(&obj->base);
1895 /* Move from whatever list we were on to the tail of execution. */
1896 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1897 list_move_tail(&obj->ring_list, &ring->active_list);
1899 obj->last_read_seqno = seqno;
1901 if (obj->fenced_gpu_access) {
1902 obj->last_fenced_seqno = seqno;
1904 /* Bump MRU to take account of the delayed flush */
1905 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1906 struct drm_i915_fence_reg *reg;
1908 reg = &dev_priv->fence_regs[obj->fence_reg];
1909 list_move_tail(®->lru_list,
1910 &dev_priv->mm.fence_list);
1916 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1918 struct drm_device *dev = obj->base.dev;
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1921 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1922 BUG_ON(!obj->active);
1924 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1926 list_del_init(&obj->ring_list);
1929 obj->last_read_seqno = 0;
1930 obj->last_write_seqno = 0;
1931 obj->base.write_domain = 0;
1933 obj->last_fenced_seqno = 0;
1934 obj->fenced_gpu_access = false;
1937 drm_gem_object_unreference(&obj->base);
1939 WARN_ON(i915_verify_lists(dev));
1943 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_ring_buffer *ring;
1949 /* Carefully retire all requests without writing to the rings */
1950 for_each_ring(ring, dev_priv, i) {
1951 ret = intel_ring_idle(ring);
1955 i915_gem_retire_requests(dev);
1957 /* Finally reset hw state */
1958 for_each_ring(ring, dev_priv, i) {
1959 intel_ring_init_seqno(ring, seqno);
1961 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1962 ring->sync_seqno[j] = 0;
1968 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1976 /* HWS page needs to be set less than what we
1977 * will inject to ring
1979 ret = i915_gem_init_seqno(dev, seqno - 1);
1983 /* Carefully set the last_seqno value so that wrap
1984 * detection still works
1986 dev_priv->next_seqno = seqno;
1987 dev_priv->last_seqno = seqno - 1;
1988 if (dev_priv->last_seqno == 0)
1989 dev_priv->last_seqno--;
1995 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1999 /* reserve 0 for non-seqno */
2000 if (dev_priv->next_seqno == 0) {
2001 int ret = i915_gem_init_seqno(dev, 0);
2005 dev_priv->next_seqno = 1;
2008 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2012 int __i915_add_request(struct intel_ring_buffer *ring,
2013 struct drm_file *file,
2014 struct drm_i915_gem_object *obj,
2017 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2018 struct drm_i915_gem_request *request;
2019 u32 request_ring_position, request_start;
2023 request_start = intel_ring_get_tail(ring);
2025 * Emit any outstanding flushes - execbuf can fail to emit the flush
2026 * after having emitted the batchbuffer command. Hence we need to fix
2027 * things up similar to emitting the lazy request. The difference here
2028 * is that the flush _must_ happen before the next request, no matter
2031 ret = intel_ring_flush_all_caches(ring);
2035 request = kmalloc(sizeof(*request), GFP_KERNEL);
2036 if (request == NULL)
2040 /* Record the position of the start of the request so that
2041 * should we detect the updated seqno part-way through the
2042 * GPU processing the request, we never over-estimate the
2043 * position of the head.
2045 request_ring_position = intel_ring_get_tail(ring);
2047 ret = ring->add_request(ring);
2053 request->seqno = intel_ring_get_seqno(ring);
2054 request->ring = ring;
2055 request->head = request_start;
2056 request->tail = request_ring_position;
2057 request->ctx = ring->last_context;
2058 request->batch_obj = obj;
2060 /* Whilst this request exists, batch_obj will be on the
2061 * active_list, and so will hold the active reference. Only when this
2062 * request is retired will the the batch_obj be moved onto the
2063 * inactive_list and lose its active reference. Hence we do not need
2064 * to explicitly hold another reference here.
2068 i915_gem_context_reference(request->ctx);
2070 request->emitted_jiffies = jiffies;
2071 was_empty = list_empty(&ring->request_list);
2072 list_add_tail(&request->list, &ring->request_list);
2073 request->file_priv = NULL;
2076 struct drm_i915_file_private *file_priv = file->driver_priv;
2078 spin_lock(&file_priv->mm.lock);
2079 request->file_priv = file_priv;
2080 list_add_tail(&request->client_list,
2081 &file_priv->mm.request_list);
2082 spin_unlock(&file_priv->mm.lock);
2085 trace_i915_gem_request_add(ring, request->seqno);
2086 ring->outstanding_lazy_request = 0;
2088 if (!dev_priv->mm.suspended) {
2089 if (i915_enable_hangcheck) {
2090 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2091 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2094 queue_delayed_work(dev_priv->wq,
2095 &dev_priv->mm.retire_work,
2096 round_jiffies_up_relative(HZ));
2097 intel_mark_busy(dev_priv->dev);
2102 *out_seqno = request->seqno;
2107 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2109 struct drm_i915_file_private *file_priv = request->file_priv;
2114 spin_lock(&file_priv->mm.lock);
2115 if (request->file_priv) {
2116 list_del(&request->client_list);
2117 request->file_priv = NULL;
2119 spin_unlock(&file_priv->mm.lock);
2122 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2124 if (acthd >= obj->gtt_offset &&
2125 acthd < obj->gtt_offset + obj->base.size)
2131 static bool i915_head_inside_request(const u32 acthd_unmasked,
2132 const u32 request_start,
2133 const u32 request_end)
2135 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2137 if (request_start < request_end) {
2138 if (acthd >= request_start && acthd < request_end)
2140 } else if (request_start > request_end) {
2141 if (acthd >= request_start || acthd < request_end)
2148 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2149 const u32 acthd, bool *inside)
2151 /* There is a possibility that unmasked head address
2152 * pointing inside the ring, matches the batch_obj address range.
2153 * However this is extremely unlikely.
2156 if (request->batch_obj) {
2157 if (i915_head_inside_object(acthd, request->batch_obj)) {
2163 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2171 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2172 struct drm_i915_gem_request *request,
2175 struct i915_ctx_hang_stats *hs = NULL;
2176 bool inside, guilty;
2178 /* Innocent until proven guilty */
2181 if (ring->hangcheck.action != wait &&
2182 i915_request_guilty(request, acthd, &inside)) {
2183 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
2185 inside ? "inside" : "flushing",
2186 request->batch_obj ?
2187 request->batch_obj->gtt_offset : 0,
2188 request->ctx ? request->ctx->id : 0,
2194 /* If contexts are disabled or this is the default context, use
2195 * file_priv->reset_state
2197 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2198 hs = &request->ctx->hang_stats;
2199 else if (request->file_priv)
2200 hs = &request->file_priv->hang_stats;
2206 hs->batch_pending++;
2210 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2212 list_del(&request->list);
2213 i915_gem_request_remove_from_client(request);
2216 i915_gem_context_unreference(request->ctx);
2221 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2222 struct intel_ring_buffer *ring)
2224 u32 completed_seqno;
2227 acthd = intel_ring_get_active_head(ring);
2228 completed_seqno = ring->get_seqno(ring, false);
2230 while (!list_empty(&ring->request_list)) {
2231 struct drm_i915_gem_request *request;
2233 request = list_first_entry(&ring->request_list,
2234 struct drm_i915_gem_request,
2237 if (request->seqno > completed_seqno)
2238 i915_set_reset_status(ring, request, acthd);
2240 i915_gem_free_request(request);
2243 while (!list_empty(&ring->active_list)) {
2244 struct drm_i915_gem_object *obj;
2246 obj = list_first_entry(&ring->active_list,
2247 struct drm_i915_gem_object,
2250 i915_gem_object_move_to_inactive(obj);
2254 void i915_gem_restore_fences(struct drm_device *dev)
2256 struct drm_i915_private *dev_priv = dev->dev_private;
2259 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2260 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2261 i915_gem_write_fence(dev, i, reg->obj);
2265 void i915_gem_reset(struct drm_device *dev)
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct drm_i915_gem_object *obj;
2269 struct intel_ring_buffer *ring;
2272 for_each_ring(ring, dev_priv, i)
2273 i915_gem_reset_ring_lists(dev_priv, ring);
2275 /* Move everything out of the GPU domains to ensure we do any
2276 * necessary invalidation upon reuse.
2278 list_for_each_entry(obj,
2279 &dev_priv->mm.inactive_list,
2282 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2285 i915_gem_restore_fences(dev);
2289 * This function clears the request list as sequence numbers are passed.
2292 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2296 if (list_empty(&ring->request_list))
2299 WARN_ON(i915_verify_lists(ring->dev));
2301 seqno = ring->get_seqno(ring, true);
2303 while (!list_empty(&ring->request_list)) {
2304 struct drm_i915_gem_request *request;
2306 request = list_first_entry(&ring->request_list,
2307 struct drm_i915_gem_request,
2310 if (!i915_seqno_passed(seqno, request->seqno))
2313 trace_i915_gem_request_retire(ring, request->seqno);
2314 /* We know the GPU must have read the request to have
2315 * sent us the seqno + interrupt, so use the position
2316 * of tail of the request to update the last known position
2319 ring->last_retired_head = request->tail;
2321 i915_gem_free_request(request);
2324 /* Move any buffers on the active list that are no longer referenced
2325 * by the ringbuffer to the flushing/inactive lists as appropriate.
2327 while (!list_empty(&ring->active_list)) {
2328 struct drm_i915_gem_object *obj;
2330 obj = list_first_entry(&ring->active_list,
2331 struct drm_i915_gem_object,
2334 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2337 i915_gem_object_move_to_inactive(obj);
2340 if (unlikely(ring->trace_irq_seqno &&
2341 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2342 ring->irq_put(ring);
2343 ring->trace_irq_seqno = 0;
2346 WARN_ON(i915_verify_lists(ring->dev));
2350 i915_gem_retire_requests(struct drm_device *dev)
2352 drm_i915_private_t *dev_priv = dev->dev_private;
2353 struct intel_ring_buffer *ring;
2356 for_each_ring(ring, dev_priv, i)
2357 i915_gem_retire_requests_ring(ring);
2361 i915_gem_retire_work_handler(struct work_struct *work)
2363 drm_i915_private_t *dev_priv;
2364 struct drm_device *dev;
2365 struct intel_ring_buffer *ring;
2369 dev_priv = container_of(work, drm_i915_private_t,
2370 mm.retire_work.work);
2371 dev = dev_priv->dev;
2373 /* Come back later if the device is busy... */
2374 if (!mutex_trylock(&dev->struct_mutex)) {
2375 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2376 round_jiffies_up_relative(HZ));
2380 i915_gem_retire_requests(dev);
2382 /* Send a periodic flush down the ring so we don't hold onto GEM
2383 * objects indefinitely.
2386 for_each_ring(ring, dev_priv, i) {
2387 if (ring->gpu_caches_dirty)
2388 i915_add_request(ring, NULL);
2390 idle &= list_empty(&ring->request_list);
2393 if (!dev_priv->mm.suspended && !idle)
2394 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2395 round_jiffies_up_relative(HZ));
2397 intel_mark_idle(dev);
2399 mutex_unlock(&dev->struct_mutex);
2403 * Ensures that an object will eventually get non-busy by flushing any required
2404 * write domains, emitting any outstanding lazy request and retiring and
2405 * completed requests.
2408 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2413 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2417 i915_gem_retire_requests_ring(obj->ring);
2424 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2425 * @DRM_IOCTL_ARGS: standard ioctl arguments
2427 * Returns 0 if successful, else an error is returned with the remaining time in
2428 * the timeout parameter.
2429 * -ETIME: object is still busy after timeout
2430 * -ERESTARTSYS: signal interrupted the wait
2431 * -ENONENT: object doesn't exist
2432 * Also possible, but rare:
2433 * -EAGAIN: GPU wedged
2435 * -ENODEV: Internal IRQ fail
2436 * -E?: The add request failed
2438 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2439 * non-zero timeout parameter the wait ioctl will wait for the given number of
2440 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2441 * without holding struct_mutex the object may become re-busied before this
2442 * function completes. A similar but shorter * race condition exists in the busy
2446 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2448 drm_i915_private_t *dev_priv = dev->dev_private;
2449 struct drm_i915_gem_wait *args = data;
2450 struct drm_i915_gem_object *obj;
2451 struct intel_ring_buffer *ring = NULL;
2452 struct timespec timeout_stack, *timeout = NULL;
2453 unsigned reset_counter;
2457 if (args->timeout_ns >= 0) {
2458 timeout_stack = ns_to_timespec(args->timeout_ns);
2459 timeout = &timeout_stack;
2462 ret = i915_mutex_lock_interruptible(dev);
2466 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2467 if (&obj->base == NULL) {
2468 mutex_unlock(&dev->struct_mutex);
2472 /* Need to make sure the object gets inactive eventually. */
2473 ret = i915_gem_object_flush_active(obj);
2478 seqno = obj->last_read_seqno;
2485 /* Do this after OLR check to make sure we make forward progress polling
2486 * on this IOCTL with a 0 timeout (like busy ioctl)
2488 if (!args->timeout_ns) {
2493 drm_gem_object_unreference(&obj->base);
2494 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2495 mutex_unlock(&dev->struct_mutex);
2497 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2499 args->timeout_ns = timespec_to_ns(timeout);
2503 drm_gem_object_unreference(&obj->base);
2504 mutex_unlock(&dev->struct_mutex);
2509 * i915_gem_object_sync - sync an object to a ring.
2511 * @obj: object which may be in use on another ring.
2512 * @to: ring we wish to use the object on. May be NULL.
2514 * This code is meant to abstract object synchronization with the GPU.
2515 * Calling with NULL implies synchronizing the object with the CPU
2516 * rather than a particular GPU ring.
2518 * Returns 0 if successful, else propagates up the lower layer error.
2521 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2522 struct intel_ring_buffer *to)
2524 struct intel_ring_buffer *from = obj->ring;
2528 if (from == NULL || to == from)
2531 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2532 return i915_gem_object_wait_rendering(obj, false);
2534 idx = intel_ring_sync_index(from, to);
2536 seqno = obj->last_read_seqno;
2537 if (seqno <= from->sync_seqno[idx])
2540 ret = i915_gem_check_olr(obj->ring, seqno);
2544 ret = to->sync_to(to, from, seqno);
2546 /* We use last_read_seqno because sync_to()
2547 * might have just caused seqno wrap under
2550 from->sync_seqno[idx] = obj->last_read_seqno;
2555 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2557 u32 old_write_domain, old_read_domains;
2559 /* Force a pagefault for domain tracking on next user access */
2560 i915_gem_release_mmap(obj);
2562 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2565 /* Wait for any direct GTT access to complete */
2568 old_read_domains = obj->base.read_domains;
2569 old_write_domain = obj->base.write_domain;
2571 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2572 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2574 trace_i915_gem_object_change_domain(obj,
2580 * Unbinds an object from the GTT aperture.
2583 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2585 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2588 if (obj->gtt_space == NULL)
2594 BUG_ON(obj->pages == NULL);
2596 ret = i915_gem_object_finish_gpu(obj);
2599 /* Continue on if we fail due to EIO, the GPU is hung so we
2600 * should be safe and we need to cleanup or else we might
2601 * cause memory corruption through use-after-free.
2604 i915_gem_object_finish_gtt(obj);
2606 /* release the fence reg _after_ flushing */
2607 ret = i915_gem_object_put_fence(obj);
2611 trace_i915_gem_object_unbind(obj);
2613 if (obj->has_global_gtt_mapping)
2614 i915_gem_gtt_unbind_object(obj);
2615 if (obj->has_aliasing_ppgtt_mapping) {
2616 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2617 obj->has_aliasing_ppgtt_mapping = 0;
2619 i915_gem_gtt_finish_object(obj);
2620 i915_gem_object_unpin_pages(obj);
2622 list_del(&obj->mm_list);
2623 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2624 /* Avoid an unnecessary call to unbind on rebind. */
2625 obj->map_and_fenceable = true;
2627 drm_mm_put_block(obj->gtt_space);
2628 obj->gtt_space = NULL;
2629 obj->gtt_offset = 0;
2634 int i915_gpu_idle(struct drm_device *dev)
2636 drm_i915_private_t *dev_priv = dev->dev_private;
2637 struct intel_ring_buffer *ring;
2640 /* Flush everything onto the inactive list. */
2641 for_each_ring(ring, dev_priv, i) {
2642 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2646 ret = intel_ring_idle(ring);
2654 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2655 struct drm_i915_gem_object *obj)
2657 drm_i915_private_t *dev_priv = dev->dev_private;
2659 int fence_pitch_shift;
2661 if (INTEL_INFO(dev)->gen >= 6) {
2662 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2663 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2665 fence_reg = FENCE_REG_965_0;
2666 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2669 fence_reg += reg * 8;
2671 /* To w/a incoherency with non-atomic 64-bit register updates,
2672 * we split the 64-bit update into two 32-bit writes. In order
2673 * for a partial fence not to be evaluated between writes, we
2674 * precede the update with write to turn off the fence register,
2675 * and only enable the fence as the last step.
2677 * For extra levels of paranoia, we make sure each step lands
2678 * before applying the next step.
2680 I915_WRITE(fence_reg, 0);
2681 POSTING_READ(fence_reg);
2684 u32 size = obj->gtt_space->size;
2687 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2689 val |= obj->gtt_offset & 0xfffff000;
2690 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2691 if (obj->tiling_mode == I915_TILING_Y)
2692 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2693 val |= I965_FENCE_REG_VALID;
2695 I915_WRITE(fence_reg + 4, val >> 32);
2696 POSTING_READ(fence_reg + 4);
2698 I915_WRITE(fence_reg + 0, val);
2699 POSTING_READ(fence_reg);
2701 I915_WRITE(fence_reg + 4, 0);
2702 POSTING_READ(fence_reg + 4);
2706 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2707 struct drm_i915_gem_object *obj)
2709 drm_i915_private_t *dev_priv = dev->dev_private;
2713 u32 size = obj->gtt_space->size;
2717 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2718 (size & -size) != size ||
2719 (obj->gtt_offset & (size - 1)),
2720 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2721 obj->gtt_offset, obj->map_and_fenceable, size);
2723 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2728 /* Note: pitch better be a power of two tile widths */
2729 pitch_val = obj->stride / tile_width;
2730 pitch_val = ffs(pitch_val) - 1;
2732 val = obj->gtt_offset;
2733 if (obj->tiling_mode == I915_TILING_Y)
2734 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2735 val |= I915_FENCE_SIZE_BITS(size);
2736 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2737 val |= I830_FENCE_REG_VALID;
2742 reg = FENCE_REG_830_0 + reg * 4;
2744 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2746 I915_WRITE(reg, val);
2750 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2751 struct drm_i915_gem_object *obj)
2753 drm_i915_private_t *dev_priv = dev->dev_private;
2757 u32 size = obj->gtt_space->size;
2760 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2761 (size & -size) != size ||
2762 (obj->gtt_offset & (size - 1)),
2763 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2764 obj->gtt_offset, size);
2766 pitch_val = obj->stride / 128;
2767 pitch_val = ffs(pitch_val) - 1;
2769 val = obj->gtt_offset;
2770 if (obj->tiling_mode == I915_TILING_Y)
2771 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2772 val |= I830_FENCE_SIZE_BITS(size);
2773 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2774 val |= I830_FENCE_REG_VALID;
2778 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2779 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2782 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2784 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2787 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2788 struct drm_i915_gem_object *obj)
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2792 /* Ensure that all CPU reads are completed before installing a fence
2793 * and all writes before removing the fence.
2795 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2798 switch (INTEL_INFO(dev)->gen) {
2802 case 4: i965_write_fence_reg(dev, reg, obj); break;
2803 case 3: i915_write_fence_reg(dev, reg, obj); break;
2804 case 2: i830_write_fence_reg(dev, reg, obj); break;
2808 /* And similarly be paranoid that no direct access to this region
2809 * is reordered to before the fence is installed.
2811 if (i915_gem_object_needs_mb(obj))
2815 static inline int fence_number(struct drm_i915_private *dev_priv,
2816 struct drm_i915_fence_reg *fence)
2818 return fence - dev_priv->fence_regs;
2821 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2822 struct drm_i915_fence_reg *fence,
2825 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2826 int reg = fence_number(dev_priv, fence);
2828 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2831 obj->fence_reg = reg;
2833 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2835 obj->fence_reg = I915_FENCE_REG_NONE;
2837 list_del_init(&fence->lru_list);
2842 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2844 if (obj->last_fenced_seqno) {
2845 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2849 obj->last_fenced_seqno = 0;
2852 obj->fenced_gpu_access = false;
2857 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2859 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2860 struct drm_i915_fence_reg *fence;
2863 ret = i915_gem_object_wait_fence(obj);
2867 if (obj->fence_reg == I915_FENCE_REG_NONE)
2870 fence = &dev_priv->fence_regs[obj->fence_reg];
2872 i915_gem_object_fence_lost(obj);
2873 i915_gem_object_update_fence(obj, fence, false);
2878 static struct drm_i915_fence_reg *
2879 i915_find_fence_reg(struct drm_device *dev)
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882 struct drm_i915_fence_reg *reg, *avail;
2885 /* First try to find a free reg */
2887 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2888 reg = &dev_priv->fence_regs[i];
2892 if (!reg->pin_count)
2899 /* None available, try to steal one or wait for a user to finish */
2900 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2911 * i915_gem_object_get_fence - set up fencing for an object
2912 * @obj: object to map through a fence reg
2914 * When mapping objects through the GTT, userspace wants to be able to write
2915 * to them without having to worry about swizzling if the object is tiled.
2916 * This function walks the fence regs looking for a free one for @obj,
2917 * stealing one if it can't find any.
2919 * It then sets up the reg based on the object's properties: address, pitch
2920 * and tiling format.
2922 * For an untiled surface, this removes any existing fence.
2925 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2927 struct drm_device *dev = obj->base.dev;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 bool enable = obj->tiling_mode != I915_TILING_NONE;
2930 struct drm_i915_fence_reg *reg;
2933 /* Have we updated the tiling parameters upon the object and so
2934 * will need to serialise the write to the associated fence register?
2936 if (obj->fence_dirty) {
2937 ret = i915_gem_object_wait_fence(obj);
2942 /* Just update our place in the LRU if our fence is getting reused. */
2943 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2944 reg = &dev_priv->fence_regs[obj->fence_reg];
2945 if (!obj->fence_dirty) {
2946 list_move_tail(®->lru_list,
2947 &dev_priv->mm.fence_list);
2950 } else if (enable) {
2951 reg = i915_find_fence_reg(dev);
2956 struct drm_i915_gem_object *old = reg->obj;
2958 ret = i915_gem_object_wait_fence(old);
2962 i915_gem_object_fence_lost(old);
2967 i915_gem_object_update_fence(obj, reg, enable);
2968 obj->fence_dirty = false;
2973 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2974 struct drm_mm_node *gtt_space,
2975 unsigned long cache_level)
2977 struct drm_mm_node *other;
2979 /* On non-LLC machines we have to be careful when putting differing
2980 * types of snoopable memory together to avoid the prefetcher
2981 * crossing memory domains and dying.
2986 if (gtt_space == NULL)
2989 if (list_empty(>t_space->node_list))
2992 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2993 if (other->allocated && !other->hole_follows && other->color != cache_level)
2996 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2997 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3003 static void i915_gem_verify_gtt(struct drm_device *dev)
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct drm_i915_gem_object *obj;
3010 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3011 if (obj->gtt_space == NULL) {
3012 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3017 if (obj->cache_level != obj->gtt_space->color) {
3018 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3019 obj->gtt_space->start,
3020 obj->gtt_space->start + obj->gtt_space->size,
3022 obj->gtt_space->color);
3027 if (!i915_gem_valid_gtt_space(dev,
3029 obj->cache_level)) {
3030 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3031 obj->gtt_space->start,
3032 obj->gtt_space->start + obj->gtt_space->size,
3044 * Finds free space in the GTT aperture and binds the object there.
3047 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3049 bool map_and_fenceable,
3052 struct drm_device *dev = obj->base.dev;
3053 drm_i915_private_t *dev_priv = dev->dev_private;
3054 struct drm_mm_node *node;
3055 u32 size, fence_size, fence_alignment, unfenced_alignment;
3056 bool mappable, fenceable;
3057 size_t gtt_max = map_and_fenceable ?
3058 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
3061 fence_size = i915_gem_get_gtt_size(dev,
3064 fence_alignment = i915_gem_get_gtt_alignment(dev,
3066 obj->tiling_mode, true);
3067 unfenced_alignment =
3068 i915_gem_get_gtt_alignment(dev,
3070 obj->tiling_mode, false);
3073 alignment = map_and_fenceable ? fence_alignment :
3075 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3076 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3080 size = map_and_fenceable ? fence_size : obj->base.size;
3082 /* If the object is bigger than the entire aperture, reject it early
3083 * before evicting everything in a vain attempt to find space.
3085 if (obj->base.size > gtt_max) {
3086 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3088 map_and_fenceable ? "mappable" : "total",
3093 ret = i915_gem_object_get_pages(obj);
3097 i915_gem_object_pin_pages(obj);
3099 node = kzalloc(sizeof(*node), GFP_KERNEL);
3101 i915_gem_object_unpin_pages(obj);
3106 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
3108 obj->cache_level, 0, gtt_max);
3110 ret = i915_gem_evict_something(dev, size, alignment,
3117 i915_gem_object_unpin_pages(obj);
3121 if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3122 i915_gem_object_unpin_pages(obj);
3123 drm_mm_put_block(node);
3127 ret = i915_gem_gtt_prepare_object(obj);
3129 i915_gem_object_unpin_pages(obj);
3130 drm_mm_put_block(node);
3134 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3135 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3137 obj->gtt_space = node;
3138 obj->gtt_offset = node->start;
3141 node->size == fence_size &&
3142 (node->start & (fence_alignment - 1)) == 0;
3145 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3147 obj->map_and_fenceable = mappable && fenceable;
3149 trace_i915_gem_object_bind(obj, map_and_fenceable);
3150 i915_gem_verify_gtt(dev);
3155 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3157 /* If we don't have a page list set up, then we're not pinned
3158 * to GPU, and we can ignore the cache flush because it'll happen
3159 * again at bind time.
3161 if (obj->pages == NULL)
3165 * Stolen memory is always coherent with the GPU as it is explicitly
3166 * marked as wc by the system, or the system is cache-coherent.
3171 /* If the GPU is snooping the contents of the CPU cache,
3172 * we do not need to manually clear the CPU cache lines. However,
3173 * the caches are only snooped when the render cache is
3174 * flushed/invalidated. As we always have to emit invalidations
3175 * and flushes when moving into and out of the RENDER domain, correct
3176 * snooping behaviour occurs naturally as the result of our domain
3179 if (obj->cache_level != I915_CACHE_NONE)
3182 trace_i915_gem_object_clflush(obj);
3184 drm_clflush_sg(obj->pages);
3187 /** Flushes the GTT write domain for the object if it's dirty. */
3189 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3191 uint32_t old_write_domain;
3193 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3196 /* No actual flushing is required for the GTT write domain. Writes
3197 * to it immediately go to main memory as far as we know, so there's
3198 * no chipset flush. It also doesn't land in render cache.
3200 * However, we do have to enforce the order so that all writes through
3201 * the GTT land before any writes to the device, such as updates to
3206 old_write_domain = obj->base.write_domain;
3207 obj->base.write_domain = 0;
3209 trace_i915_gem_object_change_domain(obj,
3210 obj->base.read_domains,
3214 /** Flushes the CPU write domain for the object if it's dirty. */
3216 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3218 uint32_t old_write_domain;
3220 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3223 i915_gem_clflush_object(obj);
3224 i915_gem_chipset_flush(obj->base.dev);
3225 old_write_domain = obj->base.write_domain;
3226 obj->base.write_domain = 0;
3228 trace_i915_gem_object_change_domain(obj,
3229 obj->base.read_domains,
3234 * Moves a single object to the GTT read, and possibly write domain.
3236 * This function returns when the move is complete, including waiting on
3240 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3242 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3243 uint32_t old_write_domain, old_read_domains;
3246 /* Not valid to be called on unbound objects. */
3247 if (obj->gtt_space == NULL)
3250 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3253 ret = i915_gem_object_wait_rendering(obj, !write);
3257 i915_gem_object_flush_cpu_write_domain(obj);
3259 /* Serialise direct access to this object with the barriers for
3260 * coherent writes from the GPU, by effectively invalidating the
3261 * GTT domain upon first access.
3263 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3266 old_write_domain = obj->base.write_domain;
3267 old_read_domains = obj->base.read_domains;
3269 /* It should now be out of any other write domains, and we can update
3270 * the domain values for our changes.
3272 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3273 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3275 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3276 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3280 trace_i915_gem_object_change_domain(obj,
3284 /* And bump the LRU for this access */
3285 if (i915_gem_object_is_inactive(obj))
3286 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3291 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3292 enum i915_cache_level cache_level)
3294 struct drm_device *dev = obj->base.dev;
3295 drm_i915_private_t *dev_priv = dev->dev_private;
3298 if (obj->cache_level == cache_level)
3301 if (obj->pin_count) {
3302 DRM_DEBUG("can not change the cache level of pinned objects\n");
3306 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3307 ret = i915_gem_object_unbind(obj);
3312 if (obj->gtt_space) {
3313 ret = i915_gem_object_finish_gpu(obj);
3317 i915_gem_object_finish_gtt(obj);
3319 /* Before SandyBridge, you could not use tiling or fence
3320 * registers with snooped memory, so relinquish any fences
3321 * currently pointing to our region in the aperture.
3323 if (INTEL_INFO(dev)->gen < 6) {
3324 ret = i915_gem_object_put_fence(obj);
3329 if (obj->has_global_gtt_mapping)
3330 i915_gem_gtt_bind_object(obj, cache_level);
3331 if (obj->has_aliasing_ppgtt_mapping)
3332 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3335 obj->gtt_space->color = cache_level;
3338 if (cache_level == I915_CACHE_NONE) {
3339 u32 old_read_domains, old_write_domain;
3341 /* If we're coming from LLC cached, then we haven't
3342 * actually been tracking whether the data is in the
3343 * CPU cache or not, since we only allow one bit set
3344 * in obj->write_domain and have been skipping the clflushes.
3345 * Just set it to the CPU cache for now.
3347 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3348 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3350 old_read_domains = obj->base.read_domains;
3351 old_write_domain = obj->base.write_domain;
3353 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3354 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3356 trace_i915_gem_object_change_domain(obj,
3361 obj->cache_level = cache_level;
3362 i915_gem_verify_gtt(dev);
3366 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3367 struct drm_file *file)
3369 struct drm_i915_gem_caching *args = data;
3370 struct drm_i915_gem_object *obj;
3373 ret = i915_mutex_lock_interruptible(dev);
3377 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3378 if (&obj->base == NULL) {
3383 args->caching = obj->cache_level != I915_CACHE_NONE;
3385 drm_gem_object_unreference(&obj->base);
3387 mutex_unlock(&dev->struct_mutex);
3391 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3392 struct drm_file *file)
3394 struct drm_i915_gem_caching *args = data;
3395 struct drm_i915_gem_object *obj;
3396 enum i915_cache_level level;
3399 switch (args->caching) {
3400 case I915_CACHING_NONE:
3401 level = I915_CACHE_NONE;
3403 case I915_CACHING_CACHED:
3404 level = I915_CACHE_LLC;
3410 ret = i915_mutex_lock_interruptible(dev);
3414 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3415 if (&obj->base == NULL) {
3420 ret = i915_gem_object_set_cache_level(obj, level);
3422 drm_gem_object_unreference(&obj->base);
3424 mutex_unlock(&dev->struct_mutex);
3429 * Prepare buffer for display plane (scanout, cursors, etc).
3430 * Can be called from an uninterruptible phase (modesetting) and allows
3431 * any flushes to be pipelined (for pageflips).
3434 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3436 struct intel_ring_buffer *pipelined)
3438 u32 old_read_domains, old_write_domain;
3441 if (pipelined != obj->ring) {
3442 ret = i915_gem_object_sync(obj, pipelined);
3447 /* The display engine is not coherent with the LLC cache on gen6. As
3448 * a result, we make sure that the pinning that is about to occur is
3449 * done with uncached PTEs. This is lowest common denominator for all
3452 * However for gen6+, we could do better by using the GFDT bit instead
3453 * of uncaching, which would allow us to flush all the LLC-cached data
3454 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3456 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3460 /* As the user may map the buffer once pinned in the display plane
3461 * (e.g. libkms for the bootup splash), we have to ensure that we
3462 * always use map_and_fenceable for all scanout buffers.
3464 ret = i915_gem_object_pin(obj, alignment, true, false);
3468 i915_gem_object_flush_cpu_write_domain(obj);
3470 old_write_domain = obj->base.write_domain;
3471 old_read_domains = obj->base.read_domains;
3473 /* It should now be out of any other write domains, and we can update
3474 * the domain values for our changes.
3476 obj->base.write_domain = 0;
3477 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3479 trace_i915_gem_object_change_domain(obj,
3487 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3491 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3494 ret = i915_gem_object_wait_rendering(obj, false);
3498 /* Ensure that we invalidate the GPU's caches and TLBs. */
3499 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3504 * Moves a single object to the CPU read, and possibly write domain.
3506 * This function returns when the move is complete, including waiting on
3510 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3512 uint32_t old_write_domain, old_read_domains;
3515 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3518 ret = i915_gem_object_wait_rendering(obj, !write);
3522 i915_gem_object_flush_gtt_write_domain(obj);
3524 old_write_domain = obj->base.write_domain;
3525 old_read_domains = obj->base.read_domains;
3527 /* Flush the CPU cache if it's still invalid. */
3528 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3529 i915_gem_clflush_object(obj);
3531 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3534 /* It should now be out of any other write domains, and we can update
3535 * the domain values for our changes.
3537 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3539 /* If we're writing through the CPU, then the GPU read domains will
3540 * need to be invalidated at next use.
3543 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3544 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3547 trace_i915_gem_object_change_domain(obj,
3554 /* Throttle our rendering by waiting until the ring has completed our requests
3555 * emitted over 20 msec ago.
3557 * Note that if we were to use the current jiffies each time around the loop,
3558 * we wouldn't escape the function with any frames outstanding if the time to
3559 * render a frame was over 20ms.
3561 * This should get us reasonable parallelism between CPU and GPU but also
3562 * relatively low latency when blocking on a particular request to finish.
3565 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3567 struct drm_i915_private *dev_priv = dev->dev_private;
3568 struct drm_i915_file_private *file_priv = file->driver_priv;
3569 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3570 struct drm_i915_gem_request *request;
3571 struct intel_ring_buffer *ring = NULL;
3572 unsigned reset_counter;
3576 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3580 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3584 spin_lock(&file_priv->mm.lock);
3585 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3586 if (time_after_eq(request->emitted_jiffies, recent_enough))
3589 ring = request->ring;
3590 seqno = request->seqno;
3592 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3593 spin_unlock(&file_priv->mm.lock);
3598 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3600 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3606 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3608 bool map_and_fenceable,
3613 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3616 if (obj->gtt_space != NULL) {
3617 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3618 (map_and_fenceable && !obj->map_and_fenceable)) {
3619 WARN(obj->pin_count,
3620 "bo is already pinned with incorrect alignment:"
3621 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3622 " obj->map_and_fenceable=%d\n",
3623 obj->gtt_offset, alignment,
3625 obj->map_and_fenceable);
3626 ret = i915_gem_object_unbind(obj);
3632 if (obj->gtt_space == NULL) {
3633 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3635 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3641 if (!dev_priv->mm.aliasing_ppgtt)
3642 i915_gem_gtt_bind_object(obj, obj->cache_level);
3645 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3646 i915_gem_gtt_bind_object(obj, obj->cache_level);
3649 obj->pin_mappable |= map_and_fenceable;
3655 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3657 BUG_ON(obj->pin_count == 0);
3658 BUG_ON(obj->gtt_space == NULL);
3660 if (--obj->pin_count == 0)
3661 obj->pin_mappable = false;
3665 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3666 struct drm_file *file)
3668 struct drm_i915_gem_pin *args = data;
3669 struct drm_i915_gem_object *obj;
3672 ret = i915_mutex_lock_interruptible(dev);
3676 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3677 if (&obj->base == NULL) {
3682 if (obj->madv != I915_MADV_WILLNEED) {
3683 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3688 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3689 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3695 if (obj->user_pin_count == 0) {
3696 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3701 obj->user_pin_count++;
3702 obj->pin_filp = file;
3704 /* XXX - flush the CPU caches for pinned objects
3705 * as the X server doesn't manage domains yet
3707 i915_gem_object_flush_cpu_write_domain(obj);
3708 args->offset = obj->gtt_offset;
3710 drm_gem_object_unreference(&obj->base);
3712 mutex_unlock(&dev->struct_mutex);
3717 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3718 struct drm_file *file)
3720 struct drm_i915_gem_pin *args = data;
3721 struct drm_i915_gem_object *obj;
3724 ret = i915_mutex_lock_interruptible(dev);
3728 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3729 if (&obj->base == NULL) {
3734 if (obj->pin_filp != file) {
3735 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3740 obj->user_pin_count--;
3741 if (obj->user_pin_count == 0) {
3742 obj->pin_filp = NULL;
3743 i915_gem_object_unpin(obj);
3747 drm_gem_object_unreference(&obj->base);
3749 mutex_unlock(&dev->struct_mutex);
3754 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3755 struct drm_file *file)
3757 struct drm_i915_gem_busy *args = data;
3758 struct drm_i915_gem_object *obj;
3761 ret = i915_mutex_lock_interruptible(dev);
3765 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3766 if (&obj->base == NULL) {
3771 /* Count all active objects as busy, even if they are currently not used
3772 * by the gpu. Users of this interface expect objects to eventually
3773 * become non-busy without any further actions, therefore emit any
3774 * necessary flushes here.
3776 ret = i915_gem_object_flush_active(obj);
3778 args->busy = obj->active;
3780 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3781 args->busy |= intel_ring_flag(obj->ring) << 16;
3784 drm_gem_object_unreference(&obj->base);
3786 mutex_unlock(&dev->struct_mutex);
3791 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3792 struct drm_file *file_priv)
3794 return i915_gem_ring_throttle(dev, file_priv);
3798 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3799 struct drm_file *file_priv)
3801 struct drm_i915_gem_madvise *args = data;
3802 struct drm_i915_gem_object *obj;
3805 switch (args->madv) {
3806 case I915_MADV_DONTNEED:
3807 case I915_MADV_WILLNEED:
3813 ret = i915_mutex_lock_interruptible(dev);
3817 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3818 if (&obj->base == NULL) {
3823 if (obj->pin_count) {
3828 if (obj->madv != __I915_MADV_PURGED)
3829 obj->madv = args->madv;
3831 /* if the object is no longer attached, discard its backing storage */
3832 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3833 i915_gem_object_truncate(obj);
3835 args->retained = obj->madv != __I915_MADV_PURGED;
3838 drm_gem_object_unreference(&obj->base);
3840 mutex_unlock(&dev->struct_mutex);
3844 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3845 const struct drm_i915_gem_object_ops *ops)
3847 INIT_LIST_HEAD(&obj->mm_list);
3848 INIT_LIST_HEAD(&obj->global_list);
3849 INIT_LIST_HEAD(&obj->ring_list);
3850 INIT_LIST_HEAD(&obj->exec_list);
3854 obj->fence_reg = I915_FENCE_REG_NONE;
3855 obj->madv = I915_MADV_WILLNEED;
3856 /* Avoid an unnecessary call to unbind on the first bind. */
3857 obj->map_and_fenceable = true;
3859 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3862 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3863 .get_pages = i915_gem_object_get_pages_gtt,
3864 .put_pages = i915_gem_object_put_pages_gtt,
3867 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3870 struct drm_i915_gem_object *obj;
3871 struct address_space *mapping;
3874 obj = i915_gem_object_alloc(dev);
3878 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3879 i915_gem_object_free(obj);
3883 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3884 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3885 /* 965gm cannot relocate objects above 4GiB. */
3886 mask &= ~__GFP_HIGHMEM;
3887 mask |= __GFP_DMA32;
3890 mapping = file_inode(obj->base.filp)->i_mapping;
3891 mapping_set_gfp_mask(mapping, mask);
3893 i915_gem_object_init(obj, &i915_gem_object_ops);
3895 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3896 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3899 /* On some devices, we can have the GPU use the LLC (the CPU
3900 * cache) for about a 10% performance improvement
3901 * compared to uncached. Graphics requests other than
3902 * display scanout are coherent with the CPU in
3903 * accessing this cache. This means in this mode we
3904 * don't need to clflush on the CPU side, and on the
3905 * GPU side we only need to flush internal caches to
3906 * get data visible to the CPU.
3908 * However, we maintain the display planes as UC, and so
3909 * need to rebind when first used as such.
3911 obj->cache_level = I915_CACHE_LLC;
3913 obj->cache_level = I915_CACHE_NONE;
3918 int i915_gem_init_object(struct drm_gem_object *obj)
3925 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3927 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3928 struct drm_device *dev = obj->base.dev;
3929 drm_i915_private_t *dev_priv = dev->dev_private;
3931 trace_i915_gem_object_destroy(obj);
3934 i915_gem_detach_phys_object(dev, obj);
3937 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3938 bool was_interruptible;
3940 was_interruptible = dev_priv->mm.interruptible;
3941 dev_priv->mm.interruptible = false;
3943 WARN_ON(i915_gem_object_unbind(obj));
3945 dev_priv->mm.interruptible = was_interruptible;
3948 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3949 * before progressing. */
3951 i915_gem_object_unpin_pages(obj);
3953 if (WARN_ON(obj->pages_pin_count))
3954 obj->pages_pin_count = 0;
3955 i915_gem_object_put_pages(obj);
3956 i915_gem_object_free_mmap_offset(obj);
3957 i915_gem_object_release_stolen(obj);
3961 if (obj->base.import_attach)
3962 drm_prime_gem_destroy(&obj->base, NULL);
3964 drm_gem_object_release(&obj->base);
3965 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3968 i915_gem_object_free(obj);
3972 i915_gem_idle(struct drm_device *dev)
3974 drm_i915_private_t *dev_priv = dev->dev_private;
3977 mutex_lock(&dev->struct_mutex);
3979 if (dev_priv->mm.suspended) {
3980 mutex_unlock(&dev->struct_mutex);
3984 ret = i915_gpu_idle(dev);
3986 mutex_unlock(&dev->struct_mutex);
3989 i915_gem_retire_requests(dev);
3991 /* Under UMS, be paranoid and evict. */
3992 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3993 i915_gem_evict_everything(dev);
3995 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3996 * We need to replace this with a semaphore, or something.
3997 * And not confound mm.suspended!
3999 dev_priv->mm.suspended = 1;
4000 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4002 i915_kernel_lost_context(dev);
4003 i915_gem_cleanup_ringbuffer(dev);
4005 mutex_unlock(&dev->struct_mutex);
4007 /* Cancel the retire work handler, which should be idle now. */
4008 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4013 void i915_gem_l3_remap(struct drm_device *dev)
4015 drm_i915_private_t *dev_priv = dev->dev_private;
4019 if (!HAS_L3_GPU_CACHE(dev))
4022 if (!dev_priv->l3_parity.remap_info)
4025 misccpctl = I915_READ(GEN7_MISCCPCTL);
4026 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4027 POSTING_READ(GEN7_MISCCPCTL);
4029 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4030 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4031 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4032 DRM_DEBUG("0x%x was already programmed to %x\n",
4033 GEN7_L3LOG_BASE + i, remap);
4034 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4035 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4036 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4039 /* Make sure all the writes land before disabling dop clock gating */
4040 POSTING_READ(GEN7_L3LOG_BASE);
4042 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4045 void i915_gem_init_swizzling(struct drm_device *dev)
4047 drm_i915_private_t *dev_priv = dev->dev_private;
4049 if (INTEL_INFO(dev)->gen < 5 ||
4050 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4053 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4054 DISP_TILE_SURFACE_SWIZZLING);
4059 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4061 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4062 else if (IS_GEN7(dev))
4063 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4069 intel_enable_blt(struct drm_device *dev)
4074 /* The blitter was dysfunctional on early prototypes */
4075 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4076 DRM_INFO("BLT not supported on this pre-production hardware;"
4077 " graphics performance will be degraded.\n");
4084 static int i915_gem_init_rings(struct drm_device *dev)
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4089 ret = intel_init_render_ring_buffer(dev);
4094 ret = intel_init_bsd_ring_buffer(dev);
4096 goto cleanup_render_ring;
4099 if (intel_enable_blt(dev)) {
4100 ret = intel_init_blt_ring_buffer(dev);
4102 goto cleanup_bsd_ring;
4105 if (HAS_VEBOX(dev)) {
4106 ret = intel_init_vebox_ring_buffer(dev);
4108 goto cleanup_blt_ring;
4112 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4114 goto cleanup_vebox_ring;
4119 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4121 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4123 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4124 cleanup_render_ring:
4125 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4131 i915_gem_init_hw(struct drm_device *dev)
4133 drm_i915_private_t *dev_priv = dev->dev_private;
4136 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4139 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4140 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4142 if (HAS_PCH_NOP(dev)) {
4143 u32 temp = I915_READ(GEN7_MSG_CTL);
4144 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4145 I915_WRITE(GEN7_MSG_CTL, temp);
4148 i915_gem_l3_remap(dev);
4150 i915_gem_init_swizzling(dev);
4152 ret = i915_gem_init_rings(dev);
4157 * XXX: There was some w/a described somewhere suggesting loading
4158 * contexts before PPGTT.
4160 i915_gem_context_init(dev);
4161 if (dev_priv->mm.aliasing_ppgtt) {
4162 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4164 i915_gem_cleanup_aliasing_ppgtt(dev);
4165 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4172 int i915_gem_init(struct drm_device *dev)
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4177 mutex_lock(&dev->struct_mutex);
4179 if (IS_VALLEYVIEW(dev)) {
4180 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4181 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4182 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4183 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4186 i915_gem_init_global_gtt(dev);
4188 ret = i915_gem_init_hw(dev);
4189 mutex_unlock(&dev->struct_mutex);
4191 i915_gem_cleanup_aliasing_ppgtt(dev);
4195 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4196 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4197 dev_priv->dri1.allow_batchbuffer = 1;
4202 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4204 drm_i915_private_t *dev_priv = dev->dev_private;
4205 struct intel_ring_buffer *ring;
4208 for_each_ring(ring, dev_priv, i)
4209 intel_cleanup_ring_buffer(ring);
4213 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4214 struct drm_file *file_priv)
4216 drm_i915_private_t *dev_priv = dev->dev_private;
4219 if (drm_core_check_feature(dev, DRIVER_MODESET))
4222 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4223 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4224 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4227 mutex_lock(&dev->struct_mutex);
4228 dev_priv->mm.suspended = 0;
4230 ret = i915_gem_init_hw(dev);
4232 mutex_unlock(&dev->struct_mutex);
4236 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4237 mutex_unlock(&dev->struct_mutex);
4239 ret = drm_irq_install(dev);
4241 goto cleanup_ringbuffer;
4246 mutex_lock(&dev->struct_mutex);
4247 i915_gem_cleanup_ringbuffer(dev);
4248 dev_priv->mm.suspended = 1;
4249 mutex_unlock(&dev->struct_mutex);
4255 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4256 struct drm_file *file_priv)
4258 if (drm_core_check_feature(dev, DRIVER_MODESET))
4261 drm_irq_uninstall(dev);
4262 return i915_gem_idle(dev);
4266 i915_gem_lastclose(struct drm_device *dev)
4270 if (drm_core_check_feature(dev, DRIVER_MODESET))
4273 ret = i915_gem_idle(dev);
4275 DRM_ERROR("failed to idle hardware: %d\n", ret);
4279 init_ring_lists(struct intel_ring_buffer *ring)
4281 INIT_LIST_HEAD(&ring->active_list);
4282 INIT_LIST_HEAD(&ring->request_list);
4286 i915_gem_load(struct drm_device *dev)
4288 drm_i915_private_t *dev_priv = dev->dev_private;
4292 kmem_cache_create("i915_gem_object",
4293 sizeof(struct drm_i915_gem_object), 0,
4297 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4298 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4299 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4300 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4301 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4302 for (i = 0; i < I915_NUM_RINGS; i++)
4303 init_ring_lists(&dev_priv->ring[i]);
4304 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4305 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4306 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4307 i915_gem_retire_work_handler);
4308 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4310 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4312 I915_WRITE(MI_ARB_STATE,
4313 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4316 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4318 /* Old X drivers will take 0-2 for front, back, depth buffers */
4319 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4320 dev_priv->fence_reg_start = 3;
4322 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4323 dev_priv->num_fence_regs = 32;
4324 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4325 dev_priv->num_fence_regs = 16;
4327 dev_priv->num_fence_regs = 8;
4329 /* Initialize fence registers to zero */
4330 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4331 i915_gem_restore_fences(dev);
4333 i915_gem_detect_bit_6_swizzle(dev);
4334 init_waitqueue_head(&dev_priv->pending_flip_queue);
4336 dev_priv->mm.interruptible = true;
4338 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4339 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4340 register_shrinker(&dev_priv->mm.inactive_shrinker);
4344 * Create a physically contiguous memory object for this object
4345 * e.g. for cursor + overlay regs
4347 static int i915_gem_init_phys_object(struct drm_device *dev,
4348 int id, int size, int align)
4350 drm_i915_private_t *dev_priv = dev->dev_private;
4351 struct drm_i915_gem_phys_object *phys_obj;
4354 if (dev_priv->mm.phys_objs[id - 1] || !size)
4357 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4363 phys_obj->handle = drm_pci_alloc(dev, size, align);
4364 if (!phys_obj->handle) {
4369 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4372 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4380 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4382 drm_i915_private_t *dev_priv = dev->dev_private;
4383 struct drm_i915_gem_phys_object *phys_obj;
4385 if (!dev_priv->mm.phys_objs[id - 1])
4388 phys_obj = dev_priv->mm.phys_objs[id - 1];
4389 if (phys_obj->cur_obj) {
4390 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4394 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4396 drm_pci_free(dev, phys_obj->handle);
4398 dev_priv->mm.phys_objs[id - 1] = NULL;
4401 void i915_gem_free_all_phys_object(struct drm_device *dev)
4405 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4406 i915_gem_free_phys_object(dev, i);
4409 void i915_gem_detach_phys_object(struct drm_device *dev,
4410 struct drm_i915_gem_object *obj)
4412 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4419 vaddr = obj->phys_obj->handle->vaddr;
4421 page_count = obj->base.size / PAGE_SIZE;
4422 for (i = 0; i < page_count; i++) {
4423 struct page *page = shmem_read_mapping_page(mapping, i);
4424 if (!IS_ERR(page)) {
4425 char *dst = kmap_atomic(page);
4426 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4429 drm_clflush_pages(&page, 1);
4431 set_page_dirty(page);
4432 mark_page_accessed(page);
4433 page_cache_release(page);
4436 i915_gem_chipset_flush(dev);
4438 obj->phys_obj->cur_obj = NULL;
4439 obj->phys_obj = NULL;
4443 i915_gem_attach_phys_object(struct drm_device *dev,
4444 struct drm_i915_gem_object *obj,
4448 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4449 drm_i915_private_t *dev_priv = dev->dev_private;
4454 if (id > I915_MAX_PHYS_OBJECT)
4457 if (obj->phys_obj) {
4458 if (obj->phys_obj->id == id)
4460 i915_gem_detach_phys_object(dev, obj);
4463 /* create a new object */
4464 if (!dev_priv->mm.phys_objs[id - 1]) {
4465 ret = i915_gem_init_phys_object(dev, id,
4466 obj->base.size, align);
4468 DRM_ERROR("failed to init phys object %d size: %zu\n",
4469 id, obj->base.size);
4474 /* bind to the object */
4475 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4476 obj->phys_obj->cur_obj = obj;
4478 page_count = obj->base.size / PAGE_SIZE;
4480 for (i = 0; i < page_count; i++) {
4484 page = shmem_read_mapping_page(mapping, i);
4486 return PTR_ERR(page);
4488 src = kmap_atomic(page);
4489 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4490 memcpy(dst, src, PAGE_SIZE);
4493 mark_page_accessed(page);
4494 page_cache_release(page);
4501 i915_gem_phys_pwrite(struct drm_device *dev,
4502 struct drm_i915_gem_object *obj,
4503 struct drm_i915_gem_pwrite *args,
4504 struct drm_file *file_priv)
4506 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4507 char __user *user_data = to_user_ptr(args->data_ptr);
4509 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4510 unsigned long unwritten;
4512 /* The physical object once assigned is fixed for the lifetime
4513 * of the obj, so we can safely drop the lock and continue
4516 mutex_unlock(&dev->struct_mutex);
4517 unwritten = copy_from_user(vaddr, user_data, args->size);
4518 mutex_lock(&dev->struct_mutex);
4523 i915_gem_chipset_flush(dev);
4527 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4529 struct drm_i915_file_private *file_priv = file->driver_priv;
4531 /* Clean up our request list when the client is going away, so that
4532 * later retire_requests won't dereference our soon-to-be-gone
4535 spin_lock(&file_priv->mm.lock);
4536 while (!list_empty(&file_priv->mm.request_list)) {
4537 struct drm_i915_gem_request *request;
4539 request = list_first_entry(&file_priv->mm.request_list,
4540 struct drm_i915_gem_request,
4542 list_del(&request->client_list);
4543 request->file_priv = NULL;
4545 spin_unlock(&file_priv->mm.lock);
4548 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4550 if (!mutex_is_locked(mutex))
4553 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4554 return mutex->owner == task;
4556 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4562 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4564 struct drm_i915_private *dev_priv =
4565 container_of(shrinker,
4566 struct drm_i915_private,
4567 mm.inactive_shrinker);
4568 struct drm_device *dev = dev_priv->dev;
4569 struct drm_i915_gem_object *obj;
4570 int nr_to_scan = sc->nr_to_scan;
4574 if (!mutex_trylock(&dev->struct_mutex)) {
4575 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4578 if (dev_priv->mm.shrinker_no_lock_stealing)
4585 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4587 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4590 i915_gem_shrink_all(dev_priv);
4594 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4595 if (obj->pages_pin_count == 0)
4596 cnt += obj->base.size >> PAGE_SHIFT;
4597 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list)
4598 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4599 cnt += obj->base.size >> PAGE_SHIFT;
4602 mutex_unlock(&dev->struct_mutex);