drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_PORT_DDI_A_LANES:
  93                 return "PORT_DDI_A_LANES";
  94         case POWER_DOMAIN_PORT_DDI_B_LANES:
  95                 return "PORT_DDI_B_LANES";
  96         case POWER_DOMAIN_PORT_DDI_C_LANES:
  97                 return "PORT_DDI_C_LANES";
  98         case POWER_DOMAIN_PORT_DDI_D_LANES:
  99                 return "PORT_DDI_D_LANES";
 100         case POWER_DOMAIN_PORT_DDI_E_LANES:
 101                 return "PORT_DDI_E_LANES";
 102         case POWER_DOMAIN_PORT_DSI:
 103                 return "PORT_DSI";
 104         case POWER_DOMAIN_PORT_CRT:
 105                 return "PORT_CRT";
 106         case POWER_DOMAIN_PORT_OTHER:
 107                 return "PORT_OTHER";
 108         case POWER_DOMAIN_VGA:
 109                 return "VGA";
 110         case POWER_DOMAIN_AUDIO:
 111                 return "AUDIO";
 112         case POWER_DOMAIN_PLLS:
 113                 return "PLLS";
 114         case POWER_DOMAIN_AUX_A:
 115                 return "AUX_A";
 116         case POWER_DOMAIN_AUX_B:
 117                 return "AUX_B";
 118         case POWER_DOMAIN_AUX_C:
 119                 return "AUX_C";
 120         case POWER_DOMAIN_AUX_D:
 121                 return "AUX_D";
 122         case POWER_DOMAIN_GMBUS:
 123                 return "GMBUS";
 124         case POWER_DOMAIN_INIT:
 125                 return "INIT";
 126         case POWER_DOMAIN_MODESET:
 127                 return "MODESET";
 128         default:
 129                 MISSING_CASE(domain);
 130                 return "?";
 131         }
 132 }
 133
 134 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 135                                     struct i915_power_well *power_well)
 136 {
 137         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 138         power_well->ops->enable(dev_priv, power_well);
 139         power_well->hw_enabled = true;
 140 }
 141
 142 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 143                                      struct i915_power_well *power_well)
 144 {
 145         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 146         power_well->hw_enabled = false;
 147         power_well->ops->disable(dev_priv, power_well);
 148 }
 149
 150 /*
 151  * We should only use the power well if we explicitly asked the hardware to
 152  * enable it, so check if it's enabled and also check if we've requested it to
 153  * be enabled.
 154  */
 155 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 156                                    struct i915_power_well *power_well)
 157 {
 158         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 159                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 160 }
 161
 162 /**
 163  * __intel_display_power_is_enabled - unlocked check for a power domain
 164  * @dev_priv: i915 device instance
 165  * @domain: power domain to check
 166  *
 167  * This is the unlocked version of intel_display_power_is_enabled() and should
 168  * only be used from error capture and recovery code where deadlocks are
 169  * possible.
 170  *
 171  * Returns:
 172  * True when the power domain is enabled, false otherwise.
 173  */
 174 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 175                                       enum intel_display_power_domain domain)
 176 {
 177         struct i915_power_domains *power_domains;
 178         struct i915_power_well *power_well;
 179         bool is_enabled;
 180         int i;
 181
 182         if (dev_priv->pm.suspended)
 183                 return false;
 184
 185         power_domains = &dev_priv->power_domains;
 186
 187         is_enabled = true;
 188
 189         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 190                 if (power_well->always_on)
 191                         continue;
 192
 193                 if (!power_well->hw_enabled) {
 194                         is_enabled = false;
 195                         break;
 196                 }
 197         }
 198
 199         return is_enabled;
 200 }
 201
 202 /**
 203  * intel_display_power_is_enabled - check for a power domain
 204  * @dev_priv: i915 device instance
 205  * @domain: power domain to check
 206  *
 207  * This function can be used to check the hw power domain state. It is mostly
 208  * used in hardware state readout functions. Everywhere else code should rely
 209  * upon explicit power domain reference counting to ensure that the hardware
 210  * block is powered up before accessing it.
 211  *
 212  * Callers must hold the relevant modesetting locks to ensure that concurrent
 213  * threads can't disable the power well while the caller tries to read a few
 214  * registers.
 215  *
 216  * Returns:
 217  * True when the power domain is enabled, false otherwise.
 218  */
 219 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 220                                     enum intel_display_power_domain domain)
 221 {
 222         struct i915_power_domains *power_domains;
 223         bool ret;
 224
 225         power_domains = &dev_priv->power_domains;
 226
 227         mutex_lock(&power_domains->lock);
 228         ret = __intel_display_power_is_enabled(dev_priv, domain);
 229         mutex_unlock(&power_domains->lock);
 230
 231         return ret;
 232 }
 233
 234 /**
 235  * intel_display_set_init_power - set the initial power domain state
 236  * @dev_priv: i915 device instance
 237  * @enable: whether to enable or disable the initial power domain state
 238  *
 239  * For simplicity our driver load/unload and system suspend/resume code assumes
 240  * that all power domains are always enabled. This functions controls the state
 241  * of this little hack. While the initial power domain state is enabled runtime
 242  * pm is effectively disabled.
 243  */
 244 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 245                                   bool enable)
 246 {
 247         if (dev_priv->power_domains.init_power_on == enable)
 248                 return;
 249
 250         if (enable)
 251                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 252         else
 253                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 254
 255         dev_priv->power_domains.init_power_on = enable;
 256 }
 257
 258 /*
 259  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 260  * when not needed anymore. We have 4 registers that can request the power well
 261  * to be enabled, and it will only be disabled if none of the registers is
 262  * requesting it to be enabled.
 263  */
 264 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 265 {
 266         struct drm_device *dev = dev_priv->dev;
 267
 268         /*
 269          * After we re-enable the power well, if we touch VGA register 0x3d5
 270          * we'll get unclaimed register interrupts. This stops after we write
 271          * anything to the VGA MSR register. The vgacon module uses this
 272          * register all the time, so if we unbind our driver and, as a
 273          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 274          * console_unlock(). So make here we touch the VGA MSR register, making
 275          * sure vgacon can keep working normally without triggering interrupts
 276          * and error messages.
 277          */
 278         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 279         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 280         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 281
 282         if (IS_BROADWELL(dev))
 283                 gen8_irq_power_well_post_enable(dev_priv,
 284                                                 1 << PIPE_C | 1 << PIPE_B);
 285 }
 286
 287 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 288                                        struct i915_power_well *power_well)
 289 {
 290         struct drm_device *dev = dev_priv->dev;
 291
 292         /*
 293          * After we re-enable the power well, if we touch VGA register 0x3d5
 294          * we'll get unclaimed register interrupts. This stops after we write
 295          * anything to the VGA MSR register. The vgacon module uses this
 296          * register all the time, so if we unbind our driver and, as a
 297          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 298          * console_unlock(). So make here we touch the VGA MSR register, making
 299          * sure vgacon can keep working normally without triggering interrupts
 300          * and error messages.
 301          */
 302         if (power_well->data == SKL_DISP_PW_2) {
 303                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 304                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 305                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 306
 307                 gen8_irq_power_well_post_enable(dev_priv,
 308                                                 1 << PIPE_C | 1 << PIPE_B);
 309         }
 310 }
 311
 312 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 313                                struct i915_power_well *power_well, bool enable)
 314 {
 315         bool is_enabled, enable_requested;
 316         uint32_t tmp;
 317
 318         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 319         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 320         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 321
 322         if (enable) {
 323                 if (!enable_requested)
 324                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 325                                    HSW_PWR_WELL_ENABLE_REQUEST);
 326
 327                 if (!is_enabled) {
 328                         DRM_DEBUG_KMS("Enabling power well\n");
 329                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 330                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 331                                 DRM_ERROR("Timeout enabling power well\n");
 332                         hsw_power_well_post_enable(dev_priv);
 333                 }
 334
 335         } else {
 336                 if (enable_requested) {
 337                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 338                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 339                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 340                 }
 341         }
 342 }
 343
 344 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 345         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 346         BIT(POWER_DOMAIN_PIPE_B) |                      \
 347         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 348         BIT(POWER_DOMAIN_PIPE_C) |                      \
 349         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 350         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 351         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 352         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 353         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 354         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 355         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 356         BIT(POWER_DOMAIN_AUX_B) |                       \
 357         BIT(POWER_DOMAIN_AUX_C) |                       \
 358         BIT(POWER_DOMAIN_AUX_D) |                       \
 359         BIT(POWER_DOMAIN_AUDIO) |                       \
 360         BIT(POWER_DOMAIN_VGA) |                         \
 361         BIT(POWER_DOMAIN_INIT))
 362 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 363         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 364         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 365         BIT(POWER_DOMAIN_INIT))
 366 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 367         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 368         BIT(POWER_DOMAIN_INIT))
 369 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 370         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 371         BIT(POWER_DOMAIN_INIT))
 372 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 373         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 374         BIT(POWER_DOMAIN_INIT))
 375 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 376         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 377         BIT(POWER_DOMAIN_MODESET) |                     \
 378         BIT(POWER_DOMAIN_AUX_A) |                       \
 379         BIT(POWER_DOMAIN_INIT))
 380 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 381         (POWER_DOMAIN_MASK & ~(                         \
 382         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 383         SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) |            \
 384         BIT(POWER_DOMAIN_INIT))
 385
 386 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 387         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 388         BIT(POWER_DOMAIN_PIPE_B) |                      \
 389         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 390         BIT(POWER_DOMAIN_PIPE_C) |                      \
 391         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 392         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 393         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 394         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 395         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 396         BIT(POWER_DOMAIN_AUX_B) |                       \
 397         BIT(POWER_DOMAIN_AUX_C) |                       \
 398         BIT(POWER_DOMAIN_AUDIO) |                       \
 399         BIT(POWER_DOMAIN_VGA) |                         \
 400         BIT(POWER_DOMAIN_GMBUS) |                       \
 401         BIT(POWER_DOMAIN_INIT))
 402 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 403         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 404         BIT(POWER_DOMAIN_PIPE_A) |                      \
 405         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 406         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 407         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 408         BIT(POWER_DOMAIN_AUX_A) |                       \
 409         BIT(POWER_DOMAIN_PLLS) |                        \
 410         BIT(POWER_DOMAIN_INIT))
 411 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 412         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 413         BIT(POWER_DOMAIN_MODESET) |                     \
 414         BIT(POWER_DOMAIN_AUX_A) |                       \
 415         BIT(POWER_DOMAIN_INIT))
 416 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 417         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 418         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 419         BIT(POWER_DOMAIN_INIT))
 420
 421 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 422 {
 423         struct drm_device *dev = dev_priv->dev;
 424
 425         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 426         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 427                 "DC9 already programmed to be enabled.\n");
 428         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 429                 "DC5 still not disabled to enable DC9.\n");
 430         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 431         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 432
 433          /*
 434           * TODO: check for the following to verify the conditions to enter DC9
 435           * state are satisfied:
 436           * 1] Check relevant display engine registers to verify if mode set
 437           * disable sequence was followed.
 438           * 2] Check if display uninitialize sequence is initialized.
 439           */
 440 }
 441
 442 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 443 {
 444         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 445         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 446                 "DC9 already programmed to be disabled.\n");
 447         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 448                 "DC5 still not disabled.\n");
 449
 450          /*
 451           * TODO: check for the following to verify DC9 state was indeed
 452           * entered before programming to disable it:
 453           * 1] Check relevant display engine registers to verify if mode
 454           *  set disable sequence was followed.
 455           * 2] Check if display uninitialize sequence is initialized.
 456           */
 457 }
 458
 459 static void gen9_set_dc_state_debugmask_memory_up(
 460                         struct drm_i915_private *dev_priv)
 461 {
 462         uint32_t val;
 463
 464         /* The below bit doesn't need to be cleared ever afterwards */
 465         val = I915_READ(DC_STATE_DEBUG);
 466         if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
 467                 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
 468                 I915_WRITE(DC_STATE_DEBUG, val);
 469                 POSTING_READ(DC_STATE_DEBUG);
 470         }
 471 }
 472
 473 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 474 {
 475         uint32_t val;
 476         uint32_t mask;
 477
 478         mask = DC_STATE_EN_UPTO_DC5;
 479         if (IS_BROXTON(dev_priv))
 480                 mask |= DC_STATE_EN_DC9;
 481         else
 482                 mask |= DC_STATE_EN_UPTO_DC6;
 483
 484         WARN_ON_ONCE(state & ~mask);
 485
 486         if (i915.enable_dc == 0)
 487                 state = DC_STATE_DISABLE;
 488         else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
 489                 state = DC_STATE_EN_UPTO_DC5;
 490
 491         if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
 492                 gen9_set_dc_state_debugmask_memory_up(dev_priv);
 493
 494         val = I915_READ(DC_STATE_EN);
 495         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 496                       val & mask, state);
 497
 498         /* Check if DMC is ignoring our DC state requests */
 499         if ((val & mask) != dev_priv->csr.dc_state)
 500                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 501                           dev_priv->csr.dc_state, val & mask);
 502
 503         val &= ~mask;
 504         val |= state;
 505         I915_WRITE(DC_STATE_EN, val);
 506         POSTING_READ(DC_STATE_EN);
 507
 508         dev_priv->csr.dc_state = val & mask;
 509 }
 510
 511 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 512 {
 513         assert_can_enable_dc9(dev_priv);
 514
 515         DRM_DEBUG_KMS("Enabling DC9\n");
 516
 517         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 518 }
 519
 520 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 521 {
 522         assert_can_disable_dc9(dev_priv);
 523
 524         DRM_DEBUG_KMS("Disabling DC9\n");
 525
 526         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 527 }
 528
 529 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 530 {
 531         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 532                   "CSR program storage start is NULL\n");
 533         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 534         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 535 }
 536
 537 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 538 {
 539         struct drm_device *dev = dev_priv->dev;
 540         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 541                                         SKL_DISP_PW_2);
 542
 543         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
 544         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 545         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 546
 547         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 548                   "DC5 already programmed to be enabled.\n");
 549         assert_rpm_wakelock_held(dev_priv);
 550
 551         assert_csr_loaded(dev_priv);
 552 }
 553
 554 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 555 {
 556         /*
 557          * During initialization, the firmware may not be loaded yet.
 558          * We still want to make sure that the DC enabling flag is cleared.
 559          */
 560         if (dev_priv->power_domains.initializing)
 561                 return;
 562
 563         assert_rpm_wakelock_held(dev_priv);
 564 }
 565
 566 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 567 {
 568         assert_can_enable_dc5(dev_priv);
 569
 570         DRM_DEBUG_KMS("Enabling DC5\n");
 571
 572         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 573 }
 574
 575 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 576 {
 577         struct drm_device *dev = dev_priv->dev;
 578
 579         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
 580         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 581         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 582                   "Backlight is not disabled.\n");
 583         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 584                   "DC6 already programmed to be enabled.\n");
 585
 586         assert_csr_loaded(dev_priv);
 587 }
 588
 589 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 590 {
 591         /*
 592          * During initialization, the firmware may not be loaded yet.
 593          * We still want to make sure that the DC enabling flag is cleared.
 594          */
 595         if (dev_priv->power_domains.initializing)
 596                 return;
 597
 598         WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 599                   "DC6 already programmed to be disabled.\n");
 600 }
 601
 602 static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
 603 {
 604         assert_can_disable_dc5(dev_priv);
 605
 606         if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1)
 607                 assert_can_disable_dc6(dev_priv);
 608
 609         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 610 }
 611
 612 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 613 {
 614         assert_can_enable_dc6(dev_priv);
 615
 616         DRM_DEBUG_KMS("Enabling DC6\n");
 617
 618         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 619
 620 }
 621
 622 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 623 {
 624         assert_can_disable_dc6(dev_priv);
 625
 626         DRM_DEBUG_KMS("Disabling DC6\n");
 627
 628         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 629 }
 630
 631 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 632                         struct i915_power_well *power_well, bool enable)
 633 {
 634         struct drm_device *dev = dev_priv->dev;
 635         uint32_t tmp, fuse_status;
 636         uint32_t req_mask, state_mask;
 637         bool is_enabled, enable_requested, check_fuse_status = false;
 638
 639         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 640         fuse_status = I915_READ(SKL_FUSE_STATUS);
 641
 642         switch (power_well->data) {
 643         case SKL_DISP_PW_1:
 644                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 645                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 646                         DRM_ERROR("PG0 not enabled\n");
 647                         return;
 648                 }
 649                 break;
 650         case SKL_DISP_PW_2:
 651                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 652                         DRM_ERROR("PG1 in disabled state\n");
 653                         return;
 654                 }
 655                 break;
 656         case SKL_DISP_PW_DDI_A_E:
 657         case SKL_DISP_PW_DDI_B:
 658         case SKL_DISP_PW_DDI_C:
 659         case SKL_DISP_PW_DDI_D:
 660         case SKL_DISP_PW_MISC_IO:
 661                 break;
 662         default:
 663                 WARN(1, "Unknown power well %lu\n", power_well->data);
 664                 return;
 665         }
 666
 667         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 668         enable_requested = tmp & req_mask;
 669         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 670         is_enabled = tmp & state_mask;
 671
 672         if (enable) {
 673                 if (!enable_requested) {
 674                         WARN((tmp & state_mask) &&
 675                                 !I915_READ(HSW_PWR_WELL_BIOS),
 676                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 677                                 when request is to disable!\n");
 678                         if (power_well->data == SKL_DISP_PW_2) {
 679                                 /*
 680                                  * DDI buffer programming unnecessary during
 681                                  * driver-load/resume as it's already done
 682                                  * during modeset initialization then. It's
 683                                  * also invalid here as encoder list is still
 684                                  * uninitialized.
 685                                  */
 686                                 if (!dev_priv->power_domains.initializing)
 687                                         intel_prepare_ddi(dev);
 688                         }
 689                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 690                 }
 691
 692                 if (!is_enabled) {
 693                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 694                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 695                                 state_mask), 1))
 696                                 DRM_ERROR("%s enable timeout\n",
 697                                         power_well->name);
 698                         check_fuse_status = true;
 699                 }
 700         } else {
 701                 if (enable_requested) {
 702                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 703                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 704                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 705                 }
 706         }
 707
 708         if (check_fuse_status) {
 709                 if (power_well->data == SKL_DISP_PW_1) {
 710                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 711                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 712                                 DRM_ERROR("PG1 distributing status timeout\n");
 713                 } else if (power_well->data == SKL_DISP_PW_2) {
 714                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 715                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 716                                 DRM_ERROR("PG2 distributing status timeout\n");
 717                 }
 718         }
 719
 720         if (enable && !is_enabled)
 721                 skl_power_well_post_enable(dev_priv, power_well);
 722 }
 723
 724 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 725                                    struct i915_power_well *power_well)
 726 {
 727         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 728
 729         /*
 730          * We're taking over the BIOS, so clear any requests made by it since
 731          * the driver is in charge now.
 732          */
 733         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 734                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 735 }
 736
 737 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 738                                   struct i915_power_well *power_well)
 739 {
 740         hsw_set_power_well(dev_priv, power_well, true);
 741 }
 742
 743 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 744                                    struct i915_power_well *power_well)
 745 {
 746         hsw_set_power_well(dev_priv, power_well, false);
 747 }
 748
 749 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 750                                         struct i915_power_well *power_well)
 751 {
 752         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 753                 SKL_POWER_WELL_STATE(power_well->data);
 754
 755         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 756 }
 757
 758 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 759                                 struct i915_power_well *power_well)
 760 {
 761         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 762
 763         /* Clear any request made by BIOS as driver is taking over */
 764         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 765 }
 766
 767 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 768                                 struct i915_power_well *power_well)
 769 {
 770         skl_set_power_well(dev_priv, power_well, true);
 771 }
 772
 773 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 774                                 struct i915_power_well *power_well)
 775 {
 776         skl_set_power_well(dev_priv, power_well, false);
 777 }
 778
 779 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 780                                            struct i915_power_well *power_well)
 781 {
 782         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 783 }
 784
 785 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 786                                           struct i915_power_well *power_well)
 787 {
 788         gen9_disable_dc5_dc6(dev_priv);
 789 }
 790
 791 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 792                                            struct i915_power_well *power_well)
 793 {
 794         if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1)
 795                 skl_enable_dc6(dev_priv);
 796         else
 797                 gen9_enable_dc5(dev_priv);
 798 }
 799
 800 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 801                                            struct i915_power_well *power_well)
 802 {
 803         if (power_well->count > 0) {
 804                 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 805         } else {
 806                 if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 &&
 807                     i915.enable_dc != 1)
 808                         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 809                 else
 810                         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 811         }
 812 }
 813
 814 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 815                                            struct i915_power_well *power_well)
 816 {
 817 }
 818
 819 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 820                                              struct i915_power_well *power_well)
 821 {
 822         return true;
 823 }
 824
 825 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 826                                struct i915_power_well *power_well, bool enable)
 827 {
 828         enum punit_power_well power_well_id = power_well->data;
 829         u32 mask;
 830         u32 state;
 831         u32 ctrl;
 832
 833         mask = PUNIT_PWRGT_MASK(power_well_id);
 834         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 835                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 836
 837         mutex_lock(&dev_priv->rps.hw_lock);
 838
 839 #define COND \
 840         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 841
 842         if (COND)
 843                 goto out;
 844
 845         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 846         ctrl &= ~mask;
 847         ctrl |= state;
 848         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 849
 850         if (wait_for(COND, 100))
 851                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 852                           state,
 853                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 854
 855 #undef COND
 856
 857 out:
 858         mutex_unlock(&dev_priv->rps.hw_lock);
 859 }
 860
 861 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 862                                    struct i915_power_well *power_well)
 863 {
 864         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 865 }
 866
 867 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 868                                   struct i915_power_well *power_well)
 869 {
 870         vlv_set_power_well(dev_priv, power_well, true);
 871 }
 872
 873 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 874                                    struct i915_power_well *power_well)
 875 {
 876         vlv_set_power_well(dev_priv, power_well, false);
 877 }
 878
 879 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 880                                    struct i915_power_well *power_well)
 881 {
 882         int power_well_id = power_well->data;
 883         bool enabled = false;
 884         u32 mask;
 885         u32 state;
 886         u32 ctrl;
 887
 888         mask = PUNIT_PWRGT_MASK(power_well_id);
 889         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 890
 891         mutex_lock(&dev_priv->rps.hw_lock);
 892
 893         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 894         /*
 895          * We only ever set the power-on and power-gate states, anything
 896          * else is unexpected.
 897          */
 898         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 899                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 900         if (state == ctrl)
 901                 enabled = true;
 902
 903         /*
 904          * A transient state at this point would mean some unexpected party
 905          * is poking at the power controls too.
 906          */
 907         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 908         WARN_ON(ctrl != state);
 909
 910         mutex_unlock(&dev_priv->rps.hw_lock);
 911
 912         return enabled;
 913 }
 914
 915 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 916 {
 917         enum pipe pipe;
 918
 919         /*
 920          * Enable the CRI clock source so we can get at the
 921          * display and the reference clock for VGA
 922          * hotplug / manual detection. Supposedly DSI also
 923          * needs the ref clock up and running.
 924          *
 925          * CHV DPLL B/C have some issues if VGA mode is enabled.
 926          */
 927         for_each_pipe(dev_priv->dev, pipe) {
 928                 u32 val = I915_READ(DPLL(pipe));
 929
 930                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 931                 if (pipe != PIPE_A)
 932                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 933
 934                 I915_WRITE(DPLL(pipe), val);
 935         }
 936
 937         spin_lock_irq(&dev_priv->irq_lock);
 938         valleyview_enable_display_irqs(dev_priv);
 939         spin_unlock_irq(&dev_priv->irq_lock);
 940
 941         /*
 942          * During driver initialization/resume we can avoid restoring the
 943          * part of the HW/SW state that will be inited anyway explicitly.
 944          */
 945         if (dev_priv->power_domains.initializing)
 946                 return;
 947
 948         intel_hpd_init(dev_priv);
 949
 950         i915_redisable_vga_power_on(dev_priv->dev);
 951 }
 952
 953 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 954 {
 955         spin_lock_irq(&dev_priv->irq_lock);
 956         valleyview_disable_display_irqs(dev_priv);
 957         spin_unlock_irq(&dev_priv->irq_lock);
 958
 959         vlv_power_sequencer_reset(dev_priv);
 960 }
 961
 962 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 963                                           struct i915_power_well *power_well)
 964 {
 965         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 966
 967         vlv_set_power_well(dev_priv, power_well, true);
 968
 969         vlv_display_power_well_init(dev_priv);
 970 }
 971
 972 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 973                                            struct i915_power_well *power_well)
 974 {
 975         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 976
 977         vlv_display_power_well_deinit(dev_priv);
 978
 979         vlv_set_power_well(dev_priv, power_well, false);
 980 }
 981
 982 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 983                                            struct i915_power_well *power_well)
 984 {
 985         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 986
 987         /* since ref/cri clock was enabled */
 988         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 989
 990         vlv_set_power_well(dev_priv, power_well, true);
 991
 992         /*
 993          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 994          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 995          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
 996          *   b. The other bits such as sfr settings / modesel may all
 997          *      be set to 0.
 998          *
 999          * This should only be done on init and resume from S3 with
1000          * both PLLs disabled, or we risk losing DPIO and PLL
1001          * synchronization.
1002          */
1003         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1004 }
1005
1006 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1007                                             struct i915_power_well *power_well)
1008 {
1009         enum pipe pipe;
1010
1011         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1012
1013         for_each_pipe(dev_priv, pipe)
1014                 assert_pll_disabled(dev_priv, pipe);
1015
1016         /* Assert common reset */
1017         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1018
1019         vlv_set_power_well(dev_priv, power_well, false);
1020 }
1021
1022 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1023
1024 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1025                                                  int power_well_id)
1026 {
1027         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1028         int i;
1029
1030         for (i = 0; i < power_domains->power_well_count; i++) {
1031                 struct i915_power_well *power_well;
1032
1033                 power_well = &power_domains->power_wells[i];
1034                 if (power_well->data == power_well_id)
1035                         return power_well;
1036         }
1037
1038         return NULL;
1039 }
1040
1041 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1042
1043 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1044 {
1045         struct i915_power_well *cmn_bc =
1046                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1047         struct i915_power_well *cmn_d =
1048                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1049         u32 phy_control = dev_priv->chv_phy_control;
1050         u32 phy_status = 0;
1051         u32 phy_status_mask = 0xffffffff;
1052         u32 tmp;
1053
1054         /*
1055          * The BIOS can leave the PHY is some weird state
1056          * where it doesn't fully power down some parts.
1057          * Disable the asserts until the PHY has been fully
1058          * reset (ie. the power well has been disabled at
1059          * least once).
1060          */
1061         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1062                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1063                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1064                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1065                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1066                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1067                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1068
1069         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1070                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1071                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1072                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1073
1074         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1075                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1076
1077                 /* this assumes override is only used to enable lanes */
1078                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1079                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1080
1081                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1082                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1083
1084                 /* CL1 is on whenever anything is on in either channel */
1085                 if (BITS_SET(phy_control,
1086                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1087                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1088                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1089
1090                 /*
1091                  * The DPLLB check accounts for the pipe B + port A usage
1092                  * with CL2 powered up but all the lanes in the second channel
1093                  * powered down.
1094                  */
1095                 if (BITS_SET(phy_control,
1096                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1097                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1098                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1099
1100                 if (BITS_SET(phy_control,
1101                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1102                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1103                 if (BITS_SET(phy_control,
1104                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1105                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1106
1107                 if (BITS_SET(phy_control,
1108                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1109                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1110                 if (BITS_SET(phy_control,
1111                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1112                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1113         }
1114
1115         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1116                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1117
1118                 /* this assumes override is only used to enable lanes */
1119                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1120                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1121
1122                 if (BITS_SET(phy_control,
1123                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1124                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1125
1126                 if (BITS_SET(phy_control,
1127                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1128                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1129                 if (BITS_SET(phy_control,
1130                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1131                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1132         }
1133
1134         phy_status &= phy_status_mask;
1135
1136         /*
1137          * The PHY may be busy with some initial calibration and whatnot,
1138          * so the power state can take a while to actually change.
1139          */
1140         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1141                 WARN(phy_status != tmp,
1142                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1143                      tmp, phy_status, dev_priv->chv_phy_control);
1144 }
1145
1146 #undef BITS_SET
1147
1148 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1149                                            struct i915_power_well *power_well)
1150 {
1151         enum dpio_phy phy;
1152         enum pipe pipe;
1153         uint32_t tmp;
1154
1155         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1156                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1157
1158         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1159                 pipe = PIPE_A;
1160                 phy = DPIO_PHY0;
1161         } else {
1162                 pipe = PIPE_C;
1163                 phy = DPIO_PHY1;
1164         }
1165
1166         /* since ref/cri clock was enabled */
1167         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1168         vlv_set_power_well(dev_priv, power_well, true);
1169
1170         /* Poll for phypwrgood signal */
1171         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1172                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1173
1174         mutex_lock(&dev_priv->sb_lock);
1175
1176         /* Enable dynamic power down */
1177         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1178         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1179                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1180         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1181
1182         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1183                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1184                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1185                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1186         } else {
1187                 /*
1188                  * Force the non-existing CL2 off. BXT does this
1189                  * too, so maybe it saves some power even though
1190                  * CL2 doesn't exist?
1191                  */
1192                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1193                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1194                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1195         }
1196
1197         mutex_unlock(&dev_priv->sb_lock);
1198
1199         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1200         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1201
1202         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1203                       phy, dev_priv->chv_phy_control);
1204
1205         assert_chv_phy_status(dev_priv);
1206 }
1207
1208 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1209                                             struct i915_power_well *power_well)
1210 {
1211         enum dpio_phy phy;
1212
1213         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1214                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1215
1216         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1217                 phy = DPIO_PHY0;
1218                 assert_pll_disabled(dev_priv, PIPE_A);
1219                 assert_pll_disabled(dev_priv, PIPE_B);
1220         } else {
1221                 phy = DPIO_PHY1;
1222                 assert_pll_disabled(dev_priv, PIPE_C);
1223         }
1224
1225         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1226         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1227
1228         vlv_set_power_well(dev_priv, power_well, false);
1229
1230         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1231                       phy, dev_priv->chv_phy_control);
1232
1233         /* PHY is fully reset now, so we can enable the PHY state asserts */
1234         dev_priv->chv_phy_assert[phy] = true;
1235
1236         assert_chv_phy_status(dev_priv);
1237 }
1238
1239 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1240                                      enum dpio_channel ch, bool override, unsigned int mask)
1241 {
1242         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1243         u32 reg, val, expected, actual;
1244
1245         /*
1246          * The BIOS can leave the PHY is some weird state
1247          * where it doesn't fully power down some parts.
1248          * Disable the asserts until the PHY has been fully
1249          * reset (ie. the power well has been disabled at
1250          * least once).
1251          */
1252         if (!dev_priv->chv_phy_assert[phy])
1253                 return;
1254
1255         if (ch == DPIO_CH0)
1256                 reg = _CHV_CMN_DW0_CH0;
1257         else
1258                 reg = _CHV_CMN_DW6_CH1;
1259
1260         mutex_lock(&dev_priv->sb_lock);
1261         val = vlv_dpio_read(dev_priv, pipe, reg);
1262         mutex_unlock(&dev_priv->sb_lock);
1263
1264         /*
1265          * This assumes !override is only used when the port is disabled.
1266          * All lanes should power down even without the override when
1267          * the port is disabled.
1268          */
1269         if (!override || mask == 0xf) {
1270                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1271                 /*
1272                  * If CH1 common lane is not active anymore
1273                  * (eg. for pipe B DPLL) the entire channel will
1274                  * shut down, which causes the common lane registers
1275                  * to read as 0. That means we can't actually check
1276                  * the lane power down status bits, but as the entire
1277                  * register reads as 0 it's a good indication that the
1278                  * channel is indeed entirely powered down.
1279                  */
1280                 if (ch == DPIO_CH1 && val == 0)
1281                         expected = 0;
1282         } else if (mask != 0x0) {
1283                 expected = DPIO_ANYDL_POWERDOWN;
1284         } else {
1285                 expected = 0;
1286         }
1287
1288         if (ch == DPIO_CH0)
1289                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1290         else
1291                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1292         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1293
1294         WARN(actual != expected,
1295              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1296              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1297              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1298              reg, val);
1299 }
1300
1301 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1302                           enum dpio_channel ch, bool override)
1303 {
1304         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1305         bool was_override;
1306
1307         mutex_lock(&power_domains->lock);
1308
1309         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1310
1311         if (override == was_override)
1312                 goto out;
1313
1314         if (override)
1315                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1316         else
1317                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1318
1319         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1320
1321         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1322                       phy, ch, dev_priv->chv_phy_control);
1323
1324         assert_chv_phy_status(dev_priv);
1325
1326 out:
1327         mutex_unlock(&power_domains->lock);
1328
1329         return was_override;
1330 }
1331
1332 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1333                              bool override, unsigned int mask)
1334 {
1335         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1336         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1337         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1338         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1339
1340         mutex_lock(&power_domains->lock);
1341
1342         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1343         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1344
1345         if (override)
1346                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1347         else
1348                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1349
1350         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1351
1352         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1353                       phy, ch, mask, dev_priv->chv_phy_control);
1354
1355         assert_chv_phy_status(dev_priv);
1356
1357         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1358
1359         mutex_unlock(&power_domains->lock);
1360 }
1361
1362 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1363                                         struct i915_power_well *power_well)
1364 {
1365         enum pipe pipe = power_well->data;
1366         bool enabled;
1367         u32 state, ctrl;
1368
1369         mutex_lock(&dev_priv->rps.hw_lock);
1370
1371         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1372         /*
1373          * We only ever set the power-on and power-gate states, anything
1374          * else is unexpected.
1375          */
1376         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1377         enabled = state == DP_SSS_PWR_ON(pipe);
1378
1379         /*
1380          * A transient state at this point would mean some unexpected party
1381          * is poking at the power controls too.
1382          */
1383         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1384         WARN_ON(ctrl << 16 != state);
1385
1386         mutex_unlock(&dev_priv->rps.hw_lock);
1387
1388         return enabled;
1389 }
1390
1391 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1392                                     struct i915_power_well *power_well,
1393                                     bool enable)
1394 {
1395         enum pipe pipe = power_well->data;
1396         u32 state;
1397         u32 ctrl;
1398
1399         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1400
1401         mutex_lock(&dev_priv->rps.hw_lock);
1402
1403 #define COND \
1404         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1405
1406         if (COND)
1407                 goto out;
1408
1409         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1410         ctrl &= ~DP_SSC_MASK(pipe);
1411         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1412         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1413
1414         if (wait_for(COND, 100))
1415                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1416                           state,
1417                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1418
1419 #undef COND
1420
1421 out:
1422         mutex_unlock(&dev_priv->rps.hw_lock);
1423 }
1424
1425 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1426                                         struct i915_power_well *power_well)
1427 {
1428         WARN_ON_ONCE(power_well->data != PIPE_A);
1429
1430         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1431 }
1432
1433 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1434                                        struct i915_power_well *power_well)
1435 {
1436         WARN_ON_ONCE(power_well->data != PIPE_A);
1437
1438         chv_set_pipe_power_well(dev_priv, power_well, true);
1439
1440         vlv_display_power_well_init(dev_priv);
1441 }
1442
1443 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1444                                         struct i915_power_well *power_well)
1445 {
1446         WARN_ON_ONCE(power_well->data != PIPE_A);
1447
1448         vlv_display_power_well_deinit(dev_priv);
1449
1450         chv_set_pipe_power_well(dev_priv, power_well, false);
1451 }
1452
1453 static void
1454 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1455                                  enum intel_display_power_domain domain)
1456 {
1457         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1458         struct i915_power_well *power_well;
1459         int i;
1460
1461         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1462                 if (!power_well->count++)
1463                         intel_power_well_enable(dev_priv, power_well);
1464         }
1465
1466         power_domains->domain_use_count[domain]++;
1467 }
1468
1469 /**
1470  * intel_display_power_get - grab a power domain reference
1471  * @dev_priv: i915 device instance
1472  * @domain: power domain to reference
1473  *
1474  * This function grabs a power domain reference for @domain and ensures that the
1475  * power domain and all its parents are powered up. Therefore users should only
1476  * grab a reference to the innermost power domain they need.
1477  *
1478  * Any power domain reference obtained by this function must have a symmetric
1479  * call to intel_display_power_put() to release the reference again.
1480  */
1481 void intel_display_power_get(struct drm_i915_private *dev_priv,
1482                              enum intel_display_power_domain domain)
1483 {
1484         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1485
1486         intel_runtime_pm_get(dev_priv);
1487
1488         mutex_lock(&power_domains->lock);
1489
1490         __intel_display_power_get_domain(dev_priv, domain);
1491
1492         mutex_unlock(&power_domains->lock);
1493 }
1494
1495 /**
1496  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1497  * @dev_priv: i915 device instance
1498  * @domain: power domain to reference
1499  *
1500  * This function grabs a power domain reference for @domain and ensures that the
1501  * power domain and all its parents are powered up. Therefore users should only
1502  * grab a reference to the innermost power domain they need.
1503  *
1504  * Any power domain reference obtained by this function must have a symmetric
1505  * call to intel_display_power_put() to release the reference again.
1506  */
1507 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1508                                         enum intel_display_power_domain domain)
1509 {
1510         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1511         bool is_enabled;
1512
1513         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1514                 return false;
1515
1516         mutex_lock(&power_domains->lock);
1517
1518         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1519                 __intel_display_power_get_domain(dev_priv, domain);
1520                 is_enabled = true;
1521         } else {
1522                 is_enabled = false;
1523         }
1524
1525         mutex_unlock(&power_domains->lock);
1526
1527         if (!is_enabled)
1528                 intel_runtime_pm_put(dev_priv);
1529
1530         return is_enabled;
1531 }
1532
1533 /**
1534  * intel_display_power_put - release a power domain reference
1535  * @dev_priv: i915 device instance
1536  * @domain: power domain to reference
1537  *
1538  * This function drops the power domain reference obtained by
1539  * intel_display_power_get() and might power down the corresponding hardware
1540  * block right away if this is the last reference.
1541  */
1542 void intel_display_power_put(struct drm_i915_private *dev_priv,
1543                              enum intel_display_power_domain domain)
1544 {
1545         struct i915_power_domains *power_domains;
1546         struct i915_power_well *power_well;
1547         int i;
1548
1549         power_domains = &dev_priv->power_domains;
1550
1551         mutex_lock(&power_domains->lock);
1552
1553         WARN(!power_domains->domain_use_count[domain],
1554              "Use count on domain %s is already zero\n",
1555              intel_display_power_domain_str(domain));
1556         power_domains->domain_use_count[domain]--;
1557
1558         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1559                 WARN(!power_well->count,
1560                      "Use count on power well %s is already zero",
1561                      power_well->name);
1562
1563                 if (!--power_well->count)
1564                         intel_power_well_disable(dev_priv, power_well);
1565         }
1566
1567         mutex_unlock(&power_domains->lock);
1568
1569         intel_runtime_pm_put(dev_priv);
1570 }
1571
1572 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1573         BIT(POWER_DOMAIN_PIPE_A) |                      \
1574         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1575         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
1576         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1577         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1578         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1579         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1580         BIT(POWER_DOMAIN_PLLS) |                        \
1581         BIT(POWER_DOMAIN_AUX_A) |                       \
1582         BIT(POWER_DOMAIN_AUX_B) |                       \
1583         BIT(POWER_DOMAIN_AUX_C) |                       \
1584         BIT(POWER_DOMAIN_AUX_D) |                       \
1585         BIT(POWER_DOMAIN_GMBUS) |                       \
1586         BIT(POWER_DOMAIN_INIT))
1587 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1588         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1589         BIT(POWER_DOMAIN_INIT))
1590
1591 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1592         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1593         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1594 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1595         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1596         BIT(POWER_DOMAIN_INIT))
1597
1598 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1599 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1600
1601 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1602         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1603         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1604         BIT(POWER_DOMAIN_PORT_CRT) |            \
1605         BIT(POWER_DOMAIN_AUX_B) |               \
1606         BIT(POWER_DOMAIN_AUX_C) |               \
1607         BIT(POWER_DOMAIN_INIT))
1608
1609 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1610         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1611         BIT(POWER_DOMAIN_AUX_B) |               \
1612         BIT(POWER_DOMAIN_INIT))
1613
1614 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1615         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1616         BIT(POWER_DOMAIN_AUX_B) |               \
1617         BIT(POWER_DOMAIN_INIT))
1618
1619 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1620         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1621         BIT(POWER_DOMAIN_AUX_C) |               \
1622         BIT(POWER_DOMAIN_INIT))
1623
1624 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1625         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1626         BIT(POWER_DOMAIN_AUX_C) |               \
1627         BIT(POWER_DOMAIN_INIT))
1628
1629 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1630         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1631         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1632         BIT(POWER_DOMAIN_AUX_B) |               \
1633         BIT(POWER_DOMAIN_AUX_C) |               \
1634         BIT(POWER_DOMAIN_INIT))
1635
1636 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1637         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1638         BIT(POWER_DOMAIN_AUX_D) |               \
1639         BIT(POWER_DOMAIN_INIT))
1640
1641 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1642         .sync_hw = i9xx_always_on_power_well_noop,
1643         .enable = i9xx_always_on_power_well_noop,
1644         .disable = i9xx_always_on_power_well_noop,
1645         .is_enabled = i9xx_always_on_power_well_enabled,
1646 };
1647
1648 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1649         .sync_hw = chv_pipe_power_well_sync_hw,
1650         .enable = chv_pipe_power_well_enable,
1651         .disable = chv_pipe_power_well_disable,
1652         .is_enabled = chv_pipe_power_well_enabled,
1653 };
1654
1655 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1656         .sync_hw = vlv_power_well_sync_hw,
1657         .enable = chv_dpio_cmn_power_well_enable,
1658         .disable = chv_dpio_cmn_power_well_disable,
1659         .is_enabled = vlv_power_well_enabled,
1660 };
1661
1662 static struct i915_power_well i9xx_always_on_power_well[] = {
1663         {
1664                 .name = "always-on",
1665                 .always_on = 1,
1666                 .domains = POWER_DOMAIN_MASK,
1667                 .ops = &i9xx_always_on_power_well_ops,
1668         },
1669 };
1670
1671 static const struct i915_power_well_ops hsw_power_well_ops = {
1672         .sync_hw = hsw_power_well_sync_hw,
1673         .enable = hsw_power_well_enable,
1674         .disable = hsw_power_well_disable,
1675         .is_enabled = hsw_power_well_enabled,
1676 };
1677
1678 static const struct i915_power_well_ops skl_power_well_ops = {
1679         .sync_hw = skl_power_well_sync_hw,
1680         .enable = skl_power_well_enable,
1681         .disable = skl_power_well_disable,
1682         .is_enabled = skl_power_well_enabled,
1683 };
1684
1685 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1686         .sync_hw = gen9_dc_off_power_well_sync_hw,
1687         .enable = gen9_dc_off_power_well_enable,
1688         .disable = gen9_dc_off_power_well_disable,
1689         .is_enabled = gen9_dc_off_power_well_enabled,
1690 };
1691
1692 static struct i915_power_well hsw_power_wells[] = {
1693         {
1694                 .name = "always-on",
1695                 .always_on = 1,
1696                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1697                 .ops = &i9xx_always_on_power_well_ops,
1698         },
1699         {
1700                 .name = "display",
1701                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1702                 .ops = &hsw_power_well_ops,
1703         },
1704 };
1705
1706 static struct i915_power_well bdw_power_wells[] = {
1707         {
1708                 .name = "always-on",
1709                 .always_on = 1,
1710                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1711                 .ops = &i9xx_always_on_power_well_ops,
1712         },
1713         {
1714                 .name = "display",
1715                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1716                 .ops = &hsw_power_well_ops,
1717         },
1718 };
1719
1720 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1721         .sync_hw = vlv_power_well_sync_hw,
1722         .enable = vlv_display_power_well_enable,
1723         .disable = vlv_display_power_well_disable,
1724         .is_enabled = vlv_power_well_enabled,
1725 };
1726
1727 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1728         .sync_hw = vlv_power_well_sync_hw,
1729         .enable = vlv_dpio_cmn_power_well_enable,
1730         .disable = vlv_dpio_cmn_power_well_disable,
1731         .is_enabled = vlv_power_well_enabled,
1732 };
1733
1734 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1735         .sync_hw = vlv_power_well_sync_hw,
1736         .enable = vlv_power_well_enable,
1737         .disable = vlv_power_well_disable,
1738         .is_enabled = vlv_power_well_enabled,
1739 };
1740
1741 static struct i915_power_well vlv_power_wells[] = {
1742         {
1743                 .name = "always-on",
1744                 .always_on = 1,
1745                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1746                 .ops = &i9xx_always_on_power_well_ops,
1747                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1748         },
1749         {
1750                 .name = "display",
1751                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1752                 .data = PUNIT_POWER_WELL_DISP2D,
1753                 .ops = &vlv_display_power_well_ops,
1754         },
1755         {
1756                 .name = "dpio-tx-b-01",
1757                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1758                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1759                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1760                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1761                 .ops = &vlv_dpio_power_well_ops,
1762                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1763         },
1764         {
1765                 .name = "dpio-tx-b-23",
1766                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1767                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1768                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1769                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1770                 .ops = &vlv_dpio_power_well_ops,
1771                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1772         },
1773         {
1774                 .name = "dpio-tx-c-01",
1775                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1776                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1777                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1778                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1779                 .ops = &vlv_dpio_power_well_ops,
1780                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1781         },
1782         {
1783                 .name = "dpio-tx-c-23",
1784                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1785                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1786                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1787                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1788                 .ops = &vlv_dpio_power_well_ops,
1789                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1790         },
1791         {
1792                 .name = "dpio-common",
1793                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1794                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1795                 .ops = &vlv_dpio_cmn_power_well_ops,
1796         },
1797 };
1798
1799 static struct i915_power_well chv_power_wells[] = {
1800         {
1801                 .name = "always-on",
1802                 .always_on = 1,
1803                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1804                 .ops = &i9xx_always_on_power_well_ops,
1805         },
1806         {
1807                 .name = "display",
1808                 /*
1809                  * Pipe A power well is the new disp2d well. Pipe B and C
1810                  * power wells don't actually exist. Pipe A power well is
1811                  * required for any pipe to work.
1812                  */
1813                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1814                 .data = PIPE_A,
1815                 .ops = &chv_pipe_power_well_ops,
1816         },
1817         {
1818                 .name = "dpio-common-bc",
1819                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1820                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1821                 .ops = &chv_dpio_cmn_power_well_ops,
1822         },
1823         {
1824                 .name = "dpio-common-d",
1825                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1826                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1827                 .ops = &chv_dpio_cmn_power_well_ops,
1828         },
1829 };
1830
1831 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1832                                     int power_well_id)
1833 {
1834         struct i915_power_well *power_well;
1835         bool ret;
1836
1837         power_well = lookup_power_well(dev_priv, power_well_id);
1838         ret = power_well->ops->is_enabled(dev_priv, power_well);
1839
1840         return ret;
1841 }
1842
1843 static struct i915_power_well skl_power_wells[] = {
1844         {
1845                 .name = "always-on",
1846                 .always_on = 1,
1847                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1848                 .ops = &i9xx_always_on_power_well_ops,
1849                 .data = SKL_DISP_PW_ALWAYS_ON,
1850         },
1851         {
1852                 .name = "power well 1",
1853                 /* Handled by the DMC firmware */
1854                 .domains = 0,
1855                 .ops = &skl_power_well_ops,
1856                 .data = SKL_DISP_PW_1,
1857         },
1858         {
1859                 .name = "MISC IO power well",
1860                 /* Handled by the DMC firmware */
1861                 .domains = 0,
1862                 .ops = &skl_power_well_ops,
1863                 .data = SKL_DISP_PW_MISC_IO,
1864         },
1865         {
1866                 .name = "DC off",
1867                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1868                 .ops = &gen9_dc_off_power_well_ops,
1869                 .data = SKL_DISP_PW_DC_OFF,
1870         },
1871         {
1872                 .name = "power well 2",
1873                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1874                 .ops = &skl_power_well_ops,
1875                 .data = SKL_DISP_PW_2,
1876         },
1877         {
1878                 .name = "DDI A/E power well",
1879                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1880                 .ops = &skl_power_well_ops,
1881                 .data = SKL_DISP_PW_DDI_A_E,
1882         },
1883         {
1884                 .name = "DDI B power well",
1885                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1886                 .ops = &skl_power_well_ops,
1887                 .data = SKL_DISP_PW_DDI_B,
1888         },
1889         {
1890                 .name = "DDI C power well",
1891                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1892                 .ops = &skl_power_well_ops,
1893                 .data = SKL_DISP_PW_DDI_C,
1894         },
1895         {
1896                 .name = "DDI D power well",
1897                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1898                 .ops = &skl_power_well_ops,
1899                 .data = SKL_DISP_PW_DDI_D,
1900         },
1901 };
1902
1903 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
1904 {
1905         struct i915_power_well *well;
1906
1907         if (!IS_SKYLAKE(dev_priv))
1908                 return;
1909
1910         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1911         intel_power_well_enable(dev_priv, well);
1912
1913         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1914         intel_power_well_enable(dev_priv, well);
1915 }
1916
1917 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
1918 {
1919         struct i915_power_well *well;
1920
1921         if (!IS_SKYLAKE(dev_priv))
1922                 return;
1923
1924         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1925         intel_power_well_disable(dev_priv, well);
1926
1927         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1928         intel_power_well_disable(dev_priv, well);
1929 }
1930
1931 static struct i915_power_well bxt_power_wells[] = {
1932         {
1933                 .name = "always-on",
1934                 .always_on = 1,
1935                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1936                 .ops = &i9xx_always_on_power_well_ops,
1937         },
1938         {
1939                 .name = "power well 1",
1940                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1941                 .ops = &skl_power_well_ops,
1942                 .data = SKL_DISP_PW_1,
1943         },
1944         {
1945                 .name = "DC off",
1946                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1947                 .ops = &gen9_dc_off_power_well_ops,
1948                 .data = SKL_DISP_PW_DC_OFF,
1949         },
1950         {
1951                 .name = "power well 2",
1952                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1953                 .ops = &skl_power_well_ops,
1954                 .data = SKL_DISP_PW_2,
1955         },
1956 };
1957
1958 static int
1959 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
1960                                    int disable_power_well)
1961 {
1962         if (disable_power_well >= 0)
1963                 return !!disable_power_well;
1964
1965         if (IS_BROXTON(dev_priv)) {
1966                 DRM_DEBUG_KMS("Disabling display power well support\n");
1967                 return 0;
1968         }
1969
1970         return 1;
1971 }
1972
1973 #define set_power_wells(power_domains, __power_wells) ({                \
1974         (power_domains)->power_wells = (__power_wells);                 \
1975         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
1976 })
1977
1978 /**
1979  * intel_power_domains_init - initializes the power domain structures
1980  * @dev_priv: i915 device instance
1981  *
1982  * Initializes the power domain structures for @dev_priv depending upon the
1983  * supported platform.
1984  */
1985 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1986 {
1987         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1988
1989         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
1990                                                      i915.disable_power_well);
1991
1992         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
1993
1994         mutex_init(&power_domains->lock);
1995
1996         /*
1997          * The enabling order will be from lower to higher indexed wells,
1998          * the disabling order is reversed.
1999          */
2000         if (IS_HASWELL(dev_priv->dev)) {
2001                 set_power_wells(power_domains, hsw_power_wells);
2002         } else if (IS_BROADWELL(dev_priv->dev)) {
2003                 set_power_wells(power_domains, bdw_power_wells);
2004         } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
2005                 set_power_wells(power_domains, skl_power_wells);
2006         } else if (IS_BROXTON(dev_priv->dev)) {
2007                 set_power_wells(power_domains, bxt_power_wells);
2008         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
2009                 set_power_wells(power_domains, chv_power_wells);
2010         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
2011                 set_power_wells(power_domains, vlv_power_wells);
2012         } else {
2013                 set_power_wells(power_domains, i9xx_always_on_power_well);
2014         }
2015
2016         return 0;
2017 }
2018
2019 /**
2020  * intel_power_domains_fini - finalizes the power domain structures
2021  * @dev_priv: i915 device instance
2022  *
2023  * Finalizes the power domain structures for @dev_priv depending upon the
2024  * supported platform. This function also disables runtime pm and ensures that
2025  * the device stays powered up so that the driver can be reloaded.
2026  */
2027 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2028 {
2029         struct device *device = &dev_priv->dev->pdev->dev;
2030
2031         /*
2032          * The i915.ko module is still not prepared to be loaded when
2033          * the power well is not enabled, so just enable it in case
2034          * we're going to unload/reload.
2035          * The following also reacquires the RPM reference the core passed
2036          * to the driver during loading, which is dropped in
2037          * intel_runtime_pm_enable(). We have to hand back the control of the
2038          * device to the core with this reference held.
2039          */
2040         intel_display_set_init_power(dev_priv, true);
2041
2042         /* Remove the refcount we took to keep power well support disabled. */
2043         if (!i915.disable_power_well)
2044                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2045
2046         /*
2047          * Remove the refcount we took in intel_runtime_pm_enable() in case
2048          * the platform doesn't support runtime PM.
2049          */
2050         if (!HAS_RUNTIME_PM(dev_priv))
2051                 pm_runtime_put(device);
2052 }
2053
2054 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2055 {
2056         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2057         struct i915_power_well *power_well;
2058         int i;
2059
2060         mutex_lock(&power_domains->lock);
2061         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2062                 power_well->ops->sync_hw(dev_priv, power_well);
2063                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2064                                                                      power_well);
2065         }
2066         mutex_unlock(&power_domains->lock);
2067 }
2068
2069 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2070                                   bool resume)
2071 {
2072         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2073         uint32_t val;
2074
2075         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2076
2077         /* enable PCH reset handshake */
2078         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2079         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2080
2081         /* enable PG1 and Misc I/O */
2082         mutex_lock(&power_domains->lock);
2083         skl_pw1_misc_io_init(dev_priv);
2084         mutex_unlock(&power_domains->lock);
2085
2086         if (!resume)
2087                 return;
2088
2089         skl_init_cdclk(dev_priv);
2090
2091         if (dev_priv->csr.dmc_payload)
2092                 intel_csr_load_program(dev_priv);
2093 }
2094
2095 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2096 {
2097         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2098
2099         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2100
2101         skl_uninit_cdclk(dev_priv);
2102
2103         /* The spec doesn't call for removing the reset handshake flag */
2104         /* disable PG1 and Misc I/O */
2105         mutex_lock(&power_domains->lock);
2106         skl_pw1_misc_io_fini(dev_priv);
2107         mutex_unlock(&power_domains->lock);
2108 }
2109
2110 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2111 {
2112         struct i915_power_well *cmn_bc =
2113                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2114         struct i915_power_well *cmn_d =
2115                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2116
2117         /*
2118          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2119          * workaround never ever read DISPLAY_PHY_CONTROL, and
2120          * instead maintain a shadow copy ourselves. Use the actual
2121          * power well state and lane status to reconstruct the
2122          * expected initial value.
2123          */
2124         dev_priv->chv_phy_control =
2125                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2126                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2127                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2128                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2129                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2130
2131         /*
2132          * If all lanes are disabled we leave the override disabled
2133          * with all power down bits cleared to match the state we
2134          * would use after disabling the port. Otherwise enable the
2135          * override and set the lane powerdown bits accding to the
2136          * current lane status.
2137          */
2138         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2139                 uint32_t status = I915_READ(DPLL(PIPE_A));
2140                 unsigned int mask;
2141
2142                 mask = status & DPLL_PORTB_READY_MASK;
2143                 if (mask == 0xf)
2144                         mask = 0x0;
2145                 else
2146                         dev_priv->chv_phy_control |=
2147                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2148
2149                 dev_priv->chv_phy_control |=
2150                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2151
2152                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2153                 if (mask == 0xf)
2154                         mask = 0x0;
2155                 else
2156                         dev_priv->chv_phy_control |=
2157                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2158
2159                 dev_priv->chv_phy_control |=
2160                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2161
2162                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2163
2164                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2165         } else {
2166                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2167         }
2168
2169         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2170                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2171                 unsigned int mask;
2172
2173                 mask = status & DPLL_PORTD_READY_MASK;
2174
2175                 if (mask == 0xf)
2176                         mask = 0x0;
2177                 else
2178                         dev_priv->chv_phy_control |=
2179                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2180
2181                 dev_priv->chv_phy_control |=
2182                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2183
2184                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2185
2186                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2187         } else {
2188                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2189         }
2190
2191         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2192
2193         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2194                       dev_priv->chv_phy_control);
2195 }
2196
2197 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2198 {
2199         struct i915_power_well *cmn =
2200                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2201         struct i915_power_well *disp2d =
2202                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2203
2204         /* If the display might be already active skip this */
2205         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2206             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2207             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2208                 return;
2209
2210         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2211
2212         /* cmnlane needs DPLL registers */
2213         disp2d->ops->enable(dev_priv, disp2d);
2214
2215         /*
2216          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2217          * Need to assert and de-assert PHY SB reset by gating the
2218          * common lane power, then un-gating it.
2219          * Simply ungating isn't enough to reset the PHY enough to get
2220          * ports and lanes running.
2221          */
2222         cmn->ops->disable(dev_priv, cmn);
2223 }
2224
2225 /**
2226  * intel_power_domains_init_hw - initialize hardware power domain state
2227  * @dev_priv: i915 device instance
2228  *
2229  * This function initializes the hardware power domain state and enables all
2230  * power domains using intel_display_set_init_power().
2231  */
2232 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2233 {
2234         struct drm_device *dev = dev_priv->dev;
2235         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2236
2237         power_domains->initializing = true;
2238
2239         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2240                 skl_display_core_init(dev_priv, resume);
2241         } else if (IS_CHERRYVIEW(dev)) {
2242                 mutex_lock(&power_domains->lock);
2243                 chv_phy_control_init(dev_priv);
2244                 mutex_unlock(&power_domains->lock);
2245         } else if (IS_VALLEYVIEW(dev)) {
2246                 mutex_lock(&power_domains->lock);
2247                 vlv_cmnlane_wa(dev_priv);
2248                 mutex_unlock(&power_domains->lock);
2249         }
2250
2251         /* For now, we need the power well to be always enabled. */
2252         intel_display_set_init_power(dev_priv, true);
2253         /* Disable power support if the user asked so. */
2254         if (!i915.disable_power_well)
2255                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2256         intel_power_domains_sync_hw(dev_priv);
2257         power_domains->initializing = false;
2258 }
2259
2260 /**
2261  * intel_power_domains_suspend - suspend power domain state
2262  * @dev_priv: i915 device instance
2263  *
2264  * This function prepares the hardware power domain state before entering
2265  * system suspend. It must be paired with intel_power_domains_init_hw().
2266  */
2267 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2268 {
2269         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2270                 skl_display_core_uninit(dev_priv);
2271
2272         /*
2273          * Even if power well support was disabled we still want to disable
2274          * power wells while we are system suspended.
2275          */
2276         if (!i915.disable_power_well)
2277                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2278 }
2279
2280 /**
2281  * intel_runtime_pm_get - grab a runtime pm reference
2282  * @dev_priv: i915 device instance
2283  *
2284  * This function grabs a device-level runtime pm reference (mostly used for GEM
2285  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2286  *
2287  * Any runtime pm reference obtained by this function must have a symmetric
2288  * call to intel_runtime_pm_put() to release the reference again.
2289  */
2290 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2291 {
2292         struct drm_device *dev = dev_priv->dev;
2293         struct device *device = &dev->pdev->dev;
2294
2295         pm_runtime_get_sync(device);
2296
2297         atomic_inc(&dev_priv->pm.wakeref_count);
2298         assert_rpm_wakelock_held(dev_priv);
2299 }
2300
2301 /**
2302  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2303  * @dev_priv: i915 device instance
2304  *
2305  * This function grabs a device-level runtime pm reference if the device is
2306  * already in use and ensures that it is powered up.
2307  *
2308  * Any runtime pm reference obtained by this function must have a symmetric
2309  * call to intel_runtime_pm_put() to release the reference again.
2310  */
2311 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2312 {
2313         struct drm_device *dev = dev_priv->dev;
2314         struct device *device = &dev->pdev->dev;
2315         int ret;
2316
2317         if (!IS_ENABLED(CONFIG_PM))
2318                 return true;
2319
2320         ret = pm_runtime_get_if_in_use(device);
2321
2322         /*
2323          * In cases runtime PM is disabled by the RPM core and we get an
2324          * -EINVAL return value we are not supposed to call this function,
2325          * since the power state is undefined. This applies atm to the
2326          * late/early system suspend/resume handlers.
2327          */
2328         WARN_ON_ONCE(ret < 0);
2329         if (ret <= 0)
2330                 return false;
2331
2332         atomic_inc(&dev_priv->pm.wakeref_count);
2333         assert_rpm_wakelock_held(dev_priv);
2334
2335         return true;
2336 }
2337
2338 /**
2339  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2340  * @dev_priv: i915 device instance
2341  *
2342  * This function grabs a device-level runtime pm reference (mostly used for GEM
2343  * code to ensure the GTT or GT is on).
2344  *
2345  * It will _not_ power up the device but instead only check that it's powered
2346  * on.  Therefore it is only valid to call this functions from contexts where
2347  * the device is known to be powered up and where trying to power it up would
2348  * result in hilarity and deadlocks. That pretty much means only the system
2349  * suspend/resume code where this is used to grab runtime pm references for
2350  * delayed setup down in work items.
2351  *
2352  * Any runtime pm reference obtained by this function must have a symmetric
2353  * call to intel_runtime_pm_put() to release the reference again.
2354  */
2355 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2356 {
2357         struct drm_device *dev = dev_priv->dev;
2358         struct device *device = &dev->pdev->dev;
2359
2360         assert_rpm_wakelock_held(dev_priv);
2361         pm_runtime_get_noresume(device);
2362
2363         atomic_inc(&dev_priv->pm.wakeref_count);
2364 }
2365
2366 /**
2367  * intel_runtime_pm_put - release a runtime pm reference
2368  * @dev_priv: i915 device instance
2369  *
2370  * This function drops the device-level runtime pm reference obtained by
2371  * intel_runtime_pm_get() and might power down the corresponding
2372  * hardware block right away if this is the last reference.
2373  */
2374 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2375 {
2376         struct drm_device *dev = dev_priv->dev;
2377         struct device *device = &dev->pdev->dev;
2378
2379         assert_rpm_wakelock_held(dev_priv);
2380         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2381                 atomic_inc(&dev_priv->pm.atomic_seq);
2382
2383         pm_runtime_mark_last_busy(device);
2384         pm_runtime_put_autosuspend(device);
2385 }
2386
2387 /**
2388  * intel_runtime_pm_enable - enable runtime pm
2389  * @dev_priv: i915 device instance
2390  *
2391  * This function enables runtime pm at the end of the driver load sequence.
2392  *
2393  * Note that this function does currently not enable runtime pm for the
2394  * subordinate display power domains. That is only done on the first modeset
2395  * using intel_display_set_init_power().
2396  */
2397 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2398 {
2399         struct drm_device *dev = dev_priv->dev;
2400         struct device *device = &dev->pdev->dev;
2401
2402         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2403         pm_runtime_mark_last_busy(device);
2404
2405         /*
2406          * Take a permanent reference to disable the RPM functionality and drop
2407          * it only when unloading the driver. Use the low level get/put helpers,
2408          * so the driver's own RPM reference tracking asserts also work on
2409          * platforms without RPM support.
2410          */
2411         if (!HAS_RUNTIME_PM(dev)) {
2412                 pm_runtime_dont_use_autosuspend(device);
2413                 pm_runtime_get_sync(device);
2414         } else {
2415                 pm_runtime_use_autosuspend(device);
2416         }
2417
2418         /*
2419          * The core calls the driver load handler with an RPM reference held.
2420          * We drop that here and will reacquire it during unloading in
2421          * intel_power_domains_fini().
2422          */
2423         pm_runtime_put_autosuspend(device);
2424 }
2425