1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot *slot)
66 return kobject_name(&slot->kobj);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 /* For PCI devices, the region numbers are assigned this way: */
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* Device-specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* Resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* Total resources associated with a PCI device */
100 /* Preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
115 enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
123 /* The number of legacy PCI INTx interrupts */
124 #define PCI_NUM_INTX 4
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
130 typedef int __bitwise pci_power_t;
132 #define PCI_D0 ((pci_power_t __force) 0)
133 #define PCI_D1 ((pci_power_t __force) 1)
134 #define PCI_D2 ((pci_power_t __force) 2)
135 #define PCI_D3hot ((pci_power_t __force) 3)
136 #define PCI_D3cold ((pci_power_t __force) 4)
137 #define PCI_UNKNOWN ((pci_power_t __force) 5)
138 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
140 /* Remember to update this when the list above changes! */
141 extern const char *pci_power_names[];
143 static inline const char *pci_power_name(pci_power_t state)
145 return pci_power_names[1 + (__force int) state];
148 #define PCI_PM_D2_DELAY 200
149 #define PCI_PM_D3_WAIT 10
150 #define PCI_PM_D3COLD_WAIT 100
151 #define PCI_PM_BUS_WAIT 50
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
158 typedef unsigned int __bitwise pci_channel_state_t;
160 enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
171 typedef unsigned int __bitwise pcie_reset_state_t;
173 enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
177 /* Use #PERST to reset PCIe device */
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
180 /* Use PCIe Hot Reset to reset device */
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
184 typedef unsigned short __bitwise pci_dev_flags_t;
186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188 /* Device configuration is irrevocably lost if disabled into D3 */
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190 /* Provide indication device is assigned by a Virtual Machine Manager */
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202 /* A non-root bridge where translation occurs, stop alias search here */
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206 /* Don't use Relaxed Ordering for TLPs directed at this device */
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
210 enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
215 typedef unsigned short __bitwise pci_bus_flags_t;
217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
222 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
223 enum pcie_link_width {
224 PCIE_LNK_WIDTH_RESRV = 0x00,
232 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
235 /* Based on the PCI Hotplug Spec, but some values are made up by us */
237 PCI_SPEED_33MHz = 0x00,
238 PCI_SPEED_66MHz = 0x01,
239 PCI_SPEED_66MHz_PCIX = 0x02,
240 PCI_SPEED_100MHz_PCIX = 0x03,
241 PCI_SPEED_133MHz_PCIX = 0x04,
242 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
243 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
244 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
245 PCI_SPEED_66MHz_PCIX_266 = 0x09,
246 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
247 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
253 PCI_SPEED_66MHz_PCIX_533 = 0x11,
254 PCI_SPEED_100MHz_PCIX_533 = 0x12,
255 PCI_SPEED_133MHz_PCIX_533 = 0x13,
256 PCIE_SPEED_2_5GT = 0x14,
257 PCIE_SPEED_5_0GT = 0x15,
258 PCIE_SPEED_8_0GT = 0x16,
259 PCI_SPEED_UNKNOWN = 0xff,
262 struct pci_cap_saved_data {
269 struct pci_cap_saved_state {
270 struct hlist_node next;
271 struct pci_cap_saved_data cap;
275 struct pcie_link_state;
280 /* The pci_dev structure describes PCI devices */
282 struct list_head bus_list; /* Node in per-bus list */
283 struct pci_bus *bus; /* Bus this device is on */
284 struct pci_bus *subordinate; /* Bus this device bridges to */
286 void *sysdata; /* Hook for sys-specific extension */
287 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
288 struct pci_slot *slot; /* Physical slot this device is in */
290 unsigned int devfn; /* Encoded device & function index */
291 unsigned short vendor;
292 unsigned short device;
293 unsigned short subsystem_vendor;
294 unsigned short subsystem_device;
295 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
296 u8 revision; /* PCI revision, low byte of class word */
297 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
298 #ifdef CONFIG_PCIEAER
299 u16 aer_cap; /* AER capability offset */
301 u8 pcie_cap; /* PCIe capability offset */
302 u8 msi_cap; /* MSI capability offset */
303 u8 msix_cap; /* MSI-X capability offset */
304 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
305 u8 rom_base_reg; /* Config register controlling ROM */
306 u8 pin; /* Interrupt pin this device uses */
307 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
308 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
310 struct pci_driver *driver; /* Driver bound to this device */
311 u64 dma_mask; /* Mask of the bits of bus address this
312 device implements. Normally this is
313 0xffffffff. You only need to change
314 this if your device has broken DMA
315 or supports 64-bit transfers. */
317 struct device_dma_parameters dma_parms;
319 pci_power_t current_state; /* Current operating state. In ACPI,
320 this is D0-D3, D0 being fully
321 functional, and D3 being off. */
322 u8 pm_cap; /* PM capability offset */
323 unsigned int pme_support:5; /* Bitmask of states from which PME#
325 unsigned int pme_poll:1; /* Poll device's PME status bit */
326 unsigned int d1_support:1; /* Low power state D1 is supported */
327 unsigned int d2_support:1; /* Low power state D2 is supported */
328 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
329 unsigned int no_d3cold:1; /* D3cold is forbidden */
330 unsigned int bridge_d3:1; /* Allow D3 for bridge */
331 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
332 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
333 decoding during BAR sizing */
334 unsigned int wakeup_prepared:1;
335 unsigned int runtime_d3cold:1; /* Whether go through runtime
336 D3cold, not set for devices
337 powered on/off by the
338 corresponding bridge */
339 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
340 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
341 controlled exclusively by
343 unsigned int d3_delay; /* D3->D0 transition time in ms */
344 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
346 #ifdef CONFIG_PCIEASPM
347 struct pcie_link_state *link_state; /* ASPM link state */
348 unsigned int ltr_path:1; /* Latency Tolerance Reporting
349 supported from root to here */
352 pci_channel_state_t error_state; /* Current connectivity state */
353 struct device dev; /* Generic device interface */
355 int cfg_size; /* Size of config space */
358 * Instead of touching interrupt line and base address registers
359 * directly, use the values stored here. They might be different!
362 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
364 bool match_driver; /* Skip attaching driver */
366 unsigned int transparent:1; /* Subtractive decode bridge */
367 unsigned int multifunction:1; /* Multi-function device */
369 unsigned int is_added:1;
370 unsigned int is_busmaster:1; /* Is busmaster */
371 unsigned int no_msi:1; /* May not use MSI */
372 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
373 unsigned int block_cfg_access:1; /* Config space access blocked */
374 unsigned int broken_parity_status:1; /* Generates false positive parity */
375 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
376 unsigned int msi_enabled:1;
377 unsigned int msix_enabled:1;
378 unsigned int ari_enabled:1; /* ARI forwarding */
379 unsigned int ats_enabled:1; /* Address Translation Svc */
380 unsigned int pasid_enabled:1; /* Process Address Space ID */
381 unsigned int pri_enabled:1; /* Page Request Interface */
382 unsigned int is_managed:1;
383 unsigned int needs_freset:1; /* Requires fundamental reset */
384 unsigned int state_saved:1;
385 unsigned int is_physfn:1;
386 unsigned int is_virtfn:1;
387 unsigned int reset_fn:1;
388 unsigned int is_hotplug_bridge:1;
389 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
390 unsigned int __aer_firmware_first_valid:1;
391 unsigned int __aer_firmware_first:1;
392 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
393 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
394 unsigned int irq_managed:1;
395 unsigned int has_secondary_link:1;
396 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
397 unsigned int is_probed:1; /* Device probing in progress */
398 pci_dev_flags_t dev_flags;
399 atomic_t enable_cnt; /* pci_enable_device has been called */
401 u32 saved_config_space[16]; /* Config space saved at suspend time */
402 struct hlist_head saved_cap_space;
403 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
404 int rom_attr_enabled; /* Display of ROM attribute enabled? */
405 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
406 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
408 #ifdef CONFIG_PCIE_PTM
409 unsigned int ptm_root:1;
410 unsigned int ptm_enabled:1;
413 #ifdef CONFIG_PCI_MSI
414 const struct attribute_group **msi_irq_groups;
417 #ifdef CONFIG_PCI_ATS
419 struct pci_sriov *sriov; /* PF: SR-IOV info */
420 struct pci_dev *physfn; /* VF: related PF */
422 u16 ats_cap; /* ATS Capability offset */
423 u8 ats_stu; /* ATS Smallest Translation Unit */
424 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
426 #ifdef CONFIG_PCI_PRI
427 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
429 #ifdef CONFIG_PCI_PASID
432 phys_addr_t rom; /* Physical address if not from BAR */
433 size_t romlen; /* Length if not from BAR */
434 char *driver_override; /* Driver name to force a match */
436 unsigned long priv_flags; /* Private flags for the PCI driver */
439 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
441 #ifdef CONFIG_PCI_IOV
448 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
450 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
451 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
453 static inline int pci_channel_offline(struct pci_dev *pdev)
455 return (pdev->error_state != pci_channel_io_normal);
458 struct pci_host_bridge {
460 struct pci_bus *bus; /* Root bus */
464 struct list_head windows; /* resource_entry */
465 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
466 int (*map_irq)(const struct pci_dev *, u8, u8);
467 void (*release_fn)(struct pci_host_bridge *);
469 struct msi_controller *msi;
470 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
471 unsigned int no_ext_tags:1; /* No Extended Tags */
472 /* Resource alignment requirements */
473 resource_size_t (*align_resource)(struct pci_dev *dev,
474 const struct resource *res,
475 resource_size_t start,
476 resource_size_t size,
477 resource_size_t align);
478 unsigned long private[0] ____cacheline_aligned;
481 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
483 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
485 return (void *)bridge->private;
488 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
490 return container_of(priv, struct pci_host_bridge, private);
493 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
494 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
496 void pci_free_host_bridge(struct pci_host_bridge *bridge);
497 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
499 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
500 void (*release_fn)(struct pci_host_bridge *),
503 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
506 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
507 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
508 * buses below host bridges or subtractive decode bridges) go in the list.
509 * Use pci_bus_for_each_resource() to iterate through all the resources.
513 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
514 * and there's no way to program the bridge with the details of the window.
515 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
516 * decode bit set, because they are explicit and can be programmed with _SRS.
518 #define PCI_SUBTRACTIVE_DECODE 0x1
520 struct pci_bus_resource {
521 struct list_head list;
522 struct resource *res;
526 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
529 struct list_head node; /* Node in list of buses */
530 struct pci_bus *parent; /* Parent bus this bridge is on */
531 struct list_head children; /* List of child buses */
532 struct list_head devices; /* List of devices on this bus */
533 struct pci_dev *self; /* Bridge device as seen by parent */
534 struct list_head slots; /* List of slots on this bus;
535 protected by pci_slot_mutex */
536 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
537 struct list_head resources; /* Address space routed to this bus */
538 struct resource busn_res; /* Bus numbers routed to this bus */
540 struct pci_ops *ops; /* Configuration access functions */
541 struct msi_controller *msi; /* MSI controller */
542 void *sysdata; /* Hook for sys-specific extension */
543 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
545 unsigned char number; /* Bus number */
546 unsigned char primary; /* Number of primary bridge */
547 unsigned char max_bus_speed; /* enum pci_bus_speed */
548 unsigned char cur_bus_speed; /* enum pci_bus_speed */
549 #ifdef CONFIG_PCI_DOMAINS_GENERIC
555 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
556 pci_bus_flags_t bus_flags; /* Inherited by child buses */
557 struct device *bridge;
559 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
560 struct bin_attribute *legacy_mem; /* Legacy mem */
561 unsigned int is_added:1;
564 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
567 * Returns true if the PCI bus is root (behind host-PCI bridge),
570 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
571 * This is incorrect because "virtual" buses added for SR-IOV (via
572 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
574 static inline bool pci_is_root_bus(struct pci_bus *pbus)
576 return !(pbus->parent);
580 * pci_is_bridge - check if the PCI device is a bridge
583 * Return true if the PCI device is bridge whether it has subordinate
586 static inline bool pci_is_bridge(struct pci_dev *dev)
588 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
589 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
592 #define for_each_pci_bridge(dev, bus) \
593 list_for_each_entry(dev, &bus->devices, bus_list) \
594 if (!pci_is_bridge(dev)) {} else
596 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
598 dev = pci_physfn(dev);
599 if (pci_is_root_bus(dev->bus))
602 return dev->bus->self;
605 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
606 void pci_put_host_bridge_device(struct device *dev);
608 #ifdef CONFIG_PCI_MSI
609 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
611 return pci_dev->msi_enabled || pci_dev->msix_enabled;
614 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
617 /* Error values that may be returned by PCI functions */
618 #define PCIBIOS_SUCCESSFUL 0x00
619 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
620 #define PCIBIOS_BAD_VENDOR_ID 0x83
621 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
622 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
623 #define PCIBIOS_SET_FAILED 0x88
624 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
626 /* Translate above to generic errno for passing back through non-PCI code */
627 static inline int pcibios_err_to_errno(int err)
629 if (err <= PCIBIOS_SUCCESSFUL)
630 return err; /* Assume already errno */
633 case PCIBIOS_FUNC_NOT_SUPPORTED:
635 case PCIBIOS_BAD_VENDOR_ID:
637 case PCIBIOS_DEVICE_NOT_FOUND:
639 case PCIBIOS_BAD_REGISTER_NUMBER:
641 case PCIBIOS_SET_FAILED:
643 case PCIBIOS_BUFFER_TOO_SMALL:
650 /* Low-level architecture-dependent routines */
653 int (*add_bus)(struct pci_bus *bus);
654 void (*remove_bus)(struct pci_bus *bus);
655 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
656 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
657 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
661 * ACPI needs to be able to access PCI config space before we've done a
662 * PCI bus scan and created pci_bus structures.
664 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
665 int reg, int len, u32 *val);
666 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
667 int reg, int len, u32 val);
669 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
670 typedef u64 pci_bus_addr_t;
672 typedef u32 pci_bus_addr_t;
675 struct pci_bus_region {
676 pci_bus_addr_t start;
681 spinlock_t lock; /* Protects list, index */
682 struct list_head list; /* For IDs added at runtime */
687 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
688 * a set of callbacks in struct pci_error_handlers, that device driver
689 * will be notified of PCI bus errors, and will be driven to recovery
690 * when an error occurs.
693 typedef unsigned int __bitwise pci_ers_result_t;
695 enum pci_ers_result {
696 /* No result/none/not supported in device driver */
697 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
699 /* Device driver can recover without slot reset */
700 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
702 /* Device driver wants slot to be reset */
703 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
705 /* Device has completely failed, is unrecoverable */
706 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
708 /* Device driver is fully recovered and operational */
709 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
711 /* No AER capabilities registered for the driver */
712 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
715 /* PCI bus error event callbacks */
716 struct pci_error_handlers {
717 /* PCI bus error detected on this device */
718 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
719 enum pci_channel_state error);
721 /* MMIO has been re-enabled, but not DMA */
722 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
724 /* PCI slot has been reset */
725 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
727 /* PCI function reset prepare or completed */
728 void (*reset_prepare)(struct pci_dev *dev);
729 void (*reset_done)(struct pci_dev *dev);
731 /* Device driver may resume normal operations */
732 void (*resume)(struct pci_dev *dev);
738 struct list_head node;
740 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
741 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
742 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
743 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
744 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
745 int (*resume_early)(struct pci_dev *dev);
746 int (*resume) (struct pci_dev *dev); /* Device woken up */
747 void (*shutdown) (struct pci_dev *dev);
748 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
749 const struct pci_error_handlers *err_handler;
750 const struct attribute_group **groups;
751 struct device_driver driver;
752 struct pci_dynids dynids;
755 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
758 * PCI_DEVICE - macro used to describe a specific PCI device
759 * @vend: the 16 bit PCI Vendor ID
760 * @dev: the 16 bit PCI Device ID
762 * This macro is used to create a struct pci_device_id that matches a
763 * specific device. The subvendor and subdevice fields will be set to
766 #define PCI_DEVICE(vend,dev) \
767 .vendor = (vend), .device = (dev), \
768 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
771 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
772 * @vend: the 16 bit PCI Vendor ID
773 * @dev: the 16 bit PCI Device ID
774 * @subvend: the 16 bit PCI Subvendor ID
775 * @subdev: the 16 bit PCI Subdevice ID
777 * This macro is used to create a struct pci_device_id that matches a
778 * specific device with subsystem information.
780 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
781 .vendor = (vend), .device = (dev), \
782 .subvendor = (subvend), .subdevice = (subdev)
785 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
786 * @dev_class: the class, subclass, prog-if triple for this device
787 * @dev_class_mask: the class mask for this device
789 * This macro is used to create a struct pci_device_id that matches a
790 * specific PCI class. The vendor, device, subvendor, and subdevice
791 * fields will be set to PCI_ANY_ID.
793 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
794 .class = (dev_class), .class_mask = (dev_class_mask), \
795 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
796 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
799 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
800 * @vend: the vendor name
801 * @dev: the 16 bit PCI Device ID
803 * This macro is used to create a struct pci_device_id that matches a
804 * specific PCI device. The subvendor, and subdevice fields will be set
805 * to PCI_ANY_ID. The macro allows the next field to follow as the device
808 #define PCI_VDEVICE(vend, dev) \
809 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
810 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
813 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
814 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
815 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
816 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
817 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
818 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
819 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
822 /* These external functions are only available when PCI support is enabled */
825 extern unsigned int pci_flags;
827 static inline void pci_set_flags(int flags) { pci_flags = flags; }
828 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
829 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
830 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
832 void pcie_bus_configure_settings(struct pci_bus *bus);
834 enum pcie_bus_config_types {
835 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
836 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
837 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
838 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
839 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
842 extern enum pcie_bus_config_types pcie_bus_config;
844 extern struct bus_type pci_bus_type;
846 /* Do NOT directly access these two variables, unless you are arch-specific PCI
847 * code, or PCI core code. */
848 extern struct list_head pci_root_buses; /* List of all known PCI buses */
849 /* Some device drivers need know if PCI is initiated */
850 int no_pci_devices(void);
852 void pcibios_resource_survey_bus(struct pci_bus *bus);
853 void pcibios_bus_add_device(struct pci_dev *pdev);
854 void pcibios_add_bus(struct pci_bus *bus);
855 void pcibios_remove_bus(struct pci_bus *bus);
856 void pcibios_fixup_bus(struct pci_bus *);
857 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
858 /* Architecture-specific versions may override this (weak) */
859 char *pcibios_setup(char *str);
861 /* Used only when drivers/pci/setup.c is used */
862 resource_size_t pcibios_align_resource(void *, const struct resource *,
866 /* Weak but can be overriden by arch */
867 void pci_fixup_cardbus(struct pci_bus *);
869 /* Generic PCI functions used internally */
871 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
872 struct resource *res);
873 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
874 struct pci_bus_region *region);
875 void pcibios_scan_specific_bus(int busn);
876 struct pci_bus *pci_find_bus(int domain, int busnr);
877 void pci_bus_add_devices(const struct pci_bus *bus);
878 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
879 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
880 struct pci_ops *ops, void *sysdata,
881 struct list_head *resources);
882 int pci_host_probe(struct pci_host_bridge *bridge);
883 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
884 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
885 void pci_bus_release_busn_res(struct pci_bus *b);
886 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
887 struct pci_ops *ops, void *sysdata,
888 struct list_head *resources);
889 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
890 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
892 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
893 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
895 struct hotplug_slot *hotplug);
896 void pci_destroy_slot(struct pci_slot *slot);
898 void pci_dev_assign_slot(struct pci_dev *dev);
900 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
902 int pci_scan_slot(struct pci_bus *bus, int devfn);
903 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
904 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
905 unsigned int pci_scan_child_bus(struct pci_bus *bus);
906 void pci_bus_add_device(struct pci_dev *dev);
907 void pci_read_bridge_bases(struct pci_bus *child);
908 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
909 struct resource *res);
910 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
911 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
912 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
913 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
914 struct pci_dev *pci_dev_get(struct pci_dev *dev);
915 void pci_dev_put(struct pci_dev *dev);
916 void pci_remove_bus(struct pci_bus *b);
917 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
918 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
919 void pci_stop_root_bus(struct pci_bus *bus);
920 void pci_remove_root_bus(struct pci_bus *bus);
921 void pci_setup_cardbus(struct pci_bus *bus);
922 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
923 void pci_sort_breadthfirst(void);
924 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
925 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
927 /* Generic PCI functions exported to card drivers */
929 enum pci_lost_interrupt_reason {
930 PCI_LOST_IRQ_NO_INFORMATION = 0,
931 PCI_LOST_IRQ_DISABLE_MSI,
932 PCI_LOST_IRQ_DISABLE_MSIX,
933 PCI_LOST_IRQ_DISABLE_ACPI,
935 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
936 int pci_find_capability(struct pci_dev *dev, int cap);
937 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
938 int pci_find_ext_capability(struct pci_dev *dev, int cap);
939 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
940 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
941 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
942 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
944 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
945 struct pci_dev *from);
946 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
947 unsigned int ss_vendor, unsigned int ss_device,
948 struct pci_dev *from);
949 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
950 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
952 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
955 return pci_get_domain_bus_and_slot(0, bus, devfn);
957 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
958 int pci_dev_present(const struct pci_device_id *ids);
960 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
962 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
963 int where, u16 *val);
964 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
965 int where, u32 *val);
966 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
968 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
970 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
973 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
974 int where, int size, u32 *val);
975 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
976 int where, int size, u32 val);
977 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
978 int where, int size, u32 *val);
979 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
980 int where, int size, u32 val);
982 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
984 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
985 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
986 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
987 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
988 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
989 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
991 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
992 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
993 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
994 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
995 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
997 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1000 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1003 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1006 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1009 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1012 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1015 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1018 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1021 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1024 /* User-space driven config access */
1025 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1026 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1027 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1028 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1029 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1030 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1032 int __must_check pci_enable_device(struct pci_dev *dev);
1033 int __must_check pci_enable_device_io(struct pci_dev *dev);
1034 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1035 int __must_check pci_reenable_device(struct pci_dev *);
1036 int __must_check pcim_enable_device(struct pci_dev *pdev);
1037 void pcim_pin_device(struct pci_dev *pdev);
1039 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1042 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1043 * writable and no quirk has marked the feature broken.
1045 return !pdev->broken_intx_masking;
1048 static inline int pci_is_enabled(struct pci_dev *pdev)
1050 return (atomic_read(&pdev->enable_cnt) > 0);
1053 static inline int pci_is_managed(struct pci_dev *pdev)
1055 return pdev->is_managed;
1058 void pci_disable_device(struct pci_dev *dev);
1060 extern unsigned int pcibios_max_latency;
1061 void pci_set_master(struct pci_dev *dev);
1062 void pci_clear_master(struct pci_dev *dev);
1064 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1065 int pci_set_cacheline_size(struct pci_dev *dev);
1066 #define HAVE_PCI_SET_MWI
1067 int __must_check pci_set_mwi(struct pci_dev *dev);
1068 int pci_try_set_mwi(struct pci_dev *dev);
1069 void pci_clear_mwi(struct pci_dev *dev);
1070 void pci_intx(struct pci_dev *dev, int enable);
1071 bool pci_check_and_mask_intx(struct pci_dev *dev);
1072 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1073 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1074 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1075 int pcix_get_max_mmrbc(struct pci_dev *dev);
1076 int pcix_get_mmrbc(struct pci_dev *dev);
1077 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1078 int pcie_get_readrq(struct pci_dev *dev);
1079 int pcie_set_readrq(struct pci_dev *dev, int rq);
1080 int pcie_get_mps(struct pci_dev *dev);
1081 int pcie_set_mps(struct pci_dev *dev, int mps);
1082 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1083 enum pcie_link_width *width);
1084 void pcie_flr(struct pci_dev *dev);
1085 int __pci_reset_function_locked(struct pci_dev *dev);
1086 int pci_reset_function(struct pci_dev *dev);
1087 int pci_reset_function_locked(struct pci_dev *dev);
1088 int pci_try_reset_function(struct pci_dev *dev);
1089 int pci_probe_reset_slot(struct pci_slot *slot);
1090 int pci_reset_slot(struct pci_slot *slot);
1091 int pci_try_reset_slot(struct pci_slot *slot);
1092 int pci_probe_reset_bus(struct pci_bus *bus);
1093 int pci_reset_bus(struct pci_bus *bus);
1094 int pci_try_reset_bus(struct pci_bus *bus);
1095 void pci_reset_secondary_bus(struct pci_dev *dev);
1096 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1097 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1098 void pci_update_resource(struct pci_dev *dev, int resno);
1099 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1100 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1101 void pci_release_resource(struct pci_dev *dev, int resno);
1102 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1103 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1104 bool pci_device_is_present(struct pci_dev *pdev);
1105 void pci_ignore_hotplug(struct pci_dev *dev);
1107 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1108 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1109 const char *fmt, ...);
1110 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1112 /* ROM control related routines */
1113 int pci_enable_rom(struct pci_dev *pdev);
1114 void pci_disable_rom(struct pci_dev *pdev);
1115 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1116 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1117 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1118 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1120 /* Power management related routines */
1121 int pci_save_state(struct pci_dev *dev);
1122 void pci_restore_state(struct pci_dev *dev);
1123 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1124 int pci_load_saved_state(struct pci_dev *dev,
1125 struct pci_saved_state *state);
1126 int pci_load_and_free_saved_state(struct pci_dev *dev,
1127 struct pci_saved_state **state);
1128 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1129 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1131 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1132 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1133 u16 cap, unsigned int size);
1134 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1135 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1136 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1137 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1138 void pci_pme_active(struct pci_dev *dev, bool enable);
1139 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1140 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1141 int pci_prepare_to_sleep(struct pci_dev *dev);
1142 int pci_back_from_sleep(struct pci_dev *dev);
1143 bool pci_dev_run_wake(struct pci_dev *dev);
1144 bool pci_check_pme_status(struct pci_dev *dev);
1145 void pci_pme_wakeup_bus(struct pci_bus *bus);
1146 void pci_d3cold_enable(struct pci_dev *dev);
1147 void pci_d3cold_disable(struct pci_dev *dev);
1148 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1150 /* PCI Virtual Channel */
1151 int pci_save_vc_state(struct pci_dev *dev);
1152 void pci_restore_vc_state(struct pci_dev *dev);
1153 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1155 /* For use by arch with custom probe code */
1156 void set_pcie_port_type(struct pci_dev *pdev);
1157 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1159 /* Functions for PCI Hotplug drivers to use */
1160 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1161 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1162 unsigned int pci_rescan_bus(struct pci_bus *bus);
1163 void pci_lock_rescan_remove(void);
1164 void pci_unlock_rescan_remove(void);
1166 /* Vital Product Data routines */
1167 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1168 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1169 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1171 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1172 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1173 void pci_bus_assign_resources(const struct pci_bus *bus);
1174 void pci_bus_claim_resources(struct pci_bus *bus);
1175 void pci_bus_size_bridges(struct pci_bus *bus);
1176 int pci_claim_resource(struct pci_dev *, int);
1177 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1178 void pci_assign_unassigned_resources(void);
1179 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1180 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1181 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1182 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1183 void pdev_enable_device(struct pci_dev *);
1184 int pci_enable_resources(struct pci_dev *, int mask);
1185 void pci_assign_irq(struct pci_dev *dev);
1186 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1187 #define HAVE_PCI_REQ_REGIONS 2
1188 int __must_check pci_request_regions(struct pci_dev *, const char *);
1189 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1190 void pci_release_regions(struct pci_dev *);
1191 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1192 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1193 void pci_release_region(struct pci_dev *, int);
1194 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1195 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1196 void pci_release_selected_regions(struct pci_dev *, int);
1198 /* drivers/pci/bus.c */
1199 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1200 void pci_bus_put(struct pci_bus *bus);
1201 void pci_add_resource(struct list_head *resources, struct resource *res);
1202 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1203 resource_size_t offset);
1204 void pci_free_resource_list(struct list_head *resources);
1205 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1206 unsigned int flags);
1207 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1208 void pci_bus_remove_resources(struct pci_bus *bus);
1209 int devm_request_pci_bus_resources(struct device *dev,
1210 struct list_head *resources);
1212 #define pci_bus_for_each_resource(bus, res, i) \
1214 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1217 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1218 struct resource *res, resource_size_t size,
1219 resource_size_t align, resource_size_t min,
1220 unsigned long type_mask,
1221 resource_size_t (*alignf)(void *,
1222 const struct resource *,
1228 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1229 unsigned long pci_address_to_pio(phys_addr_t addr);
1230 phys_addr_t pci_pio_to_address(unsigned long pio);
1231 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1232 void pci_unmap_iospace(struct resource *res);
1233 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1234 resource_size_t offset,
1235 resource_size_t size);
1236 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1237 struct resource *res);
1239 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1241 struct pci_bus_region region;
1243 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1244 return region.start;
1247 /* Proper probing supporting hot-pluggable devices */
1248 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1249 const char *mod_name);
1251 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1252 #define pci_register_driver(driver) \
1253 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1255 void pci_unregister_driver(struct pci_driver *dev);
1258 * module_pci_driver() - Helper macro for registering a PCI driver
1259 * @__pci_driver: pci_driver struct
1261 * Helper macro for PCI drivers which do not do anything special in module
1262 * init/exit. This eliminates a lot of boilerplate. Each module may only
1263 * use this macro once, and calling it replaces module_init() and module_exit()
1265 #define module_pci_driver(__pci_driver) \
1266 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1269 * builtin_pci_driver() - Helper macro for registering a PCI driver
1270 * @__pci_driver: pci_driver struct
1272 * Helper macro for PCI drivers which do not do anything special in their
1273 * init code. This eliminates a lot of boilerplate. Each driver may only
1274 * use this macro once, and calling it replaces device_initcall(...)
1276 #define builtin_pci_driver(__pci_driver) \
1277 builtin_driver(__pci_driver, pci_register_driver)
1279 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1280 int pci_add_dynid(struct pci_driver *drv,
1281 unsigned int vendor, unsigned int device,
1282 unsigned int subvendor, unsigned int subdevice,
1283 unsigned int class, unsigned int class_mask,
1284 unsigned long driver_data);
1285 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1286 struct pci_dev *dev);
1287 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1290 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1292 int pci_cfg_space_size(struct pci_dev *dev);
1293 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1294 void pci_setup_bridge(struct pci_bus *bus);
1295 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1296 unsigned long type);
1297 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1299 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1300 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1302 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1303 unsigned int command_bits, u32 flags);
1305 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1306 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1307 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1308 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1309 #define PCI_IRQ_ALL_TYPES \
1310 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1312 /* kmem_cache style wrapper around pci_alloc_consistent() */
1314 #include <linux/pci-dma.h>
1315 #include <linux/dmapool.h>
1317 #define pci_pool dma_pool
1318 #define pci_pool_create(name, pdev, size, align, allocation) \
1319 dma_pool_create(name, &pdev->dev, size, align, allocation)
1320 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1321 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1322 #define pci_pool_zalloc(pool, flags, handle) \
1323 dma_pool_zalloc(pool, flags, handle)
1324 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1327 u32 vector; /* Kernel uses to write allocated vector */
1328 u16 entry; /* Driver uses to specify entry, OS writes */
1331 #ifdef CONFIG_PCI_MSI
1332 int pci_msi_vec_count(struct pci_dev *dev);
1333 void pci_disable_msi(struct pci_dev *dev);
1334 int pci_msix_vec_count(struct pci_dev *dev);
1335 void pci_disable_msix(struct pci_dev *dev);
1336 void pci_restore_msi_state(struct pci_dev *dev);
1337 int pci_msi_enabled(void);
1338 int pci_enable_msi(struct pci_dev *dev);
1339 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1340 int minvec, int maxvec);
1341 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1342 struct msix_entry *entries, int nvec)
1344 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1349 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1350 unsigned int max_vecs, unsigned int flags,
1351 const struct irq_affinity *affd);
1353 void pci_free_irq_vectors(struct pci_dev *dev);
1354 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1355 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1356 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1359 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1360 static inline void pci_disable_msi(struct pci_dev *dev) { }
1361 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1362 static inline void pci_disable_msix(struct pci_dev *dev) { }
1363 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1364 static inline int pci_msi_enabled(void) { return 0; }
1365 static inline int pci_enable_msi(struct pci_dev *dev)
1367 static inline int pci_enable_msix_range(struct pci_dev *dev,
1368 struct msix_entry *entries, int minvec, int maxvec)
1370 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1371 struct msix_entry *entries, int nvec)
1375 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1376 unsigned int max_vecs, unsigned int flags,
1377 const struct irq_affinity *aff_desc)
1379 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1384 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1388 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1390 if (WARN_ON_ONCE(nr > 0))
1394 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1397 return cpu_possible_mask;
1400 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1402 return first_online_node;
1407 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1408 unsigned int max_vecs, unsigned int flags)
1410 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1415 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1416 * @d: the INTx IRQ domain
1417 * @node: the DT node for the device whose interrupt we're translating
1418 * @intspec: the interrupt specifier data from the DT
1419 * @intsize: the number of entries in @intspec
1420 * @out_hwirq: pointer at which to write the hwirq number
1421 * @out_type: pointer at which to write the interrupt type
1423 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1424 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1425 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1426 * INTx value to obtain the hwirq number.
1428 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1430 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1431 struct device_node *node,
1433 unsigned int intsize,
1434 unsigned long *out_hwirq,
1435 unsigned int *out_type)
1437 const u32 intx = intspec[0];
1439 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1442 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1446 #ifdef CONFIG_PCIEPORTBUS
1447 extern bool pcie_ports_disabled;
1448 extern bool pcie_ports_auto;
1450 #define pcie_ports_disabled true
1451 #define pcie_ports_auto false
1454 #ifdef CONFIG_PCIEASPM
1455 bool pcie_aspm_support_enabled(void);
1457 static inline bool pcie_aspm_support_enabled(void) { return false; }
1460 #ifdef CONFIG_PCIEAER
1461 void pci_no_aer(void);
1462 bool pci_aer_available(void);
1463 int pci_aer_init(struct pci_dev *dev);
1465 static inline void pci_no_aer(void) { }
1466 static inline bool pci_aer_available(void) { return false; }
1467 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1470 #ifdef CONFIG_PCIE_ECRC
1471 void pcie_set_ecrc_checking(struct pci_dev *dev);
1472 void pcie_ecrc_get_policy(char *str);
1474 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1475 static inline void pcie_ecrc_get_policy(char *str) { }
1478 #ifdef CONFIG_PCI_ATS
1479 /* Address Translation Service */
1480 void pci_ats_init(struct pci_dev *dev);
1481 int pci_enable_ats(struct pci_dev *dev, int ps);
1482 void pci_disable_ats(struct pci_dev *dev);
1483 int pci_ats_queue_depth(struct pci_dev *dev);
1485 static inline void pci_ats_init(struct pci_dev *d) { }
1486 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1487 static inline void pci_disable_ats(struct pci_dev *d) { }
1488 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1491 #ifdef CONFIG_PCIE_PTM
1492 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1494 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1498 void pci_cfg_access_lock(struct pci_dev *dev);
1499 bool pci_cfg_access_trylock(struct pci_dev *dev);
1500 void pci_cfg_access_unlock(struct pci_dev *dev);
1503 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1504 * a PCI domain is defined to be a set of PCI buses which share
1505 * configuration space.
1507 #ifdef CONFIG_PCI_DOMAINS
1508 extern int pci_domains_supported;
1509 int pci_get_new_domain_nr(void);
1511 enum { pci_domains_supported = 0 };
1512 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1513 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1514 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1515 #endif /* CONFIG_PCI_DOMAINS */
1518 * Generic implementation for PCI domain support. If your
1519 * architecture does not need custom management of PCI
1520 * domains then this implementation will be used
1522 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1523 static inline int pci_domain_nr(struct pci_bus *bus)
1525 return bus->domain_nr;
1528 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1530 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1533 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1536 /* Some architectures require additional setup to direct VGA traffic */
1537 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1538 unsigned int command_bits, u32 flags);
1539 void pci_register_set_vga_state(arch_set_vga_state_t func);
1542 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1544 return pci_request_selected_regions(pdev,
1545 pci_select_bars(pdev, IORESOURCE_IO), name);
1549 pci_release_io_regions(struct pci_dev *pdev)
1551 return pci_release_selected_regions(pdev,
1552 pci_select_bars(pdev, IORESOURCE_IO));
1556 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1558 return pci_request_selected_regions(pdev,
1559 pci_select_bars(pdev, IORESOURCE_MEM), name);
1563 pci_release_mem_regions(struct pci_dev *pdev)
1565 return pci_release_selected_regions(pdev,
1566 pci_select_bars(pdev, IORESOURCE_MEM));
1569 #else /* CONFIG_PCI is not enabled */
1571 static inline void pci_set_flags(int flags) { }
1572 static inline void pci_add_flags(int flags) { }
1573 static inline void pci_clear_flags(int flags) { }
1574 static inline int pci_has_flag(int flag) { return 0; }
1577 * If the system does not have PCI, clearly these return errors. Define
1578 * these as simple inline functions to avoid hair in drivers.
1580 #define _PCI_NOP(o, s, t) \
1581 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1583 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1585 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1586 _PCI_NOP(o, word, u16 x) \
1587 _PCI_NOP(o, dword, u32 x)
1588 _PCI_NOP_ALL(read, *)
1589 _PCI_NOP_ALL(write,)
1591 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1592 unsigned int device,
1593 struct pci_dev *from)
1596 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1597 unsigned int device,
1598 unsigned int ss_vendor,
1599 unsigned int ss_device,
1600 struct pci_dev *from)
1603 static inline struct pci_dev *pci_get_class(unsigned int class,
1604 struct pci_dev *from)
1607 #define pci_dev_present(ids) (0)
1608 #define no_pci_devices() (1)
1609 #define pci_dev_put(dev) do { } while (0)
1611 static inline void pci_set_master(struct pci_dev *dev) { }
1612 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1613 static inline void pci_disable_device(struct pci_dev *dev) { }
1614 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1616 static inline int __pci_register_driver(struct pci_driver *drv,
1617 struct module *owner)
1619 static inline int pci_register_driver(struct pci_driver *drv)
1621 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1622 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1624 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1627 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1630 /* Power management related routines */
1631 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1632 static inline void pci_restore_state(struct pci_dev *dev) { }
1633 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1635 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1637 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1640 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1644 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1645 struct resource *res)
1647 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1649 static inline void pci_release_regions(struct pci_dev *dev) { }
1651 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1653 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1654 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1656 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1658 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1660 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1663 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1666 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1667 unsigned int bus, unsigned int devfn)
1670 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1671 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1672 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1674 #define dev_is_pci(d) (false)
1675 #define dev_is_pf(d) (false)
1676 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1678 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1679 struct device_node *node,
1681 unsigned int intsize,
1682 unsigned long *out_hwirq,
1683 unsigned int *out_type)
1685 #endif /* CONFIG_PCI */
1687 /* Include architecture-dependent settings and functions */
1689 #include <asm/pci.h>
1691 /* These two functions provide almost identical functionality. Depennding
1692 * on the architecture, one will be implemented as a wrapper around the
1693 * other (in drivers/pci/mmap.c).
1695 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1696 * is expected to be an offset within that region.
1698 * pci_mmap_page_range() is the legacy architecture-specific interface,
1699 * which accepts a "user visible" resource address converted by
1700 * pci_resource_to_user(), as used in the legacy mmap() interface in
1703 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1704 struct vm_area_struct *vma,
1705 enum pci_mmap_state mmap_state, int write_combine);
1706 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1707 struct vm_area_struct *vma,
1708 enum pci_mmap_state mmap_state, int write_combine);
1710 #ifndef arch_can_pci_mmap_wc
1711 #define arch_can_pci_mmap_wc() 0
1714 #ifndef arch_can_pci_mmap_io
1715 #define arch_can_pci_mmap_io() 0
1716 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1718 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1721 #ifndef pci_root_bus_fwnode
1722 #define pci_root_bus_fwnode(bus) NULL
1726 * These helpers provide future and backwards compatibility
1727 * for accessing popular PCI BAR info
1729 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1730 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1731 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1732 #define pci_resource_len(dev,bar) \
1733 ((pci_resource_start((dev), (bar)) == 0 && \
1734 pci_resource_end((dev), (bar)) == \
1735 pci_resource_start((dev), (bar))) ? 0 : \
1737 (pci_resource_end((dev), (bar)) - \
1738 pci_resource_start((dev), (bar)) + 1))
1741 * Similar to the helpers above, these manipulate per-pci_dev
1742 * driver-specific data. They are really just a wrapper around
1743 * the generic device structure functions of these calls.
1745 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1747 return dev_get_drvdata(&pdev->dev);
1750 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1752 dev_set_drvdata(&pdev->dev, data);
1755 static inline const char *pci_name(const struct pci_dev *pdev)
1757 return dev_name(&pdev->dev);
1762 * Some archs don't want to expose struct resource to userland as-is
1763 * in sysfs and /proc
1765 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1766 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1767 const struct resource *rsrc,
1768 resource_size_t *start, resource_size_t *end);
1770 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1771 const struct resource *rsrc, resource_size_t *start,
1772 resource_size_t *end)
1774 *start = rsrc->start;
1777 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1781 * The world is not perfect and supplies us with broken PCI devices.
1782 * For at least a part of these bugs we need a work-around, so both
1783 * generic (drivers/pci/quirks.c) and per-architecture code can define
1784 * fixup hooks to be called for particular buggy devices.
1788 u16 vendor; /* Or PCI_ANY_ID */
1789 u16 device; /* Or PCI_ANY_ID */
1790 u32 class; /* Or PCI_ANY_ID */
1791 unsigned int class_shift; /* should be 0, 8, 16 */
1792 void (*hook)(struct pci_dev *dev);
1795 enum pci_fixup_pass {
1796 pci_fixup_early, /* Before probing BARs */
1797 pci_fixup_header, /* After reading configuration header */
1798 pci_fixup_final, /* Final phase of device fixups */
1799 pci_fixup_enable, /* pci_enable_device() time */
1800 pci_fixup_resume, /* pci_device_resume() */
1801 pci_fixup_suspend, /* pci_device_suspend() */
1802 pci_fixup_resume_early, /* pci_device_resume_early() */
1803 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1806 /* Anonymous variables would be nice... */
1807 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1808 class_shift, hook) \
1809 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1810 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1811 = { vendor, device, class, class_shift, hook };
1813 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1814 class_shift, hook) \
1815 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1816 hook, vendor, device, class, class_shift, hook)
1817 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1818 class_shift, hook) \
1819 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1820 hook, vendor, device, class, class_shift, hook)
1821 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1822 class_shift, hook) \
1823 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1824 hook, vendor, device, class, class_shift, hook)
1825 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1826 class_shift, hook) \
1827 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1828 hook, vendor, device, class, class_shift, hook)
1829 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1830 class_shift, hook) \
1831 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1832 resume##hook, vendor, device, class, class_shift, hook)
1833 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1834 class_shift, hook) \
1835 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1836 resume_early##hook, vendor, device, class, class_shift, hook)
1837 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1838 class_shift, hook) \
1839 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1840 suspend##hook, vendor, device, class, class_shift, hook)
1841 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1842 class_shift, hook) \
1843 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1844 suspend_late##hook, vendor, device, class, class_shift, hook)
1846 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1847 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1848 hook, vendor, device, PCI_ANY_ID, 0, hook)
1849 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1850 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1851 hook, vendor, device, PCI_ANY_ID, 0, hook)
1852 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1853 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1854 hook, vendor, device, PCI_ANY_ID, 0, hook)
1855 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1856 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1857 hook, vendor, device, PCI_ANY_ID, 0, hook)
1858 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1859 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1860 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1861 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1862 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1863 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1864 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1865 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1866 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1867 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1868 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1869 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1871 #ifdef CONFIG_PCI_QUIRKS
1872 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1873 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1874 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1876 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1877 struct pci_dev *dev) { }
1878 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1883 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1889 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1890 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1891 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1892 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1893 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1895 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1897 extern int pci_pci_problems;
1898 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1899 #define PCIPCI_TRITON 2
1900 #define PCIPCI_NATOMA 4
1901 #define PCIPCI_VIAETBF 8
1902 #define PCIPCI_VSFX 16
1903 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1904 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1906 extern unsigned long pci_cardbus_io_size;
1907 extern unsigned long pci_cardbus_mem_size;
1908 extern u8 pci_dfl_cache_line_size;
1909 extern u8 pci_cache_line_size;
1911 extern unsigned long pci_hotplug_io_size;
1912 extern unsigned long pci_hotplug_mem_size;
1913 extern unsigned long pci_hotplug_bus_size;
1915 /* Architecture-specific versions may override these (weak) */
1916 void pcibios_disable_device(struct pci_dev *dev);
1917 void pcibios_set_master(struct pci_dev *dev);
1918 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1919 enum pcie_reset_state state);
1920 int pcibios_add_device(struct pci_dev *dev);
1921 void pcibios_release_device(struct pci_dev *dev);
1922 void pcibios_penalize_isa_irq(int irq, int active);
1923 int pcibios_alloc_irq(struct pci_dev *dev);
1924 void pcibios_free_irq(struct pci_dev *dev);
1926 #ifdef CONFIG_HIBERNATE_CALLBACKS
1927 extern struct dev_pm_ops pcibios_pm_ops;
1930 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1931 void __init pci_mmcfg_early_init(void);
1932 void __init pci_mmcfg_late_init(void);
1934 static inline void pci_mmcfg_early_init(void) { }
1935 static inline void pci_mmcfg_late_init(void) { }
1938 int pci_ext_cfg_avail(void);
1940 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1941 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1943 #ifdef CONFIG_PCI_IOV
1944 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1945 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1947 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1948 void pci_disable_sriov(struct pci_dev *dev);
1949 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1950 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1951 int pci_num_vf(struct pci_dev *dev);
1952 int pci_vfs_assigned(struct pci_dev *dev);
1953 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1954 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1955 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1957 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1961 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1965 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1967 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
1971 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1973 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1974 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1975 static inline int pci_vfs_assigned(struct pci_dev *dev)
1977 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1979 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1981 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1985 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1986 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1987 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1991 * pci_pcie_cap - get the saved PCIe capability offset
1994 * PCIe capability offset is calculated at PCI device initialization
1995 * time and saved in the data structure. This function returns saved
1996 * PCIe capability offset. Using this instead of pci_find_capability()
1997 * reduces unnecessary search in the PCI configuration space. If you
1998 * need to calculate PCIe capability offset from raw device for some
1999 * reasons, please use pci_find_capability() instead.
2001 static inline int pci_pcie_cap(struct pci_dev *dev)
2003 return dev->pcie_cap;
2007 * pci_is_pcie - check if the PCI device is PCI Express capable
2010 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2012 static inline bool pci_is_pcie(struct pci_dev *dev)
2014 return pci_pcie_cap(dev);
2018 * pcie_caps_reg - get the PCIe Capabilities Register
2021 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2023 return dev->pcie_flags_reg;
2027 * pci_pcie_type - get the PCIe device/port type
2030 static inline int pci_pcie_type(const struct pci_dev *dev)
2032 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2035 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2038 if (!pci_is_pcie(dev))
2040 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2042 if (!dev->bus->self)
2044 dev = dev->bus->self;
2049 void pci_request_acs(void);
2050 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2051 bool pci_acs_path_enabled(struct pci_dev *start,
2052 struct pci_dev *end, u16 acs_flags);
2053 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2055 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2056 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2058 /* Large Resource Data Type Tag Item Names */
2059 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2060 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2061 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2063 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2064 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2065 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2067 /* Small Resource Data Type Tag Item Names */
2068 #define PCI_VPD_STIN_END 0x0f /* End */
2070 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2072 #define PCI_VPD_SRDT_TIN_MASK 0x78
2073 #define PCI_VPD_SRDT_LEN_MASK 0x07
2074 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2076 #define PCI_VPD_LRDT_TAG_SIZE 3
2077 #define PCI_VPD_SRDT_TAG_SIZE 1
2079 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2081 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2082 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2083 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2084 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2087 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2088 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2090 * Returns the extracted Large Resource Data Type length.
2092 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2094 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2098 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2099 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2101 * Returns the extracted Large Resource Data Type Tag item.
2103 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2105 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2109 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2110 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2112 * Returns the extracted Small Resource Data Type length.
2114 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2116 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2120 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2121 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2123 * Returns the extracted Small Resource Data Type Tag Item.
2125 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2127 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2131 * pci_vpd_info_field_size - Extracts the information field length
2132 * @lrdt: Pointer to the beginning of an information field header
2134 * Returns the extracted information field length.
2136 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2138 return info_field[2];
2142 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2143 * @buf: Pointer to buffered vpd data
2144 * @off: The offset into the buffer at which to begin the search
2145 * @len: The length of the vpd buffer
2146 * @rdt: The Resource Data Type to search for
2148 * Returns the index where the Resource Data Type was found or
2149 * -ENOENT otherwise.
2151 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2154 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2155 * @buf: Pointer to buffered vpd data
2156 * @off: The offset into the buffer at which to begin the search
2157 * @len: The length of the buffer area, relative to off, in which to search
2158 * @kw: The keyword to search for
2160 * Returns the index where the information field keyword was found or
2161 * -ENOENT otherwise.
2163 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2164 unsigned int len, const char *kw);
2166 /* PCI <-> OF binding helpers */
2170 void pci_set_of_node(struct pci_dev *dev);
2171 void pci_release_of_node(struct pci_dev *dev);
2172 void pci_set_bus_of_node(struct pci_bus *bus);
2173 void pci_release_bus_of_node(struct pci_bus *bus);
2174 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2175 int pci_parse_request_of_pci_ranges(struct device *dev,
2176 struct list_head *resources,
2177 struct resource **bus_range);
2179 /* Arch may override this (weak) */
2180 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2182 static inline struct device_node *
2183 pci_device_to_OF_node(const struct pci_dev *pdev)
2185 return pdev ? pdev->dev.of_node : NULL;
2188 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2190 return bus ? bus->dev.of_node : NULL;
2193 #else /* CONFIG_OF */
2194 static inline void pci_set_of_node(struct pci_dev *dev) { }
2195 static inline void pci_release_of_node(struct pci_dev *dev) { }
2196 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2197 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2198 static inline struct device_node *
2199 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2200 static inline struct irq_domain *
2201 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2202 static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2203 struct list_head *resources,
2204 struct resource **bus_range)
2208 #endif /* CONFIG_OF */
2211 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2214 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2216 static inline struct irq_domain *
2217 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2221 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2223 return pdev->dev.archdata.edev;
2227 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2228 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2229 int pci_for_each_dma_alias(struct pci_dev *pdev,
2230 int (*fn)(struct pci_dev *pdev,
2231 u16 alias, void *data), void *data);
2233 /* Helper functions for operation of device flag */
2234 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2236 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2238 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2240 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2242 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2244 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2248 * pci_ari_enabled - query ARI forwarding status
2251 * Returns true if ARI forwarding is enabled.
2253 static inline bool pci_ari_enabled(struct pci_bus *bus)
2255 return bus->self && bus->self->ari_enabled;
2259 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2260 * @pdev: PCI device to check
2262 * Walk upwards from @pdev and check for each encountered bridge if it's part
2263 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2264 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2266 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2268 struct pci_dev *parent = pdev;
2270 if (pdev->is_thunderbolt)
2273 while ((parent = pci_upstream_bridge(parent)))
2274 if (parent->is_thunderbolt)
2280 /* Provide the legacy pci_dma_* API */
2281 #include <linux/pci-dma-compat.h>
2283 #define pci_printk(level, pdev, fmt, arg...) \
2284 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2286 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2287 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2288 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2289 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2290 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2291 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2292 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2293 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2295 #endif /* LINUX_PCI_H */