Merge tag 'v6.7-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel...
authorStephen Boyd <sboyd@kernel.org>
Wed, 13 Dec 2023 23:26:24 +0000 (15:26 -0800)
committerStephen Boyd <sboyd@kernel.org>
Wed, 13 Dec 2023 23:26:24 +0000 (15:26 -0800)
commit8defec031c40913ef10d2f654a5ccc8a2a9730c1
treee1493c4ab0eb274877fddc28bf92db1f8c930457
parente8d66d02defd3256a31c0ec09af63382b8682c0e
parent99fe9ee56bd2f7358f1bc72551c2f3a6bbddf80a
Merge tag 'v6.7-rockchip-clkfixes1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-fixes

Pull Rockchip clk driver fixes for the merge window from Heiko Stuebner:

Fixes for a wrong clockname, a wrong clock-parent, a wrong clock-gate
and finally one new PLL rate for the rk3568 to fix display artifacts
on a handheld devices based on that soc.

* tag 'v6.7-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name
  clk: rockchip: rk3128: Fix aclk_peri_src's parent
  clk: rockchip: rk3128: Fix HCLK_OTG gate register
  clk: rockchip: rk3568: Add PLL rate for 292.5MHz