mmc: cavium-octeon: Fix interrupt enable code
authorDavid Daney <david.daney@cavium.com>
Tue, 16 May 2017 09:36:51 +0000 (11:36 +0200)
committerUlf Hansson <ulf.hansson@linaro.org>
Fri, 19 May 2017 07:17:44 +0000 (09:17 +0200)
commitaca69344c8a99e7374d913e42ba9120c398ee16f
tree4d3d8b8d19bf1319bf0bf5851f78478bf778027b
parentbae3dee0992dcb336a591468376b046e5447997b
mmc: cavium-octeon: Fix interrupt enable code

OCTEON SoCs with CIU3 do not have interrupt masking local to the MMC
bus interface.  Unfortunately, some even have a diagnostic register at
the same address of the enable register, which causes the interrupts
to fire immediately if stored to, thus breaking the driver.  The proper
action on these SoCs is not to touch this register.

Fixes: 01d95843335c ("mmc: cavium: Add MMC support for Octeon SOCs.")
Signed-off-by: David Daney <david.daney@cavium.com>
[jglauber@cavium.com: removed point after subject line]
Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/cavium-octeon.c