/* * INSNX86.H * * (c)Copyright 2016, Matthew Dillon, All Rights Reserved. See the * COPYRIGHT file at the base of the distribution. */ #define X86_REG_RAX (0x0000 | X86_SIZE_UNSPEC) #define X86_REG_RCX (0x0001 | X86_SIZE_UNSPEC) #define X86_REG_RDX (0x0002 | X86_SIZE_UNSPEC) #define X86_REG_RBX (0x0003 | X86_SIZE_UNSPEC) #define X86_REG_RSP (0x0004 | X86_SIZE_UNSPEC) #define X86_REG_RBP (0x0005 | X86_SIZE_UNSPEC) #define X86_REG_RSI (0x0006 | X86_SIZE_UNSPEC) #define X86_REG_RDI (0x0007 | X86_SIZE_UNSPEC) #define X86_REG_R8 (0x0008 | X86_SIZE_UNSPEC) #define X86_REG_R9 (0x0009 | X86_SIZE_UNSPEC) #define X86_REG_R10 (0x000A | X86_SIZE_UNSPEC) #define X86_REG_R11 (0x000B | X86_SIZE_UNSPEC) #define X86_REG_R12 (0x000C | X86_SIZE_UNSPEC) #define X86_REG_R13 (0x000D | X86_SIZE_UNSPEC) #define X86_REG_R14 (0x000E | X86_SIZE_UNSPEC) #define X86_REG_R15 (0x000F | X86_SIZE_UNSPEC) #define X86_REG_RIP (0x0010 | X86_SIZE_UNSPEC) #define X86_REG_XMM0 (0x0020 | X86_SIZE_UNSPEC) #define X86_REG_XMM1 (0x0021 | X86_SIZE_UNSPEC) #define X86_REG_XMM2 (0x0022 | X86_SIZE_UNSPEC) #define X86_REG_XMM3 (0x0023 | X86_SIZE_UNSPEC) #define X86_REG_XMM4 (0x0024 | X86_SIZE_UNSPEC) #define X86_REG_XMM5 (0x0025 | X86_SIZE_UNSPEC) #define X86_REG_XMM6 (0x0026 | X86_SIZE_UNSPEC) #define X86_REG_XMM7 (0x0027 | X86_SIZE_UNSPEC) #define X86_REG_XMM8 (0x0028 | X86_SIZE_UNSPEC) #define X86_REG_XMM9 (0x0029 | X86_SIZE_UNSPEC) #define X86_REG_XMM10 (0x002A | X86_SIZE_UNSPEC) #define X86_REG_XMM11 (0x002B | X86_SIZE_UNSPEC) #define X86_REG_XMM12 (0x002C | X86_SIZE_UNSPEC) #define X86_REG_XMM13 (0x002D | X86_SIZE_UNSPEC) #define X86_REG_XMM14 (0x002E | X86_SIZE_UNSPEC) #define X86_REG_XMM15 (0x002F | X86_SIZE_UNSPEC) #define X86_REGF_RAX (1LLU << (X86_REG_RAX & X86_REG_MASK)) #define X86_REGF_RCX (1LLU << (X86_REG_RCX & X86_REG_MASK)) #define X86_REGF_RDX (1LLU << (X86_REG_RDX & X86_REG_MASK)) #define X86_REGF_RBX (1LLU << (X86_REG_RBX & X86_REG_MASK)) #define X86_REGF_RSP (1LLU << (X86_REG_RSP & X86_REG_MASK)) #define X86_REGF_RBP (1LLU << (X86_REG_RBP & X86_REG_MASK)) #define X86_REGF_RSI (1LLU << (X86_REG_RSI & X86_REG_MASK)) #define X86_REGF_RDI (1LLU << (X86_REG_RDI & X86_REG_MASK)) #define X86_REGF_R8 (1LLU << (X86_REG_R8 & X86_REG_MASK)) #define X86_REGF_R9 (1LLU << (X86_REG_R9 & X86_REG_MASK)) #define X86_REGF_R10 (1LLU << (X86_REG_R10 & X86_REG_MASK)) #define X86_REGF_R11 (1LLU << (X86_REG_R11 & X86_REG_MASK)) #define X86_REGF_R12 (1LLU << (X86_REG_R12 & X86_REG_MASK)) #define X86_REGF_R13 (1LLU << (X86_REG_R13 & X86_REG_MASK)) #define X86_REGF_R14 (1LLU << (X86_REG_R14 & X86_REG_MASK)) #define X86_REGF_R15 (1LLU << (X86_REG_R15 & X86_REG_MASK)) #define X86_REGF_RIP (1LLU << (X86_REG_RIP & X86_REG_MASK)) #define X86_REGF_XMM0 (1LLU << (X86_REG_XMM0 & X86_REG_MASK)) #define X86_REGF_XMM1 (1LLU << (X86_REG_XMM1 & X86_REG_MASK)) #define X86_REGF_XMM2 (1LLU << (X86_REG_XMM2 & X86_REG_MASK)) #define X86_REGF_XMM3 (1LLU << (X86_REG_XMM3 & X86_REG_MASK)) #define X86_REGF_XMM4 (1LLU << (X86_REG_XMM4 & X86_REG_MASK)) #define X86_REGF_XMM5 (1LLU << (X86_REG_XMM5 & X86_REG_MASK)) #define X86_REGF_XMM6 (1LLU << (X86_REG_XMM6 & X86_REG_MASK)) #define X86_REGF_XMM7 (1LLU << (X86_REG_XMM7 & X86_REG_MASK)) #define X86_REGF_XMM8 (1LLU << (X86_REG_XMM8 & X86_REG_MASK)) #define X86_REGF_XMM9 (1LLU << (X86_REG_XMM9 & X86_REG_MASK)) #define X86_REGF_XMM10 (1LLU << (X86_REG_XMM10 & X86_REG_MASK)) #define X86_REGF_XMM11 (1LLU << (X86_REG_XMM11 & X86_REG_MASK)) #define X86_REGF_XMM12 (1LLU << (X86_REG_XMM12 & X86_REG_MASK)) #define X86_REGF_XMM13 (1LLU << (X86_REG_XMM13 & X86_REG_MASK)) #define X86_REGF_XMM14 (1LLU << (X86_REG_XMM14 & X86_REG_MASK)) #define X86_REGF_XMM15 (1LLU << (X86_REG_XMM15 & X86_REG_MASK)) #define X86_REG_MASK 0x00FF #define X86_SIZE_UNSPEC 0x0100 #define X86_REG_ILIMIT 0x0010 /* 0x00-0x0F */ #define X86_REG_IOVMAX 0x002F /* 0x00-0x1F */ #define X86_REG_FBASE 0x0020 /* 0x20-0x2F */ #define X86_REG_FLIMIT 0x0030 /* 0x20-0x2F */ #define X86_REG_FOVMAX 0x003F /* 0x20-0x3F */ #define X86_REGF_FMASK 0xFFFFFFFF00000000LLU #define X86_REGF_IMASK 0x00000000FFFFFFFFLLU #define X86_REGF_GOOD 0x0000FFFF0000FFFFLLU /* * Relaxed additional procedure-crossing registerization at the cost of * saving and restoring (up to) these registers across procedure calls. * * NOTE: Specifying XMM0 and XMM1 here would be a big waste. */ #define X86_REGF_SPECIAL_SAVE \ (X86_REGF_R8 | X86_REGF_R9 | X86_REGF_R10 | X86_REGF_R11 | \ X86_REGF_XMM8 | X86_REGF_XMM9 | X86_REGF_XMM10 | X86_REGF_XMM11) /* * Standard x86-64 calling convention (BSD/Linux) * * This ABI is used for system calls. Note that (currently) in Rune, * arguments are passed on the stack. * * Call-saved registers: * RBX, RBP, R12, R13, R14, R15, and RSP * * Argument passing: * RDI, RSI, RDX, RCX * */ #define X86_REGF_CALLSAVE_STD \ (X86_REGF_RBX | X86_REGF_RBP | \ X86_REGF_R12 | X86_REGF_R13 | X86_REGF_R14 | X86_REGF_R15) #define X86_STDF_ARG1 X86_REGF_RDI #define X86_STDF_ARG2 X86_REGF_RSI #define X86_STDF_ARG3 X86_REGF_RDX #define X86_STD_ARG1 X86_REG_RDI #define X86_STD_ARG2 X86_REG_RSI #define X86_STD_ARG3 X86_REG_RDX /* * Our run-time library calling convention. We use the microsoft ABI * for this because it retains more registers across the call and the * RAS registerizer needs as many registers as it can get. This can * be specified in GCC and CLANG in a way that allows ABI mixing * (we don't want to force libc and dynamic libs to be recompiled too!). * * This ABI is not used for system and library interfacing calls. * * The microsoft ABI: * Call-saved registers: * RBX, RBP, R12, R13, R14, R15, and RSP * + RDI, RSI, XMM6-XMM15 (additional) * * Argument passing: * RCX, RDX, R8, R9 * * * We want our run-time calls to preserve more registers to reduce the * burden on the RAS register allocator. Note that the RAS instruction * generator itself needs to use %rax, %rcx, %xmm0-3, and the run-time * argument registers. Those must never be specified on the call-saved * list. * * This must match the RUNERUNTIME() API in libruntime. */ #define X86_REGF_CALLSAVE_RUNTIME \ (X86_REGF_RBX | X86_REGF_RBP | X86_REGF_RDI | X86_REGF_RSI | \ X86_REGF_R12 | X86_REGF_R13 | X86_REGF_R14 | X86_REGF_R15 | \ X86_REGF_XMM6 | X86_REGF_XMM7 | 0 | 0 | \ X86_REGF_XMM8 | X86_REGF_XMM9 | X86_REGF_XMM10| X86_REGF_XMM11 | \ X86_REGF_XMM12| X86_REGF_XMM13| X86_REGF_XMM14| X86_REGF_XMM15) #define X86_RUNTIMEF_ARG1 X86_REGF_RCX #define X86_RUNTIMEF_ARG2 X86_REGF_RDX #define X86_RUNTIMEF_ARG3 X86_REGF_R8 #define X86_RUNTIME_ARG1 X86_REG_RCX #define X86_RUNTIME_ARG2 X86_REG_RDX #define X86_RUNTIME_ARG3 X86_REG_R8 /* * Our standard Rune calling convention also needs to preserve as many * registers as possible to make the RAS register allocator work better. * Use the same convention as RUNTIME. * * These conventions are used for rune-to-rune calls. * * WARNING! rune_entry_main's ABI (e.g. set to ms_abi) must be compatible. */ #define X86_REGF_CALLSAVE_RUNE X86_REGF_CALLSAVE_RUNTIME #define X86_RUNEF_ARG1 X86_REGF_RCX #define X86_RUNEF_ARG2 X86_REGF_RDX #define X86_RUNEF_ARG3 X86_REGF_R8 #define X86_RUNE_ARG1 X86_REG_RCX #define X86_RUNE_ARG2 X86_REG_RDX #define X86_RUNE_ARG3 X86_REG_R8 /* * Scratch on return registers */ #define X86_REGF_CALLSCR_STD (~X86_REGF_CALLSAVE_STD & X86_REGF_GOOD) #define X86_REGF_CALLSCR_RUNTIME (~X86_REGF_CALLSAVE_RUNTIME & X86_REGF_GOOD) #define X86_REGF_CALLSCR_RUNE (~X86_REGF_CALLSAVE_RUNE & X86_REGF_GOOD)