2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/icu/icu_var.h>
60 #include <machine_base/apic/ioapic_abi.h>
61 #include <machine_base/apic/lapic.h>
62 #include <machine_base/apic/ioapic.h>
63 #include <machine/psl.h>
64 #include <machine/segments.h>
65 #include <machine/tss.h>
66 #include <machine/specialreg.h>
67 #include <machine/globaldata.h>
68 #include <machine/pmap_inval.h>
70 #include <machine/md_var.h> /* setidt() */
71 #include <machine_base/icu/icu.h> /* IPIs */
72 #include <machine/intr_machdep.h> /* IPIs */
74 #define WARMBOOT_TARGET 0
75 #define WARMBOOT_OFF (KERNBASE + 0x0467)
76 #define WARMBOOT_SEG (KERNBASE + 0x0469)
78 #define CMOS_REG (0x70)
79 #define CMOS_DATA (0x71)
80 #define BIOS_RESET (0x0f)
81 #define BIOS_WARM (0x0a)
84 * this code MUST be enabled here and in mpboot.s.
85 * it follows the very early stages of AP boot by placing values in CMOS ram.
86 * it NORMALLY will never be needed and thus the primitive method for enabling.
89 #if defined(CHECK_POINTS)
90 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
91 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
93 #define CHECK_INIT(D); \
94 CHECK_WRITE(0x34, (D)); \
95 CHECK_WRITE(0x35, (D)); \
96 CHECK_WRITE(0x36, (D)); \
97 CHECK_WRITE(0x37, (D)); \
98 CHECK_WRITE(0x38, (D)); \
99 CHECK_WRITE(0x39, (D));
101 #define CHECK_PRINT(S); \
102 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
111 #else /* CHECK_POINTS */
113 #define CHECK_INIT(D)
114 #define CHECK_PRINT(S)
116 #endif /* CHECK_POINTS */
119 * Values to send to the POST hardware.
121 #define MP_BOOTADDRESS_POST 0x10
122 #define MP_PROBE_POST 0x11
123 #define MPTABLE_PASS1_POST 0x12
125 #define MP_START_POST 0x13
126 #define MP_ENABLE_POST 0x14
127 #define MPTABLE_PASS2_POST 0x15
129 #define START_ALL_APS_POST 0x16
130 #define INSTALL_AP_TRAMP_POST 0x17
131 #define START_AP_POST 0x18
133 #define MP_ANNOUNCE_POST 0x19
135 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
136 int current_postcode;
138 /** XXX FIXME: what system files declare these??? */
139 extern struct region_descriptor r_gdt, r_idt;
141 int mp_naps; /* # of Applications processors */
145 extern int64_t tsc_offsets[];
147 #ifdef SMP /* APIC-IO */
148 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
151 /* AP uses this during bootstrap. Do not staticize. */
155 /* Hotwire a 0->4MB V==P mapping */
156 extern pt_entry_t *KPTphys;
159 * SMP page table page. Setup by locore to point to a page table
160 * page from which we allocate per-cpu privatespace areas io_apics,
163 extern pt_entry_t *SMPpt;
165 struct pcb stoppcbs[MAXCPU];
168 * Local data and functions.
171 static u_int boot_address;
172 static int mp_finish;
173 static int mp_finish_lapic;
175 static void mp_enable(u_int boot_addr);
177 static int start_all_aps(u_int boot_addr);
178 static void install_ap_tramp(u_int boot_addr);
179 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
180 static int smitest(void);
181 static void cpu_simple_setup(void);
183 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
184 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
185 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
186 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
192 * Calculate usable address in base memory for AP trampoline code.
195 mp_bootaddress(u_int basemem)
197 POSTCODE(MP_BOOTADDRESS_POST);
199 base_memory = basemem;
201 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
202 if ((base_memory - boot_address) < bootMP_size)
203 boot_address -= 4096; /* not enough, lower by 4k */
209 * Startup the SMP processors.
214 POSTCODE(MP_START_POST);
215 mp_enable(boot_address);
220 * Print various information about the SMP system hardware and setup.
227 POSTCODE(MP_ANNOUNCE_POST);
229 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
230 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
231 for (x = 1; x <= mp_naps; ++x)
232 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
235 kprintf(" Warning: APIC I/O disabled\n");
239 * AP cpu's call this to sync up protected mode.
241 * WARNING! We must ensure that the cpu is sufficiently initialized to
242 * be able to use to the FP for our optimized bzero/bcopy code before
243 * we enter more mainstream C code.
245 * WARNING! %fs is not set up on entry. This routine sets up %fs.
251 int x, myid = bootAP;
253 struct mdglobaldata *md;
254 struct privatespace *ps;
256 ps = &CPU_prvspace[myid];
258 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
259 gdt_segs[GPROC0_SEL].ssd_base =
260 (int) &ps->mdglobaldata.gd_common_tss;
261 ps->mdglobaldata.mi.gd_prvspace = ps;
263 for (x = 0; x < NGDT; x++) {
264 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
267 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
268 r_gdt.rd_base = (int) &gdt[myid * NGDT];
269 lgdt(&r_gdt); /* does magic intra-segment return */
274 mdcpu->gd_currentldt = _default_ldt;
276 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
277 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
279 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
281 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
282 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
283 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
284 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
285 md->gd_common_tssd = *md->gd_tss_gdt;
289 * Set to a known state:
290 * Set by mpboot.s: CR0_PG, CR0_PE
291 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
294 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
296 pmap_set_opt(); /* PSE/4MB pages, etc */
298 /* set up CPU registers and state */
301 /* set up FPU state on the AP */
302 npxinit(__INITIAL_NPXCW__);
304 /* set up SSE registers */
308 /*******************************************************************
309 * local functions and data
313 * start the SMP system
316 mp_enable(u_int boot_addr)
320 POSTCODE(MP_ENABLE_POST);
322 error = lapic_config();
324 if (apic_io_enable) {
326 icu_reinit_noioapic();
332 /* Initialize BSP's local APIC */
335 /* start each Application Processor */
336 start_all_aps(boot_addr);
338 if (apic_io_enable) {
339 error = ioapic_config();
342 icu_reinit_noioapic();
343 lapic_fixup_noioapic();
349 * start each AP in our list
352 start_all_aps(u_int boot_addr)
360 u_long mpbioswarmvec;
361 struct mdglobaldata *gd;
362 struct privatespace *ps;
366 POSTCODE(START_ALL_APS_POST);
368 /* install the AP 1st level boot code */
369 install_ap_tramp(boot_addr);
372 /* save the current value of the warm-start vector */
373 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
374 outb(CMOS_REG, BIOS_RESET);
375 mpbiosreason = inb(CMOS_DATA);
377 /* setup a vector to our boot code */
378 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
379 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
380 outb(CMOS_REG, BIOS_RESET);
381 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
384 * If we have a TSC we can figure out the SMI interrupt rate.
385 * The SMI does not necessarily use a constant rate. Spend
386 * up to 250ms trying to figure it out.
389 if (cpu_feature & CPUID_TSC) {
390 set_apic_timer(275000);
391 smilast = read_apic_timer();
392 for (x = 0; x < 20 && read_apic_timer(); ++x) {
393 smicount = smitest();
394 if (smibest == 0 || smilast - smicount < smibest)
395 smibest = smilast - smicount;
398 if (smibest > 250000)
401 smibest = smibest * (int64_t)1000000 /
402 get_apic_timer_frequency();
406 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
407 1000000 / smibest, smibest);
410 /* set up temporary P==V mapping for AP boot */
411 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
412 kptbase = (uintptr_t)(void *)KPTphys;
413 for (x = 0; x < NKPT; x++) {
414 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
415 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
420 for (x = 1; x <= mp_naps; ++x) {
422 /* This is a bit verbose, it will go away soon. */
424 /* first page of AP's private space */
425 pg = x * i386_btop(sizeof(struct privatespace));
427 /* allocate new private data page(s) */
428 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
429 MDGLOBALDATA_BASEALLOC_SIZE);
430 /* wire it into the private page table page */
431 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
432 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
433 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
435 pg += MDGLOBALDATA_BASEALLOC_PAGES;
437 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
438 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
439 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
440 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
442 /* allocate and set up an idle stack data page */
443 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
444 for (i = 0; i < UPAGES; i++) {
445 SMPpt[pg + 4 + i] = (pt_entry_t)
446 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
449 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
450 bzero(gd, sizeof(*gd));
451 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
453 /* prime data page for it to use */
454 mi_gdinit(&gd->mi, x);
456 gd->gd_CMAP1 = &SMPpt[pg + 0];
457 gd->gd_CMAP2 = &SMPpt[pg + 1];
458 gd->gd_CMAP3 = &SMPpt[pg + 2];
459 gd->gd_PMAP1 = &SMPpt[pg + 3];
460 gd->gd_CADDR1 = ps->CPAGE1;
461 gd->gd_CADDR2 = ps->CPAGE2;
462 gd->gd_CADDR3 = ps->CPAGE3;
463 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
466 * Per-cpu pmap for get_ptbase().
468 gd->gd_GDADDR1= (unsigned *)
469 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
470 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
472 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
473 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
476 * Setup the AP boot stack
478 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
481 /* attempt to start the Application Processor */
482 CHECK_INIT(99); /* setup checkpoints */
483 if (!start_ap(gd, boot_addr, smibest)) {
484 kprintf("AP #%d (PHY# %d) failed!\n", x,
486 CHECK_PRINT("trace"); /* show checkpoints */
487 /* better panic as the AP may be running loose */
488 kprintf("panic y/n? [y] ");
492 CHECK_PRINT("trace"); /* show checkpoints */
495 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
498 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
499 for (shift = 0; (1 << shift) <= ncpus; ++shift)
502 ncpus2_shift = shift;
504 ncpus2_mask = ncpus2 - 1;
506 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
507 if ((1 << shift) < ncpus)
509 ncpus_fit = 1 << shift;
510 ncpus_fit_mask = ncpus_fit - 1;
512 /* build our map of 'other' CPUs */
513 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
514 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
515 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
517 /* restore the warmstart vector */
518 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
519 outb(CMOS_REG, BIOS_RESET);
520 outb(CMOS_DATA, mpbiosreason);
523 * NOTE! The idlestack for the BSP was setup by locore. Finish
524 * up, clean out the P==V mapping we did earlier.
526 for (x = 0; x < NKPT; x++)
531 * Wait all APs to finish initializing LAPIC
535 kprintf("SMP: Waiting APs LAPIC initialization\n");
536 if (cpu_feature & CPUID_TSC)
537 tsc0_offset = rdtsc();
540 while (smp_lapic_mask != smp_startup_mask) {
542 if (cpu_feature & CPUID_TSC)
543 tsc0_offset = rdtsc();
545 while (try_mplock() == 0)
548 /* number of APs actually started */
553 * load the 1st level AP boot code into base memory.
556 /* targets for relocation */
557 extern void bigJump(void);
558 extern void bootCodeSeg(void);
559 extern void bootDataSeg(void);
560 extern void MPentry(void);
562 extern u_int mp_gdtbase;
565 install_ap_tramp(u_int boot_addr)
568 int size = *(int *) ((u_long) & bootMP_size);
569 u_char *src = (u_char *) ((u_long) bootMP);
570 u_char *dst = (u_char *) boot_addr + KERNBASE;
571 u_int boot_base = (u_int) bootMP;
576 POSTCODE(INSTALL_AP_TRAMP_POST);
578 for (x = 0; x < size; ++x)
582 * modify addresses in code we just moved to basemem. unfortunately we
583 * need fairly detailed info about mpboot.s for this to work. changes
584 * to mpboot.s might require changes here.
587 /* boot code is located in KERNEL space */
588 dst = (u_char *) boot_addr + KERNBASE;
590 /* modify the lgdt arg */
591 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
592 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
594 /* modify the ljmp target for MPentry() */
595 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
596 *dst32 = ((u_int) MPentry - KERNBASE);
598 /* modify the target for boot code segment */
599 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
600 dst8 = (u_int8_t *) (dst16 + 1);
601 *dst16 = (u_int) boot_addr & 0xffff;
602 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
604 /* modify the target for boot data segment */
605 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
606 dst8 = (u_int8_t *) (dst16 + 1);
607 *dst16 = (u_int) boot_addr & 0xffff;
608 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
613 * This function starts the AP (application processor) identified
614 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
615 * to accomplish this. This is necessary because of the nuances
616 * of the different hardware we might encounter. It ain't pretty,
617 * but it seems to work.
619 * NOTE: eventually an AP gets to ap_init(), which is called just
620 * before the AP goes into the LWKT scheduler's idle loop.
623 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
627 u_long icr_lo, icr_hi;
629 POSTCODE(START_AP_POST);
631 /* get the PHYSICAL APIC ID# */
632 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
634 /* calculate the vector */
635 vector = (boot_addr >> 12) & 0xff;
637 /* We don't want anything interfering */
640 /* Make sure the target cpu sees everything */
644 * Try to detect when a SMI has occurred, wait up to 200ms.
646 * If a SMI occurs during an AP reset but before we issue
647 * the STARTUP command, the AP may brick. To work around
648 * this problem we hold off doing the AP startup until
649 * after we have detected the SMI. Hopefully another SMI
650 * will not occur before we finish the AP startup.
652 * Retries don't seem to help. SMIs have a window of opportunity
653 * and if USB->legacy keyboard emulation is enabled in the BIOS
654 * the interrupt rate can be quite high.
656 * NOTE: Don't worry about the L1 cache load, it might bloat
657 * ldelta a little but ndelta will be so huge when the SMI
658 * occurs the detection logic will still work fine.
661 set_apic_timer(200000);
666 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
667 * and running the target CPU. OR this INIT IPI might be latched (P5
668 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
671 * see apic/apicreg.h for icr bit definitions.
673 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
677 * Setup the address for the target AP. We can setup
678 * icr_hi once and then just trigger operations with
681 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
682 icr_hi |= (physical_cpu << 24);
683 icr_lo = lapic->icr_lo & 0xfff00000;
684 lapic->icr_hi = icr_hi;
687 * Do an INIT IPI: assert RESET
689 * Use edge triggered mode to assert INIT
691 lapic->icr_lo = icr_lo | 0x0000c500;
692 while (lapic->icr_lo & APIC_DELSTAT_MASK)
696 * The spec calls for a 10ms delay but we may have to use a
697 * MUCH lower delay to avoid bricking an AP due to a fast SMI
698 * interrupt. We have other loops here too and dividing by 2
699 * doesn't seem to be enough even after subtracting 350us,
702 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
703 * interrupt was detected we use the full 10ms.
707 else if (smibest < 150 * 4 + 350)
709 else if ((smibest - 350) / 4 < 10000)
710 u_sleep((smibest - 350) / 4);
715 * Do an INIT IPI: deassert RESET
717 * Use level triggered mode to deassert. It is unclear
718 * why we need to do this.
720 lapic->icr_lo = icr_lo | 0x00008500;
721 while (lapic->icr_lo & APIC_DELSTAT_MASK)
723 u_sleep(150); /* wait 150us */
726 * Next we do a STARTUP IPI: the previous INIT IPI might still be
727 * latched, (P5 bug) this 1st STARTUP would then terminate
728 * immediately, and the previously started INIT IPI would continue. OR
729 * the previous INIT IPI has already run. and this STARTUP IPI will
730 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
733 lapic->icr_lo = icr_lo | 0x00000600 | vector;
734 while (lapic->icr_lo & APIC_DELSTAT_MASK)
736 u_sleep(200); /* wait ~200uS */
739 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
740 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
741 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
742 * recognized after hardware RESET or INIT IPI.
744 lapic->icr_lo = icr_lo | 0x00000600 | vector;
745 while (lapic->icr_lo & APIC_DELSTAT_MASK)
748 /* Resume normal operation */
751 /* wait for it to start, see ap_init() */
752 set_apic_timer(5000000);/* == 5 seconds */
753 while (read_apic_timer()) {
754 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
755 return 1; /* return SUCCESS */
758 return 0; /* return FAILURE */
773 while (read_apic_timer()) {
775 for (count = 0; count < 100; ++count)
776 ntsc = rdtsc(); /* force loop to occur */
778 ndelta = ntsc - ltsc;
781 if (ndelta > ldelta * 2)
784 ldelta = ntsc - ltsc;
787 return(read_apic_timer());
791 * Lazy flush the TLB on all other CPU's. DEPRECATED.
793 * If for some reason we were unable to start all cpus we cannot safely
794 * use broadcast IPIs.
797 static cpumask_t smp_invltlb_req;
798 #define SMP_INVLTLB_DEBUG
804 struct mdglobaldata *md = mdcpu;
805 #ifdef SMP_INVLTLB_DEBUG
810 crit_enter_gd(&md->mi);
811 md->gd_invltlb_ret = 0;
812 ++md->mi.gd_cnt.v_smpinvltlb;
813 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
814 #ifdef SMP_INVLTLB_DEBUG
817 if (smp_startup_mask == smp_active_mask) {
818 all_but_self_ipi(XINVLTLB_OFFSET);
820 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
821 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
824 #ifdef SMP_INVLTLB_DEBUG
826 kprintf("smp_invltlb: ipi sent\n");
828 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
829 (smp_active_mask & ~md->mi.gd_cpumask)) {
832 #ifdef SMP_INVLTLB_DEBUG
834 if (++count == 400000000) {
836 kprintf("smp_invltlb: endless loop %08lx %08lx, "
837 "rflags %016lx retry",
838 (long)md->gd_invltlb_ret,
839 (long)smp_invltlb_req,
840 (long)read_eflags());
841 __asm __volatile ("sti");
846 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
850 kprintf("bcpu %d\n", bcpu);
851 xgd = globaldata_find(bcpu);
852 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
861 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
862 crit_exit_gd(&md->mi);
869 * Called from Xinvltlb assembly with interrupts disabled. We didn't
870 * bother to bump the critical section count or nested interrupt count
871 * so only do very low level operations here.
874 smp_invltlb_intr(void)
876 struct mdglobaldata *md = mdcpu;
877 struct mdglobaldata *omd;
881 mask = smp_invltlb_req;
885 cpu = BSFCPUMASK(mask);
886 mask &= ~CPUMASK(cpu);
887 omd = (struct mdglobaldata *)globaldata_find(cpu);
888 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
895 * When called the executing CPU will send an IPI to all other CPUs
896 * requesting that they halt execution.
898 * Usually (but not necessarily) called with 'other_cpus' as its arg.
900 * - Signals all CPUs in map to stop.
901 * - Waits for each to stop.
908 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
909 * from executing at same time.
912 stop_cpus(cpumask_t map)
914 map &= smp_active_mask;
916 /* send the Xcpustop IPI to all CPUs in map */
917 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
919 while ((stopped_cpus & map) != map)
927 * Called by a CPU to restart stopped CPUs.
929 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
931 * - Signals all CPUs in map to restart.
932 * - Waits for each to restart.
940 restart_cpus(cpumask_t map)
942 /* signal other cpus to restart */
943 started_cpus = map & smp_active_mask;
945 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
952 * This is called once the mpboot code has gotten us properly relocated
953 * and the MMU turned on, etc. ap_init() is actually the idle thread,
954 * and when it returns the scheduler will call the real cpu_idle() main
955 * loop for the idlethread. Interrupts are disabled on entry and should
956 * remain disabled at return.
964 * Adjust smp_startup_mask to signal the BSP that we have started
965 * up successfully. Note that we do not yet hold the BGL. The BSP
966 * is waiting for our signal.
968 * We can't set our bit in smp_active_mask yet because we are holding
969 * interrupts physically disabled and remote cpus could deadlock
970 * trying to send us an IPI.
972 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
976 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
977 * non-zero, then get the MP lock.
979 * Note: We are in a critical section.
981 * Note: we are the idle thread, we can only spin.
983 * Note: The load fence is memory volatile and prevents the compiler
984 * from improperly caching mp_finish_lapic, and the cpu from improperly
987 while (mp_finish_lapic == 0)
989 while (try_mplock() == 0)
992 if (cpu_feature & CPUID_TSC) {
994 * The BSP is constantly updating tsc0_offset, figure out
995 * the relative difference to synchronize ktrdump.
997 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1000 /* BSP may have changed PTD while we're waiting for the lock */
1003 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1007 /* Build our map of 'other' CPUs. */
1008 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1010 /* A quick check from sanity claus */
1011 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
1012 if (mycpu->gd_cpuid != cpu_id) {
1013 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
1014 kprintf("SMP: actual cpuid = %d\n", cpu_id);
1015 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1016 panic("cpuid mismatch! boom!!");
1019 /* Initialize AP's local APIC for irq's */
1022 /* LAPIC initialization is done */
1023 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1026 /* Let BSP move onto the next initialization stage */
1030 * Interlock for finalization. Wait until mp_finish is non-zero,
1031 * then get the MP lock.
1033 * Note: We are in a critical section.
1035 * Note: we are the idle thread, we can only spin.
1037 * Note: The load fence is memory volatile and prevents the compiler
1038 * from improperly caching mp_finish, and the cpu from improperly
1041 while (mp_finish == 0)
1043 while (try_mplock() == 0)
1046 /* BSP may have changed PTD while we're waiting for the lock */
1049 /* Set memory range attributes for this CPU to match the BSP */
1050 mem_range_AP_init();
1053 * Once we go active we must process any IPIQ messages that may
1054 * have been queued, because no actual IPI will occur until we
1055 * set our bit in the smp_active_mask. If we don't the IPI
1056 * message interlock could be left set which would also prevent
1059 * The idle loop doesn't expect the BGL to be held and while
1060 * lwkt_switch() normally cleans things up this is a special case
1061 * because we returning almost directly into the idle loop.
1063 * The idle thread is never placed on the runq, make sure
1064 * nothing we've done put it there.
1066 KKASSERT(get_mplock_count(curthread) == 1);
1067 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1070 * Enable interrupts here. idle_restore will also do it, but
1071 * doing it here lets us clean up any strays that got posted to
1072 * the CPU during the AP boot while we are still in a critical
1075 __asm __volatile("sti; pause; pause"::);
1076 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1078 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1079 lwkt_process_ipiq();
1082 * Releasing the mp lock lets the BSP finish up the SMP init
1085 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1089 * Get SMP fully working before we start initializing devices.
1097 kprintf("Finish MP startup\n");
1099 while (smp_active_mask != smp_startup_mask)
1101 while (try_mplock() == 0)
1104 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
1107 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1110 cpu_send_ipiq(int dcpu)
1112 if (CPUMASK(dcpu) & smp_active_mask)
1113 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1116 #if 0 /* single_apic_ipi_passive() not working yet */
1118 * Returns 0 on failure, 1 on success
1121 cpu_send_ipiq_passive(int dcpu)
1124 if (CPUMASK(dcpu) & smp_active_mask) {
1125 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1126 APIC_DELMODE_FIXED);
1133 cpu_simple_setup(void)
1135 /* build our map of 'other' CPUs */
1136 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1137 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1138 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1142 if (cpu_feature & CPUID_TSC)
1143 tsc0_offset = rdtsc();