1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */
2 /* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */
3 /* $DragonFly: src/sys/dev/netif/txp/if_txp.c,v 1.22 2005/06/10 16:10:42 joerg Exp $ */
7 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and
8 * Aaron Campbell <aaron@monkey.org>. All rights reserved.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright,
21 * Theo de Raadt and Aaron Campbell.
22 * 4. Neither the name of the author nor the names of any co-contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
36 * THE POSSIBILITY OF SUCH DAMAGE.
40 * Driver for 3c990 (Typhoon) Ethernet ASIC
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
47 #include <sys/malloc.h>
48 #include <sys/kernel.h>
49 #include <sys/socket.h>
50 #include <sys/thread2.h>
53 #include <net/ifq_var.h>
54 #include <net/if_arp.h>
55 #include <net/ethernet.h>
56 #include <net/if_dl.h>
57 #include <net/if_types.h>
58 #include <net/vlan/if_vlan_var.h>
60 #include <netinet/in.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/in_var.h>
63 #include <netinet/ip.h>
64 #include <netinet/if_ether.h>
65 #include <sys/in_cksum.h>
67 #include <net/if_media.h>
71 #include <vm/vm.h> /* for vtophys */
72 #include <vm/pmap.h> /* for vtophys */
73 #include <machine/clock.h> /* for DELAY */
74 #include <machine/bus_pio.h>
75 #include <machine/bus_memio.h>
76 #include <machine/bus.h>
77 #include <machine/resource.h>
81 #include "../mii_layer/mii.h"
82 #include "../mii_layer/miivar.h"
83 #include <bus/pci/pcireg.h>
84 #include <bus/pci/pcivar.h>
86 #define TXP_USEIOSPACE
87 #define __STRICT_ALIGNMENT
89 #include "if_txpreg.h"
93 * Various supported device vendors/types and their names.
95 static struct txp_type txp_devs[] = {
96 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95,
97 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
98 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97,
99 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM,
101 "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95,
103 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97,
105 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV,
107 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
111 static int txp_probe (device_t);
112 static int txp_attach (device_t);
113 static int txp_detach (device_t);
114 static void txp_intr (void *);
115 static void txp_tick (void *);
116 static int txp_shutdown (device_t);
117 static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *);
118 static void txp_start (struct ifnet *);
119 static void txp_stop (struct txp_softc *);
120 static void txp_init (void *);
121 static void txp_watchdog (struct ifnet *);
123 static void txp_release_resources (struct txp_softc *);
124 static int txp_chip_init (struct txp_softc *);
125 static int txp_reset_adapter (struct txp_softc *);
126 static int txp_download_fw (struct txp_softc *);
127 static int txp_download_fw_wait (struct txp_softc *);
128 static int txp_download_fw_section (struct txp_softc *,
129 struct txp_fw_section_header *, int);
130 static int txp_alloc_rings (struct txp_softc *);
131 static int txp_rxring_fill (struct txp_softc *);
132 static void txp_rxring_empty (struct txp_softc *);
133 static void txp_set_filter (struct txp_softc *);
135 static int txp_cmd_desc_numfree (struct txp_softc *);
136 static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
137 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
138 static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t,
139 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
140 struct txp_rsp_desc **, int);
141 static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
142 struct txp_rsp_desc **);
143 static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *,
144 struct txp_rsp_desc *);
145 static void txp_capabilities (struct txp_softc *);
147 static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *);
148 static int txp_ifmedia_upd (struct ifnet *);
150 static void txp_show_descriptor (void *);
152 static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *);
153 static void txp_rxbuf_reclaim (struct txp_softc *);
154 static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *);
156 #ifdef TXP_USEIOSPACE
157 #define TXP_RES SYS_RES_IOPORT
158 #define TXP_RID TXP_PCI_LOIO
160 #define TXP_RES SYS_RES_MEMORY
161 #define TXP_RID TXP_PCI_LOMEM
164 static device_method_t txp_methods[] = {
165 /* Device interface */
166 DEVMETHOD(device_probe, txp_probe),
167 DEVMETHOD(device_attach, txp_attach),
168 DEVMETHOD(device_detach, txp_detach),
169 DEVMETHOD(device_shutdown, txp_shutdown),
173 static driver_t txp_driver = {
176 sizeof(struct txp_softc)
179 static devclass_t txp_devclass;
181 DECLARE_DUMMY_MODULE(if_txp);
182 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0);
192 while(t->txp_name != NULL) {
193 if ((pci_get_vendor(dev) == t->txp_vid) &&
194 (pci_get_device(dev) == t->txp_did)) {
195 device_set_desc(dev, t->txp_name);
208 struct txp_softc *sc;
213 int unit, error = 0, rid;
215 sc = device_get_softc(dev);
216 unit = device_get_unit(dev);
219 callout_init(&sc->txp_stat_timer);
222 * Map control/status registers.
224 command = pci_read_config(dev, PCIR_COMMAND, 4);
225 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
226 pci_write_config(dev, PCIR_COMMAND, command, 4);
227 command = pci_read_config(dev, PCIR_COMMAND, 4);
229 #ifdef TXP_USEIOSPACE
230 if (!(command & PCIM_CMD_PORTEN)) {
231 device_printf(dev, "failed to enable I/O ports!\n");
236 if (!(command & PCIM_CMD_MEMEN)) {
237 device_printf(dev, "failed to enable memory mapping!\n");
244 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE);
246 if (sc->sc_res == NULL) {
247 device_printf(dev, "couldn't map ports/memory\n");
252 sc->sc_bt = rman_get_bustag(sc->sc_res);
253 sc->sc_bh = rman_get_bushandle(sc->sc_res);
255 /* Allocate interrupt */
257 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
258 RF_SHAREABLE | RF_ACTIVE);
260 if (sc->sc_irq == NULL) {
261 device_printf(dev, "couldn't map interrupt\n");
262 txp_release_resources(sc);
267 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET,
268 txp_intr, sc, &sc->sc_intrhand, NULL);
271 txp_release_resources(sc);
272 device_printf(dev, "couldn't set up irq\n");
276 if (txp_chip_init(sc)) {
277 txp_release_resources(sc);
281 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
282 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
283 error = txp_download_fw(sc);
284 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
288 txp_release_resources(sc);
292 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
293 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
294 bzero(sc->sc_ldata, sizeof(struct txp_ldata));
296 if (txp_alloc_rings(sc)) {
297 txp_release_resources(sc);
301 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
302 NULL, NULL, NULL, 1)) {
303 txp_release_resources(sc);
307 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
308 &p1, &p2, NULL, 1)) {
309 txp_release_resources(sc);
315 sc->sc_arpcom.ac_enaddr[0] = ((uint8_t *)&p1)[1];
316 sc->sc_arpcom.ac_enaddr[1] = ((uint8_t *)&p1)[0];
317 sc->sc_arpcom.ac_enaddr[2] = ((uint8_t *)&p2)[3];
318 sc->sc_arpcom.ac_enaddr[3] = ((uint8_t *)&p2)[2];
319 sc->sc_arpcom.ac_enaddr[4] = ((uint8_t *)&p2)[1];
320 sc->sc_arpcom.ac_enaddr[5] = ((uint8_t *)&p2)[0];
324 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
325 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
326 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
327 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
328 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
329 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
330 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
331 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
333 sc->sc_xcvr = TXP_XCVR_AUTO;
334 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
335 NULL, NULL, NULL, 0);
336 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
338 ifp = &sc->sc_arpcom.ac_if;
340 if_initname(ifp, "txp", unit);
341 ifp->if_mtu = ETHERMTU;
342 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
343 ifp->if_ioctl = txp_ioctl;
344 ifp->if_start = txp_start;
345 ifp->if_watchdog = txp_watchdog;
346 ifp->if_init = txp_init;
347 ifp->if_baudrate = 100000000;
348 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES);
349 ifq_set_ready(&ifp->if_snd);
350 ifp->if_hwassist = 0;
351 txp_capabilities(sc);
354 * Attach us everywhere
356 ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr);
360 txp_release_resources(sc);
368 struct txp_softc *sc;
372 sc = device_get_softc(dev);
373 ifp = &sc->sc_arpcom.ac_if;
378 ifmedia_removeall(&sc->sc_ifmedia);
381 for (i = 0; i < RXBUF_ENTRIES; i++)
382 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
384 txp_release_resources(sc);
390 txp_release_resources(sc)
391 struct txp_softc *sc;
397 if (sc->sc_intrhand != NULL)
398 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
400 if (sc->sc_irq != NULL)
401 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
403 if (sc->sc_res != NULL)
404 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
406 if (sc->sc_ldata != NULL)
407 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
414 struct txp_softc *sc;
416 /* disable interrupts */
417 WRITE_REG(sc, TXP_IER, 0);
418 WRITE_REG(sc, TXP_IMR,
419 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
420 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
423 /* ack all interrupts */
424 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
425 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
426 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
427 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
428 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
430 if (txp_reset_adapter(sc))
433 /* disable interrupts */
434 WRITE_REG(sc, TXP_IER, 0);
435 WRITE_REG(sc, TXP_IMR,
436 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
437 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
440 /* ack all interrupts */
441 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
442 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
443 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
444 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
445 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
451 txp_reset_adapter(sc)
452 struct txp_softc *sc;
457 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
459 WRITE_REG(sc, TXP_SRR, 0);
461 /* Should wait max 6 seconds */
462 for (i = 0; i < 6000; i++) {
463 r = READ_REG(sc, TXP_A2H_0);
464 if (r == STAT_WAITING_FOR_HOST_REQUEST)
469 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
470 device_printf(sc->sc_dev, "reset hung\n");
479 struct txp_softc *sc;
481 struct txp_fw_file_header *fileheader;
482 struct txp_fw_section_header *secthead;
484 u_int32_t r, i, ier, imr;
486 ier = READ_REG(sc, TXP_IER);
487 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
489 imr = READ_REG(sc, TXP_IMR);
490 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
492 for (i = 0; i < 10000; i++) {
493 r = READ_REG(sc, TXP_A2H_0);
494 if (r == STAT_WAITING_FOR_HOST_REQUEST)
498 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
499 device_printf(sc->sc_dev, "not waiting for host request\n");
504 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
506 fileheader = (struct txp_fw_file_header *)tc990image;
507 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
508 device_printf(sc->sc_dev, "fw invalid magic\n");
512 /* Tell boot firmware to get ready for image */
513 WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
514 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
516 if (txp_download_fw_wait(sc)) {
517 device_printf(sc->sc_dev, "fw wait failed, initial\n");
521 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
522 sizeof(struct txp_fw_file_header));
524 for (sect = 0; sect < fileheader->nsections; sect++) {
525 if (txp_download_fw_section(sc, secthead, sect))
527 secthead = (struct txp_fw_section_header *)
528 (((u_int8_t *)secthead) + secthead->nbytes +
532 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
534 for (i = 0; i < 10000; i++) {
535 r = READ_REG(sc, TXP_A2H_0);
536 if (r == STAT_WAITING_FOR_BOOT)
540 if (r != STAT_WAITING_FOR_BOOT) {
541 device_printf(sc->sc_dev, "not waiting for boot\n");
545 WRITE_REG(sc, TXP_IER, ier);
546 WRITE_REG(sc, TXP_IMR, imr);
552 txp_download_fw_wait(sc)
553 struct txp_softc *sc;
557 for (i = 0; i < 10000; i++) {
558 r = READ_REG(sc, TXP_ISR);
559 if (r & TXP_INT_A2H_0)
564 if (!(r & TXP_INT_A2H_0)) {
565 device_printf(sc->sc_dev, "fw wait failed comm0\n");
569 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
571 r = READ_REG(sc, TXP_A2H_0);
572 if (r != STAT_WAITING_FOR_SEGMENT) {
573 device_printf(sc->sc_dev, "fw not waiting for segment\n");
580 txp_download_fw_section(sc, sect, sectnum)
581 struct txp_softc *sc;
582 struct txp_fw_section_header *sect;
590 /* Skip zero length sections */
591 if (sect->nbytes == 0)
594 /* Make sure we aren't past the end of the image */
595 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
596 if (rseg >= sizeof(tc990image)) {
597 device_printf(sc->sc_dev, "fw invalid section address, "
598 "section %d\n", sectnum);
602 /* Make sure this section doesn't go past the end */
603 rseg += sect->nbytes;
604 if (rseg >= sizeof(tc990image)) {
605 device_printf(sc->sc_dev, "fw truncated section %d\n",
610 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
611 dma = vtophys(sc->sc_fwbuf);
614 * dummy up mbuf and verify section checksum
617 m.m_next = m.m_nextpkt = NULL;
618 m.m_len = sect->nbytes;
619 m.m_data = sc->sc_fwbuf;
621 csum = in_cksum(&m, sect->nbytes);
622 if (csum != sect->cksum) {
623 device_printf(sc->sc_dev, "fw section %d, bad "
624 "cksum (expected 0x%x got 0x%x)\n",
625 sectnum, sect->cksum, csum);
630 WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
631 WRITE_REG(sc, TXP_H2A_2, sect->cksum);
632 WRITE_REG(sc, TXP_H2A_3, sect->addr);
633 WRITE_REG(sc, TXP_H2A_4, 0);
634 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
635 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
637 if (txp_download_fw_wait(sc)) {
638 device_printf(sc->sc_dev, "fw wait failed, "
639 "section %d\n", sectnum);
651 struct txp_softc *sc = vsc;
652 struct txp_hostvar *hv = sc->sc_hostvar;
655 /* mask all interrupts */
656 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
657 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
658 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
659 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
660 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
662 isr = READ_REG(sc, TXP_ISR);
664 WRITE_REG(sc, TXP_ISR, isr);
666 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
667 txp_rx_reclaim(sc, &sc->sc_rxhir);
668 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
669 txp_rx_reclaim(sc, &sc->sc_rxlor);
671 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
672 txp_rxbuf_reclaim(sc);
674 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
675 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
676 txp_tx_reclaim(sc, &sc->sc_txhir);
678 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
679 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
680 txp_tx_reclaim(sc, &sc->sc_txlor);
682 isr = READ_REG(sc, TXP_ISR);
685 /* unmask all interrupts */
686 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
688 txp_start(&sc->sc_arpcom.ac_if);
694 txp_rx_reclaim(sc, r)
695 struct txp_softc *sc;
696 struct txp_rx_ring *r;
698 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
699 struct txp_rx_desc *rxd;
701 struct txp_swdesc *sd = NULL;
702 u_int32_t roff, woff;
706 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
708 while (roff != woff) {
710 if (rxd->rx_flags & RX_FLAGS_ERROR) {
711 device_printf(sc->sc_dev, "error 0x%x\n",
717 /* retrieve stashed pointer */
723 m->m_pkthdr.len = m->m_len = rxd->rx_len;
725 #ifdef __STRICT_ALIGNMENT
728 * XXX Nice chip, except it won't accept "off by 2"
729 * buffers, so we're force to copy. Supposedly
730 * this will be fixed in a newer firmware rev
731 * and this will be temporary.
735 MGETHDR(mnew, MB_DONTWAIT, MT_DATA);
740 if (m->m_len > (MHLEN - 2)) {
741 MCLGET(mnew, MB_DONTWAIT);
742 if (!(mnew->m_flags & M_EXT)) {
748 mnew->m_pkthdr.rcvif = ifp;
750 mnew->m_pkthdr.len = mnew->m_len = m->m_len;
751 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t));
757 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
758 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
759 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
760 m->m_pkthdr.csum_flags |=
761 CSUM_IP_CHECKED|CSUM_IP_VALID;
763 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
764 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
765 m->m_pkthdr.csum_flags |=
766 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
767 m->m_pkthdr.csum_data = 0xffff;
770 if (rxd->rx_stat & RX_STAT_VLAN)
771 VLAN_INPUT_TAG(m, htons(rxd->rx_vlan >> 16));
773 (*ifp->if_input)(ifp, m);
777 roff += sizeof(struct txp_rx_desc);
778 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
792 txp_rxbuf_reclaim(sc)
793 struct txp_softc *sc;
795 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
796 struct txp_hostvar *hv = sc->sc_hostvar;
797 struct txp_rxbuf_desc *rbd;
798 struct txp_swdesc *sd;
801 if (!(ifp->if_flags & IFF_RUNNING))
804 i = sc->sc_rxbufprod;
805 rbd = sc->sc_rxbufs + i;
809 if (sd->sd_mbuf != NULL)
812 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
813 if (sd->sd_mbuf == NULL)
816 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
817 if ((sd->sd_mbuf->m_flags & M_EXT) == 0)
819 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
820 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
822 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
826 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
828 if (++i == RXBUF_ENTRIES) {
835 sc->sc_rxbufprod = i;
840 m_freem(sd->sd_mbuf);
846 * Reclaim mbufs and entries from a transmit ring.
849 txp_tx_reclaim(sc, r)
850 struct txp_softc *sc;
851 struct txp_tx_ring *r;
853 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
854 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
855 u_int32_t cons = r->r_cons, cnt = r->r_cnt;
856 struct txp_tx_desc *txd = r->r_desc + cons;
857 struct txp_swdesc *sd = sc->sc_txd + cons;
860 while (cons != idx) {
864 if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
865 TX_FLAGS_TYPE_DATA) {
874 ifp->if_flags &= ~IFF_OACTIVE;
876 if (++cons == TX_ENTRIES) {
898 struct txp_softc *sc;
900 sc = device_get_softc(dev);
902 /* mask all interrupts */
903 WRITE_REG(sc, TXP_IMR,
904 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
905 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
908 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
909 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
910 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
917 struct txp_softc *sc;
919 struct txp_boot_record *boot;
920 struct txp_ldata *ld;
925 boot = &ld->txp_boot;
931 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
932 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
933 boot->br_hostvar_hi = 0;
934 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
936 /* hi priority tx ring */
937 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);;
938 boot->br_txhipri_hi = 0;
939 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
940 sc->sc_txhir.r_reg = TXP_H2A_1;
941 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
942 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
943 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
945 /* lo priority tx ring */
946 boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
947 boot->br_txlopri_hi = 0;
948 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
949 sc->sc_txlor.r_reg = TXP_H2A_3;
950 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
951 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
952 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
954 /* high priority rx ring */
955 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
956 boot->br_rxhipri_hi = 0;
957 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
958 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
959 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
960 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
962 /* low priority rx ring */
963 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
964 boot->br_rxlopri_hi = 0;
965 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
966 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
967 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
968 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
971 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
972 boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
974 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
975 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
976 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
977 sc->sc_cmdring.lastwrite = 0;
980 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
981 boot->br_resp_lo = vtophys(&ld->txp_rspring);
982 boot->br_resp_hi = 0;
983 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
984 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
985 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
986 sc->sc_rspring.lastwrite = 0;
988 /* receive buffer ring */
989 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
990 boot->br_rxbuf_hi = 0;
991 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
992 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
994 for (i = 0; i < RXBUF_ENTRIES; i++) {
995 struct txp_swdesc *sd;
996 if (sc->sc_rxbufs[i].rb_sd != NULL)
998 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc),
1000 if (sc->sc_rxbufs[i].rb_sd == NULL)
1002 sd = sc->sc_rxbufs[i].rb_sd;
1005 sc->sc_rxbufprod = 0;
1008 bzero(&ld->txp_zero, sizeof(u_int32_t));
1009 boot->br_zero_lo = vtophys(&ld->txp_zero);
1010 boot->br_zero_hi = 0;
1012 /* See if it's waiting for boot, and try to boot it */
1013 for (i = 0; i < 10000; i++) {
1014 r = READ_REG(sc, TXP_A2H_0);
1015 if (r == STAT_WAITING_FOR_BOOT)
1020 if (r != STAT_WAITING_FOR_BOOT) {
1021 device_printf(sc->sc_dev, "not waiting for boot\n");
1025 WRITE_REG(sc, TXP_H2A_2, 0);
1026 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
1027 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
1029 /* See if it booted */
1030 for (i = 0; i < 10000; i++) {
1031 r = READ_REG(sc, TXP_A2H_0);
1032 if (r == STAT_RUNNING)
1036 if (r != STAT_RUNNING) {
1037 device_printf(sc->sc_dev, "fw not running\n");
1041 /* Clear TX and CMD ring write registers */
1042 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
1043 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
1044 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
1045 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
1051 txp_ioctl(ifp, command, data, cr)
1057 struct txp_softc *sc = ifp->if_softc;
1058 struct ifreq *ifr = (struct ifreq *)data;
1065 if (ifp->if_flags & IFF_UP) {
1068 if (ifp->if_flags & IFF_RUNNING)
1075 * Multicast list has changed; set the hardware
1076 * filter accordingly.
1083 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1086 error = ether_ioctl(ifp, command, data);
1097 struct txp_softc *sc;
1101 struct txp_swdesc *sd;
1103 ifp = &sc->sc_arpcom.ac_if;
1105 for (i = 0; i < RXBUF_ENTRIES; i++) {
1106 sd = sc->sc_rxbufs[i].rb_sd;
1107 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
1108 if (sd->sd_mbuf == NULL)
1111 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
1112 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) {
1113 m_freem(sd->sd_mbuf);
1116 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1117 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1119 sc->sc_rxbufs[i].rb_paddrlo =
1120 vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1121 sc->sc_rxbufs[i].rb_paddrhi = 0;
1124 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1125 sizeof(struct txp_rxbuf_desc);
1131 txp_rxring_empty(sc)
1132 struct txp_softc *sc;
1135 struct txp_swdesc *sd;
1137 if (sc->sc_rxbufs == NULL)
1140 for (i = 0; i < RXBUF_ENTRIES; i++) {
1141 if (&sc->sc_rxbufs[i] == NULL)
1143 sd = sc->sc_rxbufs[i].rb_sd;
1146 if (sd->sd_mbuf != NULL) {
1147 m_freem(sd->sd_mbuf);
1159 struct txp_softc *sc;
1165 ifp = &sc->sc_arpcom.ac_if;
1167 if (ifp->if_flags & IFF_RUNNING)
1174 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1175 NULL, NULL, NULL, 1);
1177 /* Set station address. */
1178 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0];
1179 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1];
1180 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2];
1181 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3];
1182 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4];
1183 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5];
1184 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1185 NULL, NULL, NULL, 1);
1189 txp_rxring_fill(sc);
1191 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1192 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1194 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1195 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1196 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1197 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1198 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
1199 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1201 ifp->if_flags |= IFF_RUNNING;
1202 ifp->if_flags &= ~IFF_OACTIVE;
1205 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1214 struct txp_softc *sc = vsc;
1215 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1216 struct txp_rsp_desc *rsp = NULL;
1217 struct txp_ext_desc *ext;
1220 txp_rxbuf_reclaim(sc);
1222 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1225 if (rsp->rsp_numdesc != 6)
1227 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1228 NULL, NULL, NULL, 1))
1230 ext = (struct txp_ext_desc *)(rsp + 1);
1232 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1233 ext[4].ext_1 + ext[4].ext_4;
1234 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 +
1236 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 +
1238 ifp->if_opackets += rsp->rsp_par2;
1239 ifp->if_ipackets += ext[2].ext_3;
1243 free(rsp, M_DEVBUF);
1245 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1253 struct txp_softc *sc = ifp->if_softc;
1254 struct txp_tx_ring *r = &sc->sc_txhir;
1255 struct txp_tx_desc *txd;
1256 struct txp_frag_desc *fxd;
1257 struct mbuf *m, *m0;
1258 struct txp_swdesc *sd;
1259 u_int32_t firstprod, firstcnt, prod, cnt;
1262 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1269 m = ifq_poll(&ifp->if_snd);
1276 sd = sc->sc_txd + prod;
1279 if ((TX_ENTRIES - cnt) < 4)
1282 txd = r->r_desc + prod;
1284 txd->tx_flags = TX_FLAGS_TYPE_DATA;
1285 txd->tx_numdesc = 0;
1291 if (++prod == TX_ENTRIES)
1294 if (++cnt >= (TX_ENTRIES - 4))
1297 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1298 m->m_pkthdr.rcvif != NULL) {
1299 ifv = m->m_pkthdr.rcvif->if_softc;
1300 txd->tx_pflags = TX_PFLAGS_VLAN |
1301 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S);
1304 if (m->m_pkthdr.csum_flags & CSUM_IP)
1305 txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1308 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1309 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1310 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1311 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1314 fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1315 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1318 if (++cnt >= (TX_ENTRIES - 4))
1323 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1324 fxd->frag_rsvd1 = 0;
1325 fxd->frag_len = m0->m_len;
1326 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1327 fxd->frag_addrhi = 0;
1328 fxd->frag_rsvd2 = 0;
1330 if (++prod == TX_ENTRIES) {
1331 fxd = (struct txp_frag_desc *)r->r_desc;
1340 m = ifq_dequeue(&ifp->if_snd);
1342 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1350 ifp->if_flags |= IFF_OACTIVE;
1351 r->r_prod = firstprod;
1352 r->r_cnt = firstcnt;
1357 * Handle simple commands sent to the typhoon
1360 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait)
1361 struct txp_softc *sc;
1362 u_int16_t id, in1, *out1;
1363 u_int32_t in2, in3, *out2, *out3;
1366 struct txp_rsp_desc *rsp = NULL;
1368 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1375 *out1 = rsp->rsp_par1;
1377 *out2 = rsp->rsp_par2;
1379 *out3 = rsp->rsp_par3;
1380 free(rsp, M_DEVBUF);
1385 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait)
1386 struct txp_softc *sc;
1389 struct txp_ext_desc *in_extp;
1391 struct txp_rsp_desc **rspp;
1394 struct txp_hostvar *hv = sc->sc_hostvar;
1395 struct txp_cmd_desc *cmd;
1396 struct txp_ext_desc *ext;
1400 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
1401 device_printf(sc->sc_dev, "no free cmd descriptors\n");
1405 idx = sc->sc_cmdring.lastwrite;
1406 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1407 bzero(cmd, sizeof(*cmd));
1409 cmd->cmd_numdesc = in_extn;
1410 cmd->cmd_seq = seq = sc->sc_seq++;
1412 cmd->cmd_par1 = in1;
1413 cmd->cmd_par2 = in2;
1414 cmd->cmd_par3 = in3;
1415 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1416 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1418 idx += sizeof(struct txp_cmd_desc);
1419 if (idx == sc->sc_cmdring.size)
1422 for (i = 0; i < in_extn; i++) {
1423 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1424 bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1426 idx += sizeof(struct txp_cmd_desc);
1427 if (idx == sc->sc_cmdring.size)
1431 sc->sc_cmdring.lastwrite = idx;
1433 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1438 for (i = 0; i < 10000; i++) {
1439 idx = hv->hv_resp_read_idx;
1440 if (idx != hv->hv_resp_write_idx) {
1442 if (txp_response(sc, idx, id, seq, rspp))
1449 if (i == 1000 || (*rspp) == NULL) {
1450 device_printf(sc->sc_dev, "0x%x command failed\n", id);
1458 txp_response(sc, ridx, id, seq, rspp)
1459 struct txp_softc *sc;
1463 struct txp_rsp_desc **rspp;
1465 struct txp_hostvar *hv = sc->sc_hostvar;
1466 struct txp_rsp_desc *rsp;
1468 while (ridx != hv->hv_resp_write_idx) {
1469 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1471 if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1472 *rspp = (struct txp_rsp_desc *)malloc(
1473 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
1474 M_DEVBUF, M_INTWAIT);
1475 if ((*rspp) == NULL)
1477 txp_rsp_fixup(sc, rsp, *rspp);
1481 if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
1482 device_printf(sc->sc_dev, "response error!\n");
1483 txp_rsp_fixup(sc, rsp, NULL);
1484 ridx = hv->hv_resp_read_idx;
1488 switch (rsp->rsp_id) {
1489 case TXP_CMD_CYCLE_STATISTICS:
1490 case TXP_CMD_MEDIA_STATUS_READ:
1492 case TXP_CMD_HELLO_RESPONSE:
1493 device_printf(sc->sc_dev, "hello\n");
1496 device_printf(sc->sc_dev, "unknown id(0x%x)\n",
1500 txp_rsp_fixup(sc, rsp, NULL);
1501 ridx = hv->hv_resp_read_idx;
1502 hv->hv_resp_read_idx = ridx;
1509 txp_rsp_fixup(sc, rsp, dst)
1510 struct txp_softc *sc;
1511 struct txp_rsp_desc *rsp, *dst;
1513 struct txp_rsp_desc *src = rsp;
1514 struct txp_hostvar *hv = sc->sc_hostvar;
1517 ridx = hv->hv_resp_read_idx;
1519 for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1521 bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1522 ridx += sizeof(struct txp_rsp_desc);
1523 if (ridx == sc->sc_rspring.size) {
1524 src = sc->sc_rspring.base;
1528 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1531 hv->hv_resp_read_idx = ridx;
1535 txp_cmd_desc_numfree(sc)
1536 struct txp_softc *sc;
1538 struct txp_hostvar *hv = sc->sc_hostvar;
1539 struct txp_boot_record *br = sc->sc_boot;
1540 u_int32_t widx, ridx, nfree;
1542 widx = sc->sc_cmdring.lastwrite;
1543 ridx = hv->hv_cmd_read_idx;
1546 /* Ring is completely free */
1547 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1550 nfree = br->br_cmd_siz -
1551 (widx - ridx + sizeof(struct txp_cmd_desc));
1553 nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1556 return (nfree / sizeof(struct txp_cmd_desc));
1561 struct txp_softc *sc;
1565 ifp = &sc->sc_arpcom.ac_if;
1567 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1569 callout_stop(&sc->txp_stat_timer);
1571 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1572 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1574 txp_rxring_empty(sc);
1587 txp_ifmedia_upd(ifp)
1590 struct txp_softc *sc = ifp->if_softc;
1591 struct ifmedia *ifm = &sc->sc_ifmedia;
1594 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1597 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1598 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1599 new_xcvr = TXP_XCVR_10_FDX;
1601 new_xcvr = TXP_XCVR_10_HDX;
1602 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1603 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1604 new_xcvr = TXP_XCVR_100_FDX;
1606 new_xcvr = TXP_XCVR_100_HDX;
1607 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1608 new_xcvr = TXP_XCVR_AUTO;
1613 if (sc->sc_xcvr == new_xcvr)
1616 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1617 NULL, NULL, NULL, 0);
1618 sc->sc_xcvr = new_xcvr;
1624 txp_ifmedia_sts(ifp, ifmr)
1626 struct ifmediareq *ifmr;
1628 struct txp_softc *sc = ifp->if_softc;
1629 struct ifmedia *ifm = &sc->sc_ifmedia;
1630 u_int16_t bmsr, bmcr, anlpar;
1632 ifmr->ifm_status = IFM_AVALID;
1633 ifmr->ifm_active = IFM_ETHER;
1635 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1636 &bmsr, NULL, NULL, 1))
1638 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1639 &bmsr, NULL, NULL, 1))
1642 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1643 &bmcr, NULL, NULL, 1))
1646 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1647 &anlpar, NULL, NULL, 1))
1650 if (bmsr & BMSR_LINK)
1651 ifmr->ifm_status |= IFM_ACTIVE;
1653 if (bmcr & BMCR_ISO) {
1654 ifmr->ifm_active |= IFM_NONE;
1655 ifmr->ifm_status = 0;
1659 if (bmcr & BMCR_LOOP)
1660 ifmr->ifm_active |= IFM_LOOP;
1662 if (bmcr & BMCR_AUTOEN) {
1663 if ((bmsr & BMSR_ACOMP) == 0) {
1664 ifmr->ifm_active |= IFM_NONE;
1668 if (anlpar & ANLPAR_T4)
1669 ifmr->ifm_active |= IFM_100_T4;
1670 else if (anlpar & ANLPAR_TX_FD)
1671 ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1672 else if (anlpar & ANLPAR_TX)
1673 ifmr->ifm_active |= IFM_100_TX;
1674 else if (anlpar & ANLPAR_10_FD)
1675 ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1676 else if (anlpar & ANLPAR_10)
1677 ifmr->ifm_active |= IFM_10_T;
1679 ifmr->ifm_active |= IFM_NONE;
1681 ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1685 ifmr->ifm_active |= IFM_NONE;
1686 ifmr->ifm_status &= ~IFM_AVALID;
1691 txp_show_descriptor(d)
1694 struct txp_cmd_desc *cmd = d;
1695 struct txp_rsp_desc *rsp = d;
1696 struct txp_tx_desc *txd = d;
1697 struct txp_frag_desc *frgd = d;
1699 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1700 case CMD_FLAGS_TYPE_CMD:
1701 /* command descriptor */
1702 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1703 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1704 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1706 case CMD_FLAGS_TYPE_RESP:
1707 /* response descriptor */
1708 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1709 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1710 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1712 case CMD_FLAGS_TYPE_DATA:
1713 /* data header (assuming tx for now) */
1714 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1715 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1716 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1718 case CMD_FLAGS_TYPE_FRAG:
1719 /* fragment descriptor */
1720 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1721 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1722 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1725 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1726 cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1727 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1728 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1736 struct txp_softc *sc;
1738 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1739 u_int32_t crc, carry, hashbit, hash[2];
1743 struct ifmultiaddr *ifma;
1746 if (ifp->if_flags & IFF_PROMISC) {
1747 filter = TXP_RXFILT_PROMISC;
1751 filter = TXP_RXFILT_DIRECT;
1753 if (ifp->if_flags & IFF_BROADCAST)
1754 filter |= TXP_RXFILT_BROADCAST;
1756 if (ifp->if_flags & IFF_ALLMULTI)
1757 filter |= TXP_RXFILT_ALLMULTI;
1759 hash[0] = hash[1] = 0;
1761 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1762 ifma = ifma->ifma_link.le_next) {
1763 if (ifma->ifma_addr->sa_family != AF_LINK)
1766 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1770 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1772 for (j = 0; j < 8; j++) {
1773 carry = ((crc & 0x80000000) ? 1 : 0) ^
1778 crc = (crc ^ TXP_POLYNOMIAL) |
1782 hashbit = (u_int16_t)(crc & (64 - 1));
1783 hash[hashbit / 32] |= (1 << hashbit % 32);
1787 filter |= TXP_RXFILT_HASHMULTI;
1788 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1789 2, hash[0], hash[1], NULL, NULL, NULL, 0);
1795 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1796 NULL, NULL, NULL, 1);
1802 txp_capabilities(sc)
1803 struct txp_softc *sc;
1805 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1806 struct txp_rsp_desc *rsp = NULL;
1807 struct txp_ext_desc *ext;
1809 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1812 if (rsp->rsp_numdesc != 1)
1814 ext = (struct txp_ext_desc *)(rsp + 1);
1816 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1817 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1818 ifp->if_capabilities = 0;
1820 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1821 sc->sc_tx_capability |= OFFLOAD_VLAN;
1822 sc->sc_rx_capability |= OFFLOAD_VLAN;
1827 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1828 sc->sc_tx_capability |= OFFLOAD_IPSEC;
1829 sc->sc_rx_capability |= OFFLOAD_IPSEC;
1830 ifp->if_capabilities |= IFCAP_IPSEC;
1834 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1835 sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1836 sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1837 ifp->if_capabilities |= IFCAP_HWCSUM;
1838 ifp->if_hwassist |= CSUM_IP;
1841 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1843 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1845 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1846 ifp->if_capabilities |= IFCAP_HWCSUM;
1849 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1851 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1853 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1854 ifp->if_capabilities |= IFCAP_HWCSUM;
1856 ifp->if_capenable = ifp->if_capabilities;
1858 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1859 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1864 free(rsp, M_DEVBUF);