2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/i386/i386/Attic/mp_machdep.c,v 1.32 2005/02/27 10:57:24 swildner Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
40 #include <vm/vm_param.h>
42 #include <vm/vm_kern.h>
43 #include <vm/vm_extern.h>
45 #include <vm/vm_map.h>
51 #include <machine/smptests.h>
52 #include <machine/smp.h>
53 #include <machine/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
60 #include <machine/tss.h>
61 #include <machine/specialreg.h>
62 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <i386/isa/icu.h> /* IPIs */
67 #include <i386/isa/intr_machdep.h> /* IPIs */
70 #if defined(TEST_DEFAULT_CONFIG)
71 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
73 #define MPFPS_MPFB1 mpfps->mpfb1
74 #endif /* TEST_DEFAULT_CONFIG */
76 #define WARMBOOT_TARGET 0
77 #define WARMBOOT_OFF (KERNBASE + 0x0467)
78 #define WARMBOOT_SEG (KERNBASE + 0x0469)
80 #define BIOS_BASE (0xf0000)
81 #define BIOS_SIZE (0x10000)
82 #define BIOS_COUNT (BIOS_SIZE/4)
84 #define CMOS_REG (0x70)
85 #define CMOS_DATA (0x71)
86 #define BIOS_RESET (0x0f)
87 #define BIOS_WARM (0x0a)
89 #define PROCENTRY_FLAG_EN 0x01
90 #define PROCENTRY_FLAG_BP 0x02
91 #define IOAPICENTRY_FLAG_EN 0x01
94 /* MP Floating Pointer Structure */
95 typedef struct MPFPS {
108 /* MP Configuration Table Header */
109 typedef struct MPCTH {
111 u_short base_table_length;
115 u_char product_id[12];
116 void *oem_table_pointer;
117 u_short oem_table_size;
120 u_short extended_table_length;
121 u_char extended_table_checksum;
126 typedef struct PROCENTRY {
131 u_long cpu_signature;
132 u_long feature_flags;
137 typedef struct BUSENTRY {
143 typedef struct IOAPICENTRY {
149 } *io_apic_entry_ptr;
151 typedef struct INTENTRY {
161 /* descriptions of MP basetable entries */
162 typedef struct BASETABLE_ENTRY {
169 * this code MUST be enabled here and in mpboot.s.
170 * it follows the very early stages of AP boot by placing values in CMOS ram.
171 * it NORMALLY will never be needed and thus the primitive method for enabling.
174 #if defined(CHECK_POINTS)
175 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
176 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
178 #define CHECK_INIT(D); \
179 CHECK_WRITE(0x34, (D)); \
180 CHECK_WRITE(0x35, (D)); \
181 CHECK_WRITE(0x36, (D)); \
182 CHECK_WRITE(0x37, (D)); \
183 CHECK_WRITE(0x38, (D)); \
184 CHECK_WRITE(0x39, (D));
186 #define CHECK_PRINT(S); \
187 printf("%s: %d, %d, %d, %d, %d, %d\n", \
196 #else /* CHECK_POINTS */
198 #define CHECK_INIT(D)
199 #define CHECK_PRINT(S)
201 #endif /* CHECK_POINTS */
204 * Values to send to the POST hardware.
206 #define MP_BOOTADDRESS_POST 0x10
207 #define MP_PROBE_POST 0x11
208 #define MPTABLE_PASS1_POST 0x12
210 #define MP_START_POST 0x13
211 #define MP_ENABLE_POST 0x14
212 #define MPTABLE_PASS2_POST 0x15
214 #define START_ALL_APS_POST 0x16
215 #define INSTALL_AP_TRAMP_POST 0x17
216 #define START_AP_POST 0x18
218 #define MP_ANNOUNCE_POST 0x19
220 static int need_hyperthreading_fixup;
221 static u_int logical_cpus;
222 u_int logical_cpus_mask;
224 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225 int current_postcode;
227 /** XXX FIXME: what system files declare these??? */
228 extern struct region_descriptor r_gdt, r_idt;
230 int bsp_apic_ready = 0; /* flags useability of BSP apic */
231 int mp_naps; /* # of Applications processors */
232 int mp_nbusses; /* # of busses */
233 int mp_napics; /* # of IO APICs */
234 int boot_cpu_id; /* designated BSP */
235 vm_offset_t cpu_apic_address;
236 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
239 u_int32_t cpu_apic_versions[MAXCPU];
240 u_int32_t *io_apic_versions;
242 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
244 #ifdef APIC_INTR_REORDER
246 volatile int *location;
248 } apic_isrbit_location[32];
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
256 int cpu_num_to_apic_id[NAPICID];
257 int io_num_to_apic_id[NAPICID];
258 int apic_id_to_logical[NAPICID];
260 /* AP uses this during bootstrap. Do not staticize. */
264 /* Hotwire a 0->4MB V==P mapping */
265 extern pt_entry_t *KPTphys;
267 /* SMP page table page */
268 extern pt_entry_t *SMPpt;
270 struct pcb stoppcbs[MAXCPU];
273 * Local data and functions.
276 static int mp_capable;
277 static u_int boot_address;
278 static u_int base_memory;
279 static int mp_finish;
281 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
282 static mpfps_t mpfps;
283 static int search_for_sig(u_int32_t target, int count);
284 static void mp_enable(u_int boot_addr);
286 static void mptable_hyperthread_fixup(u_int id_mask);
287 static void mptable_pass1(void);
288 static int mptable_pass2(void);
289 static void default_mp_table(int type);
290 static void fix_mp_table(void);
291 static void setup_apic_irq_mapping(void);
292 static int start_all_aps(u_int boot_addr);
293 static void install_ap_tramp(u_int boot_addr);
294 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
295 static int apic_int_is_bus_type(int intr, int bus_type);
297 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
298 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
299 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
302 * Calculate usable address in base memory for AP trampoline code.
305 mp_bootaddress(u_int basemem)
307 POSTCODE(MP_BOOTADDRESS_POST);
309 base_memory = basemem * 1024; /* convert to bytes */
311 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
312 if ((base_memory - boot_address) < bootMP_size)
313 boot_address -= 4096; /* not enough, lower by 4k */
320 * Look for an Intel MP spec table (ie, SMP capable hardware).
329 POSTCODE(MP_PROBE_POST);
331 /* see if EBDA exists */
332 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
333 /* search first 1K of EBDA */
334 target = (u_int32_t) (segment << 4);
335 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
338 /* last 1K of base memory, effective 'top of base' passed in */
339 target = (u_int32_t) (base_memory - 0x400);
340 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
344 /* search the BIOS */
345 target = (u_int32_t) BIOS_BASE;
346 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
355 /* calculate needed resources */
359 /* flag fact that we are running multiple processors */
366 * Startup the SMP processors.
371 POSTCODE(MP_START_POST);
373 /* look for MP capable motherboard */
375 mp_enable(boot_address);
377 panic("MP hardware not found!");
382 * Print various information about the SMP system hardware and setup.
389 POSTCODE(MP_ANNOUNCE_POST);
391 printf("DragonFly/MP: Multiprocessor motherboard\n");
392 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
393 printf(", version: 0x%08x", cpu_apic_versions[0]);
394 printf(", at 0x%08x\n", cpu_apic_address);
395 for (x = 1; x <= mp_naps; ++x) {
396 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
397 printf(", version: 0x%08x", cpu_apic_versions[x]);
398 printf(", at 0x%08x\n", cpu_apic_address);
402 for (x = 0; x < mp_napics; ++x) {
403 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
404 printf(", version: 0x%08x", io_apic_versions[x]);
405 printf(", at 0x%08x\n", io_apic_address[x]);
408 printf(" Warning: APIC I/O disabled\n");
413 * AP cpu's call this to sync up protected mode.
415 * WARNING! We must ensure that the cpu is sufficiently initialized to
416 * be able to use to the FP for our optimized bzero/bcopy code before
417 * we enter more mainstream C code.
423 int x, myid = bootAP;
425 struct mdglobaldata *md;
426 struct privatespace *ps;
428 ps = &CPU_prvspace[myid];
430 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
431 gdt_segs[GPROC0_SEL].ssd_base =
432 (int) &ps->mdglobaldata.gd_common_tss;
433 ps->mdglobaldata.mi.gd_prvspace = ps;
435 for (x = 0; x < NGDT; x++) {
436 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
439 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
440 r_gdt.rd_base = (int) &gdt[myid * NGDT];
441 lgdt(&r_gdt); /* does magic intra-segment return */
446 mdcpu->gd_currentldt = _default_ldt;
448 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
449 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
451 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
453 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
454 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
455 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
456 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
457 md->gd_common_tssd = *md->gd_tss_gdt;
461 * Set to a known state:
462 * Set by mpboot.s: CR0_PG, CR0_PE
463 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
466 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
468 pmap_set_opt(); /* PSE/4MB pages, etc */
470 /* set up CPU registers and state */
473 /* set up FPU state on the AP */
474 npxinit(__INITIAL_NPXCW__);
476 /* set up SSE registers */
483 * Final configuration of the BSP's local APIC:
484 * - disable 'pic mode'.
485 * - disable 'virtual wire mode'.
489 bsp_apic_configure(void)
494 /* leave 'pic mode' if necessary */
496 outb(0x22, 0x70); /* select IMCR */
497 byte = inb(0x23); /* current contents */
498 byte |= 0x01; /* mask external INTR */
499 outb(0x23, byte); /* disconnect 8259s/NMI */
502 /* mask lint0 (the 8259 'virtual wire' connection) */
503 temp = lapic.lvt_lint0;
504 temp |= APIC_LVT_M; /* set the mask */
505 lapic.lvt_lint0 = temp;
507 /* setup lint1 to handle NMI */
508 temp = lapic.lvt_lint1;
509 temp &= ~APIC_LVT_M; /* clear the mask */
510 lapic.lvt_lint1 = temp;
513 apic_dump("bsp_apic_configure()");
518 /*******************************************************************
519 * local functions and data
523 * start the SMP system
526 mp_enable(u_int boot_addr)
534 POSTCODE(MP_ENABLE_POST);
536 /* turn on 4MB of V == P addressing so we can get to MP table */
537 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
540 /* examine the MP table for needed info, uses physical addresses */
546 /* can't process default configs till the CPU APIC is pmapped */
550 /* post scan cleanup */
552 setup_apic_irq_mapping();
556 /* fill the LOGICAL io_apic_versions table */
557 for (apic = 0; apic < mp_napics; ++apic) {
558 ux = io_apic_read(apic, IOAPIC_VER);
559 io_apic_versions[apic] = ux;
560 io_apic_set_id(apic, IO_TO_ID(apic));
563 /* program each IO APIC in the system */
564 for (apic = 0; apic < mp_napics; ++apic)
565 if (io_apic_setup(apic) < 0)
566 panic("IO APIC setup failure");
568 /* install a 'Spurious INTerrupt' vector */
569 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
570 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
572 /* install an inter-CPU IPI for TLB invalidation */
573 setidt(XINVLTLB_OFFSET, Xinvltlb,
574 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
576 /* install an inter-CPU IPI for IPIQ messaging */
577 setidt(XIPIQ_OFFSET, Xipiq,
578 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
580 /* install an inter-CPU IPI for all-CPU rendezvous */
581 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
582 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
584 /* install an inter-CPU IPI for CPU stop/restart */
585 setidt(XCPUSTOP_OFFSET, Xcpustop,
586 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
588 #if defined(TEST_TEST1)
589 /* install a "fake hardware INTerrupt" vector */
590 setidt(XTEST1_OFFSET, Xtest1,
591 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
592 #endif /** TEST_TEST1 */
596 /* start each Application Processor */
597 start_all_aps(boot_addr);
602 * look for the MP spec signature
605 /* string defined by the Intel MP Spec as identifying the MP table */
606 #define MP_SIG 0x5f504d5f /* _MP_ */
607 #define NEXT(X) ((X) += 4)
609 search_for_sig(u_int32_t target, int count)
612 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
614 for (x = 0; x < count; NEXT(x))
615 if (addr[x] == MP_SIG)
616 /* make array index a byte index */
617 return (target + (x * sizeof(u_int32_t)));
623 static basetable_entry basetable_entry_types[] =
625 {0, 20, "Processor"},
632 typedef struct BUSDATA {
634 enum busTypes bus_type;
637 typedef struct INTDATA {
647 typedef struct BUSTYPENAME {
652 static bus_type_name bus_type_table[] =
658 {UNKNOWN_BUSTYPE, "---"},
661 {UNKNOWN_BUSTYPE, "---"},
662 {UNKNOWN_BUSTYPE, "---"},
663 {UNKNOWN_BUSTYPE, "---"},
664 {UNKNOWN_BUSTYPE, "---"},
665 {UNKNOWN_BUSTYPE, "---"},
667 {UNKNOWN_BUSTYPE, "---"},
668 {UNKNOWN_BUSTYPE, "---"},
669 {UNKNOWN_BUSTYPE, "---"},
670 {UNKNOWN_BUSTYPE, "---"},
672 {UNKNOWN_BUSTYPE, "---"}
674 /* from MP spec v1.4, table 5-1 */
675 static int default_data[7][5] =
677 /* nbus, id0, type0, id1, type1 */
678 {1, 0, ISA, 255, 255},
679 {1, 0, EISA, 255, 255},
680 {1, 0, EISA, 255, 255},
681 {1, 0, MCA, 255, 255},
683 {2, 0, EISA, 1, PCI},
689 static bus_datum *bus_data;
691 /* the IO INT data, one entry per possible APIC INTerrupt */
692 static io_int *io_apic_ints;
696 static int processor_entry (proc_entry_ptr entry, int cpu);
697 static int bus_entry (bus_entry_ptr entry, int bus);
698 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
699 static int int_entry (int_entry_ptr entry, int intr);
700 static int lookup_bus_type (char *name);
704 * 1st pass on motherboard's Intel MP specification table.
710 * cpu_apic_address (common to all CPUs)
728 POSTCODE(MPTABLE_PASS1_POST);
730 /* clear various tables */
731 for (x = 0; x < NAPICID; ++x) {
732 io_apic_address[x] = ~0; /* IO APIC address table */
735 /* init everything to empty */
742 /* check for use of 'default' configuration */
743 if (MPFPS_MPFB1 != 0) {
744 /* use default addresses */
745 cpu_apic_address = DEFAULT_APIC_BASE;
746 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
748 /* fill in with defaults */
749 mp_naps = 2; /* includes BSP */
750 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
757 if ((cth = mpfps->pap) == 0)
758 panic("MP Configuration Table Header MISSING!");
760 cpu_apic_address = (vm_offset_t) cth->apic_address;
762 /* walk the table, recording info of interest */
763 totalSize = cth->base_table_length - sizeof(struct MPCTH);
764 position = (u_char *) cth + sizeof(struct MPCTH);
765 count = cth->entry_count;
768 switch (type = *(u_char *) position) {
769 case 0: /* processor_entry */
770 if (((proc_entry_ptr)position)->cpu_flags
771 & PROCENTRY_FLAG_EN) {
774 ((proc_entry_ptr)position)->apic_id;
777 case 1: /* bus_entry */
780 case 2: /* io_apic_entry */
781 if (((io_apic_entry_ptr)position)->apic_flags
782 & IOAPICENTRY_FLAG_EN)
783 io_apic_address[mp_napics++] =
784 (vm_offset_t)((io_apic_entry_ptr)
785 position)->apic_address;
787 case 3: /* int_entry */
790 case 4: /* int_entry */
793 panic("mpfps Base Table HOSED!");
797 totalSize -= basetable_entry_types[type].length;
798 position = (uint8_t *)position +
799 basetable_entry_types[type].length;
803 /* qualify the numbers */
804 if (mp_naps > MAXCPU) {
805 printf("Warning: only using %d of %d available CPUs!\n",
810 /* See if we need to fixup HT logical CPUs. */
811 mptable_hyperthread_fixup(id_mask);
815 * This is also used as a counter while starting the APs.
819 --mp_naps; /* subtract the BSP */
824 * 2nd pass on motherboard's Intel MP specification table.
828 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
829 * CPU_TO_ID(N), logical CPU to APIC ID table
830 * IO_TO_ID(N), logical IO to APIC ID table
837 struct PROCENTRY proc;
844 int apic, bus, cpu, intr;
848 POSTCODE(MPTABLE_PASS2_POST);
850 /* Initialize fake proc entry for use with HT fixup. */
851 bzero(&proc, sizeof(proc));
853 proc.cpu_flags = PROCENTRY_FLAG_EN;
855 pgeflag = 0; /* XXX - Not used under SMP yet. */
857 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
859 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
861 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
863 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
866 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
868 for (i = 0; i < mp_napics; i++) {
869 for (j = 0; j < mp_napics; j++) {
870 /* same page frame as a previous IO apic? */
871 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
872 (io_apic_address[i] & PG_FRAME)) {
873 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
874 + (NPTEPG-2-j) * PAGE_SIZE
875 + (io_apic_address[i] & PAGE_MASK));
878 /* use this slot if available */
879 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
880 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
881 pgeflag | (io_apic_address[i] & PG_FRAME));
882 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
883 + (NPTEPG-2-j) * PAGE_SIZE
884 + (io_apic_address[i] & PAGE_MASK));
890 /* clear various tables */
891 for (x = 0; x < NAPICID; ++x) {
892 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
893 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
894 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
897 /* clear bus data table */
898 for (x = 0; x < mp_nbusses; ++x)
899 bus_data[x].bus_id = 0xff;
901 /* clear IO APIC INT table */
902 for (x = 0; x < (nintrs + 1); ++x) {
903 io_apic_ints[x].int_type = 0xff;
904 io_apic_ints[x].int_vector = 0xff;
907 /* setup the cpu/apic mapping arrays */
910 /* record whether PIC or virtual-wire mode */
911 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
913 /* check for use of 'default' configuration */
914 if (MPFPS_MPFB1 != 0)
915 return MPFPS_MPFB1; /* return default configuration type */
917 if ((cth = mpfps->pap) == 0)
918 panic("MP Configuration Table Header MISSING!");
920 /* walk the table, recording info of interest */
921 totalSize = cth->base_table_length - sizeof(struct MPCTH);
922 position = (u_char *) cth + sizeof(struct MPCTH);
923 count = cth->entry_count;
924 apic = bus = intr = 0;
925 cpu = 1; /* pre-count the BSP */
928 switch (type = *(u_char *) position) {
930 if (processor_entry(position, cpu))
933 if (need_hyperthreading_fixup) {
935 * Create fake mptable processor entries
936 * and feed them to processor_entry() to
937 * enumerate the logical CPUs.
939 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
940 for (i = 1; i < logical_cpus; i++) {
942 (void)processor_entry(&proc, cpu);
943 logical_cpus_mask |= (1 << cpu);
949 if (bus_entry(position, bus))
953 if (io_apic_entry(position, apic))
957 if (int_entry(position, intr))
961 /* int_entry(position); */
964 panic("mpfps Base Table HOSED!");
968 totalSize -= basetable_entry_types[type].length;
969 position = (uint8_t *)position + basetable_entry_types[type].length;
972 if (boot_cpu_id == -1)
973 panic("NO BSP found!");
975 /* report fact that its NOT a default configuration */
980 * Check if we should perform a hyperthreading "fix-up" to
981 * enumerate any logical CPU's that aren't already listed
984 * XXX: We assume that all of the physical CPUs in the
985 * system have the same number of logical CPUs.
987 * XXX: We assume that APIC ID's are allocated such that
988 * the APIC ID's for a physical processor are aligned
989 * with the number of logical CPU's in the processor.
992 mptable_hyperthread_fixup(u_int id_mask)
996 /* Nothing to do if there is no HTT support. */
997 if ((cpu_feature & CPUID_HTT) == 0)
999 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1000 if (logical_cpus <= 1)
1004 * For each APIC ID of a CPU that is set in the mask,
1005 * scan the other candidate APIC ID's for this
1006 * physical processor. If any of those ID's are
1007 * already in the table, then kill the fixup.
1009 for (id = 0; id <= MAXCPU; id++) {
1010 if ((id_mask & 1 << id) == 0)
1012 /* First, make sure we are on a logical_cpus boundary. */
1013 if (id % logical_cpus != 0)
1015 for (i = id + 1; i < id + logical_cpus; i++)
1016 if ((id_mask & 1 << i) != 0)
1021 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1022 * mp_naps right now.
1024 need_hyperthreading_fixup = 1;
1025 mp_naps *= logical_cpus;
1029 assign_apic_irq(int apic, int intpin, int irq)
1033 if (int_to_apicintpin[irq].ioapic != -1)
1034 panic("assign_apic_irq: inconsistent table");
1036 int_to_apicintpin[irq].ioapic = apic;
1037 int_to_apicintpin[irq].int_pin = intpin;
1038 int_to_apicintpin[irq].apic_address = ioapic[apic];
1039 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1041 for (x = 0; x < nintrs; x++) {
1042 if ((io_apic_ints[x].int_type == 0 ||
1043 io_apic_ints[x].int_type == 3) &&
1044 io_apic_ints[x].int_vector == 0xff &&
1045 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1046 io_apic_ints[x].dst_apic_int == intpin)
1047 io_apic_ints[x].int_vector = irq;
1052 revoke_apic_irq(int irq)
1058 if (int_to_apicintpin[irq].ioapic == -1)
1059 panic("revoke_apic_irq: inconsistent table");
1061 oldapic = int_to_apicintpin[irq].ioapic;
1062 oldintpin = int_to_apicintpin[irq].int_pin;
1064 int_to_apicintpin[irq].ioapic = -1;
1065 int_to_apicintpin[irq].int_pin = 0;
1066 int_to_apicintpin[irq].apic_address = NULL;
1067 int_to_apicintpin[irq].redirindex = 0;
1069 for (x = 0; x < nintrs; x++) {
1070 if ((io_apic_ints[x].int_type == 0 ||
1071 io_apic_ints[x].int_type == 3) &&
1072 io_apic_ints[x].int_vector != 0xff &&
1073 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1074 io_apic_ints[x].dst_apic_int == oldintpin)
1075 io_apic_ints[x].int_vector = 0xff;
1081 allocate_apic_irq(int intr)
1087 if (io_apic_ints[intr].int_vector != 0xff)
1088 return; /* Interrupt handler already assigned */
1090 if (io_apic_ints[intr].int_type != 0 &&
1091 (io_apic_ints[intr].int_type != 3 ||
1092 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1093 io_apic_ints[intr].dst_apic_int == 0)))
1094 return; /* Not INT or ExtInt on != (0, 0) */
1097 while (irq < APIC_INTMAPSIZE &&
1098 int_to_apicintpin[irq].ioapic != -1)
1101 if (irq >= APIC_INTMAPSIZE)
1102 return; /* No free interrupt handlers */
1104 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1105 intpin = io_apic_ints[intr].dst_apic_int;
1107 assign_apic_irq(apic, intpin, irq);
1108 io_apic_setup_intpin(apic, intpin);
1113 swap_apic_id(int apic, int oldid, int newid)
1120 return; /* Nothing to do */
1122 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1123 apic, oldid, newid);
1125 /* Swap physical APIC IDs in interrupt entries */
1126 for (x = 0; x < nintrs; x++) {
1127 if (io_apic_ints[x].dst_apic_id == oldid)
1128 io_apic_ints[x].dst_apic_id = newid;
1129 else if (io_apic_ints[x].dst_apic_id == newid)
1130 io_apic_ints[x].dst_apic_id = oldid;
1133 /* Swap physical APIC IDs in IO_TO_ID mappings */
1134 for (oapic = 0; oapic < mp_napics; oapic++)
1135 if (IO_TO_ID(oapic) == newid)
1138 if (oapic < mp_napics) {
1139 printf("Changing APIC ID for IO APIC #%d from "
1140 "%d to %d in MP table\n",
1141 oapic, newid, oldid);
1142 IO_TO_ID(oapic) = oldid;
1144 IO_TO_ID(apic) = newid;
1149 fix_id_to_io_mapping(void)
1153 for (x = 0; x < NAPICID; x++)
1156 for (x = 0; x <= mp_naps; x++)
1157 if (CPU_TO_ID(x) < NAPICID)
1158 ID_TO_IO(CPU_TO_ID(x)) = x;
1160 for (x = 0; x < mp_napics; x++)
1161 if (IO_TO_ID(x) < NAPICID)
1162 ID_TO_IO(IO_TO_ID(x)) = x;
1167 first_free_apic_id(void)
1171 for (freeid = 0; freeid < NAPICID; freeid++) {
1172 for (x = 0; x <= mp_naps; x++)
1173 if (CPU_TO_ID(x) == freeid)
1177 for (x = 0; x < mp_napics; x++)
1178 if (IO_TO_ID(x) == freeid)
1189 io_apic_id_acceptable(int apic, int id)
1191 int cpu; /* Logical CPU number */
1192 int oapic; /* Logical IO APIC number for other IO APIC */
1195 return 0; /* Out of range */
1197 for (cpu = 0; cpu <= mp_naps; cpu++)
1198 if (CPU_TO_ID(cpu) == id)
1199 return 0; /* Conflict with CPU */
1201 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1202 if (IO_TO_ID(oapic) == id)
1203 return 0; /* Conflict with other APIC */
1205 return 1; /* ID is acceptable for IO APIC */
1210 * parse an Intel MP specification table
1217 int bus_0 = 0; /* Stop GCC warning */
1218 int bus_pci = 0; /* Stop GCC warning */
1220 int apic; /* IO APIC unit number */
1221 int freeid; /* Free physical APIC ID */
1222 int physid; /* Current physical IO APIC ID */
1225 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1226 * did it wrong. The MP spec says that when more than 1 PCI bus
1227 * exists the BIOS must begin with bus entries for the PCI bus and use
1228 * actual PCI bus numbering. This implies that when only 1 PCI bus
1229 * exists the BIOS can choose to ignore this ordering, and indeed many
1230 * MP motherboards do ignore it. This causes a problem when the PCI
1231 * sub-system makes requests of the MP sub-system based on PCI bus
1232 * numbers. So here we look for the situation and renumber the
1233 * busses and associated INTs in an effort to "make it right".
1236 /* find bus 0, PCI bus, count the number of PCI busses */
1237 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1238 if (bus_data[x].bus_id == 0) {
1241 if (bus_data[x].bus_type == PCI) {
1247 * bus_0 == slot of bus with ID of 0
1248 * bus_pci == slot of last PCI bus encountered
1251 /* check the 1 PCI bus case for sanity */
1252 /* if it is number 0 all is well */
1253 if (num_pci_bus == 1 &&
1254 bus_data[bus_pci].bus_id != 0) {
1256 /* mis-numbered, swap with whichever bus uses slot 0 */
1258 /* swap the bus entry types */
1259 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1260 bus_data[bus_0].bus_type = PCI;
1262 /* swap each relavant INTerrupt entry */
1263 id = bus_data[bus_pci].bus_id;
1264 for (x = 0; x < nintrs; ++x) {
1265 if (io_apic_ints[x].src_bus_id == id) {
1266 io_apic_ints[x].src_bus_id = 0;
1268 else if (io_apic_ints[x].src_bus_id == 0) {
1269 io_apic_ints[x].src_bus_id = id;
1274 /* Assign IO APIC IDs.
1276 * First try the existing ID. If a conflict is detected, try
1277 * the ID in the MP table. If a conflict is still detected, find
1280 * We cannot use the ID_TO_IO table before all conflicts has been
1281 * resolved and the table has been corrected.
1283 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1285 /* First try to use the value set by the BIOS */
1286 physid = io_apic_get_id(apic);
1287 if (io_apic_id_acceptable(apic, physid)) {
1288 if (IO_TO_ID(apic) != physid)
1289 swap_apic_id(apic, IO_TO_ID(apic), physid);
1293 /* Then check if the value in the MP table is acceptable */
1294 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1297 /* Last resort, find a free APIC ID and use it */
1298 freeid = first_free_apic_id();
1299 if (freeid >= NAPICID)
1300 panic("No free physical APIC IDs found");
1302 if (io_apic_id_acceptable(apic, freeid)) {
1303 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1306 panic("Free physical APIC ID not usable");
1308 fix_id_to_io_mapping();
1310 /* detect and fix broken Compaq MP table */
1311 if (apic_int_type(0, 0) == -1) {
1312 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1313 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1314 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1315 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1316 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1317 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1319 } else if (apic_int_type(0, 0) == 0) {
1320 printf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1321 for (x = 0; x < nintrs; ++x)
1322 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1323 (0 == io_apic_ints[x].dst_apic_int)) {
1324 io_apic_ints[x].int_type = 3;
1325 io_apic_ints[x].int_vector = 0xff;
1332 /* Assign low level interrupt handlers */
1334 setup_apic_irq_mapping(void)
1340 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1341 int_to_apicintpin[x].ioapic = -1;
1342 int_to_apicintpin[x].int_pin = 0;
1343 int_to_apicintpin[x].apic_address = NULL;
1344 int_to_apicintpin[x].redirindex = 0;
1347 /* First assign ISA/EISA interrupts */
1348 for (x = 0; x < nintrs; x++) {
1349 int_vector = io_apic_ints[x].src_bus_irq;
1350 if (int_vector < APIC_INTMAPSIZE &&
1351 io_apic_ints[x].int_vector == 0xff &&
1352 int_to_apicintpin[int_vector].ioapic == -1 &&
1353 (apic_int_is_bus_type(x, ISA) ||
1354 apic_int_is_bus_type(x, EISA)) &&
1355 io_apic_ints[x].int_type == 0) {
1356 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1357 io_apic_ints[x].dst_apic_int,
1362 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1363 for (x = 0; x < nintrs; x++) {
1364 if (io_apic_ints[x].dst_apic_int == 0 &&
1365 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1366 io_apic_ints[x].int_vector == 0xff &&
1367 int_to_apicintpin[0].ioapic == -1 &&
1368 io_apic_ints[x].int_type == 3) {
1369 assign_apic_irq(0, 0, 0);
1373 /* PCI interrupt assignment is deferred */
1378 processor_entry(proc_entry_ptr entry, int cpu)
1380 /* check for usability */
1381 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1384 if(entry->apic_id >= NAPICID)
1385 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1386 /* check for BSP flag */
1387 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1388 boot_cpu_id = entry->apic_id;
1389 CPU_TO_ID(0) = entry->apic_id;
1390 ID_TO_CPU(entry->apic_id) = 0;
1391 return 0; /* its already been counted */
1394 /* add another AP to list, if less than max number of CPUs */
1395 else if (cpu < MAXCPU) {
1396 CPU_TO_ID(cpu) = entry->apic_id;
1397 ID_TO_CPU(entry->apic_id) = cpu;
1406 bus_entry(bus_entry_ptr entry, int bus)
1411 /* encode the name into an index */
1412 for (x = 0; x < 6; ++x) {
1413 if ((c = entry->bus_type[x]) == ' ')
1419 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1420 panic("unknown bus type: '%s'", name);
1422 bus_data[bus].bus_id = entry->bus_id;
1423 bus_data[bus].bus_type = x;
1430 io_apic_entry(io_apic_entry_ptr entry, int apic)
1432 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1435 IO_TO_ID(apic) = entry->apic_id;
1436 if (entry->apic_id < NAPICID)
1437 ID_TO_IO(entry->apic_id) = apic;
1444 lookup_bus_type(char *name)
1448 for (x = 0; x < MAX_BUSTYPE; ++x)
1449 if (strcmp(bus_type_table[x].name, name) == 0)
1450 return bus_type_table[x].type;
1452 return UNKNOWN_BUSTYPE;
1457 int_entry(int_entry_ptr entry, int intr)
1461 io_apic_ints[intr].int_type = entry->int_type;
1462 io_apic_ints[intr].int_flags = entry->int_flags;
1463 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1464 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1465 if (entry->dst_apic_id == 255) {
1466 /* This signal goes to all IO APICS. Select an IO APIC
1467 with sufficient number of interrupt pins */
1468 for (apic = 0; apic < mp_napics; apic++)
1469 if (((io_apic_read(apic, IOAPIC_VER) &
1470 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1471 entry->dst_apic_int)
1473 if (apic < mp_napics)
1474 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1476 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1478 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1479 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1486 apic_int_is_bus_type(int intr, int bus_type)
1490 for (bus = 0; bus < mp_nbusses; ++bus)
1491 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1492 && ((int) bus_data[bus].bus_type == bus_type))
1500 * Given a traditional ISA INT mask, return an APIC mask.
1503 isa_apic_mask(u_int isa_mask)
1508 #if defined(SKIP_IRQ15_REDIRECT)
1509 if (isa_mask == (1 << 15)) {
1510 printf("skipping ISA IRQ15 redirect\n");
1513 #endif /* SKIP_IRQ15_REDIRECT */
1515 isa_irq = ffs(isa_mask); /* find its bit position */
1516 if (isa_irq == 0) /* doesn't exist */
1518 --isa_irq; /* make it zero based */
1520 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1524 return (1 << apic_pin); /* convert pin# to a mask */
1529 * Determine which APIC pin an ISA/EISA INT is attached to.
1531 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1532 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1533 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1534 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1536 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1538 isa_apic_irq(int isa_irq)
1542 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1543 if (INTTYPE(intr) == 0) { /* standard INT */
1544 if (SRCBUSIRQ(intr) == isa_irq) {
1545 if (apic_int_is_bus_type(intr, ISA) ||
1546 apic_int_is_bus_type(intr, EISA)) {
1547 if (INTIRQ(intr) == 0xff)
1548 return -1; /* unassigned */
1549 return INTIRQ(intr); /* found */
1554 return -1; /* NOT found */
1559 * Determine which APIC pin a PCI INT is attached to.
1561 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1562 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1563 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1565 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1569 --pciInt; /* zero based */
1571 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1572 if ((INTTYPE(intr) == 0) /* standard INT */
1573 && (SRCBUSID(intr) == pciBus)
1574 && (SRCBUSDEVICE(intr) == pciDevice)
1575 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1576 if (apic_int_is_bus_type(intr, PCI)) {
1577 if (INTIRQ(intr) == 0xff)
1578 allocate_apic_irq(intr);
1579 if (INTIRQ(intr) == 0xff)
1580 return -1; /* unassigned */
1581 return INTIRQ(intr); /* exact match */
1584 return -1; /* NOT found */
1588 next_apic_irq(int irq)
1595 for (intr = 0; intr < nintrs; intr++) {
1596 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1598 bus = SRCBUSID(intr);
1599 bustype = apic_bus_type(bus);
1600 if (bustype != ISA &&
1606 if (intr >= nintrs) {
1609 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1610 if (INTTYPE(ointr) != 0)
1612 if (bus != SRCBUSID(ointr))
1614 if (bustype == PCI) {
1615 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1617 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1620 if (bustype == ISA || bustype == EISA) {
1621 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1624 if (INTPIN(intr) == INTPIN(ointr))
1628 if (ointr >= nintrs) {
1631 return INTIRQ(ointr);
1645 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1648 * Exactly what this means is unclear at this point. It is a solution
1649 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1650 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1651 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1655 undirect_isa_irq(int rirq)
1659 printf("Freeing redirected ISA irq %d.\n", rirq);
1660 /** FIXME: tickle the MB redirector chip */
1664 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1671 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1674 undirect_pci_irq(int rirq)
1678 printf("Freeing redirected PCI irq %d.\n", rirq);
1680 /** FIXME: tickle the MB redirector chip */
1684 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1692 * given a bus ID, return:
1693 * the bus type if found
1697 apic_bus_type(int id)
1701 for (x = 0; x < mp_nbusses; ++x)
1702 if (bus_data[x].bus_id == id)
1703 return bus_data[x].bus_type;
1710 * given a LOGICAL APIC# and pin#, return:
1711 * the associated src bus ID if found
1715 apic_src_bus_id(int apic, int pin)
1719 /* search each of the possible INTerrupt sources */
1720 for (x = 0; x < nintrs; ++x)
1721 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1722 (pin == io_apic_ints[x].dst_apic_int))
1723 return (io_apic_ints[x].src_bus_id);
1725 return -1; /* NOT found */
1730 * given a LOGICAL APIC# and pin#, return:
1731 * the associated src bus IRQ if found
1735 apic_src_bus_irq(int apic, int pin)
1739 for (x = 0; x < nintrs; x++)
1740 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1741 (pin == io_apic_ints[x].dst_apic_int))
1742 return (io_apic_ints[x].src_bus_irq);
1744 return -1; /* NOT found */
1749 * given a LOGICAL APIC# and pin#, return:
1750 * the associated INTerrupt type if found
1754 apic_int_type(int apic, int pin)
1758 /* search each of the possible INTerrupt sources */
1759 for (x = 0; x < nintrs; ++x)
1760 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1761 (pin == io_apic_ints[x].dst_apic_int))
1762 return (io_apic_ints[x].int_type);
1764 return -1; /* NOT found */
1768 apic_irq(int apic, int pin)
1773 for (x = 0; x < nintrs; ++x)
1774 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1775 (pin == io_apic_ints[x].dst_apic_int)) {
1776 res = io_apic_ints[x].int_vector;
1779 if (apic != int_to_apicintpin[res].ioapic)
1780 panic("apic_irq: inconsistent table");
1781 if (pin != int_to_apicintpin[res].int_pin)
1782 panic("apic_irq inconsistent table (2)");
1790 * given a LOGICAL APIC# and pin#, return:
1791 * the associated trigger mode if found
1795 apic_trigger(int apic, int pin)
1799 /* search each of the possible INTerrupt sources */
1800 for (x = 0; x < nintrs; ++x)
1801 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1802 (pin == io_apic_ints[x].dst_apic_int))
1803 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1805 return -1; /* NOT found */
1810 * given a LOGICAL APIC# and pin#, return:
1811 * the associated 'active' level if found
1815 apic_polarity(int apic, int pin)
1819 /* search each of the possible INTerrupt sources */
1820 for (x = 0; x < nintrs; ++x)
1821 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1822 (pin == io_apic_ints[x].dst_apic_int))
1823 return (io_apic_ints[x].int_flags & 0x03);
1825 return -1; /* NOT found */
1830 * set data according to MP defaults
1831 * FIXME: probably not complete yet...
1834 default_mp_table(int type)
1837 #if defined(APIC_IO)
1840 #endif /* APIC_IO */
1843 printf(" MP default config type: %d\n", type);
1846 printf(" bus: ISA, APIC: 82489DX\n");
1849 printf(" bus: EISA, APIC: 82489DX\n");
1852 printf(" bus: EISA, APIC: 82489DX\n");
1855 printf(" bus: MCA, APIC: 82489DX\n");
1858 printf(" bus: ISA+PCI, APIC: Integrated\n");
1861 printf(" bus: EISA+PCI, APIC: Integrated\n");
1864 printf(" bus: MCA+PCI, APIC: Integrated\n");
1867 printf(" future type\n");
1873 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1874 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1877 CPU_TO_ID(0) = boot_cpu_id;
1878 ID_TO_CPU(boot_cpu_id) = 0;
1880 /* one and only AP */
1881 CPU_TO_ID(1) = ap_cpu_id;
1882 ID_TO_CPU(ap_cpu_id) = 1;
1884 #if defined(APIC_IO)
1885 /* one and only IO APIC */
1886 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1889 * sanity check, refer to MP spec section 3.6.6, last paragraph
1890 * necessary as some hardware isn't properly setting up the IO APIC
1892 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1893 if (io_apic_id != 2) {
1895 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1896 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1897 io_apic_set_id(0, 2);
1900 IO_TO_ID(0) = io_apic_id;
1901 ID_TO_IO(io_apic_id) = 0;
1902 #endif /* APIC_IO */
1904 /* fill out bus entries */
1913 bus_data[0].bus_id = default_data[type - 1][1];
1914 bus_data[0].bus_type = default_data[type - 1][2];
1915 bus_data[1].bus_id = default_data[type - 1][3];
1916 bus_data[1].bus_type = default_data[type - 1][4];
1919 /* case 4: case 7: MCA NOT supported */
1920 default: /* illegal/reserved */
1921 panic("BAD default MP config: %d", type);
1925 #if defined(APIC_IO)
1926 /* general cases from MP v1.4, table 5-2 */
1927 for (pin = 0; pin < 16; ++pin) {
1928 io_apic_ints[pin].int_type = 0;
1929 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1930 io_apic_ints[pin].src_bus_id = 0;
1931 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1932 io_apic_ints[pin].dst_apic_id = io_apic_id;
1933 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1936 /* special cases from MP v1.4, table 5-2 */
1938 io_apic_ints[2].int_type = 0xff; /* N/C */
1939 io_apic_ints[13].int_type = 0xff; /* N/C */
1940 #if !defined(APIC_MIXED_MODE)
1942 panic("sorry, can't support type 2 default yet");
1943 #endif /* APIC_MIXED_MODE */
1946 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1949 io_apic_ints[0].int_type = 0xff; /* N/C */
1951 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1952 #endif /* APIC_IO */
1956 * start each AP in our list
1959 start_all_aps(u_int boot_addr)
1962 u_char mpbiosreason;
1963 u_long mpbioswarmvec;
1964 struct mdglobaldata *gd;
1965 struct privatespace *ps;
1969 POSTCODE(START_ALL_APS_POST);
1971 /* initialize BSP's local APIC */
1975 /* install the AP 1st level boot code */
1976 install_ap_tramp(boot_addr);
1979 /* save the current value of the warm-start vector */
1980 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1981 outb(CMOS_REG, BIOS_RESET);
1982 mpbiosreason = inb(CMOS_DATA);
1984 /* set up temporary P==V mapping for AP boot */
1985 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
1986 kptbase = (uintptr_t)(void *)KPTphys;
1987 for (x = 0; x < NKPT; x++)
1988 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1989 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
1993 for (x = 1; x <= mp_naps; ++x) {
1995 /* This is a bit verbose, it will go away soon. */
1997 /* first page of AP's private space */
1998 pg = x * i386_btop(sizeof(struct privatespace));
2000 /* allocate a new private data page */
2001 gd = (struct mdglobaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
2003 /* wire it into the private page table page */
2004 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys_pte(gd));
2006 /* allocate and set up an idle stack data page */
2007 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
2008 for (i = 0; i < UPAGES; i++) {
2009 SMPpt[pg + 5 + i] = (pt_entry_t)
2010 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2013 SMPpt[pg + 1] = 0; /* *gd_CMAP1 */
2014 SMPpt[pg + 2] = 0; /* *gd_CMAP2 */
2015 SMPpt[pg + 3] = 0; /* *gd_CMAP3 */
2016 SMPpt[pg + 4] = 0; /* *gd_PMAP1 */
2018 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2019 bzero(gd, sizeof(*gd));
2020 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2022 /* prime data page for it to use */
2023 mi_gdinit(&gd->mi, x);
2025 gd->gd_CMAP1 = &SMPpt[pg + 1];
2026 gd->gd_CMAP2 = &SMPpt[pg + 2];
2027 gd->gd_CMAP3 = &SMPpt[pg + 3];
2028 gd->gd_PMAP1 = &SMPpt[pg + 4];
2029 gd->gd_CADDR1 = ps->CPAGE1;
2030 gd->gd_CADDR2 = ps->CPAGE2;
2031 gd->gd_CADDR3 = ps->CPAGE3;
2032 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2033 gd->mi.gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2034 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2036 /* setup a vector to our boot code */
2037 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2038 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2039 outb(CMOS_REG, BIOS_RESET);
2040 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2043 * Setup the AP boot stack
2045 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2048 /* attempt to start the Application Processor */
2049 CHECK_INIT(99); /* setup checkpoints */
2050 if (!start_ap(gd, boot_addr)) {
2051 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2052 CHECK_PRINT("trace"); /* show checkpoints */
2053 /* better panic as the AP may be running loose */
2054 printf("panic y/n? [y] ");
2055 if (cngetc() != 'n')
2058 CHECK_PRINT("trace"); /* show checkpoints */
2060 /* record its version info */
2061 cpu_apic_versions[x] = cpu_apic_versions[0];
2064 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2067 /* round ncpus down to power of 2 */
2071 ncpus2 = 1 << ncpus2_shift;
2072 ncpus2_mask = ncpus2 - 1;
2074 /* build our map of 'other' CPUs */
2075 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2076 mycpu->gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * ncpus);
2077 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2079 /* fill in our (BSP) APIC version */
2080 cpu_apic_versions[0] = lapic.version;
2082 /* restore the warmstart vector */
2083 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2084 outb(CMOS_REG, BIOS_RESET);
2085 outb(CMOS_DATA, mpbiosreason);
2088 * NOTE! The idlestack for the BSP was setup by locore. Finish
2089 * up, clean out the P==V mapping we did earlier.
2091 for (x = 0; x < NKPT; x++)
2095 /* number of APs actually started */
2101 * load the 1st level AP boot code into base memory.
2104 /* targets for relocation */
2105 extern void bigJump(void);
2106 extern void bootCodeSeg(void);
2107 extern void bootDataSeg(void);
2108 extern void MPentry(void);
2109 extern u_int MP_GDT;
2110 extern u_int mp_gdtbase;
2113 install_ap_tramp(u_int boot_addr)
2116 int size = *(int *) ((u_long) & bootMP_size);
2117 u_char *src = (u_char *) ((u_long) bootMP);
2118 u_char *dst = (u_char *) boot_addr + KERNBASE;
2119 u_int boot_base = (u_int) bootMP;
2124 POSTCODE(INSTALL_AP_TRAMP_POST);
2126 for (x = 0; x < size; ++x)
2130 * modify addresses in code we just moved to basemem. unfortunately we
2131 * need fairly detailed info about mpboot.s for this to work. changes
2132 * to mpboot.s might require changes here.
2135 /* boot code is located in KERNEL space */
2136 dst = (u_char *) boot_addr + KERNBASE;
2138 /* modify the lgdt arg */
2139 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2140 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2142 /* modify the ljmp target for MPentry() */
2143 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2144 *dst32 = ((u_int) MPentry - KERNBASE);
2146 /* modify the target for boot code segment */
2147 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2148 dst8 = (u_int8_t *) (dst16 + 1);
2149 *dst16 = (u_int) boot_addr & 0xffff;
2150 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2152 /* modify the target for boot data segment */
2153 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2154 dst8 = (u_int8_t *) (dst16 + 1);
2155 *dst16 = (u_int) boot_addr & 0xffff;
2156 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2161 * this function starts the AP (application processor) identified
2162 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2163 * to accomplish this. This is necessary because of the nuances
2164 * of the different hardware we might encounter. It ain't pretty,
2165 * but it seems to work.
2167 * NOTE: eventually an AP gets to ap_init(), which is called just
2168 * before the AP goes into the LWKT scheduler's idle loop.
2171 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2175 u_long icr_lo, icr_hi;
2177 POSTCODE(START_AP_POST);
2179 /* get the PHYSICAL APIC ID# */
2180 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2182 /* calculate the vector */
2183 vector = (boot_addr >> 12) & 0xff;
2185 /* Make sure the target cpu sees everything */
2189 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2190 * and running the target CPU. OR this INIT IPI might be latched (P5
2191 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2195 /* setup the address for the target AP */
2196 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2197 icr_hi |= (physical_cpu << 24);
2198 lapic.icr_hi = icr_hi;
2200 /* do an INIT IPI: assert RESET */
2201 icr_lo = lapic.icr_lo & 0xfff00000;
2202 lapic.icr_lo = icr_lo | 0x0000c500;
2204 /* wait for pending status end */
2205 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2208 /* do an INIT IPI: deassert RESET */
2209 lapic.icr_lo = icr_lo | 0x00008500;
2211 /* wait for pending status end */
2212 u_sleep(10000); /* wait ~10mS */
2213 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2217 * next we do a STARTUP IPI: the previous INIT IPI might still be
2218 * latched, (P5 bug) this 1st STARTUP would then terminate
2219 * immediately, and the previously started INIT IPI would continue. OR
2220 * the previous INIT IPI has already run. and this STARTUP IPI will
2221 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2225 /* do a STARTUP IPI */
2226 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2227 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2229 u_sleep(200); /* wait ~200uS */
2232 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2233 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2234 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2235 * recognized after hardware RESET or INIT IPI.
2238 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2239 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2241 u_sleep(200); /* wait ~200uS */
2243 /* wait for it to start, see ap_init() */
2244 set_apic_timer(5000000);/* == 5 seconds */
2245 while (read_apic_timer()) {
2246 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2247 return 1; /* return SUCCESS */
2249 return 0; /* return FAILURE */
2254 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2256 * If for some reason we were unable to start all cpus we cannot safely
2257 * use broadcast IPIs.
2262 #if defined(APIC_IO)
2263 if (smp_startup_mask == smp_active_mask) {
2264 all_but_self_ipi(XINVLTLB_OFFSET);
2266 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2267 APIC_DELMODE_FIXED);
2269 #endif /* APIC_IO */
2273 * When called the executing CPU will send an IPI to all other CPUs
2274 * requesting that they halt execution.
2276 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2278 * - Signals all CPUs in map to stop.
2279 * - Waits for each to stop.
2286 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2287 * from executing at same time.
2290 stop_cpus(u_int map)
2292 map &= smp_active_mask;
2294 /* send the Xcpustop IPI to all CPUs in map */
2295 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2297 while ((stopped_cpus & map) != map)
2305 * Called by a CPU to restart stopped CPUs.
2307 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2309 * - Signals all CPUs in map to restart.
2310 * - Waits for each to restart.
2318 restart_cpus(u_int map)
2320 /* signal other cpus to restart */
2321 started_cpus = map & smp_active_mask;
2323 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2330 * This is called once the mpboot code has gotten us properly relocated
2331 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2332 * and when it returns the scheduler will call the real cpu_idle() main
2333 * loop for the idlethread. Interrupts are disabled on entry and should
2334 * remain disabled at return.
2342 * Adjust smp_startup_mask to signal the BSP that we have started
2343 * up successfully. Note that we do not yet hold the BGL. The BSP
2344 * is waiting for our signal.
2346 * We can't set our bit in smp_active_mask yet because we are holding
2347 * interrupts physically disabled and remote cpus could deadlock
2348 * trying to send us an IPI.
2350 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2354 * Interlock for finalization. Wait until mp_finish is non-zero,
2355 * then get the MP lock.
2357 * Note: We are in a critical section.
2359 * Note: We have to synchronize td_mpcount to our desired MP state
2360 * before calling cpu_try_mplock().
2362 * Note: we are the idle thread, we can only spin.
2364 * Note: cpu_mb1() is memory volatile and prevents mp_finish from
2367 ++curthread->td_mpcount;
2368 while (mp_finish == 0)
2370 while (cpu_try_mplock() == 0)
2373 /* BSP may have changed PTD while we're waiting for the lock */
2376 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2380 /* Build our map of 'other' CPUs. */
2381 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2383 printf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2385 /* A quick check from sanity claus */
2386 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2387 if (mycpu->gd_cpuid != apic_id) {
2388 printf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2389 printf("SMP: apic_id = %d\n", apic_id);
2390 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2391 panic("cpuid mismatch! boom!!");
2394 /* Init local apic for irq's */
2397 /* Set memory range attributes for this CPU to match the BSP */
2398 mem_range_AP_init();
2401 * The idle loop doesn't expect the BGL to be held and while
2402 * lwkt_switch() normally cleans things up this is a special case
2403 * because we returning almost directly into the idle loop.
2405 * The idle thread is never placed on the runq, make sure
2406 * nothing we've done put it thre.
2408 KKASSERT(curthread->td_mpcount == 1);
2409 smp_active_mask |= 1 << mycpu->gd_cpuid;
2410 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2412 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2416 * Get SMP fully working before we start initializing devices.
2424 printf("Finish MP startup");
2426 while (smp_active_mask != smp_startup_mask)
2428 while (cpu_try_mplock() == 0)
2431 printf("Active CPU Mask: %08x\n", smp_active_mask);
2434 SYSINIT(finishsmp, SI_SUB_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2436 #if defined(APIC_IO) && defined(APIC_INTR_REORDER)
2438 * Maintain mapping from softintr vector to isr bit in local apic.
2441 set_lapic_isrloc(int intr, int vector)
2443 if (intr < 0 || intr > 32)
2444 panic("set_apic_isrloc: bad intr argument: %d",intr);
2445 if (vector < ICU_OFFSET || vector > 255)
2446 panic("set_apic_isrloc: bad vector argument: %d",vector);
2447 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2448 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2455 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2456 * (if specified), rendezvous, execute the action function (if specified),
2457 * rendezvous again, execute the teardown function (if specified), and then
2460 * Note that the supplied external functions _must_ be reentrant and aware
2461 * that they are running in parallel and in an unknown lock context.
2463 static void (*smp_rv_setup_func)(void *arg);
2464 static void (*smp_rv_action_func)(void *arg);
2465 static void (*smp_rv_teardown_func)(void *arg);
2466 static void *smp_rv_func_arg;
2467 static volatile int smp_rv_waiters[2];
2470 smp_rendezvous_action(void)
2472 /* setup function */
2473 if (smp_rv_setup_func != NULL)
2474 smp_rv_setup_func(smp_rv_func_arg);
2475 /* spin on entry rendezvous */
2476 atomic_add_int(&smp_rv_waiters[0], 1);
2477 while (smp_rv_waiters[0] < ncpus)
2479 /* action function */
2480 if (smp_rv_action_func != NULL)
2481 smp_rv_action_func(smp_rv_func_arg);
2482 /* spin on exit rendezvous */
2483 atomic_add_int(&smp_rv_waiters[1], 1);
2484 while (smp_rv_waiters[1] < ncpus)
2486 /* teardown function */
2487 if (smp_rv_teardown_func != NULL)
2488 smp_rv_teardown_func(smp_rv_func_arg);
2492 smp_rendezvous(void (* setup_func)(void *),
2493 void (* action_func)(void *),
2494 void (* teardown_func)(void *),
2497 /* obtain rendezvous lock. This disables interrupts */
2498 spin_lock(&smp_rv_spinlock); /* XXX sleep here? NOWAIT flag? */
2500 /* set static function pointers */
2501 smp_rv_setup_func = setup_func;
2502 smp_rv_action_func = action_func;
2503 smp_rv_teardown_func = teardown_func;
2504 smp_rv_func_arg = arg;
2505 smp_rv_waiters[0] = 0;
2506 smp_rv_waiters[1] = 0;
2509 * Signal other processors which will enter the IPI with interrupts
2510 * disabled. We cannot safely use broadcast IPIs if some of our
2511 * cpus failed to start.
2513 if (smp_startup_mask == smp_active_mask) {
2514 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2516 selected_apic_ipi(smp_active_mask, XRENDEZVOUS_OFFSET,
2517 APIC_DELMODE_FIXED);
2520 /* call executor function */
2521 smp_rendezvous_action();
2524 spin_unlock(&smp_rv_spinlock);
2528 cpu_send_ipiq(int dcpu)
2530 if ((1 << dcpu) & smp_active_mask)
2531 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2534 #if 0 /* single_apic_ipi_passive() not working yet */
2536 * Returns 0 on failure, 1 on success
2539 cpu_send_ipiq_passive(int dcpu)
2542 if ((1 << dcpu) & smp_active_mask) {
2543 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2544 APIC_DELMODE_FIXED);