2 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org>
3 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
4 * Copyright Luigi Rizzo, 1997,1998
5 * Copyright by Hannu Savolainen 1994, 1995
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * $FreeBSD: src/sys/dev/sound/isa/mss.c,v 1.48.2.11 2002/12/24 21:17:41 semenu Exp $
30 * $DragonFly: src/sys/dev/sound/isa/mss.c,v 1.5 2005/06/10 23:06:58 dillon Exp $
33 #include <dev/sound/pcm/sound.h>
35 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/isa/mss.c,v 1.5 2005/06/10 23:06:58 dillon Exp $");
37 /* board-specific include files */
38 #include <dev/sound/isa/mss.h>
39 #include <dev/sound/isa/sb.h>
40 #include <dev/sound/chip.h>
44 #define MSS_DEFAULT_BUFSZ (4096)
45 #define abs(x) (((x) < 0) ? -(x) : (x))
46 #define MSS_INDEXED_REGS 0x20
47 #define OPL_INDEXED_REGS 0x19
52 struct mss_info *parent;
53 struct pcm_channel *channel;
54 struct snd_dbuf *buffer;
60 struct resource *io_base; /* primary I/O address for the board */
62 struct resource *conf_base; /* and the opti931 also has a config space */
66 struct resource *drq1; /* play */
68 struct resource *drq2; /* rec */
71 bus_dma_tag_t parent_dmat;
74 char mss_indexed_regs[MSS_INDEXED_REGS];
75 char opl_indexed_regs[OPL_INDEXED_REGS];
76 int bd_id; /* used to hold board-id info, eg. sb version,
77 * mss codec type, etc. etc.
79 int opti_offset; /* offset from config_base for opti931 */
80 u_long bd_flags; /* board-specific flags */
81 int optibase; /* base address for OPTi9xx config */
82 struct resource *indir; /* Indirect register index address */
84 int password; /* password for opti9xx cards */
85 int passwdreg; /* password register */
87 struct mss_chinfo pch, rch;
90 static int mss_probe(device_t dev);
91 static int mss_attach(device_t dev);
93 static driver_intr_t mss_intr;
95 /* prototypes for local functions */
96 static int mss_detect(device_t dev, struct mss_info *mss);
97 static int opti_detect(device_t dev, struct mss_info *mss);
98 static char *ymf_test(device_t dev, struct mss_info *mss);
99 static void ad_unmute(struct mss_info *mss);
101 /* mixer set funcs */
102 static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
103 static int mss_set_recsrc(struct mss_info *mss, int mask);
106 static int ad_wait_init(struct mss_info *mss, int x);
107 static int ad_read(struct mss_info *mss, int reg);
108 static void ad_write(struct mss_info *mss, int reg, u_char data);
109 static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
110 static void ad_enter_MCE(struct mss_info *mss);
111 static void ad_leave_MCE(struct mss_info *mss);
113 /* OPTi-specific functions */
114 static void opti_write(struct mss_info *mss, u_char reg,
116 static u_char opti_read(struct mss_info *mss, u_char reg);
117 static int opti_init(device_t dev, struct mss_info *mss);
120 static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
121 static u_char conf_rd(struct mss_info *mss, u_char reg);
123 static int pnpmss_probe(device_t dev);
124 static int pnpmss_attach(device_t dev);
126 static driver_intr_t opti931_intr;
128 static u_int32_t mss_fmt[] = {
130 AFMT_STEREO | AFMT_U8,
132 AFMT_STEREO | AFMT_S16_LE,
134 AFMT_STEREO | AFMT_MU_LAW,
136 AFMT_STEREO | AFMT_A_LAW,
139 static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0};
141 static u_int32_t guspnp_fmt[] = {
143 AFMT_STEREO | AFMT_U8,
145 AFMT_STEREO | AFMT_S16_LE,
147 AFMT_STEREO | AFMT_A_LAW,
150 static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0};
152 static u_int32_t opti931_fmt[] = {
154 AFMT_STEREO | AFMT_U8,
156 AFMT_STEREO | AFMT_S16_LE,
159 static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0};
161 #define MD_AD1848 0x91
162 #define MD_AD1845 0x92
163 #define MD_CS42XX 0xA1
164 #define MD_OPTI930 0xB0
165 #define MD_OPTI931 0xB1
166 #define MD_OPTI925 0xB2
167 #define MD_OPTI924 0xB3
168 #define MD_GUSPNP 0xB8
169 #define MD_GUSMAX 0xB9
170 #define MD_YM0020 0xC1
173 #define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
175 #define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX)
178 mss_lock(struct mss_info *mss)
180 snd_mtxlock(mss->lock);
184 mss_unlock(struct mss_info *mss)
186 snd_mtxunlock(mss->lock);
190 port_rd(struct resource *port, int off)
193 return bus_space_read_1(rman_get_bustag(port),
194 rman_get_bushandle(port),
201 port_wr(struct resource *port, int off, u_int8_t data)
204 bus_space_write_1(rman_get_bustag(port),
205 rman_get_bushandle(port),
210 io_rd(struct mss_info *mss, int reg)
212 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
213 return port_rd(mss->io_base, reg);
217 io_wr(struct mss_info *mss, int reg, u_int8_t data)
219 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
220 port_wr(mss->io_base, reg, data);
224 conf_wr(struct mss_info *mss, u_char reg, u_char value)
226 port_wr(mss->conf_base, 0, reg);
227 port_wr(mss->conf_base, 1, value);
231 conf_rd(struct mss_info *mss, u_char reg)
233 port_wr(mss->conf_base, 0, reg);
234 return port_rd(mss->conf_base, 1);
238 opti_wr(struct mss_info *mss, u_char reg, u_char value)
240 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
241 port_wr(mss->conf_base, mss->opti_offset + 1, value);
245 opti_rd(struct mss_info *mss, u_char reg)
247 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
248 return port_rd(mss->conf_base, mss->opti_offset + 1);
252 gus_wr(struct mss_info *mss, u_char reg, u_char value)
254 port_wr(mss->conf_base, 3, reg);
255 port_wr(mss->conf_base, 5, value);
259 gus_rd(struct mss_info *mss, u_char reg)
261 port_wr(mss->conf_base, 3, reg);
262 return port_rd(mss->conf_base, 5);
266 mss_release_resources(struct mss_info *mss, device_t dev)
270 bus_teardown_intr(dev, mss->irq, mss->ih);
271 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
276 if (mss->drq2 != mss->drq1) {
277 isa_dma_release(rman_get_start(mss->drq2));
278 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
284 isa_dma_release(rman_get_start(mss->drq1));
285 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
290 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
294 if (mss->conf_base) {
295 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
300 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
304 if (mss->parent_dmat) {
305 bus_dma_tag_destroy(mss->parent_dmat);
306 mss->parent_dmat = 0;
308 if (mss->lock) snd_mtxfree(mss->lock);
314 mss_alloc_resources(struct mss_info *mss, device_t dev)
316 int pdma, rdma, ok = 1;
318 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
319 0, ~0, 1, RF_ACTIVE);
321 mss->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &mss->irq_rid,
322 0, ~0, 1, RF_ACTIVE);
324 mss->drq1 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq1_rid,
325 0, ~0, 1, RF_ACTIVE);
326 if (mss->conf_rid >= 0 && !mss->conf_base)
327 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
328 0, ~0, 1, RF_ACTIVE);
329 if (mss->drq2_rid >= 0 && !mss->drq2)
330 mss->drq2 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq2_rid,
331 0, ~0, 1, RF_ACTIVE);
333 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
334 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
335 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
338 pdma = rman_get_start(mss->drq1);
339 isa_dma_acquire(pdma);
340 isa_dmainit(pdma, mss->bufsize);
341 mss->bd_flags &= ~BD_F_DUPLEX;
343 rdma = rman_get_start(mss->drq2);
344 isa_dma_acquire(rdma);
345 isa_dmainit(rdma, mss->bufsize);
346 mss->bd_flags |= BD_F_DUPLEX;
347 } else mss->drq2 = mss->drq1;
353 * The various mixers use a variety of bitmasks etc. The Voxware
354 * driver had a very nice technique to describe a mixer and interface
355 * to it. A table defines, for each channel, which register, bits,
356 * offset, polarity to use. This procedure creates the new value
357 * using the table and the old value.
361 change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval)
366 DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x "
367 "r %d p %d bit %d off %d\n",
368 dev, chn, newval, *regval,
369 (*t)[dev][chn].regno, (*t)[dev][chn].polarity,
370 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) );
372 if ( (*t)[dev][chn].polarity == 1) /* reverse */
373 newval = 100 - newval ;
375 mask = (1 << (*t)[dev][chn].nbits) - 1;
376 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
377 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/;
379 *regval &= ~(mask << shift); /* Filter out the previous value */
380 *regval |= (newval & mask) << shift; /* Set the new value */
383 /* -------------------------------------------------------------------- */
384 /* only one source can be set... */
386 mss_set_recsrc(struct mss_info *mss, int mask)
391 case SOUND_MASK_LINE:
392 case SOUND_MASK_LINE3:
397 case SOUND_MASK_LINE1:
401 case SOUND_MASK_IMIX:
407 mask = SOUND_MASK_MIC;
410 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
411 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
415 /* there are differences in the mixer depending on the actual sound card. */
417 mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
423 switch (mss->bd_id) {
425 mix_d = &opti931_devices;
428 mix_d = &opti930_devices;
431 mix_d = &mix_devices;
434 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) {
435 DEB(printf("nbits = 0 for dev %d\n", dev));
439 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */
441 /* Set the left channel */
443 regoffs = (*mix_d)[dev][LEFT_CHN].regno;
444 old = val = ad_read(mss, regoffs);
445 /* if volume is 0, mute chan. Otherwise, unmute. */
446 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f;
447 change_bits(mix_d, &val, dev, LEFT_CHN, left);
448 ad_write(mss, regoffs, val);
450 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n",
451 dev, regoffs, old, val));
453 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */
454 /* Set the right channel */
455 regoffs = (*mix_d)[dev][RIGHT_CHN].regno;
456 old = val = ad_read(mss, regoffs);
457 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f;
458 change_bits(mix_d, &val, dev, RIGHT_CHN, right);
459 ad_write(mss, regoffs, val);
461 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n",
462 dev, regoffs, old, val));
464 return 0; /* success */
467 /* -------------------------------------------------------------------- */
470 mssmix_init(struct snd_mixer *m)
472 struct mss_info *mss = mix_getdevinfo(m);
474 mix_setdevs(m, MODE2_MIXER_DEVICES);
475 mix_setrecdevs(m, MSS_REC_DEVICES);
478 mix_setdevs(m, OPTI930_MIXER_DEVICES);
482 mix_setdevs(m, OPTI931_MIXER_DEVICES);
484 ad_write(mss, 20, 0x88);
485 ad_write(mss, 21, 0x88);
490 mix_setdevs(m, MODE1_MIXER_DEVICES);
495 /* this is only necessary in mode 3 ... */
497 ad_write(mss, 22, 0x88);
498 ad_write(mss, 23, 0x88);
506 mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
508 struct mss_info *mss = mix_getdevinfo(m);
511 mss_mixer_set(mss, dev, left, right);
514 return left | (right << 8);
518 mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
520 struct mss_info *mss = mix_getdevinfo(m);
523 src = mss_set_recsrc(mss, src);
528 static kobj_method_t mssmix_mixer_methods[] = {
529 KOBJMETHOD(mixer_init, mssmix_init),
530 KOBJMETHOD(mixer_set, mssmix_set),
531 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc),
534 MIXER_DECLARE(mssmix_mixer);
536 /* -------------------------------------------------------------------- */
539 ymmix_init(struct snd_mixer *m)
541 struct mss_info *mss = mix_getdevinfo(m);
544 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC
545 | SOUND_MASK_BASS | SOUND_MASK_TREBLE);
546 /* Set master volume */
548 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
549 conf_wr(mss, OPL3SAx_VOLUMER, 7);
556 ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
558 struct mss_info *mss = mix_getdevinfo(m);
563 case SOUND_MIXER_VOLUME:
564 if (left) t = 15 - (left * 15) / 100;
565 else t = 0x80; /* mute */
566 conf_wr(mss, OPL3SAx_VOLUMEL, t);
567 if (right) t = 15 - (right * 15) / 100;
568 else t = 0x80; /* mute */
569 conf_wr(mss, OPL3SAx_VOLUMER, t);
572 case SOUND_MIXER_MIC:
574 if (left) t = 31 - (left * 31) / 100;
575 else t = 0x80; /* mute */
576 conf_wr(mss, OPL3SAx_MIC, t);
579 case SOUND_MIXER_BASS:
580 l = (left * 7) / 100;
581 r = (right * 7) / 100;
583 conf_wr(mss, OPL3SAx_BASS, t);
586 case SOUND_MIXER_TREBLE:
587 l = (left * 7) / 100;
588 r = (right * 7) / 100;
590 conf_wr(mss, OPL3SAx_TREBLE, t);
594 mss_mixer_set(mss, dev, left, right);
598 return left | (right << 8);
602 ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src)
604 struct mss_info *mss = mix_getdevinfo(m);
606 src = mss_set_recsrc(mss, src);
611 static kobj_method_t ymmix_mixer_methods[] = {
612 KOBJMETHOD(mixer_init, ymmix_init),
613 KOBJMETHOD(mixer_set, ymmix_set),
614 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc),
617 MIXER_DECLARE(ymmix_mixer);
619 /* -------------------------------------------------------------------- */
621 * XXX This might be better off in the gusc driver.
624 gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
626 static const unsigned char irq_bits[16] = {
627 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7
629 static const unsigned char dma_bits[8] = {
630 0, 1, 0, 2, 0, 3, 4, 5
632 device_t parent = device_get_parent(dev);
633 unsigned char irqctl, dmactl;
637 port_wr(alt, 0x0f, 0x05);
638 port_wr(alt, 0x00, 0x0c);
639 port_wr(alt, 0x0b, 0x00);
641 port_wr(alt, 0x0f, 0x00);
643 irqctl = irq_bits[isa_get_irq(parent)];
644 /* Share the IRQ with the MIDI driver. */
646 dmactl = dma_bits[isa_get_drq(parent)];
647 if (device_get_flags(parent) & DV_F_DUAL_DMA)
648 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK]
652 * Set the DMA and IRQ control latches.
654 port_wr(alt, 0x00, 0x0c);
655 port_wr(alt, 0x0b, dmactl | 0x80);
656 port_wr(alt, 0x00, 0x4c);
657 port_wr(alt, 0x0b, irqctl);
659 port_wr(alt, 0x00, 0x0c);
660 port_wr(alt, 0x0b, dmactl);
661 port_wr(alt, 0x00, 0x4c);
662 port_wr(alt, 0x0b, irqctl);
664 port_wr(mss->conf_base, 2, 0);
665 port_wr(alt, 0x00, 0x0c);
666 port_wr(mss->conf_base, 2, 0);
672 mss_init(struct mss_info *mss, device_t dev)
675 struct resource *alt;
678 mss->bd_flags |= BD_F_MCE_BIT;
682 * The MED3931 v.1.0 allocates 3 bytes for the config
683 * space, whereas v.2.0 allocates 4 bytes. What I know
684 * for sure is that the upper two ports must be used,
685 * and they should end on a boundary of 4 bytes. So I
686 * need the following trick.
689 (rman_get_start(mss->conf_base) & ~3) + 2
690 - rman_get_start(mss->conf_base);
691 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset));
692 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
693 ad_write(mss, 10, 2); /* enable interrupts */
694 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
695 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
700 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
702 /* release reset and enable DAC */
703 gus_wr(mss, 0x4c /* _URSTI */, 3);
708 alt = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
709 0, ~0, 1, RF_ACTIVE);
711 printf("XXX couldn't init GUS PnP/MAX\n");
714 port_wr(alt, 0, 0xC); /* enable int and dma */
715 if (mss->bd_id == MD_GUSMAX)
716 gusmax_setup(mss, dev, alt);
717 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt);
720 * unmute left & right line. Need to go in mode3, unmute,
723 tmp = ad_read(mss, 0x0c);
724 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
725 ad_write(mss, 0x19, 0); /* unmute left */
726 ad_write(mss, 0x1b, 0); /* unmute right */
727 ad_write(mss, 0x0c, tmp); /* restore old mode */
729 /* send codec interrupts on irq1 and only use that one */
730 gus_wr(mss, 0x5a, 0x4f);
732 /* enable access to hidden regs */
733 tmp = gus_rd(mss, 0x5b /* IVERI */);
734 gus_wr(mss, 0x5b, tmp | 1);
735 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4)));
739 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
740 r6 = conf_rd(mss, OPL3SAx_DMACONF);
741 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
742 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);)
743 /* yamaha - set volume to max */
744 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
745 conf_wr(mss, OPL3SAx_VOLUMER, 0);
746 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
749 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
750 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
752 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
754 ad_write(mss, 10, 2); /* int enable */
755 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
756 /* the following seem required on the CS4232 */
763 * main irq handler for the CS423x. The OPTi931 code is
765 * The correct way to operate for a device with multiple internal
766 * interrupt sources is to loop on the status register and ack
767 * interrupts until all interrupts are served and none are reported. At
768 * this point the IRQ line to the ISA IRQ controller should go low
769 * and be raised at the next interrupt.
771 * Since the ISA IRQ controller is sent EOI _before_ passing control
772 * to the isr, it might happen that we serve an interrupt early, in
773 * which case the status register at the next interrupt should just
774 * say that there are no more interrupts...
780 struct mss_info *mss = arg;
781 u_char c = 0, served = 0;
784 DEB(printf("mss_intr\n"));
786 ad_read(mss, 11); /* fake read of status bits */
788 /* loop until there are interrupts, but no more than 10 times. */
789 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
790 /* get exact reason for full-duplex boards */
791 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
793 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
795 chn_intr(mss->pch.channel);
797 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
799 chn_intr(mss->rch.channel);
801 /* now ack the interrupt */
802 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
803 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
806 BVDDB(printf("mss_intr: irq, but not from mss\n"));
807 } else if (served == 0) {
808 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c));
810 * this should not happen... I have no idea what to do now.
811 * maybe should do a sanity check and restart dmas ?
813 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
819 * AD_WAIT_INIT waits if we are initializing the board and
820 * we cannot modify its settings
823 ad_wait_init(struct mss_info *mss, int x)
825 int arg = x, n = 0; /* to shut up the compiler... */
827 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
829 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n);
834 ad_read(struct mss_info *mss, int reg)
838 ad_wait_init(mss, 201000);
839 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
840 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
841 x = io_rd(mss, MSS_IDATA);
842 /* printf("ad_read %d, %x\n", reg, x); */
847 ad_write(struct mss_info *mss, int reg, u_char data)
851 /* printf("ad_write %d, %x\n", reg, data); */
852 ad_wait_init(mss, 1002000);
853 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
854 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
855 io_wr(mss, MSS_IDATA, data);
859 ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
861 ad_write(mss, reg+1, cnt & 0xff);
862 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
866 wait_for_calibration(struct mss_info *mss)
871 * Wait until the auto calibration process has finished.
873 * 1) Wait until the chip becomes ready (reads don't return 0x80).
874 * 2) Wait until the ACI bit of I11 gets on
875 * 3) Wait until the ACI bit of I11 gets off
878 t = ad_wait_init(mss, 1000000);
879 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
882 * The calibration mode for chips that support it is set so that
883 * we never see ACI go on.
885 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
886 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
889 * XXX This should only be enabled for cards that *really*
890 * need it. Are there any?
892 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
894 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
898 ad_unmute(struct mss_info *mss)
900 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
901 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
905 ad_enter_MCE(struct mss_info *mss)
909 mss->bd_flags |= BD_F_MCE_BIT;
910 ad_wait_init(mss, 203000);
911 prev = io_rd(mss, MSS_INDEX);
913 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
917 ad_leave_MCE(struct mss_info *mss)
921 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
922 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n"));
926 ad_wait_init(mss, 1000000);
928 mss->bd_flags &= ~BD_F_MCE_BIT;
930 prev = io_rd(mss, MSS_INDEX);
932 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
933 wait_for_calibration(mss);
937 mss_speed(struct mss_chinfo *ch, int speed)
939 struct mss_info *mss = ch->parent;
941 * In the CS4231, the low 4 bits of I8 are used to hold the
942 * sample rate. Only a fixed number of values is allowed. This
943 * table lists them. The speed-setting routines scans the table
944 * looking for the closest match. This is the only supported method.
946 * In the CS4236, there is an alternate metod (which we do not
947 * support yet) which provides almost arbitrary frequency setting.
948 * In the AD1845, it looks like the sample rate can be
949 * almost arbitrary, and written directly to a register.
950 * In the OPTi931, there is a SB command which provides for
951 * almost arbitrary frequency setting.
955 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
956 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
957 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
958 /* XXX must also do something in I27 for the ad1845 */
960 int i, sel = 0; /* assume entry 0 does not contain -1 */
961 static int speeds[] =
962 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050,
963 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615};
965 for (i = 1; i < 16; i++)
967 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i;
969 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
977 * mss_format checks that the format is supported (or defaults to AFMT_U8)
978 * and returns the bit setting for the 1848 register corresponding to
979 * the desired format.
985 mss_format(struct mss_chinfo *ch, u_int32_t format)
987 struct mss_info *mss = ch->parent;
988 int i, arg = format & ~AFMT_STEREO;
991 * The data format uses 3 bits (just 2 on the 1848). For each
992 * bit setting, the following array returns the corresponding format.
993 * The code scans the array looking for a suitable format. In
994 * case it is not found, default to AFMT_U8 (not such a good
995 * choice, but let's do it for compatibility...).
999 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW,
1000 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1};
1003 for (i = 0; i < 8; i++) if (arg == fmts[i]) break;
1005 if (format & AFMT_STEREO) arg |= 1;
1008 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
1009 if (FULL_DUPLEX(mss)) ad_write(mss, 28, arg); /* capture mode */
1015 mss_trigger(struct mss_chinfo *ch, int go)
1017 struct mss_info *mss = ch->parent;
1019 int retry, wr, cnt, ss;
1022 ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0;
1023 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0;
1025 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0;
1026 m = ad_read(mss, 9);
1029 cnt = (ch->blksz / ss) - 1;
1031 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m););
1032 m |= wr? I9_PEN : I9_CEN; /* enable DMA */
1033 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1037 case PCMTRIG_ABORT: /* XXX check this... */
1038 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */
1041 * try to disable DMA by clearing count registers. Not sure it
1042 * is needed, and it might cause false interrupts when the
1043 * DMA is re-enabled later.
1045 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1048 /* on the OPTi931 the enable bit seems hard to set... */
1049 for (retry = 10; retry > 0; retry--) {
1050 ad_write(mss, 9, m);
1051 if (ad_read(mss, 9) == m) break;
1053 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \
1054 m, ad_read(mss, 9)));
1060 * the opti931 seems to miss interrupts when working in full
1061 * duplex, so we try some heuristics to catch them.
1064 opti931_intr(void *arg)
1066 struct mss_info *mss = (struct mss_info *)arg;
1067 u_char masked = 0, i11, mc11, c = 0;
1068 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */
1072 reason = io_rd(mss, MSS_STATUS);
1073 if (!(reason & 1)) {/* no int, maybe a shared line ? */
1074 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
1079 i11 = ad_read(mss, 11); /* XXX what's for ? */
1082 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1085 DEB(printf("Warning: CD interrupt\n");)
1089 DEB(printf("Warning: MPU interrupt\n");)
1092 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\
1096 * the nice OPTi931 sets the IRQ line before setting the bits in
1097 * mc11. So, on some occasions I have to retry (max 10 times).
1099 if (mc11 == 0) { /* perhaps can return ... */
1100 reason = io_rd(mss, MSS_STATUS);
1102 DEB(printf("one more try...\n");)
1103 if (--loops) goto again;
1104 else DDB(printf("intr, but mc11 not set\n");)
1106 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11));
1111 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) chn_intr(mss->rch.channel);
1112 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) chn_intr(mss->pch.channel);
1113 opti_wr(mss, 11, ~mc11); /* ack */
1114 if (--loops) goto again;
1116 DEB(printf("xxx too many loops\n");)
1119 /* -------------------------------------------------------------------- */
1120 /* channel interface */
1122 msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1124 struct mss_info *mss = devinfo;
1125 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1131 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, mss->bufsize) == -1) return NULL;
1132 sndbuf_isadmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
1137 msschan_setformat(kobj_t obj, void *data, u_int32_t format)
1139 struct mss_chinfo *ch = data;
1140 struct mss_info *mss = ch->parent;
1143 mss_format(ch, format);
1149 msschan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1151 struct mss_chinfo *ch = data;
1152 struct mss_info *mss = ch->parent;
1156 r = mss_speed(ch, speed);
1163 msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1165 struct mss_chinfo *ch = data;
1167 ch->blksz = blocksize;
1168 sndbuf_resize(ch->buffer, 2, ch->blksz);
1174 msschan_trigger(kobj_t obj, void *data, int go)
1176 struct mss_chinfo *ch = data;
1177 struct mss_info *mss = ch->parent;
1179 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
1182 sndbuf_isadma(ch->buffer, go);
1184 mss_trigger(ch, go);
1190 msschan_getptr(kobj_t obj, void *data)
1192 struct mss_chinfo *ch = data;
1193 return sndbuf_isadmaptr(ch->buffer);
1196 static struct pcmchan_caps *
1197 msschan_getcaps(kobj_t obj, void *data)
1199 struct mss_chinfo *ch = data;
1201 switch(ch->parent->bd_id) {
1203 return &opti931_caps;
1208 return &guspnp_caps;
1217 static kobj_method_t msschan_methods[] = {
1218 KOBJMETHOD(channel_init, msschan_init),
1219 KOBJMETHOD(channel_setformat, msschan_setformat),
1220 KOBJMETHOD(channel_setspeed, msschan_setspeed),
1221 KOBJMETHOD(channel_setblocksize, msschan_setblocksize),
1222 KOBJMETHOD(channel_trigger, msschan_trigger),
1223 KOBJMETHOD(channel_getptr, msschan_getptr),
1224 KOBJMETHOD(channel_getcaps, msschan_getcaps),
1227 CHANNEL_DECLARE(msschan);
1229 /* -------------------------------------------------------------------- */
1232 * mss_probe() is the probe routine. Note, it is not necessary to
1233 * go through this for PnP devices, since they are already
1234 * indentified precisely using their PnP id.
1236 * The base address supplied in the device refers to the old MSS
1237 * specs where the four 4 registers in io space contain configuration
1238 * information. Some boards (as an example, early MSS boards)
1239 * has such a block of registers, whereas others (generally CS42xx)
1240 * do not. In order to distinguish between the two and do not have
1241 * to supply two separate probe routines, the flags entry in isa_device
1242 * has a bit to mark this.
1247 mss_probe(device_t dev)
1250 int flags, irq, drq, result = ENXIO, setres = 0;
1251 struct mss_info *mss;
1253 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */
1255 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1256 if (!mss) return ENXIO;
1263 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1264 0, ~0, 8, RF_ACTIVE);
1265 if (!mss->io_base) {
1266 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530));
1268 /* XXX verify this */
1270 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
1272 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1273 0, ~0, 8, RF_ACTIVE);
1275 if (!mss->io_base) goto no;
1277 /* got irq/dma regs? */
1278 flags = device_get_flags(dev);
1279 irq = isa_get_irq(dev);
1280 drq = isa_get_drq(dev);
1282 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end;
1285 * Check if the IO port returns valid signature. The original MS
1286 * Sound system returns 0x04 while some cards
1287 * (AudioTriX Pro for example) return 0x00 or 0x0f.
1290 device_set_desc(dev, "MSS");
1291 tmpx = tmp = io_rd(mss, 3);
1292 if (tmp == 0xff) { /* Bus float */
1293 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp));
1294 device_set_flags(dev, flags & ~DV_F_TRUE_MSS);
1298 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) {
1299 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n",
1300 rman_get_start(mss->io_base), tmpx));
1308 printf("MSS: Bad IRQ %d\n", irq);
1311 if (!(drq == 0 || drq == 1 || drq == 3)) {
1312 printf("MSS: Bad DMA %d\n", drq);
1316 /* 8-bit board: only drq1/3 and irq7/9 */
1318 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1321 if (!(irq == 7 || irq == 9)) {
1322 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n",
1328 result = mss_detect(dev, mss);
1330 mss_release_resources(mss, dev);
1332 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev,
1333 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
1339 mss_detect(device_t dev, struct mss_info *mss)
1342 u_char tmp = 0, tmp1, tmp2;
1343 char *name, *yamaha;
1345 if (mss->bd_id != 0) {
1346 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
1347 device_get_desc(dev));
1352 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
1355 if (opti_detect(dev, mss)) {
1356 switch (mss->bd_id) {
1364 printf("Found OPTi device %s\n", name);
1365 if (opti_init(dev, mss) == 0) goto gotit;
1370 * Check that the I/O address is in use.
1372 * bit 7 of the base I/O port is known to be 0 after the chip has
1373 * performed its power on initialization. Just assume this has
1374 * happened before the OS is starting.
1376 * If the I/O address is unused, it typically returns 0xff.
1379 for (i = 0; i < 10; i++)
1380 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
1383 if (i >= 10) { /* Not a AD1848 */
1384 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp));
1388 * Test if it's possible to change contents of the indirect
1389 * registers. Registers 0 and 1 are ADC volume registers. The bit
1390 * 0x10 is read only so try to avoid using it.
1393 ad_write(mss, 0, 0xaa);
1394 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
1395 tmp1 = ad_read(mss, 0);
1396 tmp2 = ad_read(mss, 1);
1397 if (tmp1 != 0xaa || tmp2 != 0x45) {
1398 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2));
1402 ad_write(mss, 0, 0x45);
1403 ad_write(mss, 1, 0xaa);
1404 tmp1 = ad_read(mss, 0);
1405 tmp2 = ad_read(mss, 1);
1406 if (tmp1 != 0x45 || tmp2 != 0xaa) {
1407 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2));
1412 * The indirect register I12 has some read only bits. Lets try to
1416 tmp = ad_read(mss, 12);
1417 ad_write(mss, 12, (~tmp) & 0x0f);
1418 tmp1 = ad_read(mss, 12);
1420 if ((tmp & 0x0f) != (tmp1 & 0x0f)) {
1421 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp));
1426 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1428 * 0x0A=RevC. also CS4231/CS4231A and OPTi931
1431 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);)
1434 * The original AD1848/CS4248 has just 16 indirect registers. This
1435 * means that I0 and I16 should return the same value (etc.). Ensure
1436 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1440 ad_write(mss, 12, 0); /* Mode2=disabled */
1442 for (i = 0; i < 16; i++) {
1443 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
1444 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n",
1447 * note - this seems to fail on the 4232 on I11. So we just break
1448 * rather than fail. (which makes this test pointless - cg)
1450 break; /* return 0; */
1455 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
1456 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231.
1458 * On the OPTi931, however, I12 is readonly and only contains the
1459 * chip revision ID (as in the CS4231A). The upper bits return 0.
1462 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
1464 tmp1 = ad_read(mss, 12);
1465 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */
1466 if ((tmp1 & 0xf0) == 0x00) {
1467 BVDDB(printf("this should be an OPTi931\n");)
1468 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit;
1470 * The 4231 has bit7=1 always, and bit6 we just set to 1.
1471 * We want to check that this is really a CS4231
1472 * Verify that setting I0 doesn't change I16.
1474 ad_write(mss, 16, 0); /* Set I16 to known value */
1475 ad_write(mss, 0, 0x45);
1476 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
1478 ad_write(mss, 0, 0xaa);
1479 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
1480 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1));
1483 /* Verify that some bits of I25 are read only. */
1484 tmp1 = ad_read(mss, 25); /* Original bits */
1485 ad_write(mss, 25, ~tmp1); /* Invert all bits */
1486 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
1489 /* It's at least CS4231 */
1491 mss->bd_id = MD_CS42XX;
1494 * It could be an AD1845 or CS4231A as well.
1495 * CS4231 and AD1845 report the same revision info in I25
1496 * while the CS4231A reports different.
1499 id = ad_read(mss, 25) & 0xe7;
1501 * b7-b5 = version number;
1511 mss->bd_id = MD_CS42XX;
1516 mss->bd_id = MD_CS42XX;
1520 /* strange: the 4231 data sheet says b4-b3 are XX
1521 * so this should be the same as 0xa2
1524 mss->bd_id = MD_CS42XX;
1529 * It must be a CS4231 or AD1845. The register I23
1530 * of CS4231 is undefined and it appears to be read
1531 * only. AD1845 uses I23 for setting sample rate.
1532 * Assume the chip is AD1845 if I23 is changeable.
1535 tmp = ad_read(mss, 23);
1537 ad_write(mss, 23, ~tmp);
1538 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
1540 mss->bd_id = MD_AD1845;
1542 ad_write(mss, 23, tmp); /* Restore */
1544 yamaha = ymf_test(dev, mss);
1546 mss->bd_id = MD_YM0020;
1551 case 0x83: /* CS4236 */
1552 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */
1554 mss->bd_id = MD_CS42XX;
1557 default: /* Assume CS4231 */
1558 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);)
1559 mss->bd_id = MD_CS42XX;
1562 ad_write(mss, 25, tmp1); /* Restore bits */
1564 BVDDB(printf("mss_detect() - Detected %s\n", name));
1565 device_set_desc(dev, name);
1566 device_set_flags(dev,
1567 ((device_get_flags(dev) & ~DV_F_DEV_MASK) |
1568 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
1575 opti_detect(device_t dev, struct mss_info *mss)
1578 static const struct opticard {
1585 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */
1586 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */
1591 for (c = 0; cards[c].base; c++) {
1592 mss->optibase = cards[c].base;
1593 mss->password = cards[c].password;
1594 mss->passwdreg = cards[c].passwdreg;
1595 mss->bd_id = cards[c].boardid;
1597 if (cards[c].indir_reg)
1598 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
1599 &mss->indir_rid, cards[c].indir_reg,
1600 cards[c].indir_reg+1, 1, RF_ACTIVE);
1602 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
1603 &mss->conf_rid, mss->optibase, mss->optibase+9,
1606 if (opti_read(mss, 1) != 0xff) {
1610 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
1613 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
1614 mss->conf_base = NULL;
1621 ymf_test(device_t dev, struct mss_info *mss)
1623 static int ports[] = {0x370, 0x310, 0x538};
1624 int p, i, j, version;
1625 static char *chipset[] = {
1627 "OPL3-SA2 (YMF711)", /* 1 */
1628 "OPL3-SA3 (YMF715)", /* 2 */
1629 "OPL3-SA3 (YMF715)", /* 3 */
1630 "OPL3-SAx (YMF719)", /* 4 */
1631 "OPL3-SAx (YMF719)", /* 5 */
1632 "OPL3-SAx (YMF719)", /* 6 */
1633 "OPL3-SAx (YMF719)", /* 7 */
1636 for (p = 0; p < 3; p++) {
1638 mss->conf_base = bus_alloc_resource(dev,
1641 ports[p], ports[p] + 1, 2,
1643 if (!mss->conf_base) return 0;
1645 /* Test the index port of the config registers */
1646 i = port_rd(mss->conf_base, 0);
1647 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
1648 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
1649 port_wr(mss->conf_base, 0, i);
1651 bus_release_resource(dev, SYS_RES_IOPORT,
1652 mss->conf_rid, mss->conf_base);
1654 /* PC98 need this. I don't know reason why. */
1655 bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid);
1660 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
1661 return chipset[version];
1667 mss_doattach(device_t dev, struct mss_info *mss)
1669 int pdma, rdma, flags = device_get_flags(dev);
1670 char status[SND_STATUSLEN], status2[SND_STATUSLEN];
1672 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
1673 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
1674 if (!mss_alloc_resources(mss, dev)) goto no;
1676 pdma = rman_get_start(mss->drq1);
1677 rdma = rman_get_start(mss->drq2);
1678 if (flags & DV_F_TRUE_MSS) {
1679 /* has IRQ/DMA registers, set IRQ and DMA addr */
1680 #ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */
1681 static char interrupt_bits[13] =
1682 {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20};
1684 static char interrupt_bits[12] =
1685 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20};
1687 static char pdma_bits[4] = {1, 2, -1, 3};
1688 static char valid_rdma[4] = {1, 0, -1, 0};
1691 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
1693 #ifndef PC98 /* CS423[12] in PC98 don't support this. */
1694 io_wr(mss, 0, bits | 0x40); /* config port */
1695 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
1697 /* Write IRQ+DMA setup */
1698 if (pdma_bits[pdma] == -1) goto no;
1699 bits |= pdma_bits[pdma];
1701 if (rdma == valid_rdma[pdma]) bits |= 4;
1703 printf("invalid dual dma config %d:%d\n", pdma, rdma);
1707 io_wr(mss, 0, bits);
1708 printf("drq/irq conf %x\n", io_rd(mss, 0));
1710 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
1711 switch (mss->bd_id) {
1713 snd_setup_intr(dev, mss->irq, INTR_MPSAFE, opti931_intr, mss, &mss->ih, NULL);
1716 snd_setup_intr(dev, mss->irq, INTR_MPSAFE, mss_intr, mss, &mss->ih, NULL);
1719 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX);
1720 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
1721 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT,
1722 /*highaddr*/BUS_SPACE_MAXADDR,
1723 /*filter*/NULL, /*filterarg*/NULL,
1724 /*maxsize*/mss->bufsize, /*nsegments*/1,
1726 /*flags*/0, &mss->parent_dmat) != 0) {
1727 device_printf(dev, "unable to create dma tag\n");
1732 snprintf(status2, SND_STATUSLEN, ":%d", rdma);
1736 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u",
1737 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
1739 if (pcm_register(dev, mss, 1, 1)) goto no;
1740 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
1741 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
1742 pcm_setstatus(dev, status);
1746 mss_release_resources(mss, dev);
1751 mss_detach(device_t dev)
1754 struct mss_info *mss;
1756 r = pcm_unregister(dev);
1760 mss = pcm_getdevinfo(dev);
1761 mss_release_resources(mss, dev);
1767 mss_attach(device_t dev)
1769 struct mss_info *mss;
1770 int flags = device_get_flags(dev);
1772 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1773 if (!mss) return ENXIO;
1780 if (flags & DV_F_DUAL_DMA) {
1781 bus_set_resource(dev, SYS_RES_DRQ, 1,
1782 flags & DV_F_DRQ_MASK, 1);
1785 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
1786 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
1787 return mss_doattach(dev, mss);
1791 * mss_resume() is the code to allow a laptop to resume using the sound
1794 * This routine re-sets the state of the board to the state before going
1795 * to sleep. According to the yamaha docs this is the right thing to do,
1796 * but getting DMA restarted appears to be a bit of a trick, so the device
1797 * has to be closed and re-opened to be re-used, but there is no skipping
1798 * problem, and volume, bass/treble and most other things are restored
1804 mss_resume(device_t dev)
1807 * Restore the state taken below.
1809 struct mss_info *mss;
1812 mss = pcm_getdevinfo(dev);
1814 if (mss->bd_id == MD_YM0020)
1816 /* This works on a Toshiba Libretto 100CT. */
1817 for (i = 0; i < MSS_INDEXED_REGS; i++)
1818 ad_write(mss, i, mss->mss_indexed_regs[i]);
1819 for (i = 0; i < OPL_INDEXED_REGS; i++)
1820 conf_wr(mss, i, mss->opl_indexed_regs[i]);
1828 * mss_suspend() is the code that gets called right before a laptop
1831 * This code saves the state of the sound card right before shutdown
1832 * so it can be restored above.
1837 mss_suspend(device_t dev)
1840 struct mss_info *mss;
1842 mss = pcm_getdevinfo(dev);
1844 if(mss->bd_id == MD_YM0020)
1846 /* this stops playback. */
1847 conf_wr(mss, 0x12, 0x0c);
1848 for(i = 0; i < MSS_INDEXED_REGS; i++)
1849 mss->mss_indexed_regs[i] = ad_read(mss, i);
1850 for(i = 0; i < OPL_INDEXED_REGS; i++)
1851 mss->opl_indexed_regs[i] = conf_rd(mss, i);
1852 mss->opl_indexed_regs[0x12] = 0x0;
1857 static device_method_t mss_methods[] = {
1858 /* Device interface */
1859 DEVMETHOD(device_probe, mss_probe),
1860 DEVMETHOD(device_attach, mss_attach),
1861 DEVMETHOD(device_detach, mss_detach),
1862 DEVMETHOD(device_suspend, mss_suspend),
1863 DEVMETHOD(device_resume, mss_resume),
1868 static driver_t mss_driver = {
1874 DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0);
1875 MODULE_DEPEND(snd_mss, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
1876 MODULE_VERSION(snd_mss, 1);
1879 azt2320_mss_mode(struct mss_info *mss, device_t dev)
1881 struct resource *sbport;
1886 sbport = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1887 0, ~0, 1, RF_ACTIVE);
1889 for (i = 0; i < 1000; i++) {
1890 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1891 DELAY((i > 100) ? 1000 : 10);
1893 port_wr(sbport, SBDSP_CMD, 0x09);
1897 for (i = 0; i < 1000; i++) {
1898 if ((port_rd(sbport, SBDSP_STATUS) & 0x80))
1899 DELAY((i > 100) ? 1000 : 10);
1901 port_wr(sbport, SBDSP_CMD, 0x00);
1907 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport);
1912 static struct isa_pnp_id pnpmss_ids[] = {
1913 {0x0000630e, "CS423x"}, /* CSC0000 */
1914 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */
1915 {0x01000000, "CMI8330"}, /* @@@0001 */
1916 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */
1917 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */
1918 {0x1093143e, "OPTi931"}, /* OPT9310 */
1919 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */
1920 {0x0000143e, "OPTi924"}, /* OPT0924 */
1921 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */
1922 {0x01005407, "Aztech 2320"}, /* AZT0001 */
1924 {0x0000561e, "GusPnP"}, /* GRV0000 */
1930 pnpmss_probe(device_t dev)
1934 lid = isa_get_logicalid(dev);
1935 vid = isa_get_vendorid(dev);
1936 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */
1938 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids);
1942 pnpmss_attach(device_t dev)
1944 struct mss_info *mss;
1946 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1955 mss->bd_id = MD_CS42XX;
1957 switch (isa_get_logicalid(dev)) {
1958 case 0x0000630e: /* CSC0000 */
1959 case 0x0001630e: /* CSC0100 */
1960 mss->bd_flags |= BD_F_MSS_OFFSET;
1963 case 0x2100a865: /* YHM0021 */
1966 mss->bd_id = MD_YM0020;
1969 case 0x1110d315: /* ENS1011 */
1971 mss->bd_id = MD_VIVO;
1974 case 0x1093143e: /* OPT9310 */
1975 mss->bd_flags |= BD_F_MSS_OFFSET;
1977 mss->bd_id = MD_OPTI931;
1980 case 0x5092143e: /* OPT9250 XXX guess */
1983 mss->bd_id = MD_OPTI925;
1986 case 0x0000143e: /* OPT0924 */
1987 mss->password = 0xe5;
1989 mss->optibase = 0xf0c;
1992 mss->bd_id = MD_OPTI924;
1993 mss->bd_flags |= BD_F_924PNP;
1994 if(opti_init(dev, mss) != 0)
1998 case 0x1022b839: /* NMX2210 */
2002 case 0x01005407: /* AZT0001 */
2003 /* put into MSS mode first (snatched from NetBSD) */
2004 if (azt2320_mss_mode(mss, dev) == -1)
2007 mss->bd_flags |= BD_F_MSS_OFFSET;
2012 case 0x0000561e: /* GRV0000 */
2013 mss->bd_flags |= BD_F_MSS_OFFSET;
2018 mss->bd_id = MD_GUSPNP;
2021 case 0x01000000: /* @@@0001 */
2025 /* Unknown MSS default. We could let the CSC0000 stuff match too */
2027 mss->bd_flags |= BD_F_MSS_OFFSET;
2030 return mss_doattach(dev, mss);
2034 opti_init(device_t dev, struct mss_info *mss)
2036 int flags = device_get_flags(dev);
2039 if (!mss->conf_base) {
2040 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
2041 mss->optibase, 0x9);
2043 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2044 &mss->conf_rid, mss->optibase, mss->optibase+0x9,
2048 if (!mss->conf_base)
2052 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2053 &mss->io_rid, 0, ~0, 8, RF_ACTIVE);
2055 if (!mss->io_base) /* No hint specified, use 0x530 */
2056 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2057 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
2062 switch (rman_get_start(mss->io_base)) {
2076 printf("opti_init: invalid MSS base address!\n");
2081 switch (mss->bd_id) {
2083 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */
2084 opti_write(mss, 2, 0x00); /* Disable CD */
2085 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */
2086 opti_write(mss, 4, 0xf0);
2087 opti_write(mss, 5, 0x00);
2088 opti_write(mss, 6, 0x02); /* MPU stuff */
2092 opti_write(mss, 1, 0x00 | basebits);
2093 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */
2094 opti_write(mss, 4, 0x52); /* Empty FIFO */
2095 opti_write(mss, 5, 0x3c); /* Mode 2 */
2096 opti_write(mss, 6, 0x02); /* Enable MSS */
2100 if (mss->bd_flags & BD_F_924PNP) {
2101 u_int32_t irq = isa_get_irq(dev);
2102 u_int32_t drq = isa_get_drq(dev);
2103 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
2104 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
2105 if (flags & DV_F_DUAL_DMA) {
2106 bus_set_resource(dev, SYS_RES_DRQ, 1,
2107 flags & DV_F_DRQ_MASK, 1);
2112 /* OPTixxx has I/DRQ registers */
2114 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS);
2120 opti_write(struct mss_info *mss, u_char reg, u_char val)
2122 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2124 switch(mss->bd_id) {
2126 if (reg > 7) { /* Indirect register */
2127 port_wr(mss->conf_base, mss->passwdreg, reg);
2128 port_wr(mss->conf_base, mss->passwdreg,
2130 port_wr(mss->conf_base, 9, val);
2133 port_wr(mss->conf_base, reg, val);
2137 port_wr(mss->indir, 0, reg);
2138 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2139 port_wr(mss->indir, 1, val);
2145 opti_read(struct mss_info *mss, u_char reg)
2147 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2149 switch(mss->bd_id) {
2151 if (reg > 7) { /* Indirect register */
2152 port_wr(mss->conf_base, mss->passwdreg, reg);
2153 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2154 return(port_rd(mss->conf_base, 9));
2156 return(port_rd(mss->conf_base, reg));
2160 port_wr(mss->indir, 0, reg);
2161 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2162 return port_rd(mss->indir, 1);
2168 static device_method_t pnpmss_methods[] = {
2169 /* Device interface */
2170 DEVMETHOD(device_probe, pnpmss_probe),
2171 DEVMETHOD(device_attach, pnpmss_attach),
2172 DEVMETHOD(device_detach, mss_detach),
2173 DEVMETHOD(device_suspend, mss_suspend),
2174 DEVMETHOD(device_resume, mss_resume),
2179 static driver_t pnpmss_driver = {
2185 DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0);
2186 MODULE_DEPEND(snd_pnpmss, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
2187 MODULE_VERSION(snd_pnpmss, 1);
2190 guspcm_probe(device_t dev)
2192 struct sndcard_func *func;
2194 func = device_get_ivars(dev);
2195 if (func == NULL || func->func != SCF_PCM)
2198 device_set_desc(dev, "GUS CS4231");
2203 guspcm_attach(device_t dev)
2205 device_t parent = device_get_parent(dev);
2206 struct mss_info *mss;
2210 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
2214 mss->bd_flags = BD_F_MSS_OFFSET;
2221 if (isa_get_logicalid(parent) == 0)
2222 mss->bd_id = MD_GUSMAX;
2224 mss->bd_id = MD_GUSPNP;
2229 flags = device_get_flags(parent);
2230 if (flags & DV_F_DUAL_DMA)
2233 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
2234 0, ~0, 8, RF_ACTIVE);
2236 if (mss->conf_base == NULL) {
2237 mss_release_resources(mss, dev);
2241 base = isa_get_port(parent);
2243 ctl = 0x40; /* CS4231 enable */
2244 if (isa_get_drq(dev) > 3)
2245 ctl |= 0x10; /* 16-bit dma channel 1 */
2246 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3)
2247 ctl |= 0x20; /* 16-bit dma channel 2 */
2248 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */
2249 port_wr(mss->conf_base, 6, ctl);
2252 return mss_doattach(dev, mss);
2255 static device_method_t guspcm_methods[] = {
2256 DEVMETHOD(device_probe, guspcm_probe),
2257 DEVMETHOD(device_attach, guspcm_attach),
2258 DEVMETHOD(device_detach, mss_detach),
2263 static driver_t guspcm_driver = {
2269 DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0);
2270 MODULE_DEPEND(snd_guspcm, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
2271 MODULE_VERSION(snd_guspcm, 1);