2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <sys/resourcevar.h>
56 #include <sys/sfbuf.h>
59 #include <drm/i915_drm.h>
61 #include "intel_drv.h"
62 #include "intel_ringbuffer.h"
63 #include <linux/completion.h>
64 #include <linux/jiffies.h>
65 #include <linux/time.h>
67 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
68 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
69 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
71 bool map_and_fenceable,
73 static int i915_gem_phys_pwrite(struct drm_device *dev,
74 struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
75 uint64_t size, struct drm_file *file_priv);
77 static void i915_gem_write_fence(struct drm_device *dev, int reg,
78 struct drm_i915_gem_object *obj);
79 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
80 struct drm_i915_fence_reg *fence,
83 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
85 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
86 uint32_t size, int tiling_mode);
87 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
89 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
90 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
92 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
95 i915_gem_release_mmap(obj);
97 /* As we do not have an associated fence register, we will force
98 * a tiling change if we ever need to acquire one.
100 obj->fence_dirty = false;
101 obj->fence_reg = I915_FENCE_REG_NONE;
104 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
105 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
106 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
107 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
108 static void i915_gem_reset_fences(struct drm_device *dev);
109 static void i915_gem_lowmem(void *arg);
111 static int i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
112 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file);
114 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
115 long i915_gem_wired_pages_cnt;
117 /* some bookkeeping */
118 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
121 dev_priv->mm.object_count++;
122 dev_priv->mm.object_memory += size;
125 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
128 dev_priv->mm.object_count--;
129 dev_priv->mm.object_memory -= size;
133 i915_gem_wait_for_error(struct drm_device *dev)
135 struct drm_i915_private *dev_priv = dev->dev_private;
136 struct completion *x = &dev_priv->error_completion;
139 if (!atomic_read(&dev_priv->mm.wedged))
143 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
144 * userspace. If it takes that long something really bad is going on and
145 * we should simply try to bail out and fail as gracefully as possible.
147 ret = wait_for_completion_interruptible_timeout(x, 10*hz);
149 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
151 } else if (ret < 0) {
155 if (atomic_read(&dev_priv->mm.wedged)) {
156 /* GPU is hung, bump the completion count to account for
157 * the token we just consumed so that we never hit zero and
158 * end up waiting upon a subsequent completion event that
161 spin_lock(&x->wait.lock);
163 spin_unlock(&x->wait.lock);
168 int i915_mutex_lock_interruptible(struct drm_device *dev)
172 ret = i915_gem_wait_for_error(dev);
176 ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
180 WARN_ON(i915_verify_lists(dev));
185 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
191 i915_gem_init_ioctl(struct drm_device *dev, void *data,
192 struct drm_file *file)
194 struct drm_i915_gem_init *args = data;
196 if (drm_core_check_feature(dev, DRIVER_MODESET))
199 if (args->gtt_start >= args->gtt_end ||
200 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
203 /* GEM with user mode setting was never supported on ilk and later. */
204 if (INTEL_INFO(dev)->gen >= 5)
207 lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
208 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
209 lockmgr(&dev->dev_lock, LK_RELEASE);
215 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
216 struct drm_file *file)
218 struct drm_i915_private *dev_priv = dev->dev_private;
219 struct drm_i915_gem_get_aperture *args = data;
220 struct drm_i915_gem_object *obj;
225 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
227 pinned += obj->gtt_space->size;
230 args->aper_size = dev_priv->mm.gtt_total;
231 args->aper_available_size = args->aper_size - pinned;
237 i915_gem_create(struct drm_file *file,
238 struct drm_device *dev,
242 struct drm_i915_gem_object *obj;
246 size = roundup(size, PAGE_SIZE);
250 /* Allocate the new object */
251 obj = i915_gem_alloc_object(dev, size);
256 ret = drm_gem_handle_create(file, &obj->base, &handle);
258 drm_gem_object_release(&obj->base);
259 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
260 drm_free(obj, DRM_I915_GEM);
264 /* drop reference from allocate - handle holds it now */
265 drm_gem_object_unreference(&obj->base);
271 i915_gem_dumb_create(struct drm_file *file,
272 struct drm_device *dev,
273 struct drm_mode_create_dumb *args)
276 /* have to work out size/pitch and return them */
277 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
278 args->size = args->pitch * args->height;
279 return i915_gem_create(file, dev,
280 args->size, &args->handle);
283 int i915_gem_dumb_destroy(struct drm_file *file,
284 struct drm_device *dev,
288 return drm_gem_handle_delete(file, handle);
292 * Creates a new mm object and returns a handle to it.
295 i915_gem_create_ioctl(struct drm_device *dev, void *data,
296 struct drm_file *file)
298 struct drm_i915_gem_create *args = data;
300 return i915_gem_create(file, dev,
301 args->size, &args->handle);
304 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
306 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
308 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
309 obj->tiling_mode != I915_TILING_NONE;
313 * Reads data from the object referenced by handle.
315 * On error, the contents of *data are undefined.
318 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
319 struct drm_file *file)
321 struct drm_i915_gem_pread *args = data;
323 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
324 args->offset, UIO_READ, file));
328 * Writes data to the object referenced by handle.
330 * On error, the contents of the buffer that were to be modified are undefined.
333 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
334 struct drm_file *file)
336 struct drm_i915_gem_pwrite *args = data;
338 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
339 args->offset, UIO_WRITE, file));
343 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
346 if (atomic_read(&dev_priv->mm.wedged)) {
347 struct completion *x = &dev_priv->error_completion;
348 bool recovery_complete;
350 /* Give the error handler a chance to run. */
351 spin_lock(&x->wait.lock);
352 recovery_complete = x->done > 0;
353 spin_unlock(&x->wait.lock);
355 /* Non-interruptible callers can't handle -EAGAIN, hence return
356 * -EIO unconditionally for these. */
360 /* Recovery complete, but still wedged means reset failure. */
361 if (recovery_complete)
371 * Compare seqno against outstanding lazy request. Emit a request if they are
375 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
379 DRM_LOCK_ASSERT(ring->dev);
382 if (seqno == ring->outstanding_lazy_request)
383 ret = i915_add_request(ring, NULL, NULL);
389 * __wait_seqno - wait until execution of seqno has finished
390 * @ring: the ring expected to report seqno
392 * @interruptible: do an interruptible wait (normally yes)
393 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
395 * Returns 0 if the seqno was found within the alloted time. Else returns the
396 * errno with remaining time filled in timeout argument.
398 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
399 bool interruptible, struct timespec *timeout)
401 drm_i915_private_t *dev_priv = ring->dev->dev_private;
402 struct timespec before, now, wait_time={1,0};
403 unsigned long timeout_jiffies;
405 bool wait_forever = true;
408 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
411 if (timeout != NULL) {
412 wait_time = *timeout;
413 wait_forever = false;
416 timeout_jiffies = timespec_to_jiffies(&wait_time);
418 if (WARN_ON(!ring->irq_get(ring)))
421 /* Record current time in case interrupted by signal, or wedged * */
422 getrawmonotonic(&before);
425 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
426 atomic_read(&dev_priv->mm.wedged))
429 end = wait_event_interruptible_timeout(ring->irq_queue,
433 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
436 ret = i915_gem_check_wedge(dev_priv, interruptible);
439 } while (end == 0 && wait_forever);
441 getrawmonotonic(&now);
447 struct timespec sleep_time = timespec_sub(now, before);
448 *timeout = timespec_sub(*timeout, sleep_time);
453 case -EAGAIN: /* Wedged */
454 case -ERESTARTSYS: /* Signal */
456 case 0: /* Timeout */
458 set_normalized_timespec(timeout, 0, 0);
459 return -ETIMEDOUT; /* -ETIME on Linux */
460 default: /* Completed */
461 WARN_ON(end < 0); /* We're not aware of other errors */
467 * Waits for a sequence number to be signaled, and cleans up the
468 * request and object lists appropriately for that event.
471 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
473 struct drm_device *dev = ring->dev;
474 struct drm_i915_private *dev_priv = dev->dev_private;
477 DRM_LOCK_ASSERT(dev);
480 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
484 ret = i915_gem_check_olr(ring, seqno);
488 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
494 * Ensures that all rendering to the object has completed and the object is
495 * safe to unbind from the GTT or access from the CPU.
497 static __must_check int
498 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
501 struct intel_ring_buffer *ring = obj->ring;
505 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
509 ret = i915_wait_seqno(ring, seqno);
513 i915_gem_retire_requests_ring(ring);
515 /* Manually manage the write flush as we may have not yet
516 * retired the buffer.
518 if (obj->last_write_seqno &&
519 i915_seqno_passed(seqno, obj->last_write_seqno)) {
520 obj->last_write_seqno = 0;
521 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
527 /* A nonblocking variant of the above wait. This is a highly dangerous routine
528 * as the object state may change during this call.
530 static __must_check int
531 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
534 struct drm_device *dev = obj->base.dev;
535 struct drm_i915_private *dev_priv = dev->dev_private;
536 struct intel_ring_buffer *ring = obj->ring;
540 DRM_LOCK_ASSERT(dev);
541 BUG_ON(!dev_priv->mm.interruptible);
543 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
547 ret = i915_gem_check_wedge(dev_priv, true);
551 ret = i915_gem_check_olr(ring, seqno);
556 ret = __wait_seqno(ring, seqno, true, NULL);
559 i915_gem_retire_requests_ring(ring);
561 /* Manually manage the write flush as we may have not yet
562 * retired the buffer.
564 if (obj->last_write_seqno &&
565 i915_seqno_passed(seqno, obj->last_write_seqno)) {
566 obj->last_write_seqno = 0;
567 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
574 * Called when user space prepares to use an object with the CPU, either
575 * through the mmap ioctl's mapping or a GTT mapping.
578 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
579 struct drm_file *file)
581 struct drm_i915_gem_set_domain *args = data;
582 struct drm_i915_gem_object *obj;
583 uint32_t read_domains = args->read_domains;
584 uint32_t write_domain = args->write_domain;
587 /* Only handle setting domains to types used by the CPU. */
588 if (write_domain & I915_GEM_GPU_DOMAINS)
591 if (read_domains & I915_GEM_GPU_DOMAINS)
594 /* Having something in the write domain implies it's in the read
595 * domain, and only that read domain. Enforce that in the request.
597 if (write_domain != 0 && read_domains != write_domain)
600 ret = i915_mutex_lock_interruptible(dev);
604 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
605 if (&obj->base == NULL) {
610 /* Try to flush the object off the GPU without holding the lock.
611 * We will repeat the flush holding the lock in the normal manner
612 * to catch cases where we are gazumped.
614 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
618 if (read_domains & I915_GEM_DOMAIN_GTT) {
619 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
621 /* Silently promote "you're not bound, there was nothing to do"
622 * to success, since the client was just asking us to
623 * make sure everything was done.
628 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
632 drm_gem_object_unreference(&obj->base);
639 * Called when user space has done writes to this buffer
642 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
643 struct drm_file *file)
645 struct drm_i915_gem_sw_finish *args = data;
646 struct drm_i915_gem_object *obj;
649 ret = i915_mutex_lock_interruptible(dev);
652 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
653 if (&obj->base == NULL) {
658 /* Pinned buffers may be scanout, so flush the cache */
660 i915_gem_object_flush_cpu_write_domain(obj);
662 drm_gem_object_unreference(&obj->base);
669 * Maps the contents of an object, returning the address it is mapped
672 * While the mapping holds a reference on the contents of the object, it doesn't
673 * imply a ref on the object itself.
676 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
677 struct drm_file *file)
679 struct drm_i915_gem_mmap *args = data;
680 struct drm_gem_object *obj;
681 struct proc *p = curproc;
682 vm_map_t map = &p->p_vmspace->vm_map;
687 obj = drm_gem_object_lookup(dev, file, args->handle);
694 size = round_page(args->size);
696 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
704 vm_object_hold(obj->vm_obj);
705 vm_object_reference_locked(obj->vm_obj);
706 vm_object_drop(obj->vm_obj);
707 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
708 PAGE_SIZE, /* align */
710 VM_MAPTYPE_NORMAL, /* maptype */
711 VM_PROT_READ | VM_PROT_WRITE, /* prot */
712 VM_PROT_READ | VM_PROT_WRITE, /* max */
713 MAP_SHARED /* cow */);
714 if (rv != KERN_SUCCESS) {
715 vm_object_deallocate(obj->vm_obj);
716 error = -vm_mmap_to_errno(rv);
718 args->addr_ptr = (uint64_t)addr;
721 drm_gem_object_unreference(obj);
726 * i915_gem_release_mmap - remove physical page mappings
727 * @obj: obj in question
729 * Preserve the reservation of the mmapping with the DRM core code, but
730 * relinquish ownership of the pages back to the system.
732 * It is vital that we remove the page mapping if we have mapped a tiled
733 * object through the GTT and then lose the fence register due to
734 * resource pressure. Similarly if the object has been moved out of the
735 * aperture, than pages mapped into userspace must be revoked. Removing the
736 * mapping will then trigger a page fault on the next user access, allowing
737 * fixup by i915_gem_fault().
740 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
746 if (!obj->fault_mappable)
749 devobj = cdev_pager_lookup(obj);
750 if (devobj != NULL) {
751 page_count = OFF_TO_IDX(obj->base.size);
753 VM_OBJECT_LOCK(devobj);
754 for (i = 0; i < page_count; i++) {
755 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
758 cdev_pager_free_page(devobj, m);
760 VM_OBJECT_UNLOCK(devobj);
761 vm_object_deallocate(devobj);
764 obj->fault_mappable = false;
768 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
772 if (INTEL_INFO(dev)->gen >= 4 ||
773 tiling_mode == I915_TILING_NONE)
776 /* Previous chips need a power-of-two fence region when tiling */
777 if (INTEL_INFO(dev)->gen == 3)
778 gtt_size = 1024*1024;
782 while (gtt_size < size)
789 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
790 * @obj: object to check
792 * Return the required GTT alignment for an object, taking into account
793 * potential fence register mapping.
796 i915_gem_get_gtt_alignment(struct drm_device *dev,
802 * Minimum alignment is 4k (GTT page size), but might be greater
803 * if a fence register is needed for the object.
805 if (INTEL_INFO(dev)->gen >= 4 ||
806 tiling_mode == I915_TILING_NONE)
810 * Previous chips need to be aligned to the size of the smallest
811 * fence register that can contain the object.
813 return i915_gem_get_gtt_size(dev, size, tiling_mode);
817 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
820 * @size: size of the object
821 * @tiling_mode: tiling mode of the object
823 * Return the required GTT alignment for an object, only taking into account
824 * unfenced tiled surface requirements.
827 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
832 * Minimum alignment is 4k (GTT page size) for sane hw.
834 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
835 tiling_mode == I915_TILING_NONE)
838 /* Previous hardware however needs to be aligned to a power-of-two
839 * tile height. The simplest method for determining this is to reuse
840 * the power-of-tile object size.
842 return i915_gem_get_gtt_size(dev, size, tiling_mode);
846 i915_gem_mmap_gtt(struct drm_file *file,
847 struct drm_device *dev,
851 struct drm_i915_private *dev_priv = dev->dev_private;
852 struct drm_i915_gem_object *obj;
855 ret = i915_mutex_lock_interruptible(dev);
859 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
860 if (&obj->base == NULL) {
865 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
870 if (obj->madv != I915_MADV_WILLNEED) {
871 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
876 ret = drm_gem_create_mmap_offset(&obj->base);
880 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
883 drm_gem_object_unreference(&obj->base);
890 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
892 * @data: GTT mapping ioctl data
893 * @file: GEM object info
895 * Simply returns the fake offset to userspace so it can mmap it.
896 * The mmap call will end up in drm_gem_mmap(), which will set things
897 * up so we can get faults in the handler above.
899 * The fault handler will take care of binding the object into the GTT
900 * (since it may have been evicted to make room for something), allocating
901 * a fence register, and mapping the appropriate aperture address into
905 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
906 struct drm_file *file)
908 struct drm_i915_gem_mmap_gtt *args = data;
910 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
913 /* Immediately discard the backing storage */
915 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
919 vm_obj = obj->base.vm_obj;
920 VM_OBJECT_LOCK(vm_obj);
921 vm_object_page_remove(vm_obj, 0, 0, false);
922 VM_OBJECT_UNLOCK(vm_obj);
923 obj->madv = __I915_MADV_PURGED;
927 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
929 return obj->madv == I915_MADV_DONTNEED;
932 static inline void vm_page_reference(vm_page_t m)
934 vm_page_flag_set(m, PG_REFERENCED);
938 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
943 BUG_ON(obj->madv == __I915_MADV_PURGED);
945 if (obj->tiling_mode != I915_TILING_NONE)
946 i915_gem_object_save_bit_17_swizzle(obj);
947 if (obj->madv == I915_MADV_DONTNEED)
949 page_count = obj->base.size / PAGE_SIZE;
950 VM_OBJECT_LOCK(obj->base.vm_obj);
951 #if GEM_PARANOID_CHECK_GTT
952 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
954 for (i = 0; i < page_count; i++) {
958 if (obj->madv == I915_MADV_WILLNEED)
959 vm_page_reference(m);
960 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
961 vm_page_unwire(obj->pages[i], 1);
962 vm_page_wakeup(obj->pages[i]);
963 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
965 VM_OBJECT_UNLOCK(obj->base.vm_obj);
967 drm_free(obj->pages, DRM_I915_GEM);
972 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
975 struct drm_device *dev;
978 int page_count, i, j;
981 KASSERT(obj->pages == NULL, ("Obj already has pages"));
982 page_count = obj->base.size / PAGE_SIZE;
983 obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
985 vm_obj = obj->base.vm_obj;
986 VM_OBJECT_LOCK(vm_obj);
987 for (i = 0; i < page_count; i++) {
988 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
991 VM_OBJECT_UNLOCK(vm_obj);
992 if (i915_gem_object_needs_bit17_swizzle(obj))
993 i915_gem_object_do_bit_17_swizzle(obj);
997 for (j = 0; j < i; j++) {
999 vm_page_busy_wait(m, FALSE, "i915gem");
1000 vm_page_unwire(m, 0);
1002 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1004 VM_OBJECT_UNLOCK(vm_obj);
1005 drm_free(obj->pages, DRM_I915_GEM);
1011 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1012 struct intel_ring_buffer *ring)
1014 struct drm_device *dev = obj->base.dev;
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1016 u32 seqno = intel_ring_get_seqno(ring);
1018 BUG_ON(ring == NULL);
1021 /* Add a reference if we're newly entering the active list. */
1023 drm_gem_object_reference(&obj->base);
1027 /* Move from whatever list we were on to the tail of execution. */
1028 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1029 list_move_tail(&obj->ring_list, &ring->active_list);
1031 obj->last_read_seqno = seqno;
1033 if (obj->fenced_gpu_access) {
1034 obj->last_fenced_seqno = seqno;
1036 /* Bump MRU to take account of the delayed flush */
1037 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1038 struct drm_i915_fence_reg *reg;
1040 reg = &dev_priv->fence_regs[obj->fence_reg];
1041 list_move_tail(®->lru_list,
1042 &dev_priv->mm.fence_list);
1048 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1050 struct drm_device *dev = obj->base.dev;
1051 struct drm_i915_private *dev_priv = dev->dev_private;
1053 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1054 BUG_ON(!obj->active);
1056 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1058 list_del_init(&obj->ring_list);
1061 obj->last_read_seqno = 0;
1062 obj->last_write_seqno = 0;
1063 obj->base.write_domain = 0;
1065 obj->last_fenced_seqno = 0;
1066 obj->fenced_gpu_access = false;
1069 drm_gem_object_unreference(&obj->base);
1071 WARN_ON(i915_verify_lists(dev));
1075 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 struct intel_ring_buffer *ring;
1081 /* The hardware uses various monotonic 32-bit counters, if we
1082 * detect that they will wraparound we need to idle the GPU
1083 * and reset those counters.
1086 for_each_ring(ring, dev_priv, i) {
1087 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1088 ret |= ring->sync_seqno[j] != 0;
1093 ret = i915_gpu_idle(dev);
1097 i915_gem_retire_requests(dev);
1098 for_each_ring(ring, dev_priv, i) {
1099 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1100 ring->sync_seqno[j] = 0;
1107 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1109 struct drm_i915_private *dev_priv = dev->dev_private;
1111 /* reserve 0 for non-seqno */
1112 if (dev_priv->next_seqno == 0) {
1113 int ret = i915_gem_handle_seqno_wrap(dev);
1117 dev_priv->next_seqno = 1;
1120 *seqno = dev_priv->next_seqno++;
1125 i915_add_request(struct intel_ring_buffer *ring,
1126 struct drm_file *file,
1129 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1130 struct drm_i915_gem_request *request;
1131 u32 request_ring_position;
1136 * Emit any outstanding flushes - execbuf can fail to emit the flush
1137 * after having emitted the batchbuffer command. Hence we need to fix
1138 * things up similar to emitting the lazy request. The difference here
1139 * is that the flush _must_ happen before the next request, no matter
1142 ret = intel_ring_flush_all_caches(ring);
1146 request = kmalloc(sizeof(*request), DRM_I915_GEM, M_WAITOK | M_ZERO);
1147 if (request == NULL)
1151 /* Record the position of the start of the request so that
1152 * should we detect the updated seqno part-way through the
1153 * GPU processing the request, we never over-estimate the
1154 * position of the head.
1156 request_ring_position = intel_ring_get_tail(ring);
1158 ret = ring->add_request(ring);
1160 kfree(request, DRM_I915_GEM);
1164 request->seqno = intel_ring_get_seqno(ring);
1165 request->ring = ring;
1166 request->tail = request_ring_position;
1167 request->emitted_jiffies = jiffies;
1168 was_empty = list_empty(&ring->request_list);
1169 list_add_tail(&request->list, &ring->request_list);
1170 request->file_priv = NULL;
1173 struct drm_i915_file_private *file_priv = file->driver_priv;
1175 spin_lock(&file_priv->mm.lock);
1176 request->file_priv = file_priv;
1177 list_add_tail(&request->client_list,
1178 &file_priv->mm.request_list);
1179 spin_unlock(&file_priv->mm.lock);
1182 ring->outstanding_lazy_request = 0;
1184 if (!dev_priv->mm.suspended) {
1185 if (i915_enable_hangcheck) {
1186 mod_timer(&dev_priv->hangcheck_timer,
1187 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1190 queue_delayed_work(dev_priv->wq,
1191 &dev_priv->mm.retire_work,
1192 round_jiffies_up_relative(hz));
1193 intel_mark_busy(dev_priv->dev);
1198 *out_seqno = request->seqno;
1203 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1205 struct drm_i915_file_private *file_priv = request->file_priv;
1210 spin_lock(&file_priv->mm.lock);
1211 if (request->file_priv) {
1212 list_del(&request->client_list);
1213 request->file_priv = NULL;
1215 spin_unlock(&file_priv->mm.lock);
1218 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1219 struct intel_ring_buffer *ring)
1221 while (!list_empty(&ring->request_list)) {
1222 struct drm_i915_gem_request *request;
1224 request = list_first_entry(&ring->request_list,
1225 struct drm_i915_gem_request,
1228 list_del(&request->list);
1229 i915_gem_request_remove_from_client(request);
1230 drm_free(request, DRM_I915_GEM);
1233 while (!list_empty(&ring->active_list)) {
1234 struct drm_i915_gem_object *obj;
1236 obj = list_first_entry(&ring->active_list,
1237 struct drm_i915_gem_object,
1240 i915_gem_object_move_to_inactive(obj);
1244 static void i915_gem_reset_fences(struct drm_device *dev)
1246 struct drm_i915_private *dev_priv = dev->dev_private;
1249 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1250 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1252 i915_gem_write_fence(dev, i, NULL);
1255 i915_gem_object_fence_lost(reg->obj);
1259 INIT_LIST_HEAD(®->lru_list);
1262 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1265 void i915_gem_reset(struct drm_device *dev)
1267 struct drm_i915_private *dev_priv = dev->dev_private;
1268 struct drm_i915_gem_object *obj;
1269 struct intel_ring_buffer *ring;
1272 for_each_ring(ring, dev_priv, i)
1273 i915_gem_reset_ring_lists(dev_priv, ring);
1275 /* Move everything out of the GPU domains to ensure we do any
1276 * necessary invalidation upon reuse.
1278 list_for_each_entry(obj,
1279 &dev_priv->mm.inactive_list,
1282 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1285 /* The fence registers are invalidated so clear them out */
1286 i915_gem_reset_fences(dev);
1290 * This function clears the request list as sequence numbers are passed.
1293 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1297 if (list_empty(&ring->request_list))
1300 WARN_ON(i915_verify_lists(ring->dev));
1302 seqno = ring->get_seqno(ring, true);
1304 while (!list_empty(&ring->request_list)) {
1305 struct drm_i915_gem_request *request;
1307 request = list_first_entry(&ring->request_list,
1308 struct drm_i915_gem_request,
1311 if (!i915_seqno_passed(seqno, request->seqno))
1314 /* We know the GPU must have read the request to have
1315 * sent us the seqno + interrupt, so use the position
1316 * of tail of the request to update the last known position
1319 ring->last_retired_head = request->tail;
1321 list_del(&request->list);
1322 i915_gem_request_remove_from_client(request);
1323 kfree(request, DRM_I915_GEM);
1326 /* Move any buffers on the active list that are no longer referenced
1327 * by the ringbuffer to the flushing/inactive lists as appropriate.
1329 while (!list_empty(&ring->active_list)) {
1330 struct drm_i915_gem_object *obj;
1332 obj = list_first_entry(&ring->active_list,
1333 struct drm_i915_gem_object,
1336 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1339 i915_gem_object_move_to_inactive(obj);
1342 if (unlikely(ring->trace_irq_seqno &&
1343 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1344 ring->irq_put(ring);
1345 ring->trace_irq_seqno = 0;
1351 i915_gem_retire_requests(struct drm_device *dev)
1353 drm_i915_private_t *dev_priv = dev->dev_private;
1354 struct intel_ring_buffer *ring;
1357 for_each_ring(ring, dev_priv, i)
1358 i915_gem_retire_requests_ring(ring);
1362 i915_gem_retire_work_handler(struct work_struct *work)
1364 drm_i915_private_t *dev_priv;
1365 struct drm_device *dev;
1366 struct intel_ring_buffer *ring;
1370 dev_priv = container_of(work, drm_i915_private_t,
1371 mm.retire_work.work);
1372 dev = dev_priv->dev;
1374 /* Come back later if the device is busy... */
1375 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
1376 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1377 round_jiffies_up_relative(hz));
1381 i915_gem_retire_requests(dev);
1383 /* Send a periodic flush down the ring so we don't hold onto GEM
1384 * objects indefinitely.
1387 for_each_ring(ring, dev_priv, i) {
1388 if (ring->gpu_caches_dirty)
1389 i915_add_request(ring, NULL, NULL);
1391 idle &= list_empty(&ring->request_list);
1394 if (!dev_priv->mm.suspended && !idle)
1395 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1396 round_jiffies_up_relative(hz));
1398 intel_mark_idle(dev);
1403 * Ensures that an object will eventually get non-busy by flushing any required
1404 * write domains, emitting any outstanding lazy request and retiring and
1405 * completed requests.
1408 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
1413 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
1417 i915_gem_retire_requests_ring(obj->ring);
1424 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
1425 * @DRM_IOCTL_ARGS: standard ioctl arguments
1427 * Returns 0 if successful, else an error is returned with the remaining time in
1428 * the timeout parameter.
1429 * -ETIME: object is still busy after timeout
1430 * -ERESTARTSYS: signal interrupted the wait
1431 * -ENONENT: object doesn't exist
1432 * Also possible, but rare:
1433 * -EAGAIN: GPU wedged
1435 * -ENODEV: Internal IRQ fail
1436 * -E?: The add request failed
1438 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
1439 * non-zero timeout parameter the wait ioctl will wait for the given number of
1440 * nanoseconds on an object becoming unbusy. Since the wait itself does so
1441 * without holding struct_mutex the object may become re-busied before this
1442 * function completes. A similar but shorter * race condition exists in the busy
1446 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1448 struct drm_i915_gem_wait *args = data;
1449 struct drm_i915_gem_object *obj;
1450 struct intel_ring_buffer *ring = NULL;
1451 struct timespec timeout_stack, *timeout = NULL;
1455 if (args->timeout_ns >= 0) {
1456 timeout_stack = ns_to_timespec(args->timeout_ns);
1457 timeout = &timeout_stack;
1460 ret = i915_mutex_lock_interruptible(dev);
1464 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
1465 if (&obj->base == NULL) {
1470 /* Need to make sure the object gets inactive eventually. */
1471 ret = i915_gem_object_flush_active(obj);
1476 seqno = obj->last_read_seqno;
1483 /* Do this after OLR check to make sure we make forward progress polling
1484 * on this IOCTL with a 0 timeout (like busy ioctl)
1486 if (!args->timeout_ns) {
1491 drm_gem_object_unreference(&obj->base);
1494 ret = __wait_seqno(ring, seqno, true, timeout);
1496 WARN_ON(!timespec_valid(timeout));
1497 args->timeout_ns = timespec_to_ns(timeout);
1502 drm_gem_object_unreference(&obj->base);
1508 * i915_gem_object_sync - sync an object to a ring.
1510 * @obj: object which may be in use on another ring.
1511 * @to: ring we wish to use the object on. May be NULL.
1513 * This code is meant to abstract object synchronization with the GPU.
1514 * Calling with NULL implies synchronizing the object with the CPU
1515 * rather than a particular GPU ring.
1517 * Returns 0 if successful, else propagates up the lower layer error.
1520 i915_gem_object_sync(struct drm_i915_gem_object *obj,
1521 struct intel_ring_buffer *to)
1523 struct intel_ring_buffer *from = obj->ring;
1527 if (from == NULL || to == from)
1530 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
1531 return i915_gem_object_wait_rendering(obj, false);
1533 idx = intel_ring_sync_index(from, to);
1535 seqno = obj->last_read_seqno;
1536 if (seqno <= from->sync_seqno[idx])
1539 ret = i915_gem_check_olr(obj->ring, seqno);
1543 ret = to->sync_to(to, from, seqno);
1545 /* We use last_read_seqno because sync_to()
1546 * might have just caused seqno wrap under
1549 from->sync_seqno[idx] = obj->last_read_seqno;
1554 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
1556 u32 old_write_domain, old_read_domains;
1558 /* Act a barrier for all accesses through the GTT */
1561 /* Force a pagefault for domain tracking on next user access */
1562 i915_gem_release_mmap(obj);
1564 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
1567 old_read_domains = obj->base.read_domains;
1568 old_write_domain = obj->base.write_domain;
1570 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
1571 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
1576 * Unbinds an object from the GTT aperture.
1579 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
1581 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1584 if (obj->gtt_space == NULL)
1590 ret = i915_gem_object_finish_gpu(obj);
1593 /* Continue on if we fail due to EIO, the GPU is hung so we
1594 * should be safe and we need to cleanup or else we might
1595 * cause memory corruption through use-after-free.
1598 i915_gem_object_finish_gtt(obj);
1600 /* Move the object to the CPU domain to ensure that
1601 * any possible CPU writes while it's not in the GTT
1602 * are flushed when we go to remap it.
1605 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1606 if (ret == -ERESTART || ret == -EINTR)
1609 /* In the event of a disaster, abandon all caches and
1610 * hope for the best.
1612 i915_gem_clflush_object(obj);
1613 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1616 /* release the fence reg _after_ flushing */
1617 ret = i915_gem_object_put_fence(obj);
1621 if (obj->has_global_gtt_mapping)
1622 i915_gem_gtt_unbind_object(obj);
1623 if (obj->has_aliasing_ppgtt_mapping) {
1624 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
1625 obj->has_aliasing_ppgtt_mapping = 0;
1627 i915_gem_gtt_finish_object(obj);
1629 i915_gem_object_put_pages_gtt(obj);
1631 list_del_init(&obj->gtt_list);
1632 list_del_init(&obj->mm_list);
1633 /* Avoid an unnecessary call to unbind on rebind. */
1634 obj->map_and_fenceable = true;
1636 drm_mm_put_block(obj->gtt_space);
1637 obj->gtt_space = NULL;
1638 obj->gtt_offset = 0;
1640 if (i915_gem_object_is_purgeable(obj))
1641 i915_gem_object_truncate(obj);
1646 int i915_gpu_idle(struct drm_device *dev)
1648 drm_i915_private_t *dev_priv = dev->dev_private;
1649 struct intel_ring_buffer *ring;
1652 /* Flush everything onto the inactive list. */
1653 for_each_ring(ring, dev_priv, i) {
1654 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
1658 ret = intel_ring_idle(ring);
1666 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
1667 struct drm_i915_gem_object *obj)
1669 drm_i915_private_t *dev_priv = dev->dev_private;
1673 u32 size = obj->gtt_space->size;
1675 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1677 val |= obj->gtt_offset & 0xfffff000;
1678 val |= (uint64_t)((obj->stride / 128) - 1) <<
1679 SANDYBRIDGE_FENCE_PITCH_SHIFT;
1681 if (obj->tiling_mode == I915_TILING_Y)
1682 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1683 val |= I965_FENCE_REG_VALID;
1687 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
1688 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
1691 static void i965_write_fence_reg(struct drm_device *dev, int reg,
1692 struct drm_i915_gem_object *obj)
1694 drm_i915_private_t *dev_priv = dev->dev_private;
1698 u32 size = obj->gtt_space->size;
1700 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1702 val |= obj->gtt_offset & 0xfffff000;
1703 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1704 if (obj->tiling_mode == I915_TILING_Y)
1705 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1706 val |= I965_FENCE_REG_VALID;
1710 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
1711 POSTING_READ(FENCE_REG_965_0 + reg * 8);
1714 static void i915_write_fence_reg(struct drm_device *dev, int reg,
1715 struct drm_i915_gem_object *obj)
1717 drm_i915_private_t *dev_priv = dev->dev_private;
1721 u32 size = obj->gtt_space->size;
1725 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
1726 (size & -size) != size ||
1727 (obj->gtt_offset & (size - 1)),
1728 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
1729 obj->gtt_offset, obj->map_and_fenceable, size);
1731 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1736 /* Note: pitch better be a power of two tile widths */
1737 pitch_val = obj->stride / tile_width;
1738 pitch_val = ffs(pitch_val) - 1;
1740 val = obj->gtt_offset;
1741 if (obj->tiling_mode == I915_TILING_Y)
1742 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1743 val |= I915_FENCE_SIZE_BITS(size);
1744 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1745 val |= I830_FENCE_REG_VALID;
1750 reg = FENCE_REG_830_0 + reg * 4;
1752 reg = FENCE_REG_945_8 + (reg - 8) * 4;
1754 I915_WRITE(reg, val);
1758 static void i830_write_fence_reg(struct drm_device *dev, int reg,
1759 struct drm_i915_gem_object *obj)
1761 drm_i915_private_t *dev_priv = dev->dev_private;
1765 u32 size = obj->gtt_space->size;
1768 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
1769 (size & -size) != size ||
1770 (obj->gtt_offset & (size - 1)),
1771 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
1772 obj->gtt_offset, size);
1774 pitch_val = obj->stride / 128;
1775 pitch_val = ffs(pitch_val) - 1;
1777 val = obj->gtt_offset;
1778 if (obj->tiling_mode == I915_TILING_Y)
1779 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1780 val |= I830_FENCE_SIZE_BITS(size);
1781 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1782 val |= I830_FENCE_REG_VALID;
1786 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
1787 POSTING_READ(FENCE_REG_830_0 + reg * 4);
1790 static void i915_gem_write_fence(struct drm_device *dev, int reg,
1791 struct drm_i915_gem_object *obj)
1793 switch (INTEL_INFO(dev)->gen) {
1795 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
1797 case 4: i965_write_fence_reg(dev, reg, obj); break;
1798 case 3: i915_write_fence_reg(dev, reg, obj); break;
1799 case 2: i830_write_fence_reg(dev, reg, obj); break;
1804 static inline int fence_number(struct drm_i915_private *dev_priv,
1805 struct drm_i915_fence_reg *fence)
1807 return fence - dev_priv->fence_regs;
1810 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
1811 struct drm_i915_fence_reg *fence,
1814 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1815 int reg = fence_number(dev_priv, fence);
1817 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
1820 obj->fence_reg = reg;
1822 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
1824 obj->fence_reg = I915_FENCE_REG_NONE;
1826 list_del_init(&fence->lru_list);
1831 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
1833 if (obj->last_fenced_seqno) {
1834 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
1838 obj->last_fenced_seqno = 0;
1841 /* Ensure that all CPU reads are completed before installing a fence
1842 * and all writes before removing the fence.
1844 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
1847 obj->fenced_gpu_access = false;
1852 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
1854 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1857 ret = i915_gem_object_flush_fence(obj);
1861 if (obj->fence_reg == I915_FENCE_REG_NONE)
1864 i915_gem_object_update_fence(obj,
1865 &dev_priv->fence_regs[obj->fence_reg],
1867 i915_gem_object_fence_lost(obj);
1872 static struct drm_i915_fence_reg *
1873 i915_find_fence_reg(struct drm_device *dev)
1875 struct drm_i915_private *dev_priv = dev->dev_private;
1876 struct drm_i915_fence_reg *reg, *avail;
1879 /* First try to find a free reg */
1881 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1882 reg = &dev_priv->fence_regs[i];
1886 if (!reg->pin_count)
1893 /* None available, try to steal one or wait for a user to finish */
1894 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
1905 * i915_gem_object_get_fence - set up fencing for an object
1906 * @obj: object to map through a fence reg
1908 * When mapping objects through the GTT, userspace wants to be able to write
1909 * to them without having to worry about swizzling if the object is tiled.
1910 * This function walks the fence regs looking for a free one for @obj,
1911 * stealing one if it can't find any.
1913 * It then sets up the reg based on the object's properties: address, pitch
1914 * and tiling format.
1916 * For an untiled surface, this removes any existing fence.
1919 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
1921 struct drm_device *dev = obj->base.dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 bool enable = obj->tiling_mode != I915_TILING_NONE;
1924 struct drm_i915_fence_reg *reg;
1927 /* Have we updated the tiling parameters upon the object and so
1928 * will need to serialise the write to the associated fence register?
1930 if (obj->fence_dirty) {
1931 ret = i915_gem_object_flush_fence(obj);
1936 /* Just update our place in the LRU if our fence is getting reused. */
1937 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1938 reg = &dev_priv->fence_regs[obj->fence_reg];
1939 if (!obj->fence_dirty) {
1940 list_move_tail(®->lru_list,
1941 &dev_priv->mm.fence_list);
1944 } else if (enable) {
1945 reg = i915_find_fence_reg(dev);
1950 struct drm_i915_gem_object *old = reg->obj;
1952 ret = i915_gem_object_flush_fence(old);
1956 i915_gem_object_fence_lost(old);
1961 i915_gem_object_update_fence(obj, reg, enable);
1962 obj->fence_dirty = false;
1968 * Finds free space in the GTT aperture and binds the object there.
1971 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1973 bool map_and_fenceable,
1976 struct drm_device *dev = obj->base.dev;
1977 drm_i915_private_t *dev_priv = dev->dev_private;
1978 struct drm_mm_node *free_space;
1979 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
1980 bool mappable, fenceable;
1983 if (obj->madv != I915_MADV_WILLNEED) {
1984 DRM_ERROR("Attempting to bind a purgeable object\n");
1988 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
1990 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
1992 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
1993 obj->base.size, obj->tiling_mode);
1995 alignment = map_and_fenceable ? fence_alignment :
1997 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
1998 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2002 size = map_and_fenceable ? fence_size : obj->base.size;
2004 /* If the object is bigger than the entire aperture, reject it early
2005 * before evicting everything in a vain attempt to find space.
2007 if (obj->base.size > (map_and_fenceable ?
2008 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2010 "Attempting to bind an object larger than the aperture\n");
2015 if (map_and_fenceable)
2016 free_space = drm_mm_search_free_in_range(
2017 &dev_priv->mm.gtt_space, size, alignment, 0,
2018 dev_priv->mm.gtt_mappable_end, 0);
2020 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2021 size, alignment, 0);
2022 if (free_space != NULL) {
2024 if (map_and_fenceable)
2025 obj->gtt_space = drm_mm_get_block_range_generic(
2026 free_space, size, alignment, color, 0,
2027 dev_priv->mm.gtt_mappable_end, 1);
2029 obj->gtt_space = drm_mm_get_block_generic(free_space,
2030 size, alignment, color, 1);
2032 if (obj->gtt_space == NULL) {
2033 ret = i915_gem_evict_something(dev, size, alignment,
2043 * NOTE: i915_gem_object_get_pages_gtt() cannot
2044 * return ENOMEM, since we used VM_ALLOC_RETRY.
2046 ret = i915_gem_object_get_pages_gtt(obj, 0);
2048 drm_mm_put_block(obj->gtt_space);
2049 obj->gtt_space = NULL;
2053 i915_gem_gtt_bind_object(obj, obj->cache_level);
2055 i915_gem_object_put_pages_gtt(obj);
2056 drm_mm_put_block(obj->gtt_space);
2057 obj->gtt_space = NULL;
2058 if (i915_gem_evict_everything(dev))
2063 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2064 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2066 obj->gtt_offset = obj->gtt_space->start;
2069 obj->gtt_space->size == fence_size &&
2070 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2073 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2074 obj->map_and_fenceable = mappable && fenceable;
2080 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2083 /* If we don't have a page list set up, then we're not pinned
2084 * to GPU, and we can ignore the cache flush because it'll happen
2085 * again at bind time.
2087 if (obj->pages == NULL)
2090 /* If the GPU is snooping the contents of the CPU cache,
2091 * we do not need to manually clear the CPU cache lines. However,
2092 * the caches are only snooped when the render cache is
2093 * flushed/invalidated. As we always have to emit invalidations
2094 * and flushes when moving into and out of the RENDER domain, correct
2095 * snooping behaviour occurs naturally as the result of our domain
2098 if (obj->cache_level != I915_CACHE_NONE)
2101 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2104 /** Flushes the GTT write domain for the object if it's dirty. */
2106 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2108 uint32_t old_write_domain;
2110 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2113 /* No actual flushing is required for the GTT write domain. Writes
2114 * to it immediately go to main memory as far as we know, so there's
2115 * no chipset flush. It also doesn't land in render cache.
2117 * However, we do have to enforce the order so that all writes through
2118 * the GTT land before any writes to the device, such as updates to
2123 old_write_domain = obj->base.write_domain;
2124 obj->base.write_domain = 0;
2127 /** Flushes the CPU write domain for the object if it's dirty. */
2129 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2131 uint32_t old_write_domain;
2133 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2136 i915_gem_clflush_object(obj);
2137 intel_gtt_chipset_flush();
2138 old_write_domain = obj->base.write_domain;
2139 obj->base.write_domain = 0;
2143 * Moves a single object to the GTT read, and possibly write domain.
2145 * This function returns when the move is complete, including waiting on
2149 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2151 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2152 uint32_t old_write_domain, old_read_domains;
2155 /* Not valid to be called on unbound objects. */
2156 if (obj->gtt_space == NULL)
2159 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2162 ret = i915_gem_object_wait_rendering(obj, !write);
2166 i915_gem_object_flush_cpu_write_domain(obj);
2168 old_write_domain = obj->base.write_domain;
2169 old_read_domains = obj->base.read_domains;
2171 /* It should now be out of any other write domains, and we can update
2172 * the domain values for our changes.
2174 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2175 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2177 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2178 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2182 /* And bump the LRU for this access */
2183 if (i915_gem_object_is_inactive(obj))
2184 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2189 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2190 enum i915_cache_level cache_level)
2192 struct drm_device *dev = obj->base.dev;
2193 drm_i915_private_t *dev_priv = dev->dev_private;
2196 if (obj->cache_level == cache_level)
2199 if (obj->pin_count) {
2200 DRM_DEBUG("can not change the cache level of pinned objects\n");
2204 if (obj->gtt_space) {
2205 ret = i915_gem_object_finish_gpu(obj);
2209 i915_gem_object_finish_gtt(obj);
2211 /* Before SandyBridge, you could not use tiling or fence
2212 * registers with snooped memory, so relinquish any fences
2213 * currently pointing to our region in the aperture.
2215 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2216 ret = i915_gem_object_put_fence(obj);
2221 if (obj->has_global_gtt_mapping)
2222 i915_gem_gtt_bind_object(obj, cache_level);
2223 if (obj->has_aliasing_ppgtt_mapping)
2224 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2228 if (cache_level == I915_CACHE_NONE) {
2229 u32 old_read_domains, old_write_domain;
2231 /* If we're coming from LLC cached, then we haven't
2232 * actually been tracking whether the data is in the
2233 * CPU cache or not, since we only allow one bit set
2234 * in obj->write_domain and have been skipping the clflushes.
2235 * Just set it to the CPU cache for now.
2237 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2238 ("obj %p in CPU write domain", obj));
2239 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
2240 ("obj %p in CPU read domain", obj));
2242 old_read_domains = obj->base.read_domains;
2243 old_write_domain = obj->base.write_domain;
2245 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2246 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2250 obj->cache_level = cache_level;
2254 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2255 struct drm_file *file)
2257 struct drm_i915_gem_caching *args = data;
2258 struct drm_i915_gem_object *obj;
2261 ret = i915_mutex_lock_interruptible(dev);
2265 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2266 if (&obj->base == NULL) {
2271 args->caching = obj->cache_level != I915_CACHE_NONE;
2273 drm_gem_object_unreference(&obj->base);
2279 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2280 struct drm_file *file)
2282 struct drm_i915_gem_caching *args = data;
2283 struct drm_i915_gem_object *obj;
2284 enum i915_cache_level level;
2287 switch (args->caching) {
2288 case I915_CACHING_NONE:
2289 level = I915_CACHE_NONE;
2291 case I915_CACHING_CACHED:
2292 level = I915_CACHE_LLC;
2298 ret = i915_mutex_lock_interruptible(dev);
2302 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2303 if (&obj->base == NULL) {
2308 ret = i915_gem_object_set_cache_level(obj, level);
2310 drm_gem_object_unreference(&obj->base);
2317 * Prepare buffer for display plane (scanout, cursors, etc).
2318 * Can be called from an uninterruptible phase (modesetting) and allows
2319 * any flushes to be pipelined (for pageflips).
2322 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2324 struct intel_ring_buffer *pipelined)
2326 u32 old_read_domains, old_write_domain;
2329 if (pipelined != obj->ring) {
2330 ret = i915_gem_object_sync(obj, pipelined);
2335 /* The display engine is not coherent with the LLC cache on gen6. As
2336 * a result, we make sure that the pinning that is about to occur is
2337 * done with uncached PTEs. This is lowest common denominator for all
2340 * However for gen6+, we could do better by using the GFDT bit instead
2341 * of uncaching, which would allow us to flush all the LLC-cached data
2342 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2344 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2348 /* As the user may map the buffer once pinned in the display plane
2349 * (e.g. libkms for the bootup splash), we have to ensure that we
2350 * always use map_and_fenceable for all scanout buffers.
2352 ret = i915_gem_object_pin(obj, alignment, true, false);
2356 i915_gem_object_flush_cpu_write_domain(obj);
2358 old_write_domain = obj->base.write_domain;
2359 old_read_domains = obj->base.read_domains;
2361 /* It should now be out of any other write domains, and we can update
2362 * the domain values for our changes.
2364 obj->base.write_domain = 0;
2365 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2371 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2375 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2378 ret = i915_gem_object_wait_rendering(obj, false);
2382 /* Ensure that we invalidate the GPU's caches and TLBs. */
2383 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2388 * Moves a single object to the CPU read, and possibly write domain.
2390 * This function returns when the move is complete, including waiting on
2394 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2396 uint32_t old_write_domain, old_read_domains;
2399 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2402 ret = i915_gem_object_wait_rendering(obj, !write);
2406 i915_gem_object_flush_gtt_write_domain(obj);
2408 old_write_domain = obj->base.write_domain;
2409 old_read_domains = obj->base.read_domains;
2411 /* Flush the CPU cache if it's still invalid. */
2412 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2413 i915_gem_clflush_object(obj);
2415 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2418 /* It should now be out of any other write domains, and we can update
2419 * the domain values for our changes.
2421 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2423 /* If we're writing through the CPU, then the GPU read domains will
2424 * need to be invalidated at next use.
2427 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2428 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2434 /* Throttle our rendering by waiting until the ring has completed our requests
2435 * emitted over 20 msec ago.
2437 * Note that if we were to use the current jiffies each time around the loop,
2438 * we wouldn't escape the function with any frames outstanding if the time to
2439 * render a frame was over 20ms.
2441 * This should get us reasonable parallelism between CPU and GPU but also
2442 * relatively low latency when blocking on a particular request to finish.
2445 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 struct drm_i915_file_private *file_priv = file->driver_priv;
2449 unsigned long recent_enough = ticks - (20 * hz / 1000);
2450 struct drm_i915_gem_request *request;
2451 struct intel_ring_buffer *ring = NULL;
2455 if (atomic_read(&dev_priv->mm.wedged))
2458 spin_lock(&file_priv->mm.lock);
2459 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
2460 if (time_after_eq(request->emitted_jiffies, recent_enough))
2463 ring = request->ring;
2464 seqno = request->seqno;
2466 spin_unlock(&file_priv->mm.lock);
2471 ret = __wait_seqno(ring, seqno, true, NULL);
2474 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
2480 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2482 bool map_and_fenceable,
2487 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
2490 if (obj->gtt_space != NULL) {
2491 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
2492 (map_and_fenceable && !obj->map_and_fenceable)) {
2493 WARN(obj->pin_count,
2494 "bo is already pinned with incorrect alignment:"
2495 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
2496 " obj->map_and_fenceable=%d\n",
2497 obj->gtt_offset, alignment,
2499 obj->map_and_fenceable);
2500 ret = i915_gem_object_unbind(obj);
2506 if (obj->gtt_space == NULL) {
2507 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2509 ret = i915_gem_object_bind_to_gtt(obj, alignment,
2515 if (!dev_priv->mm.aliasing_ppgtt)
2516 i915_gem_gtt_bind_object(obj, obj->cache_level);
2519 if (!obj->has_global_gtt_mapping && map_and_fenceable)
2520 i915_gem_gtt_bind_object(obj, obj->cache_level);
2523 obj->pin_mappable |= map_and_fenceable;
2529 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
2531 BUG_ON(obj->pin_count == 0);
2532 BUG_ON(obj->gtt_space == NULL);
2534 if (--obj->pin_count == 0)
2535 obj->pin_mappable = false;
2539 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2540 struct drm_file *file)
2542 struct drm_i915_gem_pin *args = data;
2543 struct drm_i915_gem_object *obj;
2546 ret = i915_mutex_lock_interruptible(dev);
2550 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2551 if (&obj->base == NULL) {
2556 if (obj->madv != I915_MADV_WILLNEED) {
2557 DRM_ERROR("Attempting to pin a purgeable buffer\n");
2562 if (obj->pin_filp != NULL && obj->pin_filp != file) {
2563 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2569 if (obj->user_pin_count == 0) {
2570 ret = i915_gem_object_pin(obj, args->alignment, true, false);
2575 obj->user_pin_count++;
2576 obj->pin_filp = file;
2578 /* XXX - flush the CPU caches for pinned objects
2579 * as the X server doesn't manage domains yet
2581 i915_gem_object_flush_cpu_write_domain(obj);
2582 args->offset = obj->gtt_offset;
2584 drm_gem_object_unreference(&obj->base);
2591 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2592 struct drm_file *file)
2594 struct drm_i915_gem_pin *args = data;
2595 struct drm_i915_gem_object *obj;
2598 ret = i915_mutex_lock_interruptible(dev);
2602 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2603 if (&obj->base == NULL) {
2608 if (obj->pin_filp != file) {
2609 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2614 obj->user_pin_count--;
2615 if (obj->user_pin_count == 0) {
2616 obj->pin_filp = NULL;
2617 i915_gem_object_unpin(obj);
2621 drm_gem_object_unreference(&obj->base);
2628 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2629 struct drm_file *file)
2631 struct drm_i915_gem_busy *args = data;
2632 struct drm_i915_gem_object *obj;
2635 ret = i915_mutex_lock_interruptible(dev);
2639 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2640 if (&obj->base == NULL) {
2645 /* Count all active objects as busy, even if they are currently not used
2646 * by the gpu. Users of this interface expect objects to eventually
2647 * become non-busy without any further actions, therefore emit any
2648 * necessary flushes here.
2650 ret = i915_gem_object_flush_active(obj);
2652 args->busy = obj->active;
2654 args->busy |= intel_ring_flag(obj->ring) << 17;
2657 drm_gem_object_unreference(&obj->base);
2664 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2665 struct drm_file *file_priv)
2667 return i915_gem_ring_throttle(dev, file_priv);
2671 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2672 struct drm_file *file_priv)
2674 struct drm_i915_gem_madvise *args = data;
2675 struct drm_i915_gem_object *obj;
2678 switch (args->madv) {
2679 case I915_MADV_DONTNEED:
2680 case I915_MADV_WILLNEED:
2686 ret = i915_mutex_lock_interruptible(dev);
2690 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
2691 if (&obj->base == NULL) {
2696 if (obj->pin_count) {
2701 if (obj->madv != __I915_MADV_PURGED)
2702 obj->madv = args->madv;
2704 /* if the object is no longer attached, discard its backing storage */
2705 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
2706 i915_gem_object_truncate(obj);
2708 args->retained = obj->madv != __I915_MADV_PURGED;
2711 drm_gem_object_unreference(&obj->base);
2717 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2720 struct drm_i915_private *dev_priv;
2721 struct drm_i915_gem_object *obj;
2723 dev_priv = dev->dev_private;
2725 obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
2727 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
2728 drm_free(obj, DRM_I915_GEM);
2732 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2733 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2736 /* On some devices, we can have the GPU use the LLC (the CPU
2737 * cache) for about a 10% performance improvement
2738 * compared to uncached. Graphics requests other than
2739 * display scanout are coherent with the CPU in
2740 * accessing this cache. This means in this mode we
2741 * don't need to clflush on the CPU side, and on the
2742 * GPU side we only need to flush internal caches to
2743 * get data visible to the CPU.
2745 * However, we maintain the display planes as UC, and so
2746 * need to rebind when first used as such.
2748 obj->cache_level = I915_CACHE_LLC;
2750 obj->cache_level = I915_CACHE_NONE;
2751 obj->base.driver_private = NULL;
2752 obj->fence_reg = I915_FENCE_REG_NONE;
2753 INIT_LIST_HEAD(&obj->mm_list);
2754 INIT_LIST_HEAD(&obj->gtt_list);
2755 INIT_LIST_HEAD(&obj->ring_list);
2756 INIT_LIST_HEAD(&obj->exec_list);
2757 obj->madv = I915_MADV_WILLNEED;
2758 /* Avoid an unnecessary call to unbind on the first bind. */
2759 obj->map_and_fenceable = true;
2761 i915_gem_info_add_obj(dev_priv, size);
2766 int i915_gem_init_object(struct drm_gem_object *obj)
2773 void i915_gem_free_object(struct drm_gem_object *gem_obj)
2775 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
2776 struct drm_device *dev = obj->base.dev;
2777 drm_i915_private_t *dev_priv = dev->dev_private;
2780 i915_gem_detach_phys_object(dev, obj);
2783 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
2784 bool was_interruptible;
2786 was_interruptible = dev_priv->mm.interruptible;
2787 dev_priv->mm.interruptible = false;
2789 WARN_ON(i915_gem_object_unbind(obj));
2791 dev_priv->mm.interruptible = was_interruptible;
2794 drm_gem_free_mmap_offset(&obj->base);
2796 drm_gem_object_release(&obj->base);
2797 i915_gem_info_remove_obj(dev_priv, obj->base.size);
2799 drm_free(obj->bit_17, DRM_I915_GEM);
2800 drm_free(obj, DRM_I915_GEM);
2804 i915_gem_do_init(struct drm_device *dev, unsigned long start,
2805 unsigned long mappable_end, unsigned long end)
2807 drm_i915_private_t *dev_priv;
2808 unsigned long mappable;
2811 dev_priv = dev->dev_private;
2812 mappable = min(end, mappable_end) - start;
2814 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
2816 dev_priv->mm.gtt_start = start;
2817 dev_priv->mm.gtt_mappable_end = mappable_end;
2818 dev_priv->mm.gtt_end = end;
2819 dev_priv->mm.gtt_total = end - start;
2820 dev_priv->mm.mappable_gtt_total = mappable;
2822 /* Take over this portion of the GTT */
2823 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
2824 device_printf(dev->dev,
2825 "taking over the fictitious range 0x%lx-0x%lx\n",
2826 dev->agp->base + start, dev->agp->base + start + mappable);
2827 error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
2828 dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
2833 i915_gem_idle(struct drm_device *dev)
2835 drm_i915_private_t *dev_priv = dev->dev_private;
2840 if (dev_priv->mm.suspended) {
2845 ret = i915_gpu_idle(dev);
2850 i915_gem_retire_requests(dev);
2852 /* Under UMS, be paranoid and evict. */
2853 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2854 i915_gem_evict_everything(dev);
2856 i915_gem_reset_fences(dev);
2858 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2859 * We need to replace this with a semaphore, or something.
2860 * And not confound mm.suspended!
2862 dev_priv->mm.suspended = 1;
2863 del_timer_sync(&dev_priv->hangcheck_timer);
2865 i915_kernel_lost_context(dev);
2866 i915_gem_cleanup_ringbuffer(dev);
2870 /* Cancel the retire work handler, which should be idle now. */
2871 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2876 void i915_gem_l3_remap(struct drm_device *dev)
2878 drm_i915_private_t *dev_priv = dev->dev_private;
2882 if (!HAS_L3_GPU_CACHE(dev))
2885 if (!dev_priv->l3_parity.remap_info)
2888 misccpctl = I915_READ(GEN7_MISCCPCTL);
2889 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
2890 POSTING_READ(GEN7_MISCCPCTL);
2892 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
2893 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
2894 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
2895 DRM_DEBUG("0x%x was already programmed to %x\n",
2896 GEN7_L3LOG_BASE + i, remap);
2897 if (remap && !dev_priv->l3_parity.remap_info[i/4])
2898 DRM_DEBUG_DRIVER("Clearing remapped register\n");
2899 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
2902 /* Make sure all the writes land before disabling dop clock gating */
2903 POSTING_READ(GEN7_L3LOG_BASE);
2905 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
2908 void i915_gem_init_swizzling(struct drm_device *dev)
2910 drm_i915_private_t *dev_priv = dev->dev_private;
2912 if (INTEL_INFO(dev)->gen < 5 ||
2913 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
2916 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
2917 DISP_TILE_SURFACE_SWIZZLING);
2922 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
2924 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
2926 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
2930 intel_enable_blt(struct drm_device *dev)
2937 /* The blitter was dysfunctional on early prototypes */
2938 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
2939 if (IS_GEN6(dev) && revision < 8) {
2940 DRM_INFO("BLT not supported on this pre-production hardware;"
2941 " graphics performance will be degraded.\n");
2949 i915_gem_init_hw(struct drm_device *dev)
2951 drm_i915_private_t *dev_priv = dev->dev_private;
2954 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
2955 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
2957 i915_gem_l3_remap(dev);
2959 i915_gem_init_swizzling(dev);
2961 ret = intel_init_render_ring_buffer(dev);
2966 ret = intel_init_bsd_ring_buffer(dev);
2968 goto cleanup_render_ring;
2971 if (intel_enable_blt(dev)) {
2972 ret = intel_init_blt_ring_buffer(dev);
2974 goto cleanup_bsd_ring;
2977 dev_priv->next_seqno = 1;
2980 * XXX: There was some w/a described somewhere suggesting loading
2981 * contexts before PPGTT.
2983 i915_gem_context_init(dev);
2984 i915_gem_init_ppgtt(dev);
2989 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
2990 cleanup_render_ring:
2991 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
2996 intel_enable_ppgtt(struct drm_device *dev)
2998 if (i915_enable_ppgtt >= 0)
2999 return i915_enable_ppgtt;
3001 /* Disable ppgtt on SNB if VT-d is on. */
3002 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
3008 int i915_gem_init(struct drm_device *dev)
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 unsigned long prealloc_size, gtt_size, mappable_size;
3014 prealloc_size = dev_priv->mm.gtt->stolen_size;
3015 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3016 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3018 /* Basic memrange allocator for stolen space */
3019 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
3022 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3023 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3024 * aperture accordingly when using aliasing ppgtt. */
3025 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3026 /* For paranoia keep the guard page in between. */
3027 gtt_size -= PAGE_SIZE;
3029 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
3031 ret = i915_gem_init_aliasing_ppgtt(dev);
3037 /* Let GEM Manage all of the aperture.
3039 * However, leave one page at the end still bound to the scratch
3040 * page. There are a number of places where the hardware
3041 * apparently prefetches past the end of the object, and we've
3042 * seen multiple hangs with the GPU head pointer stuck in a
3043 * batchbuffer bound at the last page of the aperture. One page
3044 * should be enough to keep any prefetching inside of the
3047 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
3050 ret = i915_gem_init_hw(dev);
3053 i915_gem_cleanup_aliasing_ppgtt(dev);
3058 /* Try to set up FBC with a reasonable compressed buffer size */
3059 if (I915_HAS_FBC(dev) && i915_powersave) {
3062 /* Leave 1M for line length buffer & misc. */
3064 /* Try to get a 32M buffer... */
3065 if (prealloc_size > (36*1024*1024))
3066 cfb_size = 32*1024*1024;
3067 else /* fall back to 7/8 of the stolen space */
3068 cfb_size = prealloc_size * 7 / 8;
3069 i915_setup_compression(dev, cfb_size);
3073 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3074 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3075 dev_priv->dri1.allow_batchbuffer = 1;
3080 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3082 drm_i915_private_t *dev_priv = dev->dev_private;
3083 struct intel_ring_buffer *ring;
3086 for_each_ring(ring, dev_priv, i)
3087 intel_cleanup_ring_buffer(ring);
3091 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3092 struct drm_file *file_priv)
3094 drm_i915_private_t *dev_priv = dev->dev_private;
3097 if (drm_core_check_feature(dev, DRIVER_MODESET))
3100 if (atomic_read(&dev_priv->mm.wedged)) {
3101 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3102 atomic_set(&dev_priv->mm.wedged, 0);
3106 dev_priv->mm.suspended = 0;
3108 ret = i915_gem_init_hw(dev);
3114 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
3117 ret = drm_irq_install(dev);
3119 goto cleanup_ringbuffer;
3125 i915_gem_cleanup_ringbuffer(dev);
3126 dev_priv->mm.suspended = 1;
3133 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3134 struct drm_file *file_priv)
3136 if (drm_core_check_feature(dev, DRIVER_MODESET))
3139 drm_irq_uninstall(dev);
3140 return i915_gem_idle(dev);
3144 i915_gem_lastclose(struct drm_device *dev)
3148 if (drm_core_check_feature(dev, DRIVER_MODESET))
3151 ret = i915_gem_idle(dev);
3153 DRM_ERROR("failed to idle hardware: %d\n", ret);
3157 init_ring_lists(struct intel_ring_buffer *ring)
3159 INIT_LIST_HEAD(&ring->active_list);
3160 INIT_LIST_HEAD(&ring->request_list);
3164 i915_gem_load(struct drm_device *dev)
3167 drm_i915_private_t *dev_priv = dev->dev_private;
3169 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3170 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3171 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3172 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3173 for (i = 0; i < I915_NUM_RINGS; i++)
3174 init_ring_lists(&dev_priv->ring[i]);
3175 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3176 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3177 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3178 i915_gem_retire_work_handler);
3179 init_completion(&dev_priv->error_completion);
3181 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3183 I915_WRITE(MI_ARB_STATE,
3184 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3187 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3189 /* Old X drivers will take 0-2 for front, back, depth buffers */
3190 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3191 dev_priv->fence_reg_start = 3;
3193 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3194 dev_priv->num_fence_regs = 16;
3196 dev_priv->num_fence_regs = 8;
3198 /* Initialize fence registers to zero */
3199 i915_gem_reset_fences(dev);
3201 i915_gem_detect_bit_6_swizzle(dev);
3202 init_waitqueue_head(&dev_priv->pending_flip_queue);
3204 dev_priv->mm.interruptible = true;
3207 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3208 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3209 register_shrinker(&dev_priv->mm.inactive_shrinker);
3211 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
3212 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
3217 * Create a physically contiguous memory object for this object
3218 * e.g. for cursor + overlay regs
3220 static int i915_gem_init_phys_object(struct drm_device *dev,
3221 int id, int size, int align)
3223 drm_i915_private_t *dev_priv = dev->dev_private;
3224 struct drm_i915_gem_phys_object *phys_obj;
3227 if (dev_priv->mm.phys_objs[id - 1] || !size)
3230 phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3237 phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3238 if (!phys_obj->handle) {
3242 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3243 size / PAGE_SIZE, PAT_WRITE_COMBINING);
3245 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3250 drm_free(phys_obj, DRM_I915_GEM);
3254 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3256 drm_i915_private_t *dev_priv = dev->dev_private;
3257 struct drm_i915_gem_phys_object *phys_obj;
3259 if (!dev_priv->mm.phys_objs[id - 1])
3262 phys_obj = dev_priv->mm.phys_objs[id - 1];
3263 if (phys_obj->cur_obj) {
3264 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3267 drm_pci_free(dev, phys_obj->handle);
3268 drm_free(phys_obj, DRM_I915_GEM);
3269 dev_priv->mm.phys_objs[id - 1] = NULL;
3272 void i915_gem_free_all_phys_object(struct drm_device *dev)
3276 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3277 i915_gem_free_phys_object(dev, i);
3280 void i915_gem_detach_phys_object(struct drm_device *dev,
3281 struct drm_i915_gem_object *obj)
3290 vaddr = obj->phys_obj->handle->vaddr;
3292 page_count = obj->base.size / PAGE_SIZE;
3293 VM_OBJECT_LOCK(obj->base.vm_obj);
3294 for (i = 0; i < page_count; i++) {
3295 m = i915_gem_wire_page(obj->base.vm_obj, i);
3299 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3300 sf = sf_buf_alloc(m);
3302 dst = (char *)sf_buf_kva(sf);
3303 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3306 drm_clflush_pages(&m, 1);
3308 VM_OBJECT_LOCK(obj->base.vm_obj);
3309 vm_page_reference(m);
3311 vm_page_busy_wait(m, FALSE, "i915gem");
3312 vm_page_unwire(m, 0);
3314 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3316 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3317 intel_gtt_chipset_flush();
3319 obj->phys_obj->cur_obj = NULL;
3320 obj->phys_obj = NULL;
3324 i915_gem_attach_phys_object(struct drm_device *dev,
3325 struct drm_i915_gem_object *obj,
3329 drm_i915_private_t *dev_priv = dev->dev_private;
3333 int i, page_count, ret;
3335 if (id > I915_MAX_PHYS_OBJECT)
3338 if (obj->phys_obj) {
3339 if (obj->phys_obj->id == id)
3341 i915_gem_detach_phys_object(dev, obj);
3344 /* create a new object */
3345 if (!dev_priv->mm.phys_objs[id - 1]) {
3346 ret = i915_gem_init_phys_object(dev, id,
3347 obj->base.size, align);
3349 DRM_ERROR("failed to init phys object %d size: %zu\n",
3350 id, obj->base.size);
3355 /* bind to the object */
3356 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3357 obj->phys_obj->cur_obj = obj;
3359 page_count = obj->base.size / PAGE_SIZE;
3361 VM_OBJECT_LOCK(obj->base.vm_obj);
3363 for (i = 0; i < page_count; i++) {
3364 m = i915_gem_wire_page(obj->base.vm_obj, i);
3369 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3370 sf = sf_buf_alloc(m);
3371 src = (char *)sf_buf_kva(sf);
3372 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3373 memcpy(dst, src, PAGE_SIZE);
3376 VM_OBJECT_LOCK(obj->base.vm_obj);
3378 vm_page_reference(m);
3379 vm_page_busy_wait(m, FALSE, "i915gem");
3380 vm_page_unwire(m, 0);
3382 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3384 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3390 i915_gem_phys_pwrite(struct drm_device *dev,
3391 struct drm_i915_gem_object *obj,
3395 struct drm_file *file_priv)
3397 char *user_data, *vaddr;
3400 vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3401 user_data = (char *)(uintptr_t)data_ptr;
3403 if (copyin_nofault(user_data, vaddr, size) != 0) {
3404 /* The physical object once assigned is fixed for the lifetime
3405 * of the obj, so we can safely drop the lock and continue
3409 ret = -copyin(user_data, vaddr, size);
3415 intel_gtt_chipset_flush();
3419 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3421 struct drm_i915_file_private *file_priv = file->driver_priv;
3423 /* Clean up our request list when the client is going away, so that
3424 * later retire_requests won't dereference our soon-to-be-gone
3427 spin_lock(&file_priv->mm.lock);
3428 while (!list_empty(&file_priv->mm.request_list)) {
3429 struct drm_i915_gem_request *request;
3431 request = list_first_entry(&file_priv->mm.request_list,
3432 struct drm_i915_gem_request,
3434 list_del(&request->client_list);
3435 request->file_priv = NULL;
3437 spin_unlock(&file_priv->mm.lock);
3441 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
3442 uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
3443 struct drm_file *file)
3450 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
3452 if (obj->gtt_offset != 0 && rw == UIO_READ)
3453 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
3455 do_bit17_swizzling = 0;
3458 vm_obj = obj->base.vm_obj;
3461 VM_OBJECT_LOCK(vm_obj);
3462 vm_object_pip_add(vm_obj, 1);
3464 obj_pi = OFF_TO_IDX(offset);
3465 obj_po = offset & PAGE_MASK;
3467 m = i915_gem_wire_page(vm_obj, obj_pi);
3468 VM_OBJECT_UNLOCK(vm_obj);
3470 sf = sf_buf_alloc(m);
3471 mkva = sf_buf_kva(sf);
3472 length = min(size, PAGE_SIZE - obj_po);
3473 while (length > 0) {
3474 if (do_bit17_swizzling &&
3475 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
3476 cnt = roundup2(obj_po + 1, 64);
3477 cnt = min(cnt - obj_po, length);
3478 swizzled_po = obj_po ^ 64;
3481 swizzled_po = obj_po;
3484 ret = -copyout_nofault(
3485 (char *)mkva + swizzled_po,
3486 (void *)(uintptr_t)data_ptr, cnt);
3488 ret = -copyin_nofault(
3489 (void *)(uintptr_t)data_ptr,
3490 (char *)mkva + swizzled_po, cnt);
3500 VM_OBJECT_LOCK(vm_obj);
3501 if (rw == UIO_WRITE)
3503 vm_page_reference(m);
3504 vm_page_busy_wait(m, FALSE, "i915gem");
3505 vm_page_unwire(m, 1);
3507 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3512 vm_object_pip_wakeup(vm_obj);
3513 VM_OBJECT_UNLOCK(vm_obj);
3519 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
3520 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
3526 * Pass the unaligned physical address and size to pmap_mapdev_attr()
3527 * so it can properly calculate whether an extra page needs to be
3528 * mapped or not to cover the requested range. The function will
3529 * add the page offset into the returned mkva for us.
3531 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
3532 offset, size, PAT_WRITE_COMBINING);
3533 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
3534 pmap_unmapdev(mkva, size);
3539 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
3540 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
3542 struct drm_i915_gem_object *obj;
3544 vm_offset_t start, end;
3549 start = trunc_page(data_ptr);
3550 end = round_page(data_ptr + size);
3551 npages = howmany(end - start, PAGE_SIZE);
3552 ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
3554 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
3555 (vm_offset_t)data_ptr, size,
3556 (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
3562 ret = i915_mutex_lock_interruptible(dev);
3566 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
3567 if (&obj->base == NULL) {
3571 if (offset > obj->base.size || size > obj->base.size - offset) {
3576 if (rw == UIO_READ) {
3577 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3580 if (obj->phys_obj) {
3581 ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
3583 } else if (obj->gtt_space &&
3584 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
3585 ret = i915_gem_object_pin(obj, 0, true, false);
3588 ret = i915_gem_object_set_to_gtt_domain(obj, true);
3591 ret = i915_gem_object_put_fence(obj);
3594 ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
3597 i915_gem_object_unpin(obj);
3599 ret = i915_gem_object_set_to_cpu_domain(obj, true);
3602 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3607 drm_gem_object_unreference(&obj->base);
3611 vm_page_unhold_pages(ma, npages);
3613 drm_free(ma, DRM_I915_GEM);
3618 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
3619 vm_ooffset_t foff, struct ucred *cred, u_short *color)
3622 *color = 0; /* XXXKIB */
3629 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
3632 struct drm_gem_object *gem_obj;
3633 struct drm_i915_gem_object *obj;
3634 struct drm_device *dev;
3635 drm_i915_private_t *dev_priv;
3640 gem_obj = vm_obj->handle;
3641 obj = to_intel_bo(gem_obj);
3642 dev = obj->base.dev;
3643 dev_priv = dev->dev_private;
3645 write = (prot & VM_PROT_WRITE) != 0;
3649 vm_object_pip_add(vm_obj, 1);
3652 * Remove the placeholder page inserted by vm_fault() from the
3653 * object before dropping the object lock. If
3654 * i915_gem_release_mmap() is active in parallel on this gem
3655 * object, then it owns the drm device sx and might find the
3656 * placeholder already. Then, since the page is busy,
3657 * i915_gem_release_mmap() sleeps waiting for the busy state
3658 * of the page cleared. We will be not able to acquire drm
3659 * device lock until i915_gem_release_mmap() is able to make a
3662 if (*mres != NULL) {
3664 vm_page_remove(oldm);
3669 VM_OBJECT_UNLOCK(vm_obj);
3675 ret = i915_mutex_lock_interruptible(dev);
3684 * Since the object lock was dropped, other thread might have
3685 * faulted on the same GTT address and instantiated the
3686 * mapping for the page. Recheck.
3688 VM_OBJECT_LOCK(vm_obj);
3689 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
3691 if ((m->flags & PG_BUSY) != 0) {
3694 vm_page_sleep(m, "915pee");
3700 VM_OBJECT_UNLOCK(vm_obj);
3702 /* Now bind it into the GTT if needed */
3703 if (!obj->map_and_fenceable) {
3704 ret = i915_gem_object_unbind(obj);
3710 if (!obj->gtt_space) {
3711 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
3717 ret = i915_gem_object_set_to_gtt_domain(obj, write);
3724 if (obj->tiling_mode == I915_TILING_NONE)
3725 ret = i915_gem_object_put_fence(obj);
3727 ret = i915_gem_object_get_fence(obj);
3733 if (i915_gem_object_is_inactive(obj))
3734 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3736 obj->fault_mappable = true;
3737 VM_OBJECT_LOCK(vm_obj);
3738 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
3745 KASSERT((m->flags & PG_FICTITIOUS) != 0,
3746 ("not fictitious %p", m));
3747 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
3749 if ((m->flags & PG_BUSY) != 0) {
3752 vm_page_sleep(m, "915pbs");
3756 m->valid = VM_PAGE_BITS_ALL;
3757 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
3760 vm_page_busy_try(m, false);
3766 vm_object_pip_wakeup(vm_obj);
3767 return (VM_PAGER_OK);
3772 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
3773 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
3774 goto unlocked_vmobj;
3776 VM_OBJECT_LOCK(vm_obj);
3777 vm_object_pip_wakeup(vm_obj);
3778 return (VM_PAGER_ERROR);
3782 i915_gem_pager_dtor(void *handle)
3784 struct drm_gem_object *obj;
3785 struct drm_device *dev;
3791 drm_gem_free_mmap_offset(obj);
3792 i915_gem_release_mmap(to_intel_bo(obj));
3793 drm_gem_object_unreference(obj);
3797 struct cdev_pager_ops i915_gem_pager_ops = {
3798 .cdev_pg_fault = i915_gem_pager_fault,
3799 .cdev_pg_ctor = i915_gem_pager_ctor,
3800 .cdev_pg_dtor = i915_gem_pager_dtor
3803 #define GEM_PARANOID_CHECK_GTT 0
3804 #if GEM_PARANOID_CHECK_GTT
3806 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
3809 struct drm_i915_private *dev_priv;
3811 unsigned long start, end;
3815 dev_priv = dev->dev_private;
3816 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
3817 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
3818 for (i = start; i < end; i++) {
3819 pa = intel_gtt_read_pte_paddr(i);
3820 for (j = 0; j < page_count; j++) {
3821 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
3822 panic("Page %p in GTT pte index %d pte %x",
3823 ma[i], i, intel_gtt_read_pte(i));
3830 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
3833 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
3838 VM_OBJECT_LOCK_ASSERT_OWNED(object);
3839 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
3840 if (m->valid != VM_PAGE_BITS_ALL) {
3841 if (vm_pager_has_page(object, pindex)) {
3842 rv = vm_pager_get_page(object, &m, 1);
3843 m = vm_page_lookup(object, pindex);
3846 if (rv != VM_PAGER_OK) {
3851 pmap_zero_page(VM_PAGE_TO_PHYS(m));
3852 m->valid = VM_PAGE_BITS_ALL;
3858 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
3863 i915_gpu_is_active(struct drm_device *dev)
3865 drm_i915_private_t *dev_priv = dev->dev_private;
3867 return !list_empty(&dev_priv->mm.active_list);
3871 i915_gem_lowmem(void *arg)
3873 struct drm_device *dev;
3874 struct drm_i915_private *dev_priv;
3875 struct drm_i915_gem_object *obj, *next;
3876 int cnt, cnt_fail, cnt_total;
3879 dev_priv = dev->dev_private;
3881 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3885 /* first scan for clean buffers */
3886 i915_gem_retire_requests(dev);
3888 cnt_total = cnt_fail = cnt = 0;
3890 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3892 if (i915_gem_object_is_purgeable(obj)) {
3893 if (i915_gem_object_unbind(obj) != 0)
3899 /* second pass, evict/count anything still on the inactive list */
3900 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3902 if (i915_gem_object_unbind(obj) == 0)
3908 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3910 * We are desperate for pages, so as a last resort, wait
3911 * for the GPU to finish and discard whatever we can.
3912 * This has a dramatic impact to reduce the number of
3913 * OOM-killer events whilst running the GPU aggressively.
3915 if (i915_gpu_idle(dev) == 0)
3922 i915_gem_unload(struct drm_device *dev)
3924 struct drm_i915_private *dev_priv;
3926 dev_priv = dev->dev_private;
3927 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);