2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/highmem.h>
37 struct list_head objects;
40 struct drm_i915_gem_object *lut[0];
41 struct hlist_head buckets[0];
45 static struct eb_objects *
46 eb_create(struct drm_i915_gem_execbuffer2 *args)
48 struct eb_objects *eb = NULL;
50 if (args->flags & I915_EXEC_HANDLE_LUT) {
51 int size = args->buffer_count;
52 size *= sizeof(struct drm_i915_gem_object *);
53 size += sizeof(struct eb_objects);
54 eb = kmalloc(size, M_DRM, M_WAITOK);
58 int size = args->buffer_count;
59 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
60 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
61 while (count > 2*size)
63 eb = kzalloc(count*sizeof(struct hlist_head) +
64 sizeof(struct eb_objects),
71 eb->and = -args->buffer_count;
73 INIT_LIST_HEAD(&eb->objects);
78 eb_reset(struct eb_objects *eb)
81 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
85 eb_lookup_objects(struct eb_objects *eb,
86 struct drm_i915_gem_exec_object2 *exec,
87 const struct drm_i915_gem_execbuffer2 *args,
88 struct drm_file *file)
92 lockmgr(&file->table_lock, LK_EXCLUSIVE);
93 for (i = 0; i < args->buffer_count; i++) {
94 struct drm_i915_gem_object *obj;
96 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
98 lockmgr(&file->table_lock, LK_RELEASE);
99 DRM_DEBUG("Invalid object handle %d at index %d\n",
104 if (!list_empty(&obj->exec_list)) {
105 lockmgr(&file->table_lock, LK_RELEASE);
106 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
107 obj, exec[i].handle, i);
111 drm_gem_object_reference(&obj->base);
112 list_add_tail(&obj->exec_list, &eb->objects);
114 obj->exec_entry = &exec[i];
118 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
119 obj->exec_handle = handle;
120 hlist_add_head(&obj->exec_node,
121 &eb->buckets[handle & eb->and]);
124 lockmgr(&file->table_lock, LK_RELEASE);
129 static struct drm_i915_gem_object *
130 eb_get_object(struct eb_objects *eb, unsigned long handle)
133 if (handle >= -eb->and)
135 return eb->lut[handle];
137 struct hlist_head *head;
138 struct hlist_node *node;
140 head = &eb->buckets[handle & eb->and];
141 hlist_for_each(node, head) {
142 struct drm_i915_gem_object *obj;
144 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
145 if (obj->exec_handle == handle)
153 eb_destroy(struct eb_objects *eb)
155 while (!list_empty(&eb->objects)) {
156 struct drm_i915_gem_object *obj;
158 obj = list_first_entry(&eb->objects,
159 struct drm_i915_gem_object,
161 list_del_init(&obj->exec_list);
162 drm_gem_object_unreference(&obj->base);
167 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
169 return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
170 !obj->map_and_fenceable ||
171 obj->cache_level != I915_CACHE_NONE);
175 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
176 struct eb_objects *eb,
177 struct drm_i915_gem_relocation_entry *reloc)
179 struct drm_device *dev = obj->base.dev;
180 struct drm_gem_object *target_obj;
181 struct drm_i915_gem_object *target_i915_obj;
182 uint32_t target_offset;
185 /* we've already hold a reference to all valid objects */
186 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
187 if (unlikely(target_obj == NULL))
190 target_i915_obj = to_intel_bo(target_obj);
191 target_offset = target_i915_obj->gtt_offset;
193 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
194 * pipe_control writes because the gpu doesn't properly redirect them
195 * through the ppgtt for non_secure batchbuffers. */
196 if (unlikely(IS_GEN6(dev) &&
197 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
198 !target_i915_obj->has_global_gtt_mapping)) {
199 i915_gem_gtt_bind_object(target_i915_obj,
200 target_i915_obj->cache_level);
203 /* Validate that the target is in a valid r/w GPU domain */
204 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
205 DRM_DEBUG("reloc with multiple write domains: "
206 "obj %p target %d offset %d "
207 "read %08x write %08x",
208 obj, reloc->target_handle,
211 reloc->write_domain);
214 if (unlikely((reloc->write_domain | reloc->read_domains)
215 & ~I915_GEM_GPU_DOMAINS)) {
216 DRM_DEBUG("reloc with read/write non-GPU domains: "
217 "obj %p target %d offset %d "
218 "read %08x write %08x",
219 obj, reloc->target_handle,
222 reloc->write_domain);
226 target_obj->pending_read_domains |= reloc->read_domains;
227 target_obj->pending_write_domain |= reloc->write_domain;
229 /* If the relocation already has the right value in it, no
230 * more work needs to be done.
232 if (target_offset == reloc->presumed_offset)
235 /* Check that the relocation address is valid... */
236 if (unlikely(reloc->offset > obj->base.size - 4)) {
237 DRM_DEBUG("Relocation beyond object bounds: "
238 "obj %p target %d offset %d size %d.\n",
239 obj, reloc->target_handle,
241 (int) obj->base.size);
244 if (unlikely(reloc->offset & 3)) {
245 DRM_DEBUG("Relocation not 4-byte aligned: "
246 "obj %p target %d offset %d.\n",
247 obj, reloc->target_handle,
248 (int) reloc->offset);
252 /* We can't wait for rendering with pagefaults disabled */
253 if (obj->active && (curthread->td_flags & TDF_NOFAULT))
256 reloc->delta += target_offset;
257 if (use_cpu_reloc(obj)) {
258 uint32_t page_offset = reloc->offset & PAGE_MASK;
261 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
265 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
266 reloc->offset >> PAGE_SHIFT));
267 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
268 kunmap_atomic(vaddr);
270 uint32_t __iomem *reloc_entry;
271 char __iomem *reloc_page;
273 ret = i915_gem_object_set_to_gtt_domain(obj, true);
277 ret = i915_gem_object_put_fence(obj);
281 /* Map the page containing the relocation we're going to perform. */
282 reloc->offset += obj->gtt_offset;
283 reloc_page = pmap_mapdev_attr(dev->agp->base + (reloc->offset &
284 ~PAGE_MASK), PAGE_SIZE, PAT_WRITE_COMBINING);
285 reloc_entry = (uint32_t *)(reloc_page + (reloc->offset &
287 iowrite32(reloc->delta, reloc_entry);
288 pmap_unmapdev((vm_offset_t)reloc_page, PAGE_SIZE);
291 /* and update the user's relocation entry */
292 reloc->presumed_offset = target_offset;
298 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
299 struct eb_objects *eb)
301 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
302 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
303 struct drm_i915_gem_relocation_entry __user *user_relocs;
304 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
307 user_relocs = to_user_ptr(entry->relocs_ptr);
309 remain = entry->relocation_count;
311 struct drm_i915_gem_relocation_entry *r = stack_reloc;
313 if (count > ARRAY_SIZE(stack_reloc))
314 count = ARRAY_SIZE(stack_reloc);
317 if (copyin_nofault(user_relocs, r, count*sizeof(r[0])))
321 u64 offset = r->presumed_offset;
323 ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
327 if (r->presumed_offset != offset &&
328 copyout_nofault(&r->presumed_offset,
329 &user_relocs->presumed_offset,
330 sizeof(r->presumed_offset))) {
344 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
345 struct eb_objects *eb,
346 struct drm_i915_gem_relocation_entry *relocs)
348 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
351 for (i = 0; i < entry->relocation_count; i++) {
352 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
361 i915_gem_execbuffer_relocate(struct eb_objects *eb)
363 struct drm_i915_gem_object *obj;
366 /* This is the fast path and we cannot handle a pagefault whilst
367 * holding the struct mutex lest the user pass in the relocations
368 * contained within a mmaped bo. For in such a case we, the page
369 * fault handler would call i915_gem_fault() and we would try to
370 * acquire the struct mutex again. Obviously this is bad and so
371 * lockdep complains vehemently.
376 list_for_each_entry(obj, &eb->objects, exec_list) {
377 ret = i915_gem_execbuffer_relocate_object(obj, eb);
388 #define __EXEC_OBJECT_HAS_PIN (1<<31)
389 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
392 need_reloc_mappable(struct drm_i915_gem_object *obj)
394 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
395 return entry->relocation_count && !use_cpu_reloc(obj);
399 i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
400 struct intel_ring_buffer *ring,
403 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
404 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
405 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
406 bool need_fence, need_mappable;
410 has_fenced_gpu_access &&
411 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
412 obj->tiling_mode != I915_TILING_NONE;
413 need_mappable = need_fence || need_reloc_mappable(obj);
415 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false);
419 entry->flags |= __EXEC_OBJECT_HAS_PIN;
421 if (has_fenced_gpu_access) {
422 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
423 ret = i915_gem_object_get_fence(obj);
427 if (i915_gem_object_pin_fence(obj))
428 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
430 obj->pending_fenced_gpu_access = true;
434 /* Ensure ppgtt mapping exists if needed */
435 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
436 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
437 obj, obj->cache_level);
439 obj->has_aliasing_ppgtt_mapping = 1;
442 if (entry->offset != obj->gtt_offset) {
443 entry->offset = obj->gtt_offset;
447 if (entry->flags & EXEC_OBJECT_WRITE) {
448 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
449 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
452 if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
453 !obj->has_global_gtt_mapping)
454 i915_gem_gtt_bind_object(obj, obj->cache_level);
460 i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
462 struct drm_i915_gem_exec_object2 *entry;
467 entry = obj->exec_entry;
469 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
470 i915_gem_object_unpin_fence(obj);
472 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
473 i915_gem_object_unpin(obj);
475 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
479 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
480 struct list_head *objects,
483 struct drm_i915_gem_object *obj;
484 struct list_head ordered_objects;
485 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
488 INIT_LIST_HEAD(&ordered_objects);
489 while (!list_empty(objects)) {
490 struct drm_i915_gem_exec_object2 *entry;
491 bool need_fence, need_mappable;
493 obj = list_first_entry(objects,
494 struct drm_i915_gem_object,
496 entry = obj->exec_entry;
499 has_fenced_gpu_access &&
500 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
501 obj->tiling_mode != I915_TILING_NONE;
502 need_mappable = need_fence || need_reloc_mappable(obj);
505 list_move(&obj->exec_list, &ordered_objects);
507 list_move_tail(&obj->exec_list, &ordered_objects);
509 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
510 obj->base.pending_write_domain = 0;
511 obj->pending_fenced_gpu_access = false;
513 list_splice(&ordered_objects, objects);
515 /* Attempt to pin all of the buffers into the GTT.
516 * This is done in 3 phases:
518 * 1a. Unbind all objects that do not match the GTT constraints for
519 * the execbuffer (fenceable, mappable, alignment etc).
520 * 1b. Increment pin count for already bound objects.
521 * 2. Bind new objects.
522 * 3. Decrement pin count.
524 * This avoid unnecessary unbinding of later objects in order to make
525 * room for the earlier objects *unless* we need to defragment.
531 /* Unbind any ill-fitting objects or pin. */
532 list_for_each_entry(obj, objects, exec_list) {
533 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
534 bool need_fence, need_mappable;
540 has_fenced_gpu_access &&
541 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
542 obj->tiling_mode != I915_TILING_NONE;
543 need_mappable = need_fence || need_reloc_mappable(obj);
545 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
546 (need_mappable && !obj->map_and_fenceable))
547 ret = i915_gem_object_unbind(obj);
549 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
554 /* Bind fresh objects */
555 list_for_each_entry(obj, objects, exec_list) {
559 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
564 err: /* Decrement pin count for bound objects */
565 list_for_each_entry(obj, objects, exec_list)
566 i915_gem_execbuffer_unreserve_object(obj);
568 if (ret != -ENOSPC || retry++)
571 ret = i915_gem_evict_everything(ring->dev);
578 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
579 struct drm_i915_gem_execbuffer2 *args,
580 struct drm_file *file,
581 struct intel_ring_buffer *ring,
582 struct eb_objects *eb,
583 struct drm_i915_gem_exec_object2 *exec)
585 struct drm_i915_gem_relocation_entry *reloc;
586 struct drm_i915_gem_object *obj;
590 int count = args->buffer_count;
592 /* We may process another execbuffer during the unlock... */
593 while (!list_empty(&eb->objects)) {
594 obj = list_first_entry(&eb->objects,
595 struct drm_i915_gem_object,
597 list_del_init(&obj->exec_list);
598 drm_gem_object_unreference(&obj->base);
601 mutex_unlock(&dev->struct_mutex);
604 for (i = 0; i < count; i++)
605 total += exec[i].relocation_count;
607 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
608 reloc = drm_malloc_ab(total, sizeof(*reloc));
609 if (reloc == NULL || reloc_offset == NULL) {
610 drm_free_large(reloc);
611 drm_free_large(reloc_offset);
612 mutex_lock(&dev->struct_mutex);
617 for (i = 0; i < count; i++) {
618 struct drm_i915_gem_relocation_entry __user *user_relocs;
619 u64 invalid_offset = (u64)-1;
622 user_relocs = to_user_ptr(exec[i].relocs_ptr);
624 if (copy_from_user(reloc+total, user_relocs,
625 exec[i].relocation_count * sizeof(*reloc))) {
627 mutex_lock(&dev->struct_mutex);
631 /* As we do not update the known relocation offsets after
632 * relocating (due to the complexities in lock handling),
633 * we need to mark them as invalid now so that we force the
634 * relocation processing next time. Just in case the target
635 * object is evicted and then rebound into its old
636 * presumed_offset before the next execbuffer - if that
637 * happened we would make the mistake of assuming that the
638 * relocations were valid.
640 for (j = 0; j < exec[i].relocation_count; j++) {
641 if (copy_to_user(&user_relocs[j].presumed_offset,
643 sizeof(invalid_offset))) {
645 mutex_lock(&dev->struct_mutex);
650 reloc_offset[i] = total;
651 total += exec[i].relocation_count;
654 ret = i915_mutex_lock_interruptible(dev);
656 mutex_lock(&dev->struct_mutex);
660 /* reacquire the objects */
662 ret = eb_lookup_objects(eb, exec, args, file);
666 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
667 ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs);
671 list_for_each_entry(obj, &eb->objects, exec_list) {
672 int offset = obj->exec_entry - exec;
673 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
674 reloc + reloc_offset[offset]);
679 /* Leave the user relocations as are, this is the painfully slow path,
680 * and we want to avoid the complication of dropping the lock whilst
681 * having buffers reserved in the aperture and so causing spurious
682 * ENOSPC for random operations.
686 drm_free_large(reloc);
687 drm_free_large(reloc_offset);
692 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
693 struct list_head *objects)
695 struct drm_i915_gem_object *obj;
696 uint32_t flush_domains = 0;
699 list_for_each_entry(obj, objects, exec_list) {
700 ret = i915_gem_object_sync(obj, ring);
704 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
705 i915_gem_clflush_object(obj);
707 flush_domains |= obj->base.write_domain;
710 if (flush_domains & I915_GEM_DOMAIN_CPU)
711 i915_gem_chipset_flush(ring->dev);
713 if (flush_domains & I915_GEM_DOMAIN_GTT)
716 /* Unconditionally invalidate gpu caches and ensure that we do flush
717 * any residual writes from the previous batch.
719 return intel_ring_invalidate_all_caches(ring);
723 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
725 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
728 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
732 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
736 int relocs_total = 0;
737 int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
739 for (i = 0; i < count; i++) {
741 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
743 int length; /* limited by fault_in_pages_readable() */
745 if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
748 /* First check for malicious input causing overflow in
749 * the worst case where we need to allocate the entire
750 * relocation tree as a single array.
752 if (exec[i].relocation_count > relocs_max - relocs_total)
754 relocs_total += exec[i].relocation_count;
756 length = exec[i].relocation_count *
757 sizeof(struct drm_i915_gem_relocation_entry);
760 * We must check that the entire relocation array is safe
761 * to read, but since we may need to update the presumed
762 * offsets during execution, check for full write access.
764 if (!access_ok(VERIFY_WRITE, ptr, length))
767 if (fault_in_multipages_readable(ptr, length))
776 i915_gem_execbuffer_move_to_active(struct list_head *objects,
777 struct intel_ring_buffer *ring)
779 struct drm_i915_gem_object *obj;
781 list_for_each_entry(obj, objects, exec_list) {
783 obj->base.write_domain = obj->base.pending_write_domain;
784 if (obj->base.write_domain == 0)
785 obj->base.pending_read_domains |= obj->base.read_domains;
786 obj->base.read_domains = obj->base.pending_read_domains;
787 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
789 i915_gem_object_move_to_active(obj, ring);
790 if (obj->base.write_domain) {
792 obj->last_write_seqno = intel_ring_get_seqno(ring);
793 if (obj->pin_count) /* check for potential scanout */
794 intel_mark_fb_busy(obj);
797 trace_i915_gem_object_change_domain(obj, old_read, old_write);
802 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
803 struct drm_file *file,
804 struct intel_ring_buffer *ring)
806 /* Unconditionally force add_request to emit a full flush. */
807 ring->gpu_caches_dirty = true;
809 /* Add a breadcrumb for the completion of the batch buffer */
810 (void)i915_add_request(ring, file, NULL);
814 i915_reset_gen7_sol_offsets(struct drm_device *dev,
815 struct intel_ring_buffer *ring)
817 drm_i915_private_t *dev_priv = dev->dev_private;
820 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
823 ret = intel_ring_begin(ring, 4 * 3);
827 for (i = 0; i < 4; i++) {
828 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
829 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
830 intel_ring_emit(ring, 0);
833 intel_ring_advance(ring);
839 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
840 struct drm_file *file,
841 struct drm_i915_gem_execbuffer2 *args,
842 struct drm_i915_gem_exec_object2 *exec)
844 drm_i915_private_t *dev_priv = dev->dev_private;
845 struct eb_objects *eb;
846 struct drm_i915_gem_object *batch_obj;
847 struct drm_clip_rect *cliprects = NULL;
848 struct intel_ring_buffer *ring;
849 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
850 u32 exec_start, exec_len;
855 if (!i915_gem_check_execbuffer(args))
858 ret = validate_exec_list(exec, args->buffer_count);
863 if (args->flags & I915_EXEC_SECURE) {
864 flags |= I915_DISPATCH_SECURE;
866 if (args->flags & I915_EXEC_IS_PINNED)
867 flags |= I915_DISPATCH_PINNED;
869 switch (args->flags & I915_EXEC_RING_MASK) {
870 case I915_EXEC_DEFAULT:
871 case I915_EXEC_RENDER:
872 ring = &dev_priv->ring[RCS];
875 ring = &dev_priv->ring[VCS];
877 DRM_DEBUG("Ring %s doesn't support contexts\n",
883 ring = &dev_priv->ring[BCS];
885 DRM_DEBUG("Ring %s doesn't support contexts\n",
891 DRM_DEBUG("execbuf with unknown ring: %d\n",
892 (int)(args->flags & I915_EXEC_RING_MASK));
895 if (!intel_ring_initialized(ring)) {
896 DRM_DEBUG("execbuf with invalid ring: %d\n",
897 (int)(args->flags & I915_EXEC_RING_MASK));
901 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
902 mask = I915_EXEC_CONSTANTS_MASK;
904 case I915_EXEC_CONSTANTS_REL_GENERAL:
905 case I915_EXEC_CONSTANTS_ABSOLUTE:
906 case I915_EXEC_CONSTANTS_REL_SURFACE:
907 if (ring == &dev_priv->ring[RCS] &&
908 mode != dev_priv->relative_constants_mode) {
909 if (INTEL_INFO(dev)->gen < 4)
912 if (INTEL_INFO(dev)->gen > 5 &&
913 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
916 /* The HW changed the meaning on this bit on gen6 */
917 if (INTEL_INFO(dev)->gen >= 6)
918 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
922 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
926 if (args->buffer_count < 1) {
927 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
931 if (args->num_cliprects != 0) {
932 if (ring != &dev_priv->ring[RCS]) {
933 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
937 if (INTEL_INFO(dev)->gen >= 5) {
938 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
942 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
943 DRM_DEBUG("execbuf with %u cliprects\n",
944 args->num_cliprects);
948 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
950 if (cliprects == NULL) {
955 if (copy_from_user(cliprects,
956 to_user_ptr(args->cliprects_ptr),
957 sizeof(*cliprects)*args->num_cliprects)) {
963 ret = i915_mutex_lock_interruptible(dev);
967 if (dev_priv->mm.suspended) {
968 mutex_unlock(&dev->struct_mutex);
973 eb = eb_create(args);
975 mutex_unlock(&dev->struct_mutex);
980 /* Look up object handles */
981 ret = eb_lookup_objects(eb, exec, args, file);
985 /* take note of the batch buffer before we might reorder the lists */
986 batch_obj = list_entry(eb->objects.prev,
987 struct drm_i915_gem_object,
990 /* Move the objects en-masse into the GTT, evicting if necessary. */
991 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
992 ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs);
996 /* The objects are in their final locations, apply the relocations. */
998 ret = i915_gem_execbuffer_relocate(eb);
1000 if (ret == -EFAULT) {
1001 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1003 DRM_LOCK_ASSERT(dev);
1009 /* Set the pending read domains for the batch buffer to COMMAND */
1010 if (batch_obj->base.pending_write_domain) {
1011 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1015 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1017 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1018 * batch" bit. Hence we need to pin secure batches into the global gtt.
1019 * hsw should have this fixed, but let's be paranoid and do it
1020 * unconditionally for now. */
1021 if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
1022 i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
1024 ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects);
1028 ret = i915_switch_context(ring, file, ctx_id);
1032 if (ring == &dev_priv->ring[RCS] &&
1033 mode != dev_priv->relative_constants_mode) {
1034 ret = intel_ring_begin(ring, 4);
1038 intel_ring_emit(ring, MI_NOOP);
1039 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1040 intel_ring_emit(ring, INSTPM);
1041 intel_ring_emit(ring, mask << 16 | mode);
1042 intel_ring_advance(ring);
1044 dev_priv->relative_constants_mode = mode;
1047 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1048 ret = i915_reset_gen7_sol_offsets(dev, ring);
1053 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1054 exec_len = args->batch_len;
1056 for (i = 0; i < args->num_cliprects; i++) {
1057 ret = i915_emit_box(dev, &cliprects[i],
1058 args->DR1, args->DR4);
1062 ret = ring->dispatch_execbuffer(ring,
1063 exec_start, exec_len,
1069 ret = ring->dispatch_execbuffer(ring,
1070 exec_start, exec_len,
1076 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1078 i915_gem_execbuffer_move_to_active(&eb->objects, ring);
1079 i915_gem_execbuffer_retire_commands(dev, file, ring);
1084 mutex_unlock(&dev->struct_mutex);
1087 drm_free(cliprects, M_DRM);
1092 * Legacy execbuffer just creates an exec2 list from the original exec object
1093 * list array and passes it to the real function.
1096 i915_gem_execbuffer(struct drm_device *dev, void *data,
1097 struct drm_file *file)
1099 struct drm_i915_gem_execbuffer *args = data;
1100 struct drm_i915_gem_execbuffer2 exec2;
1101 struct drm_i915_gem_exec_object *exec_list = NULL;
1102 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1105 if (args->buffer_count < 1) {
1106 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1110 /* Copy in the exec list from userland */
1111 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1112 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1113 if (exec_list == NULL || exec2_list == NULL) {
1114 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1115 args->buffer_count);
1116 drm_free_large(exec_list);
1117 drm_free_large(exec2_list);
1120 ret = copy_from_user(exec_list,
1121 to_user_ptr(args->buffers_ptr),
1122 sizeof(*exec_list) * args->buffer_count);
1124 DRM_DEBUG("copy %d exec entries failed %d\n",
1125 args->buffer_count, ret);
1126 drm_free_large(exec_list);
1127 drm_free_large(exec2_list);
1131 for (i = 0; i < args->buffer_count; i++) {
1132 exec2_list[i].handle = exec_list[i].handle;
1133 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1134 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1135 exec2_list[i].alignment = exec_list[i].alignment;
1136 exec2_list[i].offset = exec_list[i].offset;
1137 if (INTEL_INFO(dev)->gen < 4)
1138 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1140 exec2_list[i].flags = 0;
1143 exec2.buffers_ptr = args->buffers_ptr;
1144 exec2.buffer_count = args->buffer_count;
1145 exec2.batch_start_offset = args->batch_start_offset;
1146 exec2.batch_len = args->batch_len;
1147 exec2.DR1 = args->DR1;
1148 exec2.DR4 = args->DR4;
1149 exec2.num_cliprects = args->num_cliprects;
1150 exec2.cliprects_ptr = args->cliprects_ptr;
1151 exec2.flags = I915_EXEC_RENDER;
1152 i915_execbuffer2_set_context_id(exec2, 0);
1154 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1156 /* Copy the new buffer offsets back to the user's exec list. */
1157 for (i = 0; i < args->buffer_count; i++)
1158 exec_list[i].offset = exec2_list[i].offset;
1159 /* ... and back out to userspace */
1160 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1162 sizeof(*exec_list) * args->buffer_count);
1165 DRM_DEBUG("failed to copy %d exec entries "
1166 "back to user (%d)\n",
1167 args->buffer_count, ret);
1171 drm_free_large(exec_list);
1172 drm_free_large(exec2_list);
1177 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1178 struct drm_file *file)
1180 struct drm_i915_gem_execbuffer2 *args = data;
1181 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1184 if (args->buffer_count < 1 ||
1185 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1186 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1190 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1192 if (exec2_list == NULL)
1193 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1194 args->buffer_count);
1195 if (exec2_list == NULL) {
1196 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1197 args->buffer_count);
1200 ret = copy_from_user(exec2_list,
1201 to_user_ptr(args->buffers_ptr),
1202 sizeof(*exec2_list) * args->buffer_count);
1204 DRM_DEBUG("copy %d exec entries failed %d\n",
1205 args->buffer_count, ret);
1206 drm_free_large(exec2_list);
1210 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1212 /* Copy the new buffer offsets back to the user's exec list. */
1213 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1215 sizeof(*exec2_list) * args->buffer_count);
1218 DRM_DEBUG("failed to copy %d exec entries "
1219 "back to user (%d)\n",
1220 args->buffer_count, ret);
1224 drm_free_large(exec2_list);