2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_i2c.c 254885 2013-08-25 19:37:15Z dumbbell $
30 #include <drm/drm_edid.h>
31 #include <uapi_drm/radeon_drm.h>
32 #include <bus/iicbus/iic.h>
33 #include <bus/iicbus/iiconf.h>
34 #include <bus/iicbus/iicbus.h>
35 #include <sys/mplock2.h>
38 #include "iicbus_if.h"
45 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
50 struct iic_msg msgs[] = {
52 .slave = DDC_ADDR << 1,
58 .slave = DDC_ADDR << 1,
65 /* on hw with routers, select right port */
66 if (radeon_connector->router.ddc_valid)
67 radeon_router_select_ddc_port(radeon_connector);
70 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
71 ret = iicbus_transfer(dig->dp_i2c_bus->adapter, msgs, 2);
73 ret = iicbus_transfer(radeon_connector->ddc_bus->adapter, msgs, 2);
77 /* Couldn't find an accessible DDC on this connector */
79 /* Probe also for valid EDID header
80 * EDID header starts with:
81 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
82 * Only the first 6 bytes must be valid as
83 * drm_edid_block_valid() can fix the last 2 bytes */
84 if (drm_edid_header_is_valid(buf) < 6) {
85 /* Couldn't find an accessible EDID on this
94 static int radeon_iicbb_pre_xfer(device_t dev)
96 struct radeon_i2c_chan *i2c = device_get_softc(dev);
97 struct radeon_device *rdev = i2c->dev->dev_private;
98 struct radeon_i2c_bus_rec *rec = &i2c->rec;
101 /* RV410 appears to have a bug where the hw i2c in reset
102 * holds the i2c port in a bad state - switch hw i2c away before
103 * doing DDC - do this for all r200s/r300s/r400s for safety sake
105 if (rec->hw_capable) {
106 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
109 if (rdev->family >= CHIP_RV350)
110 reg = RADEON_GPIO_MONID;
111 else if ((rdev->family == CHIP_R300) ||
112 (rdev->family == CHIP_R350))
113 reg = RADEON_GPIO_DVI_DDC;
115 reg = RADEON_GPIO_CRT2_DDC;
117 lockmgr(&rdev->dc_hw_i2c_mutex, LK_EXCLUSIVE);
118 if (rec->a_clk_reg == reg) {
119 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
120 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
122 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
123 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
125 lockmgr(&rdev->dc_hw_i2c_mutex, LK_RELEASE);
129 /* switch the pads to ddc mode */
130 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
131 temp = RREG32(rec->mask_clk_reg);
133 WREG32(rec->mask_clk_reg, temp);
136 /* clear the output pin values */
137 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
138 WREG32(rec->a_clk_reg, temp);
140 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
141 WREG32(rec->a_data_reg, temp);
143 /* set the pins to input */
144 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
145 WREG32(rec->en_clk_reg, temp);
147 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
148 WREG32(rec->en_data_reg, temp);
150 /* mask the gpio pins for software use */
151 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
152 WREG32(rec->mask_clk_reg, temp);
153 temp = RREG32(rec->mask_clk_reg);
155 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
156 WREG32(rec->mask_data_reg, temp);
157 temp = RREG32(rec->mask_data_reg);
162 static void radeon_iicbb_post_xfer(device_t dev)
164 struct radeon_i2c_chan *i2c = device_get_softc(dev);
165 struct radeon_device *rdev = i2c->dev->dev_private;
166 struct radeon_i2c_bus_rec *rec = &i2c->rec;
169 /* unmask the gpio pins for software use */
170 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
171 WREG32(rec->mask_clk_reg, temp);
172 temp = RREG32(rec->mask_clk_reg);
174 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
175 WREG32(rec->mask_data_reg, temp);
176 temp = RREG32(rec->mask_data_reg);
179 static int radeon_iicbb_get_clock(device_t dev)
181 struct radeon_i2c_chan *i2c = device_get_softc(dev);
182 struct radeon_device *rdev = i2c->dev->dev_private;
183 struct radeon_i2c_bus_rec *rec = &i2c->rec;
186 /* read the value off the pin */
187 val = RREG32(rec->y_clk_reg);
188 val &= rec->y_clk_mask;
194 static int radeon_iicbb_get_data(device_t dev)
196 struct radeon_i2c_chan *i2c = device_get_softc(dev);
197 struct radeon_device *rdev = i2c->dev->dev_private;
198 struct radeon_i2c_bus_rec *rec = &i2c->rec;
201 /* read the value off the pin */
202 val = RREG32(rec->y_data_reg);
203 val &= rec->y_data_mask;
208 static void radeon_iicbb_set_clock(device_t dev, int clock)
210 struct radeon_i2c_chan *i2c = device_get_softc(dev);
211 struct radeon_device *rdev = i2c->dev->dev_private;
212 struct radeon_i2c_bus_rec *rec = &i2c->rec;
215 /* set pin direction */
216 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
217 val |= clock ? 0 : rec->en_clk_mask;
218 WREG32(rec->en_clk_reg, val);
221 static void radeon_iicbb_set_data(device_t dev, int data)
223 struct radeon_i2c_chan *i2c = device_get_softc(dev);
224 struct radeon_device *rdev = i2c->dev->dev_private;
225 struct radeon_i2c_bus_rec *rec = &i2c->rec;
228 /* set pin direction */
229 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
230 val |= data ? 0 : rec->en_data_mask;
231 WREG32(rec->en_data_reg, val);
235 radeon_iicbb_probe(device_t dev)
238 return (BUS_PROBE_DEFAULT);
242 radeon_iicbb_attach(device_t dev)
244 struct radeon_i2c_chan *i2c;
247 i2c = device_get_softc(dev);
248 device_set_desc(dev, i2c->name);
250 /* add generic bit-banging code */
251 iic_dev = device_add_child(dev, "iicbb", -1);
254 device_quiet(iic_dev);
256 /* attach and probe added child */
257 bus_generic_attach(dev);
263 radeon_iicbb_detach(device_t dev)
266 /* detach bit-banding code. */
267 bus_generic_detach(dev);
269 /* delete bit-banding code. */
270 device_delete_children(dev);
275 radeon_iicbb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
278 /* Not sure what to do here. */
282 static device_method_t radeon_iicbb_methods[] = {
283 DEVMETHOD(device_probe, radeon_iicbb_probe),
284 DEVMETHOD(device_attach, radeon_iicbb_attach),
285 DEVMETHOD(device_detach, radeon_iicbb_detach),
287 DEVMETHOD(bus_add_child, bus_generic_add_child),
288 DEVMETHOD(bus_print_child, bus_generic_print_child),
290 DEVMETHOD(iicbb_reset, radeon_iicbb_reset),
291 DEVMETHOD(iicbb_pre_xfer, radeon_iicbb_pre_xfer),
292 DEVMETHOD(iicbb_post_xfer, radeon_iicbb_post_xfer),
293 DEVMETHOD(iicbb_setsda, radeon_iicbb_set_data),
294 DEVMETHOD(iicbb_setscl, radeon_iicbb_set_clock),
295 DEVMETHOD(iicbb_getsda, radeon_iicbb_get_data),
296 DEVMETHOD(iicbb_getscl, radeon_iicbb_get_clock),
300 static driver_t radeon_iicbb_driver = {
302 radeon_iicbb_methods,
303 0 /* softc will be allocated by parent */
305 static devclass_t radeon_iicbb_devclass;
306 DRIVER_MODULE_ORDERED(radeon_iicbb, drm, radeon_iicbb_driver,
307 radeon_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
308 DRIVER_MODULE(iicbb, radeon_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL);
312 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
314 u32 sclk = rdev->pm.current_sclk;
320 switch (rdev->family) {
334 nm = (sclk * 10) / (i2c_clock * 4);
335 for (loop = 1; loop < 255; loop++) {
336 if ((nm / loop) < loop)
341 prescale = m | (n << 8);
349 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
363 if (rdev->family == CHIP_R520)
364 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
366 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
392 DRM_ERROR("i2c: unhandled radeon chip\n");
399 /* hw i2c engine for r1xx-4xx hardware
400 * hw can buffer up to 15 bytes
402 static int r100_hw_i2c_xfer(struct radeon_i2c_chan *i2c,
403 struct iic_msg *msgs, int num)
405 struct radeon_device *rdev = i2c->dev->dev_private;
406 struct radeon_i2c_bus_rec *rec = &i2c->rec;
408 int i, j, k, ret = 0;
410 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
413 lockmgr(&rdev->dc_hw_i2c_mutex, LK_EXCLUSIVE);
414 /* take the pm lock since we need a constant sclk */
415 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
417 prescale = radeon_get_i2c_prescale(rdev);
419 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
420 RADEON_I2C_DRIVE_EN |
425 if (rdev->is_atom_bios) {
426 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
427 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
431 i2c_cntl_0 = RADEON_I2C_CNTL_0;
432 i2c_cntl_1 = RADEON_I2C_CNTL_1;
433 i2c_data = RADEON_I2C_DATA;
435 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
436 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
437 i2c_data = RADEON_DVI_I2C_DATA;
439 switch (rdev->family) {
446 switch (rec->mask_clk_reg) {
447 case RADEON_GPIO_DVI_DDC:
448 /* no gpio select bit */
451 DRM_ERROR("gpio not supported with hw i2c\n");
457 /* only bit 4 on r200 */
458 switch (rec->mask_clk_reg) {
459 case RADEON_GPIO_DVI_DDC:
460 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
462 case RADEON_GPIO_MONID:
463 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
466 DRM_ERROR("gpio not supported with hw i2c\n");
474 switch (rec->mask_clk_reg) {
475 case RADEON_GPIO_DVI_DDC:
476 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
478 case RADEON_GPIO_VGA_DDC:
479 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
481 case RADEON_GPIO_CRT2_DDC:
482 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
485 DRM_ERROR("gpio not supported with hw i2c\n");
492 /* only bit 4 on r300/r350 */
493 switch (rec->mask_clk_reg) {
494 case RADEON_GPIO_VGA_DDC:
495 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
497 case RADEON_GPIO_DVI_DDC:
498 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
501 DRM_ERROR("gpio not supported with hw i2c\n");
514 switch (rec->mask_clk_reg) {
515 case RADEON_GPIO_VGA_DDC:
516 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
518 case RADEON_GPIO_DVI_DDC:
519 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
521 case RADEON_GPIO_MONID:
522 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
525 DRM_ERROR("gpio not supported with hw i2c\n");
531 DRM_ERROR("unsupported asic\n");
538 /* check for bus probe */
540 if ((num == 1) && (p->len == 0)) {
541 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
544 RADEON_I2C_SOFT_RST));
545 WREG32(i2c_data, (p->slave << 1) & 0xff);
547 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
548 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
550 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
551 WREG32(i2c_cntl_0, reg);
552 for (k = 0; k < 32; k++) {
554 tmp = RREG32(i2c_cntl_0);
555 if (tmp & RADEON_I2C_GO)
557 tmp = RREG32(i2c_cntl_0);
558 if (tmp & RADEON_I2C_DONE)
561 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
562 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
570 for (i = 0; i < num; i++) {
572 for (j = 0; j < p->len; j++) {
573 if (p->flags & IIC_M_RD) {
574 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
577 RADEON_I2C_SOFT_RST));
578 WREG32(i2c_data, ((p->slave << 1) & 0xff) | 0x1);
579 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
580 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
582 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
583 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
584 for (k = 0; k < 32; k++) {
586 tmp = RREG32(i2c_cntl_0);
587 if (tmp & RADEON_I2C_GO)
589 tmp = RREG32(i2c_cntl_0);
590 if (tmp & RADEON_I2C_DONE)
593 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
594 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
599 p->buf[j] = RREG32(i2c_data) & 0xff;
601 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
604 RADEON_I2C_SOFT_RST));
605 WREG32(i2c_data, (p->slave << 1) & 0xff);
606 WREG32(i2c_data, p->buf[j]);
607 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
608 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
610 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
611 WREG32(i2c_cntl_0, reg);
612 for (k = 0; k < 32; k++) {
614 tmp = RREG32(i2c_cntl_0);
615 if (tmp & RADEON_I2C_GO)
617 tmp = RREG32(i2c_cntl_0);
618 if (tmp & RADEON_I2C_DONE)
621 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
622 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
632 WREG32(i2c_cntl_0, 0);
633 WREG32(i2c_cntl_1, 0);
634 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
637 RADEON_I2C_SOFT_RST));
639 if (rdev->is_atom_bios) {
640 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
641 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
642 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
645 lockmgr(&rdev->pm.mutex, LK_RELEASE);
646 lockmgr(&rdev->dc_hw_i2c_mutex, LK_RELEASE);
651 /* hw i2c engine for r5xx hardware
652 * hw can buffer up to 15 bytes
654 static int r500_hw_i2c_xfer(struct radeon_i2c_chan *i2c,
655 struct iic_msg *msgs, int num)
657 struct radeon_device *rdev = i2c->dev->dev_private;
658 struct radeon_i2c_bus_rec *rec = &i2c->rec;
660 int i, j, remaining, current_count, buffer_offset, ret = 0;
665 lockmgr(&rdev->dc_hw_i2c_mutex, LK_EXCLUSIVE);
666 /* take the pm lock since we need a constant sclk */
667 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
669 prescale = radeon_get_i2c_prescale(rdev);
671 /* clear gpio mask bits */
672 tmp = RREG32(rec->mask_clk_reg);
673 tmp &= ~rec->mask_clk_mask;
674 WREG32(rec->mask_clk_reg, tmp);
675 tmp = RREG32(rec->mask_clk_reg);
677 tmp = RREG32(rec->mask_data_reg);
678 tmp &= ~rec->mask_data_mask;
679 WREG32(rec->mask_data_reg, tmp);
680 tmp = RREG32(rec->mask_data_reg);
682 /* clear pin values */
683 tmp = RREG32(rec->a_clk_reg);
684 tmp &= ~rec->a_clk_mask;
685 WREG32(rec->a_clk_reg, tmp);
686 tmp = RREG32(rec->a_clk_reg);
688 tmp = RREG32(rec->a_data_reg);
689 tmp &= ~rec->a_data_mask;
690 WREG32(rec->a_data_reg, tmp);
691 tmp = RREG32(rec->a_data_reg);
693 /* set the pins to input */
694 tmp = RREG32(rec->en_clk_reg);
695 tmp &= ~rec->en_clk_mask;
696 WREG32(rec->en_clk_reg, tmp);
697 tmp = RREG32(rec->en_clk_reg);
699 tmp = RREG32(rec->en_data_reg);
700 tmp &= ~rec->en_data_mask;
701 WREG32(rec->en_data_reg, tmp);
702 tmp = RREG32(rec->en_data_reg);
705 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
706 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
707 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
708 saved2 = RREG32(0x494);
709 WREG32(0x494, saved2 | 0x1);
711 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
712 for (i = 0; i < 50; i++) {
714 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
718 DRM_ERROR("failed to get i2c bus\n");
723 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
724 switch (rec->mask_clk_reg) {
725 case AVIVO_DC_GPIO_DDC1_MASK:
726 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
728 case AVIVO_DC_GPIO_DDC2_MASK:
729 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
731 case AVIVO_DC_GPIO_DDC3_MASK:
732 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
735 DRM_ERROR("gpio not supported with hw i2c\n");
740 /* check for bus probe */
742 if ((num == 1) && (p->len == 0)) {
743 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
746 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
748 WREG32(AVIVO_DC_I2C_RESET, 0);
750 WREG32(AVIVO_DC_I2C_DATA, (p->slave << 1) & 0xff);
751 WREG32(AVIVO_DC_I2C_DATA, 0);
753 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
754 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
755 AVIVO_DC_I2C_DATA_COUNT(1) |
757 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
758 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
759 for (j = 0; j < 200; j++) {
761 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
762 if (tmp & AVIVO_DC_I2C_GO)
764 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
765 if (tmp & AVIVO_DC_I2C_DONE)
768 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
769 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
777 for (i = 0; i < num; i++) {
781 if (p->flags & IIC_M_RD) {
786 current_count = remaining;
787 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
790 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
792 WREG32(AVIVO_DC_I2C_RESET, 0);
794 WREG32(AVIVO_DC_I2C_DATA, ((p->slave << 1) & 0xff) | 0x1);
795 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
796 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
797 AVIVO_DC_I2C_DATA_COUNT(current_count) |
799 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
800 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
801 for (j = 0; j < 200; j++) {
803 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
804 if (tmp & AVIVO_DC_I2C_GO)
806 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
807 if (tmp & AVIVO_DC_I2C_DONE)
810 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
811 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
816 for (j = 0; j < current_count; j++)
817 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
818 remaining -= current_count;
819 buffer_offset += current_count;
826 current_count = remaining;
827 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
830 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
832 WREG32(AVIVO_DC_I2C_RESET, 0);
834 WREG32(AVIVO_DC_I2C_DATA, (p->slave << 1) & 0xff);
835 for (j = 0; j < current_count; j++)
836 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
838 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
839 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
840 AVIVO_DC_I2C_DATA_COUNT(current_count) |
842 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
843 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
844 for (j = 0; j < 200; j++) {
846 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
847 if (tmp & AVIVO_DC_I2C_GO)
849 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
850 if (tmp & AVIVO_DC_I2C_DONE)
853 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
854 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
859 remaining -= current_count;
860 buffer_offset += current_count;
866 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
869 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
871 WREG32(AVIVO_DC_I2C_RESET, 0);
873 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
874 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
875 WREG32(0x494, saved2);
876 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
877 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
878 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
880 lockmgr(&rdev->pm.mutex, LK_RELEASE);
881 lockmgr(&rdev->dc_hw_i2c_mutex, LK_RELEASE);
886 static int radeon_hw_i2c_xfer(device_t dev,
887 struct iic_msg *msgs, uint32_t num)
889 struct radeon_i2c_chan *i2c = device_get_softc(dev);
890 struct radeon_device *rdev = i2c->dev->dev_private;
891 struct radeon_i2c_bus_rec *rec = &i2c->rec;
894 switch (rdev->family) {
913 ret = r100_hw_i2c_xfer(i2c, msgs, num);
918 /* XXX fill in hw i2c implementation */
927 ret = r100_hw_i2c_xfer(i2c, msgs, num);
929 ret = r500_hw_i2c_xfer(i2c, msgs, num);
935 /* XXX fill in hw i2c implementation */
945 /* XXX fill in hw i2c implementation */
952 /* XXX fill in hw i2c implementation */
955 DRM_ERROR("i2c: unhandled radeon chip\n");
964 radeon_hw_i2c_probe(device_t dev)
967 return (BUS_PROBE_SPECIFIC);
971 radeon_hw_i2c_attach(device_t dev)
973 struct radeon_i2c_chan *i2c;
976 i2c = device_get_softc(dev);
977 device_set_desc(dev, i2c->name);
979 /* add generic bit-banging code */
980 iic_dev = device_add_child(dev, "iicbus", -1);
983 device_quiet(iic_dev);
985 /* attach and probe added child */
986 bus_generic_attach(dev);
992 radeon_hw_i2c_detach(device_t dev)
995 /* detach bit-banding code. */
996 bus_generic_detach(dev);
998 /* delete bit-banding code. */
999 device_delete_children(dev);
1004 radeon_hw_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
1007 /* Not sure what to do here. */
1012 static device_method_t radeon_hw_i2c_methods[] = {
1013 DEVMETHOD(device_probe, radeon_hw_i2c_probe),
1014 DEVMETHOD(device_attach, radeon_hw_i2c_attach),
1015 DEVMETHOD(device_detach, radeon_hw_i2c_detach),
1016 DEVMETHOD(iicbus_reset, radeon_hw_i2c_reset),
1017 DEVMETHOD(iicbus_transfer, radeon_hw_i2c_xfer),
1021 static driver_t radeon_hw_i2c_driver = {
1023 radeon_hw_i2c_methods,
1024 0 /* softc will be allocated by parent */
1027 static devclass_t radeon_hw_i2c_devclass;
1028 DRIVER_MODULE_ORDERED(radeon_hw_i2c, drm, radeon_hw_i2c_driver,
1029 radeon_hw_i2c_devclass, 0, 0, SI_ORDER_FIRST);
1030 DRIVER_MODULE(iicbus, radeon_hw_i2c, iicbus_driver, iicbus_devclass, NULL, NULL);
1032 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
1033 struct radeon_i2c_bus_rec *rec,
1036 struct radeon_device *rdev = dev->dev_private;
1037 struct radeon_i2c_chan *i2c;
1038 device_t iicbus_dev;
1041 /* don't add the mm_i2c bus unless hw_i2c is enabled */
1042 if (rec->mm_i2c && (radeon_hw_i2c == 0))
1045 i2c = kmalloc(sizeof(struct radeon_i2c_chan), DRM_MEM_DRIVER,
1051 * Grab Giant before messing with newbus devices, just in case
1052 * we do not hold it already.
1061 ((rdev->family <= CHIP_RS480) ||
1062 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
1063 /* set the radeon hw i2c adapter */
1064 ksnprintf(i2c->name, sizeof(i2c->name),
1065 "Radeon i2c hw bus %s", name);
1066 iicbus_dev = device_add_child(dev->dev, "radeon_hw_i2c", -1);
1067 if (iicbus_dev == NULL) {
1068 DRM_ERROR("Failed to create bridge for hw i2c %s\n",
1072 device_quiet(iicbus_dev);
1073 device_set_softc(iicbus_dev, i2c);
1075 ret = device_probe_and_attach(iicbus_dev);
1077 DRM_ERROR("Attach failed for bridge for hw i2c %s\n",
1079 device_delete_child(dev->dev, iicbus_dev);
1083 i2c->adapter = device_find_child(iicbus_dev, "iicbus", -1);
1084 if (i2c->adapter == NULL) {
1085 DRM_ERROR("hw i2c bridge doesn't have iicbus child\n");
1086 device_delete_child(dev->dev, iicbus_dev);
1089 } else if (rec->hw_capable &&
1091 ASIC_IS_DCE3(rdev)) {
1092 /* hw i2c using atom */
1093 ksnprintf(i2c->name, sizeof(i2c->name),
1094 "Radeon i2c hw bus %s", name);
1095 iicbus_dev = device_add_child(dev->dev, "radeon_atom_hw_i2c", -1);
1096 if (iicbus_dev == NULL) {
1097 DRM_ERROR("Failed to create bridge for hw i2c %s\n",
1101 device_quiet(iicbus_dev);
1102 device_set_softc(iicbus_dev, i2c);
1104 ret = device_probe_and_attach(iicbus_dev);
1106 DRM_ERROR("Attach failed for bridge for hw i2c %s\n",
1108 device_delete_child(dev->dev, iicbus_dev);
1112 i2c->adapter = device_find_child(iicbus_dev, "iicbus", -1);
1113 if (i2c->adapter == NULL) {
1114 DRM_ERROR("hw i2c bridge doesn't have iicbus child\n");
1115 device_delete_child(dev->dev, iicbus_dev);
1121 /* set the radeon bit adapter */
1122 ksnprintf(i2c->name, sizeof(i2c->name),
1123 "Radeon i2c bit bus %s", name);
1124 iicbus_dev = device_add_child(dev->dev, "radeon_iicbb", -1);
1125 if (iicbus_dev == NULL) {
1126 DRM_ERROR("Failed to create bridge for bb i2c %s\n",
1130 device_quiet(iicbus_dev);
1131 device_set_softc(iicbus_dev, i2c);
1133 ret = device_probe_and_attach(iicbus_dev);
1135 DRM_ERROR("Attach failed for bridge for bb i2c %s\n",
1137 device_delete_child(dev->dev, iicbus_dev);
1141 iicbb_dev = device_find_child(iicbus_dev, "iicbb", -1);
1142 if (iicbb_dev == NULL) {
1143 DRM_ERROR("bb i2c bridge doesn't have iicbb child\n");
1144 device_delete_child(dev->dev, iicbus_dev);
1148 i2c->adapter = device_find_child(iicbb_dev, "iicbus", -1);
1149 if (i2c->adapter == NULL) {
1151 "bbbus bridge doesn't have iicbus grandchild\n");
1152 device_delete_child(dev->dev, iicbus_dev);
1157 i2c->iic_bus = iicbus_dev;
1164 drm_free(i2c, DRM_MEM_DRIVER);
1169 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
1170 struct radeon_i2c_bus_rec *rec,
1173 struct radeon_i2c_chan *i2c;
1176 i2c = kmalloc(sizeof(struct radeon_i2c_chan), DRM_MEM_DRIVER,
1183 ksnprintf(i2c->name, sizeof(i2c->name), "Radeon aux bus %s", name);
1184 ret = iic_dp_aux_add_bus(dev->dev, i2c->name,
1185 radeon_dp_i2c_aux_ch, i2c, &i2c->iic_bus,
1188 DRM_INFO("Failed to register i2c %s\n", name);
1194 drm_free(i2c, DRM_MEM_DRIVER);
1199 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
1203 if (i2c->iic_bus != NULL) {
1207 ret = device_delete_child(i2c->dev->dev, i2c->iic_bus);
1209 KASSERT(ret == 0, ("unable to detach iic bus %s: %d",
1212 drm_free(i2c, DRM_MEM_DRIVER);
1215 /* Add the default buses */
1216 void radeon_i2c_init(struct radeon_device *rdev)
1218 if (rdev->is_atom_bios)
1219 radeon_atombios_i2c_init(rdev);
1221 radeon_combios_i2c_init(rdev);
1224 /* remove all the buses */
1225 void radeon_i2c_fini(struct radeon_device *rdev)
1229 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1230 if (rdev->i2c_bus[i]) {
1231 radeon_i2c_destroy(rdev->i2c_bus[i]);
1232 rdev->i2c_bus[i] = NULL;
1237 /* Add additional buses */
1238 void radeon_i2c_add(struct radeon_device *rdev,
1239 struct radeon_i2c_bus_rec *rec,
1242 struct drm_device *dev = rdev->ddev;
1245 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1246 if (!rdev->i2c_bus[i]) {
1247 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1253 /* looks up bus based on id */
1254 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1255 struct radeon_i2c_bus_rec *i2c_bus)
1259 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1260 if (rdev->i2c_bus[i] &&
1261 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1262 return rdev->i2c_bus[i];
1268 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1273 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1280 struct iic_msg msgs[] = {
1282 .slave = slave_addr << 1,
1288 .slave = slave_addr << 1,
1298 if (iicbus_transfer(i2c_bus->adapter, msgs, 2) == 0) {
1300 DRM_DEBUG("val = 0x%02x\n", *val);
1302 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1307 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1313 struct iic_msg msg = {
1314 .slave = slave_addr << 1,
1323 if (iicbus_transfer(i2c_bus->adapter, &msg, 1) != 0)
1324 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1328 /* ddc router switching */
1329 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1333 if (!radeon_connector->router.ddc_valid)
1336 if (!radeon_connector->router_bus)
1339 radeon_i2c_get_byte(radeon_connector->router_bus,
1340 radeon_connector->router.i2c_addr,
1342 val &= ~radeon_connector->router.ddc_mux_control_pin;
1343 radeon_i2c_put_byte(radeon_connector->router_bus,
1344 radeon_connector->router.i2c_addr,
1346 radeon_i2c_get_byte(radeon_connector->router_bus,
1347 radeon_connector->router.i2c_addr,
1349 val &= ~radeon_connector->router.ddc_mux_control_pin;
1350 val |= radeon_connector->router.ddc_mux_state;
1351 radeon_i2c_put_byte(radeon_connector->router_bus,
1352 radeon_connector->router.i2c_addr,
1356 /* clock/data router switching */
1357 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1361 if (!radeon_connector->router.cd_valid)
1364 if (!radeon_connector->router_bus)
1367 radeon_i2c_get_byte(radeon_connector->router_bus,
1368 radeon_connector->router.i2c_addr,
1370 val &= ~radeon_connector->router.cd_mux_control_pin;
1371 radeon_i2c_put_byte(radeon_connector->router_bus,
1372 radeon_connector->router.i2c_addr,
1374 radeon_i2c_get_byte(radeon_connector->router_bus,
1375 radeon_connector->router.i2c_addr,
1377 val &= ~radeon_connector->router.cd_mux_control_pin;
1378 val |= radeon_connector->router.cd_mux_state;
1379 radeon_i2c_put_byte(radeon_connector->router_bus,
1380 radeon_connector->router.i2c_addr,