sys/dev/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27 #include <drm/drmP.h>
  28 #include <uapi_drm/radeon_drm.h>
  29 #include "radeon.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include <drm/drm_dp_helper.h>
  34
  35 /* move these to drm_dp_helper.c/h */
  36 #define DP_LINK_CONFIGURATION_SIZE 9
  37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  38
  39 static char *voltage_names[] = {
  40         "0.4V", "0.6V", "0.8V", "1.2V"
  41 };
  42 static char *pre_emph_names[] = {
  43         "0dB", "3.5dB", "6dB", "9.5dB"
  44 };
  45
  46 /***** radeon AUX functions *****/
  47
  48 /* Atom needs data in little endian format
  49  * so swap as appropriate when copying data to
  50  * or from atom. Note that atom operates on
  51  * dw units.
  52  */
  53 static void radeon_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
  54 {
  55 #ifdef __BIG_ENDIAN
  56         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
  57         u32 *dst32, *src32;
  58         int i;
  59
  60         memcpy(src_tmp, src, num_bytes);
  61         src32 = (u32 *)src_tmp;
  62         dst32 = (u32 *)dst_tmp;
  63         if (to_le) {
  64                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  65                         dst32[i] = cpu_to_le32(src32[i]);
  66                 memcpy(dst, dst_tmp, num_bytes);
  67         } else {
  68                 u8 dws = num_bytes & ~3;
  69                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  70                         dst32[i] = le32_to_cpu(src32[i]);
  71                 memcpy(dst, dst_tmp, dws);
  72                 if (num_bytes % 4) {
  73                         for (i = 0; i < (num_bytes % 4); i++)
  74                                 dst[dws+i] = dst_tmp[dws+i];
  75                 }
  76         }
  77 #else
  78         memcpy(dst, src, num_bytes);
  79 #endif
  80 }
  81
  82 union aux_channel_transaction {
  83         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  84         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  85 };
  86
  87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  88                                  u8 *send, int send_bytes,
  89                                  u8 *recv, int recv_size,
  90                                  u8 delay, u8 *ack)
  91 {
  92         struct drm_device *dev = chan->dev;
  93         struct radeon_device *rdev = dev->dev_private;
  94         union aux_channel_transaction args;
  95         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  96         unsigned char *base;
  97         int recv_bytes;
  98
  99         memset(&args, 0, sizeof(args));
 100
 101         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
 102
 103         radeon_copy_swap(base, send, send_bytes, true);
 104
 105         args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
 106         args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
 107         args.v1.ucDataOutLen = 0;
 108         args.v1.ucChannelID = chan->rec.i2c_id;
 109         args.v1.ucDelay = delay / 10;
 110         if (ASIC_IS_DCE4(rdev))
 111                 args.v2.ucHPD_ID = chan->rec.hpd;
 112
 113         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114
 115         *ack = args.v1.ucReplyStatus;
 116
 117         /* timeout */
 118         if (args.v1.ucReplyStatus == 1) {
 119                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 120                 return -ETIMEDOUT;
 121         }
 122
 123         /* flags not zero */
 124         if (args.v1.ucReplyStatus == 2) {
 125                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 126                 return -EBUSY;
 127         }
 128
 129         /* error */
 130         if (args.v1.ucReplyStatus == 3) {
 131                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 132                 return -EIO;
 133         }
 134
 135         recv_bytes = args.v1.ucDataOutLen;
 136         if (recv_bytes > recv_size)
 137                 recv_bytes = recv_size;
 138
 139         if (recv && recv_size)
 140                 radeon_copy_swap(recv, base + 16, recv_bytes, false);
 141
 142         return recv_bytes;
 143 }
 144
 145 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
 146                                       u16 address, u8 *send, u8 send_bytes, u8 delay)
 147 {
 148         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 149         int ret;
 150         u8 msg[20];
 151         int msg_bytes = send_bytes + 4;
 152         u8 ack;
 153         unsigned retry;
 154
 155         if (send_bytes > 16)
 156                 return -1;
 157
 158         msg[0] = address;
 159         msg[1] = address >> 8;
 160         msg[2] = DP_AUX_NATIVE_WRITE << 4;
 161         msg[3] = (msg_bytes << 4) | (send_bytes - 1);
 162         memcpy(&msg[4], send, send_bytes);
 163
 164         for (retry = 0; retry < 4; retry++) {
 165                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 166                                             msg, msg_bytes, NULL, 0, delay, &ack);
 167                 if (ret == -EBUSY)
 168                         continue;
 169                 else if (ret < 0)
 170                         return ret;
 171                 ack >>= 4;
 172                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 173                         return send_bytes;
 174                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 175                         udelay(400);
 176                 else
 177                         return -EIO;
 178         }
 179
 180         return -EIO;
 181 }
 182
 183 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
 184                                      u16 address, u8 *recv, int recv_bytes, u8 delay)
 185 {
 186         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 187         u8 msg[4];
 188         int msg_bytes = 4;
 189         u8 ack;
 190         int ret;
 191         unsigned retry;
 192
 193         msg[0] = address;
 194         msg[1] = address >> 8;
 195         msg[2] = DP_AUX_NATIVE_READ << 4;
 196         msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
 197
 198         for (retry = 0; retry < 4; retry++) {
 199                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 200                                             msg, msg_bytes, recv, recv_bytes, delay, &ack);
 201                 if (ret == -EBUSY)
 202                         continue;
 203                 else if (ret < 0)
 204                         return ret;
 205                 ack >>= 4;
 206                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 207                         return ret;
 208                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 209                         udelay(400);
 210                 else if (ret == 0)
 211                         return -EPROTO;
 212                 else
 213                         return -EIO;
 214         }
 215
 216         return -EIO;
 217 }
 218
 219 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
 220                                  u16 reg, u8 val)
 221 {
 222         radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
 223 }
 224
 225 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
 226                                u16 reg)
 227 {
 228         u8 val = 0;
 229
 230         radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
 231
 232         return val;
 233 }
 234
 235 int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte)
 236 {
 237         struct i2c_algo_dp_aux_data *algo_data = device_get_softc(dev);
 238         struct radeon_i2c_chan *auxch = algo_data->priv;
 239         u16 address = algo_data->address;
 240         u8 msg[5];
 241         u8 reply[2];
 242         unsigned retry;
 243         int msg_bytes;
 244         int reply_bytes = 1;
 245         int ret;
 246         u8 ack;
 247
 248         /* Set up the command byte */
 249         if (mode & MODE_I2C_READ)
 250                 msg[2] = DP_AUX_I2C_READ << 4;
 251         else
 252                 msg[2] = DP_AUX_I2C_WRITE << 4;
 253
 254         if (!(mode & MODE_I2C_STOP))
 255                 msg[2] |= DP_AUX_I2C_MOT << 4;
 256
 257         msg[0] = address;
 258         msg[1] = address >> 8;
 259
 260         switch (mode) {
 261         case MODE_I2C_WRITE:
 262                 msg_bytes = 5;
 263                 msg[3] = msg_bytes << 4;
 264                 msg[4] = write_byte;
 265                 break;
 266         case MODE_I2C_READ:
 267                 msg_bytes = 4;
 268                 msg[3] = msg_bytes << 4;
 269                 break;
 270         default:
 271                 msg_bytes = 4;
 272                 msg[3] = 3 << 4;
 273                 break;
 274         }
 275
 276         for (retry = 0; retry < 4; retry++) {
 277                 ret = radeon_process_aux_ch(auxch,
 278                                             msg, msg_bytes, reply, reply_bytes, 0, &ack);
 279                 if (ret == -EBUSY)
 280                         continue;
 281                 else if (ret < 0) {
 282                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 283                         return ret;
 284                 }
 285
 286                 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
 287                 case DP_AUX_NATIVE_REPLY_ACK:
 288                         /* I2C-over-AUX Reply field is only valid
 289                          * when paired with AUX ACK.
 290                          */
 291                         break;
 292                 case DP_AUX_NATIVE_REPLY_NACK:
 293                         DRM_DEBUG_KMS("aux_ch native nack\n");
 294                         return -EREMOTEIO;
 295                 case DP_AUX_NATIVE_REPLY_DEFER:
 296                         DRM_DEBUG_KMS("aux_ch native defer\n");
 297                         udelay(400);
 298                         continue;
 299                 default:
 300                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
 301                         return -EREMOTEIO;
 302                 }
 303
 304                 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
 305                 case DP_AUX_I2C_REPLY_ACK:
 306                         if (mode == MODE_I2C_READ)
 307                                 *read_byte = reply[0];
 308                         return ret;
 309                 case DP_AUX_I2C_REPLY_NACK:
 310                         DRM_DEBUG_KMS("aux_i2c nack\n");
 311                         return -EREMOTEIO;
 312                 case DP_AUX_I2C_REPLY_DEFER:
 313                         DRM_DEBUG_KMS("aux_i2c defer\n");
 314                         udelay(400);
 315                         break;
 316                 default:
 317                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
 318                         return -EREMOTEIO;
 319                 }
 320         }
 321
 322         DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
 323         return -EREMOTEIO;
 324 }
 325
 326 /***** general DP utility functions *****/
 327
 328 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
 329 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
 330
 331 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 332                                 int lane_count,
 333                                 u8 train_set[4])
 334 {
 335         u8 v = 0;
 336         u8 p = 0;
 337         int lane;
 338
 339         for (lane = 0; lane < lane_count; lane++) {
 340                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 341                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 342
 343                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 344                           lane,
 345                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 346                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 347
 348                 if (this_v > v)
 349                         v = this_v;
 350                 if (this_p > p)
 351                         p = this_p;
 352         }
 353
 354         if (v >= DP_VOLTAGE_MAX)
 355                 v |= DP_TRAIN_MAX_SWING_REACHED;
 356
 357         if (p >= DP_PRE_EMPHASIS_MAX)
 358                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 359
 360         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 361                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 362                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 363
 364         for (lane = 0; lane < 4; lane++)
 365                 train_set[lane] = v | p;
 366 }
 367
 368 /* convert bits per color to bits per pixel */
 369 /* get bpc from the EDID */
 370 static int convert_bpc_to_bpp(int bpc)
 371 {
 372         if (bpc == 0)
 373                 return 24;
 374         else
 375                 return bpc * 3;
 376 }
 377
 378 /* get the max pix clock supported by the link rate and lane num */
 379 static int dp_get_max_dp_pix_clock(int link_rate,
 380                                    int lane_num,
 381                                    int bpp)
 382 {
 383         return (link_rate * lane_num * 8) / bpp;
 384 }
 385
 386 /***** radeon specific DP functions *****/
 387
 388 /* First get the min lane# when low rate is used according to pixel clock
 389  * (prefer low rate), second check max lane# supported by DP panel,
 390  * if the max lane# < low rate lane# then use max lane# instead.
 391  */
 392 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 393                                         u8 dpcd[DP_DPCD_SIZE],
 394                                         int pix_clock)
 395 {
 396         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 397         int max_link_rate = drm_dp_max_link_rate(dpcd);
 398         int max_lane_num = drm_dp_max_lane_count(dpcd);
 399         int lane_num;
 400         int max_dp_pix_clock;
 401
 402         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 403                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 404                 if (pix_clock <= max_dp_pix_clock)
 405                         break;
 406         }
 407
 408         return lane_num;
 409 }
 410
 411 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 412                                        u8 dpcd[DP_DPCD_SIZE],
 413                                        int pix_clock)
 414 {
 415         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 416         int lane_num, max_pix_clock;
 417
 418         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 419             ENCODER_OBJECT_ID_NUTMEG)
 420                 return 270000;
 421
 422         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 423         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 424         if (pix_clock <= max_pix_clock)
 425                 return 162000;
 426         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 427         if (pix_clock <= max_pix_clock)
 428                 return 270000;
 429         if (radeon_connector_is_dp12_capable(connector)) {
 430                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 431                 if (pix_clock <= max_pix_clock)
 432                         return 540000;
 433         }
 434
 435         return drm_dp_max_link_rate(dpcd);
 436 }
 437
 438 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 439                                     int action, int dp_clock,
 440                                     u8 ucconfig, u8 lane_num)
 441 {
 442         DP_ENCODER_SERVICE_PARAMETERS args;
 443         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 444
 445         memset(&args, 0, sizeof(args));
 446         args.ucLinkClock = dp_clock / 10;
 447         args.ucConfig = ucconfig;
 448         args.ucAction = action;
 449         args.ucLaneNum = lane_num;
 450         args.ucStatus = 0;
 451
 452         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 453         return args.ucStatus;
 454 }
 455
 456 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 457 {
 458         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 459         struct drm_device *dev = radeon_connector->base.dev;
 460         struct radeon_device *rdev = dev->dev_private;
 461
 462         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 463                                          dig_connector->dp_i2c_bus->rec.i2c_id, 0);
 464 }
 465
 466 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 467 {
 468         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 469         u8 buf[3];
 470
 471         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 472                 return;
 473
 474         if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
 475                 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n",
 476                               buf[0], buf[1], buf[2]);
 477
 478         if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
 479                 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n",
 480                               buf[0], buf[1], buf[2]);
 481 }
 482
 483 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 484 {
 485         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 486         u8 msg[DP_DPCD_SIZE];
 487         int ret, i;
 488
 489         ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
 490                                         DP_DPCD_SIZE, 0);
 491         if (ret > 0) {
 492                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 493                 DRM_DEBUG_KMS("DPCD: ");
 494                 for (i = 0; i < DP_DPCD_SIZE; i++)
 495                         DRM_DEBUG_KMS("%02x ", msg[i]);
 496                 DRM_DEBUG_KMS("\n");
 497
 498                 radeon_dp_probe_oui(radeon_connector);
 499
 500                 return true;
 501         }
 502         dig_connector->dpcd[0] = 0;
 503         return false;
 504 }
 505
 506 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 507                              struct drm_connector *connector)
 508 {
 509         struct drm_device *dev = encoder->dev;
 510         struct radeon_device *rdev = dev->dev_private;
 511         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 512         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 513         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 514         u8 tmp;
 515
 516         if (!ASIC_IS_DCE4(rdev))
 517                 return panel_mode;
 518
 519         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 520                 /* DP bridge chips */
 521                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
 522                 if (tmp & 1)
 523                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 524                 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 525                          (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 526                         panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 527                 else
 528                         panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 529         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 530                 /* eDP */
 531                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
 532                 if (tmp & 1)
 533                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 534         }
 535
 536         return panel_mode;
 537 }
 538
 539 void radeon_dp_set_link_config(struct drm_connector *connector,
 540                                const struct drm_display_mode *mode)
 541 {
 542         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 543         struct radeon_connector_atom_dig *dig_connector;
 544
 545         if (!radeon_connector->con_priv)
 546                 return;
 547         dig_connector = radeon_connector->con_priv;
 548
 549         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 550             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 551                 dig_connector->dp_clock =
 552                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 553                 dig_connector->dp_lane_count =
 554                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 555         }
 556 }
 557
 558 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 559                                 struct drm_display_mode *mode)
 560 {
 561         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 562         struct radeon_connector_atom_dig *dig_connector;
 563         int dp_clock;
 564
 565         if (!radeon_connector->con_priv)
 566                 return MODE_CLOCK_HIGH;
 567         dig_connector = radeon_connector->con_priv;
 568
 569         dp_clock =
 570                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 571
 572         if ((dp_clock == 540000) &&
 573             (!radeon_connector_is_dp12_capable(connector)))
 574                 return MODE_CLOCK_HIGH;
 575
 576         return MODE_OK;
 577 }
 578
 579 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
 580                                       u8 link_status[DP_LINK_STATUS_SIZE])
 581 {
 582         int ret;
 583         ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
 584                                         link_status, DP_LINK_STATUS_SIZE, 100);
 585         if (ret <= 0) {
 586                 return false;
 587         }
 588
 589         DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
 590         return true;
 591 }
 592
 593 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 594 {
 595         u8 link_status[DP_LINK_STATUS_SIZE];
 596         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 597
 598         if (!radeon_dp_get_link_status(radeon_connector, link_status))
 599                 return false;
 600         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 601                 return false;
 602         return true;
 603 }
 604
 605 struct radeon_dp_link_train_info {
 606         struct radeon_device *rdev;
 607         struct drm_encoder *encoder;
 608         struct drm_connector *connector;
 609         struct radeon_connector *radeon_connector;
 610         int enc_id;
 611         int dp_clock;
 612         int dp_lane_count;
 613         bool tp3_supported;
 614         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 615         u8 train_set[4];
 616         u8 link_status[DP_LINK_STATUS_SIZE];
 617         u8 tries;
 618         bool use_dpencoder;
 619 };
 620
 621 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 622 {
 623         /* set the initial vs/emph on the source */
 624         atombios_dig_transmitter_setup(dp_info->encoder,
 625                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 626                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 627
 628         /* set the vs/emph on the sink */
 629         radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
 630                                    dp_info->train_set, dp_info->dp_lane_count, 0);
 631 }
 632
 633 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 634 {
 635         int rtp = 0;
 636
 637         /* set training pattern on the source */
 638         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 639                 switch (tp) {
 640                 case DP_TRAINING_PATTERN_1:
 641                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 642                         break;
 643                 case DP_TRAINING_PATTERN_2:
 644                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 645                         break;
 646                 case DP_TRAINING_PATTERN_3:
 647                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 648                         break;
 649                 }
 650                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 651         } else {
 652                 switch (tp) {
 653                 case DP_TRAINING_PATTERN_1:
 654                         rtp = 0;
 655                         break;
 656                 case DP_TRAINING_PATTERN_2:
 657                         rtp = 1;
 658                         break;
 659                 }
 660                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 661                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 662         }
 663
 664         /* enable training pattern on the sink */
 665         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
 666 }
 667
 668 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 669 {
 670         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 671         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 672         u8 tmp;
 673
 674         /* power up the sink */
 675         if (dp_info->dpcd[0] >= 0x11)
 676                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 677                                       DP_SET_POWER, DP_SET_POWER_D0);
 678
 679         /* possibly enable downspread on the sink */
 680         if (dp_info->dpcd[3] & 0x1)
 681                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 682                                       DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 683         else
 684                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 685                                       DP_DOWNSPREAD_CTRL, 0);
 686
 687         if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
 688             (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
 689                 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
 690         }
 691
 692         /* set the lane count on the sink */
 693         tmp = dp_info->dp_lane_count;
 694         if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
 695             dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
 696                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 697         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
 698
 699         /* set the link rate on the sink */
 700         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 701         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
 702
 703         /* start training on the source */
 704         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 705                 atombios_dig_encoder_setup(dp_info->encoder,
 706                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 707         else
 708                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 709                                           dp_info->dp_clock, dp_info->enc_id, 0);
 710
 711         /* disable the training pattern on the sink */
 712         radeon_write_dpcd_reg(dp_info->radeon_connector,
 713                               DP_TRAINING_PATTERN_SET,
 714                               DP_TRAINING_PATTERN_DISABLE);
 715
 716         return 0;
 717 }
 718
 719 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 720 {
 721         udelay(400);
 722
 723         /* disable the training pattern on the sink */
 724         radeon_write_dpcd_reg(dp_info->radeon_connector,
 725                               DP_TRAINING_PATTERN_SET,
 726                               DP_TRAINING_PATTERN_DISABLE);
 727
 728         /* disable the training pattern on the source */
 729         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 730                 atombios_dig_encoder_setup(dp_info->encoder,
 731                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 732         else
 733                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 734                                           dp_info->dp_clock, dp_info->enc_id, 0);
 735
 736         return 0;
 737 }
 738
 739 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 740 {
 741         bool clock_recovery;
 742         u8 voltage;
 743         int i;
 744
 745         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 746         memset(dp_info->train_set, 0, 4);
 747         radeon_dp_update_vs_emph(dp_info);
 748
 749         udelay(400);
 750
 751         /* clock recovery loop */
 752         clock_recovery = false;
 753         dp_info->tries = 0;
 754         voltage = 0xff;
 755         while (1) {
 756                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 757
 758                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
 759                         DRM_ERROR("displayport link status failed\n");
 760                         break;
 761                 }
 762
 763                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 764                         clock_recovery = true;
 765                         break;
 766                 }
 767
 768                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 769                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 770                                 break;
 771                 }
 772                 if (i == dp_info->dp_lane_count) {
 773                         DRM_ERROR("clock recovery reached max voltage\n");
 774                         break;
 775                 }
 776
 777                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 778                         ++dp_info->tries;
 779                         if (dp_info->tries == 5) {
 780                                 DRM_ERROR("clock recovery tried 5 times\n");
 781                                 break;
 782                         }
 783                 } else
 784                         dp_info->tries = 0;
 785
 786                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 787
 788                 /* Compute new train_set as requested by sink */
 789                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 790
 791                 radeon_dp_update_vs_emph(dp_info);
 792         }
 793         if (!clock_recovery) {
 794                 DRM_ERROR("clock recovery failed\n");
 795                 return -1;
 796         } else {
 797                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 798                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 799                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 800                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 801                 return 0;
 802         }
 803 }
 804
 805 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 806 {
 807         bool channel_eq;
 808
 809         if (dp_info->tp3_supported)
 810                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 811         else
 812                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 813
 814         /* channel equalization loop */
 815         dp_info->tries = 0;
 816         channel_eq = false;
 817         while (1) {
 818                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 819
 820                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
 821                         DRM_ERROR("displayport link status failed\n");
 822                         break;
 823                 }
 824
 825                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 826                         channel_eq = true;
 827                         break;
 828                 }
 829
 830                 /* Try 5 times */
 831                 if (dp_info->tries > 5) {
 832                         DRM_ERROR("channel eq failed: 5 tries\n");
 833                         break;
 834                 }
 835
 836                 /* Compute new train_set as requested by sink */
 837                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 838
 839                 radeon_dp_update_vs_emph(dp_info);
 840                 dp_info->tries++;
 841         }
 842
 843         if (!channel_eq) {
 844                 DRM_ERROR("channel eq failed\n");
 845                 return -1;
 846         } else {
 847                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 848                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 849                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 850                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 851                 return 0;
 852         }
 853 }
 854
 855 void radeon_dp_link_train(struct drm_encoder *encoder,
 856                           struct drm_connector *connector)
 857 {
 858         struct drm_device *dev = encoder->dev;
 859         struct radeon_device *rdev = dev->dev_private;
 860         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 861         struct radeon_encoder_atom_dig *dig;
 862         struct radeon_connector *radeon_connector;
 863         struct radeon_connector_atom_dig *dig_connector;
 864         struct radeon_dp_link_train_info dp_info;
 865         int index;
 866         u8 tmp, frev, crev;
 867
 868         if (!radeon_encoder->enc_priv)
 869                 return;
 870         dig = radeon_encoder->enc_priv;
 871
 872         radeon_connector = to_radeon_connector(connector);
 873         if (!radeon_connector->con_priv)
 874                 return;
 875         dig_connector = radeon_connector->con_priv;
 876
 877         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 878             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 879                 return;
 880
 881         /* DPEncoderService newer than 1.1 can't program properly the
 882          * training pattern. When facing such version use the
 883          * DIGXEncoderControl (X== 1 | 2)
 884          */
 885         dp_info.use_dpencoder = true;
 886         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 887         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 888                 if (crev > 1) {
 889                         dp_info.use_dpencoder = false;
 890                 }
 891         }
 892
 893         dp_info.enc_id = 0;
 894         if (dig->dig_encoder)
 895                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 896         else
 897                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 898         if (dig->linkb)
 899                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 900         else
 901                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 902
 903         tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
 904         if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 905                 dp_info.tp3_supported = true;
 906         else
 907                 dp_info.tp3_supported = false;
 908
 909         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 910         dp_info.rdev = rdev;
 911         dp_info.encoder = encoder;
 912         dp_info.connector = connector;
 913         dp_info.radeon_connector = radeon_connector;
 914         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 915         dp_info.dp_clock = dig_connector->dp_clock;
 916
 917         if (radeon_dp_link_train_init(&dp_info))
 918                 goto done;
 919         if (radeon_dp_link_train_cr(&dp_info))
 920                 goto done;
 921         if (radeon_dp_link_train_ce(&dp_info))
 922                 goto done;
 923 done:
 924         if (radeon_dp_link_train_finish(&dp_info))
 925                 return;
 926 }