2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <sys/resourcevar.h>
56 #include <sys/sfbuf.h>
59 #include <drm/i915_drm.h>
61 #include "intel_drv.h"
62 #include "intel_ringbuffer.h"
63 #include <linux/completion.h>
64 #include <linux/highmem.h>
65 #include <linux/jiffies.h>
66 #include <linux/time.h>
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
70 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
72 bool map_and_fenceable,
74 static int i915_gem_phys_pwrite(struct drm_device *dev,
75 struct drm_i915_gem_object *obj,
76 struct drm_i915_gem_pwrite *args,
77 struct drm_file *file);
79 static void i915_gem_write_fence(struct drm_device *dev, int reg,
80 struct drm_i915_gem_object *obj);
81 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
82 struct drm_i915_fence_reg *fence,
85 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
87 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
88 uint32_t size, int tiling_mode);
89 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
90 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
92 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
95 i915_gem_release_mmap(obj);
97 /* As we do not have an associated fence register, we will force
98 * a tiling change if we ever need to acquire one.
100 obj->fence_dirty = false;
101 obj->fence_reg = I915_FENCE_REG_NONE;
104 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
105 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
106 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
107 static vm_page_t shmem_read_mapping_page(vm_object_t, vm_pindex_t);
108 static void i915_gem_reset_fences(struct drm_device *dev);
109 static void i915_gem_lowmem(void *arg);
111 /* some bookkeeping */
112 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
115 dev_priv->mm.object_count++;
116 dev_priv->mm.object_memory += size;
119 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
122 dev_priv->mm.object_count--;
123 dev_priv->mm.object_memory -= size;
127 i915_gem_wait_for_error(struct drm_device *dev)
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct completion *x = &dev_priv->error_completion;
133 if (!atomic_read(&dev_priv->mm.wedged))
137 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
138 * userspace. If it takes that long something really bad is going on and
139 * we should simply try to bail out and fail as gracefully as possible.
141 ret = wait_for_completion_interruptible_timeout(x, 10*hz);
143 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
145 } else if (ret < 0) {
149 if (atomic_read(&dev_priv->mm.wedged)) {
150 /* GPU is hung, bump the completion count to account for
151 * the token we just consumed so that we never hit zero and
152 * end up waiting upon a subsequent completion event that
155 lockmgr(&x->wait.lock, LK_EXCLUSIVE);
157 lockmgr(&x->wait.lock, LK_RELEASE);
162 int i915_mutex_lock_interruptible(struct drm_device *dev)
166 ret = i915_gem_wait_for_error(dev);
170 ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
174 WARN_ON(i915_verify_lists(dev));
179 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
185 i915_gem_init_ioctl(struct drm_device *dev, void *data,
186 struct drm_file *file)
188 struct drm_i915_gem_init *args = data;
190 if (drm_core_check_feature(dev, DRIVER_MODESET))
193 if (args->gtt_start >= args->gtt_end ||
194 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
197 /* GEM with user mode setting was never supported on ilk and later. */
198 if (INTEL_INFO(dev)->gen >= 5)
201 lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
202 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
203 lockmgr(&dev->dev_lock, LK_RELEASE);
209 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
210 struct drm_file *file)
212 struct drm_i915_private *dev_priv = dev->dev_private;
213 struct drm_i915_gem_get_aperture *args = data;
214 struct drm_i915_gem_object *obj;
219 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
221 pinned += obj->gtt_space->size;
224 args->aper_size = dev_priv->mm.gtt_total;
225 args->aper_available_size = args->aper_size - pinned;
231 i915_gem_create(struct drm_file *file,
232 struct drm_device *dev,
236 struct drm_i915_gem_object *obj;
240 size = roundup(size, PAGE_SIZE);
244 /* Allocate the new object */
245 obj = i915_gem_alloc_object(dev, size);
250 ret = drm_gem_handle_create(file, &obj->base, &handle);
252 drm_gem_object_release(&obj->base);
253 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
254 drm_free(obj, M_DRM);
258 /* drop reference from allocate - handle holds it now */
259 drm_gem_object_unreference(&obj->base);
265 i915_gem_dumb_create(struct drm_file *file,
266 struct drm_device *dev,
267 struct drm_mode_create_dumb *args)
270 /* have to work out size/pitch and return them */
271 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
272 args->size = args->pitch * args->height;
273 return i915_gem_create(file, dev,
274 args->size, &args->handle);
277 int i915_gem_dumb_destroy(struct drm_file *file,
278 struct drm_device *dev,
282 return drm_gem_handle_delete(file, handle);
286 * Creates a new mm object and returns a handle to it.
289 i915_gem_create_ioctl(struct drm_device *dev, void *data,
290 struct drm_file *file)
292 struct drm_i915_gem_create *args = data;
294 return i915_gem_create(file, dev,
295 args->size, &args->handle);
298 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
300 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
302 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
303 obj->tiling_mode != I915_TILING_NONE;
306 static inline void vm_page_reference(vm_page_t m)
308 vm_page_flag_set(m, PG_REFERENCED);
312 i915_gem_shmem_pread(struct drm_device *dev,
313 struct drm_i915_gem_object *obj,
314 struct drm_i915_gem_pread *args,
315 struct drm_file *file)
322 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
324 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
327 vm_obj = obj->base.vm_obj;
330 VM_OBJECT_LOCK(vm_obj);
331 vm_object_pip_add(vm_obj, 1);
332 while (args->size > 0) {
333 obj_pi = OFF_TO_IDX(args->offset);
334 obj_po = args->offset & PAGE_MASK;
336 m = shmem_read_mapping_page(vm_obj, obj_pi);
337 VM_OBJECT_UNLOCK(vm_obj);
339 sf = sf_buf_alloc(m);
340 mkva = sf_buf_kva(sf);
341 length = min(args->size, PAGE_SIZE - obj_po);
343 if (do_bit17_swizzling &&
344 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
345 cnt = roundup2(obj_po + 1, 64);
346 cnt = min(cnt - obj_po, length);
347 swizzled_po = obj_po ^ 64;
350 swizzled_po = obj_po;
352 ret = -copyout_nofault(
353 (char *)mkva + swizzled_po,
354 (void *)(uintptr_t)args->data_ptr, cnt);
357 args->data_ptr += cnt;
364 VM_OBJECT_LOCK(vm_obj);
365 vm_page_reference(m);
366 vm_page_busy_wait(m, FALSE, "i915gem");
367 vm_page_unwire(m, 1);
373 vm_object_pip_wakeup(vm_obj);
374 VM_OBJECT_UNLOCK(vm_obj);
380 * Reads data from the object referenced by handle.
382 * On error, the contents of *data are undefined.
385 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
386 struct drm_file *file)
388 struct drm_i915_gem_pread *args = data;
389 struct drm_i915_gem_object *obj;
395 ret = i915_mutex_lock_interruptible(dev);
399 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
400 if (&obj->base == NULL) {
405 /* Bounds check source. */
406 if (args->offset > obj->base.size ||
407 args->size > obj->base.size - args->offset) {
412 ret = i915_gem_shmem_pread(dev, obj, args, file);
414 drm_gem_object_unreference(&obj->base);
421 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
422 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
428 * Pass the unaligned physical address and size to pmap_mapdev_attr()
429 * so it can properly calculate whether an extra page needs to be
430 * mapped or not to cover the requested range. The function will
431 * add the page offset into the returned mkva for us.
433 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
434 offset, size, PAT_WRITE_COMBINING);
435 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
436 pmap_unmapdev(mkva, size);
441 i915_gem_shmem_pwrite(struct drm_device *dev,
442 struct drm_i915_gem_object *obj,
443 struct drm_i915_gem_pwrite *args,
444 struct drm_file *file)
451 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
453 do_bit17_swizzling = 0;
456 vm_obj = obj->base.vm_obj;
459 VM_OBJECT_LOCK(vm_obj);
460 vm_object_pip_add(vm_obj, 1);
461 while (args->size > 0) {
462 obj_pi = OFF_TO_IDX(args->offset);
463 obj_po = args->offset & PAGE_MASK;
465 m = shmem_read_mapping_page(vm_obj, obj_pi);
466 VM_OBJECT_UNLOCK(vm_obj);
468 sf = sf_buf_alloc(m);
469 mkva = sf_buf_kva(sf);
470 length = min(args->size, PAGE_SIZE - obj_po);
472 if (do_bit17_swizzling &&
473 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
474 cnt = roundup2(obj_po + 1, 64);
475 cnt = min(cnt - obj_po, length);
476 swizzled_po = obj_po ^ 64;
479 swizzled_po = obj_po;
481 ret = -copyin_nofault(
482 (void *)(uintptr_t)args->data_ptr,
483 (char *)mkva + swizzled_po, cnt);
486 args->data_ptr += cnt;
493 VM_OBJECT_LOCK(vm_obj);
495 vm_page_reference(m);
496 vm_page_busy_wait(m, FALSE, "i915gem");
497 vm_page_unwire(m, 1);
503 vm_object_pip_wakeup(vm_obj);
504 VM_OBJECT_UNLOCK(vm_obj);
510 * Writes data to the object referenced by handle.
512 * On error, the contents of the buffer that were to be modified are undefined.
515 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
516 struct drm_file *file)
518 struct drm_i915_gem_pwrite *args = data;
519 struct drm_i915_gem_object *obj;
521 vm_offset_t start, end;
527 start = trunc_page(args->data_ptr);
528 end = round_page(args->data_ptr + args->size);
529 npages = howmany(end - start, PAGE_SIZE);
530 ma = kmalloc(npages * sizeof(vm_page_t), M_DRM, M_WAITOK |
532 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
533 (vm_offset_t)args->data_ptr, args->size,
534 VM_PROT_READ, ma, npages);
540 ret = i915_mutex_lock_interruptible(dev);
544 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
545 if (&obj->base == NULL) {
550 /* Bounds check destination. */
551 if (args->offset > obj->base.size ||
552 args->size > obj->base.size - args->offset) {
558 ret = i915_gem_phys_pwrite(dev, obj, args, file);
559 } else if (obj->gtt_space &&
560 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
561 ret = i915_gem_object_pin(obj, 0, true, false);
564 ret = i915_gem_object_set_to_gtt_domain(obj, true);
567 ret = i915_gem_object_put_fence(obj);
570 ret = i915_gem_gtt_write(dev, obj, args->data_ptr, args->size,
573 i915_gem_object_unpin(obj);
575 ret = i915_gem_object_set_to_cpu_domain(obj, true);
578 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
581 drm_gem_object_unreference(&obj->base);
585 vm_page_unhold_pages(ma, npages);
592 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
595 if (atomic_read(&dev_priv->mm.wedged)) {
596 struct completion *x = &dev_priv->error_completion;
597 bool recovery_complete;
599 /* Give the error handler a chance to run. */
600 lockmgr(&x->wait.lock, LK_EXCLUSIVE);
601 recovery_complete = x->done > 0;
602 lockmgr(&x->wait.lock, LK_RELEASE);
604 /* Non-interruptible callers can't handle -EAGAIN, hence return
605 * -EIO unconditionally for these. */
609 /* Recovery complete, but still wedged means reset failure. */
610 if (recovery_complete)
620 * Compare seqno against outstanding lazy request. Emit a request if they are
624 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
628 DRM_LOCK_ASSERT(ring->dev);
631 if (seqno == ring->outstanding_lazy_request)
632 ret = i915_add_request(ring, NULL, NULL);
638 * __wait_seqno - wait until execution of seqno has finished
639 * @ring: the ring expected to report seqno
641 * @interruptible: do an interruptible wait (normally yes)
642 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
644 * Returns 0 if the seqno was found within the alloted time. Else returns the
645 * errno with remaining time filled in timeout argument.
647 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
648 bool interruptible, struct timespec *timeout)
650 drm_i915_private_t *dev_priv = ring->dev->dev_private;
651 struct timespec before, now, wait_time={1,0};
652 unsigned long timeout_jiffies;
654 bool wait_forever = true;
657 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
660 if (timeout != NULL) {
661 wait_time = *timeout;
662 wait_forever = false;
665 timeout_jiffies = timespec_to_jiffies(&wait_time);
667 if (WARN_ON(!ring->irq_get(ring)))
670 /* Record current time in case interrupted by signal, or wedged * */
671 getrawmonotonic(&before);
674 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
675 atomic_read(&dev_priv->mm.wedged))
678 end = wait_event_interruptible_timeout(ring->irq_queue,
682 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
685 ret = i915_gem_check_wedge(dev_priv, interruptible);
688 } while (end == 0 && wait_forever);
690 getrawmonotonic(&now);
696 struct timespec sleep_time = timespec_sub(now, before);
697 *timeout = timespec_sub(*timeout, sleep_time);
702 case -EAGAIN: /* Wedged */
703 case -ERESTARTSYS: /* Signal */
705 case 0: /* Timeout */
707 set_normalized_timespec(timeout, 0, 0);
708 return -ETIMEDOUT; /* -ETIME on Linux */
709 default: /* Completed */
710 WARN_ON(end < 0); /* We're not aware of other errors */
716 * Waits for a sequence number to be signaled, and cleans up the
717 * request and object lists appropriately for that event.
720 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
722 struct drm_device *dev = ring->dev;
723 struct drm_i915_private *dev_priv = dev->dev_private;
726 DRM_LOCK_ASSERT(dev);
729 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
733 ret = i915_gem_check_olr(ring, seqno);
737 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
743 * Ensures that all rendering to the object has completed and the object is
744 * safe to unbind from the GTT or access from the CPU.
746 static __must_check int
747 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
750 struct intel_ring_buffer *ring = obj->ring;
754 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
758 ret = i915_wait_seqno(ring, seqno);
762 i915_gem_retire_requests_ring(ring);
764 /* Manually manage the write flush as we may have not yet
765 * retired the buffer.
767 if (obj->last_write_seqno &&
768 i915_seqno_passed(seqno, obj->last_write_seqno)) {
769 obj->last_write_seqno = 0;
770 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
776 /* A nonblocking variant of the above wait. This is a highly dangerous routine
777 * as the object state may change during this call.
779 static __must_check int
780 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
783 struct drm_device *dev = obj->base.dev;
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 struct intel_ring_buffer *ring = obj->ring;
789 DRM_LOCK_ASSERT(dev);
790 BUG_ON(!dev_priv->mm.interruptible);
792 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
796 ret = i915_gem_check_wedge(dev_priv, true);
800 ret = i915_gem_check_olr(ring, seqno);
805 ret = __wait_seqno(ring, seqno, true, NULL);
808 i915_gem_retire_requests_ring(ring);
810 /* Manually manage the write flush as we may have not yet
811 * retired the buffer.
813 if (obj->last_write_seqno &&
814 i915_seqno_passed(seqno, obj->last_write_seqno)) {
815 obj->last_write_seqno = 0;
816 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
823 * Called when user space prepares to use an object with the CPU, either
824 * through the mmap ioctl's mapping or a GTT mapping.
827 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
828 struct drm_file *file)
830 struct drm_i915_gem_set_domain *args = data;
831 struct drm_i915_gem_object *obj;
832 uint32_t read_domains = args->read_domains;
833 uint32_t write_domain = args->write_domain;
836 /* Only handle setting domains to types used by the CPU. */
837 if (write_domain & I915_GEM_GPU_DOMAINS)
840 if (read_domains & I915_GEM_GPU_DOMAINS)
843 /* Having something in the write domain implies it's in the read
844 * domain, and only that read domain. Enforce that in the request.
846 if (write_domain != 0 && read_domains != write_domain)
849 ret = i915_mutex_lock_interruptible(dev);
853 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
854 if (&obj->base == NULL) {
859 /* Try to flush the object off the GPU without holding the lock.
860 * We will repeat the flush holding the lock in the normal manner
861 * to catch cases where we are gazumped.
863 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
867 if (read_domains & I915_GEM_DOMAIN_GTT) {
868 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
870 /* Silently promote "you're not bound, there was nothing to do"
871 * to success, since the client was just asking us to
872 * make sure everything was done.
877 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
881 drm_gem_object_unreference(&obj->base);
888 * Called when user space has done writes to this buffer
891 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
892 struct drm_file *file)
894 struct drm_i915_gem_sw_finish *args = data;
895 struct drm_i915_gem_object *obj;
898 ret = i915_mutex_lock_interruptible(dev);
901 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
902 if (&obj->base == NULL) {
907 /* Pinned buffers may be scanout, so flush the cache */
909 i915_gem_object_flush_cpu_write_domain(obj);
911 drm_gem_object_unreference(&obj->base);
918 * Maps the contents of an object, returning the address it is mapped
921 * While the mapping holds a reference on the contents of the object, it doesn't
922 * imply a ref on the object itself.
925 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
926 struct drm_file *file)
928 struct drm_i915_gem_mmap *args = data;
929 struct drm_gem_object *obj;
930 struct proc *p = curproc;
931 vm_map_t map = &p->p_vmspace->vm_map;
936 obj = drm_gem_object_lookup(dev, file, args->handle);
943 size = round_page(args->size);
944 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
950 vm_object_hold(obj->vm_obj);
951 vm_object_reference_locked(obj->vm_obj);
952 vm_object_drop(obj->vm_obj);
953 rv = vm_map_find(map, obj->vm_obj, NULL,
954 args->offset, &addr, args->size,
955 PAGE_SIZE, /* align */
957 VM_MAPTYPE_NORMAL, /* maptype */
958 VM_PROT_READ | VM_PROT_WRITE, /* prot */
959 VM_PROT_READ | VM_PROT_WRITE, /* max */
960 MAP_SHARED /* cow */);
961 if (rv != KERN_SUCCESS) {
962 vm_object_deallocate(obj->vm_obj);
963 error = -vm_mmap_to_errno(rv);
965 args->addr_ptr = (uint64_t)addr;
968 drm_gem_object_unreference(obj);
973 * i915_gem_release_mmap - remove physical page mappings
974 * @obj: obj in question
976 * Preserve the reservation of the mmapping with the DRM core code, but
977 * relinquish ownership of the pages back to the system.
979 * It is vital that we remove the page mapping if we have mapped a tiled
980 * object through the GTT and then lose the fence register due to
981 * resource pressure. Similarly if the object has been moved out of the
982 * aperture, than pages mapped into userspace must be revoked. Removing the
983 * mapping will then trigger a page fault on the next user access, allowing
984 * fixup by i915_gem_fault().
987 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
993 if (!obj->fault_mappable)
996 devobj = cdev_pager_lookup(obj);
997 if (devobj != NULL) {
998 page_count = OFF_TO_IDX(obj->base.size);
1000 VM_OBJECT_LOCK(devobj);
1001 for (i = 0; i < page_count; i++) {
1002 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1005 cdev_pager_free_page(devobj, m);
1007 VM_OBJECT_UNLOCK(devobj);
1008 vm_object_deallocate(devobj);
1011 obj->fault_mappable = false;
1015 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1019 if (INTEL_INFO(dev)->gen >= 4 ||
1020 tiling_mode == I915_TILING_NONE)
1023 /* Previous chips need a power-of-two fence region when tiling */
1024 if (INTEL_INFO(dev)->gen == 3)
1025 gtt_size = 1024*1024;
1027 gtt_size = 512*1024;
1029 while (gtt_size < size)
1036 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1037 * @obj: object to check
1039 * Return the required GTT alignment for an object, taking into account
1040 * potential fence register mapping.
1043 i915_gem_get_gtt_alignment(struct drm_device *dev,
1049 * Minimum alignment is 4k (GTT page size), but might be greater
1050 * if a fence register is needed for the object.
1052 if (INTEL_INFO(dev)->gen >= 4 ||
1053 tiling_mode == I915_TILING_NONE)
1057 * Previous chips need to be aligned to the size of the smallest
1058 * fence register that can contain the object.
1060 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1064 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1067 * @size: size of the object
1068 * @tiling_mode: tiling mode of the object
1070 * Return the required GTT alignment for an object, only taking into account
1071 * unfenced tiled surface requirements.
1074 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1079 * Minimum alignment is 4k (GTT page size) for sane hw.
1081 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1082 tiling_mode == I915_TILING_NONE)
1085 /* Previous hardware however needs to be aligned to a power-of-two
1086 * tile height. The simplest method for determining this is to reuse
1087 * the power-of-tile object size.
1089 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1093 i915_gem_mmap_gtt(struct drm_file *file,
1094 struct drm_device *dev,
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 struct drm_i915_gem_object *obj;
1102 ret = i915_mutex_lock_interruptible(dev);
1106 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1107 if (&obj->base == NULL) {
1112 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1117 if (obj->madv != I915_MADV_WILLNEED) {
1118 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1123 ret = drm_gem_create_mmap_offset(&obj->base);
1127 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1128 DRM_GEM_MAPPING_KEY;
1130 drm_gem_object_unreference(&obj->base);
1137 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1139 * @data: GTT mapping ioctl data
1140 * @file: GEM object info
1142 * Simply returns the fake offset to userspace so it can mmap it.
1143 * The mmap call will end up in drm_gem_mmap(), which will set things
1144 * up so we can get faults in the handler above.
1146 * The fault handler will take care of binding the object into the GTT
1147 * (since it may have been evicted to make room for something), allocating
1148 * a fence register, and mapping the appropriate aperture address into
1152 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1153 struct drm_file *file)
1155 struct drm_i915_gem_mmap_gtt *args = data;
1157 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1160 /* Immediately discard the backing storage */
1162 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1166 vm_obj = obj->base.vm_obj;
1167 VM_OBJECT_LOCK(vm_obj);
1168 vm_object_page_remove(vm_obj, 0, 0, false);
1169 VM_OBJECT_UNLOCK(vm_obj);
1170 obj->madv = __I915_MADV_PURGED;
1174 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1176 return obj->madv == I915_MADV_DONTNEED;
1180 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1185 BUG_ON(obj->madv == __I915_MADV_PURGED);
1187 if (obj->tiling_mode != I915_TILING_NONE)
1188 i915_gem_object_save_bit_17_swizzle(obj);
1189 if (obj->madv == I915_MADV_DONTNEED)
1191 page_count = obj->base.size / PAGE_SIZE;
1192 VM_OBJECT_LOCK(obj->base.vm_obj);
1193 #if GEM_PARANOID_CHECK_GTT
1194 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
1196 for (i = 0; i < page_count; i++) {
1200 if (obj->madv == I915_MADV_WILLNEED)
1201 vm_page_reference(m);
1202 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
1203 vm_page_unwire(obj->pages[i], 1);
1204 vm_page_wakeup(obj->pages[i]);
1206 VM_OBJECT_UNLOCK(obj->base.vm_obj);
1208 drm_free(obj->pages, M_DRM);
1213 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1215 struct drm_device *dev;
1217 int page_count, i, j;
1218 struct vm_page *page;
1220 dev = obj->base.dev;
1221 KASSERT(obj->pages == NULL, ("Obj already has pages"));
1222 page_count = obj->base.size / PAGE_SIZE;
1223 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
1226 vm_obj = obj->base.vm_obj;
1227 VM_OBJECT_LOCK(vm_obj);
1229 for (i = 0; i < page_count; i++) {
1230 page = shmem_read_mapping_page(vm_obj, i);
1234 obj->pages[i] = page;
1237 VM_OBJECT_UNLOCK(vm_obj);
1238 if (i915_gem_object_needs_bit17_swizzle(obj))
1239 i915_gem_object_do_bit_17_swizzle(obj);
1244 for (j = 0; j < i; j++) {
1245 page = obj->pages[j];
1246 vm_page_busy_wait(page, FALSE, "i915gem");
1247 vm_page_unwire(page, 0);
1248 vm_page_wakeup(page);
1250 VM_OBJECT_UNLOCK(vm_obj);
1251 drm_free(obj->pages, M_DRM);
1257 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1258 struct intel_ring_buffer *ring)
1260 struct drm_device *dev = obj->base.dev;
1261 struct drm_i915_private *dev_priv = dev->dev_private;
1262 u32 seqno = intel_ring_get_seqno(ring);
1264 BUG_ON(ring == NULL);
1267 /* Add a reference if we're newly entering the active list. */
1269 drm_gem_object_reference(&obj->base);
1273 /* Move from whatever list we were on to the tail of execution. */
1274 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1275 list_move_tail(&obj->ring_list, &ring->active_list);
1277 obj->last_read_seqno = seqno;
1279 if (obj->fenced_gpu_access) {
1280 obj->last_fenced_seqno = seqno;
1282 /* Bump MRU to take account of the delayed flush */
1283 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1284 struct drm_i915_fence_reg *reg;
1286 reg = &dev_priv->fence_regs[obj->fence_reg];
1287 list_move_tail(®->lru_list,
1288 &dev_priv->mm.fence_list);
1294 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1296 struct drm_device *dev = obj->base.dev;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1299 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1300 BUG_ON(!obj->active);
1302 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1304 list_del_init(&obj->ring_list);
1307 obj->last_read_seqno = 0;
1308 obj->last_write_seqno = 0;
1309 obj->base.write_domain = 0;
1311 obj->last_fenced_seqno = 0;
1312 obj->fenced_gpu_access = false;
1315 drm_gem_object_unreference(&obj->base);
1317 WARN_ON(i915_verify_lists(dev));
1321 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1323 struct drm_i915_private *dev_priv = dev->dev_private;
1324 struct intel_ring_buffer *ring;
1327 /* The hardware uses various monotonic 32-bit counters, if we
1328 * detect that they will wraparound we need to idle the GPU
1329 * and reset those counters.
1332 for_each_ring(ring, dev_priv, i) {
1333 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1334 ret |= ring->sync_seqno[j] != 0;
1339 ret = i915_gpu_idle(dev);
1343 i915_gem_retire_requests(dev);
1344 for_each_ring(ring, dev_priv, i) {
1345 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1346 ring->sync_seqno[j] = 0;
1353 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1357 /* reserve 0 for non-seqno */
1358 if (dev_priv->next_seqno == 0) {
1359 int ret = i915_gem_handle_seqno_wrap(dev);
1363 dev_priv->next_seqno = 1;
1366 *seqno = dev_priv->next_seqno++;
1371 i915_add_request(struct intel_ring_buffer *ring,
1372 struct drm_file *file,
1375 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1376 struct drm_i915_gem_request *request;
1377 u32 request_ring_position;
1382 * Emit any outstanding flushes - execbuf can fail to emit the flush
1383 * after having emitted the batchbuffer command. Hence we need to fix
1384 * things up similar to emitting the lazy request. The difference here
1385 * is that the flush _must_ happen before the next request, no matter
1388 ret = intel_ring_flush_all_caches(ring);
1392 request = kmalloc(sizeof(*request), M_DRM, M_WAITOK | M_ZERO);
1393 if (request == NULL)
1397 /* Record the position of the start of the request so that
1398 * should we detect the updated seqno part-way through the
1399 * GPU processing the request, we never over-estimate the
1400 * position of the head.
1402 request_ring_position = intel_ring_get_tail(ring);
1404 ret = ring->add_request(ring);
1406 kfree(request, M_DRM);
1410 request->seqno = intel_ring_get_seqno(ring);
1411 request->ring = ring;
1412 request->tail = request_ring_position;
1413 request->emitted_jiffies = jiffies;
1414 was_empty = list_empty(&ring->request_list);
1415 list_add_tail(&request->list, &ring->request_list);
1416 request->file_priv = NULL;
1419 struct drm_i915_file_private *file_priv = file->driver_priv;
1421 spin_lock(&file_priv->mm.lock);
1422 request->file_priv = file_priv;
1423 list_add_tail(&request->client_list,
1424 &file_priv->mm.request_list);
1425 spin_unlock(&file_priv->mm.lock);
1428 ring->outstanding_lazy_request = 0;
1430 if (!dev_priv->mm.suspended) {
1431 if (i915_enable_hangcheck) {
1432 mod_timer(&dev_priv->hangcheck_timer,
1433 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1436 queue_delayed_work(dev_priv->wq,
1437 &dev_priv->mm.retire_work,
1438 round_jiffies_up_relative(hz));
1439 intel_mark_busy(dev_priv->dev);
1444 *out_seqno = request->seqno;
1449 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1451 struct drm_i915_file_private *file_priv = request->file_priv;
1456 spin_lock(&file_priv->mm.lock);
1457 if (request->file_priv) {
1458 list_del(&request->client_list);
1459 request->file_priv = NULL;
1461 spin_unlock(&file_priv->mm.lock);
1464 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1465 struct intel_ring_buffer *ring)
1467 while (!list_empty(&ring->request_list)) {
1468 struct drm_i915_gem_request *request;
1470 request = list_first_entry(&ring->request_list,
1471 struct drm_i915_gem_request,
1474 list_del(&request->list);
1475 i915_gem_request_remove_from_client(request);
1476 drm_free(request, M_DRM);
1479 while (!list_empty(&ring->active_list)) {
1480 struct drm_i915_gem_object *obj;
1482 obj = list_first_entry(&ring->active_list,
1483 struct drm_i915_gem_object,
1486 i915_gem_object_move_to_inactive(obj);
1490 static void i915_gem_reset_fences(struct drm_device *dev)
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1495 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1496 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1498 i915_gem_write_fence(dev, i, NULL);
1501 i915_gem_object_fence_lost(reg->obj);
1505 INIT_LIST_HEAD(®->lru_list);
1508 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1511 void i915_gem_reset(struct drm_device *dev)
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514 struct drm_i915_gem_object *obj;
1515 struct intel_ring_buffer *ring;
1518 for_each_ring(ring, dev_priv, i)
1519 i915_gem_reset_ring_lists(dev_priv, ring);
1521 /* Move everything out of the GPU domains to ensure we do any
1522 * necessary invalidation upon reuse.
1524 list_for_each_entry(obj,
1525 &dev_priv->mm.inactive_list,
1528 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1531 /* The fence registers are invalidated so clear them out */
1532 i915_gem_reset_fences(dev);
1536 * This function clears the request list as sequence numbers are passed.
1539 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1543 if (list_empty(&ring->request_list))
1546 WARN_ON(i915_verify_lists(ring->dev));
1548 seqno = ring->get_seqno(ring, true);
1550 while (!list_empty(&ring->request_list)) {
1551 struct drm_i915_gem_request *request;
1553 request = list_first_entry(&ring->request_list,
1554 struct drm_i915_gem_request,
1557 if (!i915_seqno_passed(seqno, request->seqno))
1560 /* We know the GPU must have read the request to have
1561 * sent us the seqno + interrupt, so use the position
1562 * of tail of the request to update the last known position
1565 ring->last_retired_head = request->tail;
1567 list_del(&request->list);
1568 i915_gem_request_remove_from_client(request);
1569 kfree(request, M_DRM);
1572 /* Move any buffers on the active list that are no longer referenced
1573 * by the ringbuffer to the flushing/inactive lists as appropriate.
1575 while (!list_empty(&ring->active_list)) {
1576 struct drm_i915_gem_object *obj;
1578 obj = list_first_entry(&ring->active_list,
1579 struct drm_i915_gem_object,
1582 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1585 i915_gem_object_move_to_inactive(obj);
1588 if (unlikely(ring->trace_irq_seqno &&
1589 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1590 ring->irq_put(ring);
1591 ring->trace_irq_seqno = 0;
1597 i915_gem_retire_requests(struct drm_device *dev)
1599 drm_i915_private_t *dev_priv = dev->dev_private;
1600 struct intel_ring_buffer *ring;
1603 for_each_ring(ring, dev_priv, i)
1604 i915_gem_retire_requests_ring(ring);
1608 i915_gem_retire_work_handler(struct work_struct *work)
1610 drm_i915_private_t *dev_priv;
1611 struct drm_device *dev;
1612 struct intel_ring_buffer *ring;
1616 dev_priv = container_of(work, drm_i915_private_t,
1617 mm.retire_work.work);
1618 dev = dev_priv->dev;
1620 /* Come back later if the device is busy... */
1621 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
1622 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1623 round_jiffies_up_relative(hz));
1627 i915_gem_retire_requests(dev);
1629 /* Send a periodic flush down the ring so we don't hold onto GEM
1630 * objects indefinitely.
1633 for_each_ring(ring, dev_priv, i) {
1634 if (ring->gpu_caches_dirty)
1635 i915_add_request(ring, NULL, NULL);
1637 idle &= list_empty(&ring->request_list);
1640 if (!dev_priv->mm.suspended && !idle)
1641 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1642 round_jiffies_up_relative(hz));
1644 intel_mark_idle(dev);
1649 * Ensures that an object will eventually get non-busy by flushing any required
1650 * write domains, emitting any outstanding lazy request and retiring and
1651 * completed requests.
1654 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
1659 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
1663 i915_gem_retire_requests_ring(obj->ring);
1670 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
1671 * @DRM_IOCTL_ARGS: standard ioctl arguments
1673 * Returns 0 if successful, else an error is returned with the remaining time in
1674 * the timeout parameter.
1675 * -ETIME: object is still busy after timeout
1676 * -ERESTARTSYS: signal interrupted the wait
1677 * -ENONENT: object doesn't exist
1678 * Also possible, but rare:
1679 * -EAGAIN: GPU wedged
1681 * -ENODEV: Internal IRQ fail
1682 * -E?: The add request failed
1684 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
1685 * non-zero timeout parameter the wait ioctl will wait for the given number of
1686 * nanoseconds on an object becoming unbusy. Since the wait itself does so
1687 * without holding struct_mutex the object may become re-busied before this
1688 * function completes. A similar but shorter * race condition exists in the busy
1692 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1694 struct drm_i915_gem_wait *args = data;
1695 struct drm_i915_gem_object *obj;
1696 struct intel_ring_buffer *ring = NULL;
1697 struct timespec timeout_stack, *timeout = NULL;
1701 if (args->timeout_ns >= 0) {
1702 timeout_stack = ns_to_timespec(args->timeout_ns);
1703 timeout = &timeout_stack;
1706 ret = i915_mutex_lock_interruptible(dev);
1710 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
1711 if (&obj->base == NULL) {
1716 /* Need to make sure the object gets inactive eventually. */
1717 ret = i915_gem_object_flush_active(obj);
1722 seqno = obj->last_read_seqno;
1729 /* Do this after OLR check to make sure we make forward progress polling
1730 * on this IOCTL with a 0 timeout (like busy ioctl)
1732 if (!args->timeout_ns) {
1737 drm_gem_object_unreference(&obj->base);
1740 ret = __wait_seqno(ring, seqno, true, timeout);
1742 WARN_ON(!timespec_valid(timeout));
1743 args->timeout_ns = timespec_to_ns(timeout);
1748 drm_gem_object_unreference(&obj->base);
1754 * i915_gem_object_sync - sync an object to a ring.
1756 * @obj: object which may be in use on another ring.
1757 * @to: ring we wish to use the object on. May be NULL.
1759 * This code is meant to abstract object synchronization with the GPU.
1760 * Calling with NULL implies synchronizing the object with the CPU
1761 * rather than a particular GPU ring.
1763 * Returns 0 if successful, else propagates up the lower layer error.
1766 i915_gem_object_sync(struct drm_i915_gem_object *obj,
1767 struct intel_ring_buffer *to)
1769 struct intel_ring_buffer *from = obj->ring;
1773 if (from == NULL || to == from)
1776 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
1777 return i915_gem_object_wait_rendering(obj, false);
1779 idx = intel_ring_sync_index(from, to);
1781 seqno = obj->last_read_seqno;
1782 if (seqno <= from->sync_seqno[idx])
1785 ret = i915_gem_check_olr(obj->ring, seqno);
1789 ret = to->sync_to(to, from, seqno);
1791 /* We use last_read_seqno because sync_to()
1792 * might have just caused seqno wrap under
1795 from->sync_seqno[idx] = obj->last_read_seqno;
1800 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
1802 u32 old_write_domain, old_read_domains;
1804 /* Act a barrier for all accesses through the GTT */
1807 /* Force a pagefault for domain tracking on next user access */
1808 i915_gem_release_mmap(obj);
1810 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
1813 old_read_domains = obj->base.read_domains;
1814 old_write_domain = obj->base.write_domain;
1816 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
1817 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
1822 * Unbinds an object from the GTT aperture.
1825 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
1827 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1830 if (obj->gtt_space == NULL)
1836 ret = i915_gem_object_finish_gpu(obj);
1839 /* Continue on if we fail due to EIO, the GPU is hung so we
1840 * should be safe and we need to cleanup or else we might
1841 * cause memory corruption through use-after-free.
1844 i915_gem_object_finish_gtt(obj);
1846 /* Move the object to the CPU domain to ensure that
1847 * any possible CPU writes while it's not in the GTT
1848 * are flushed when we go to remap it.
1851 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1852 if (ret == -ERESTARTSYS)
1855 /* In the event of a disaster, abandon all caches and
1856 * hope for the best.
1858 i915_gem_clflush_object(obj);
1859 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1862 /* release the fence reg _after_ flushing */
1863 ret = i915_gem_object_put_fence(obj);
1867 if (obj->has_global_gtt_mapping)
1868 i915_gem_gtt_unbind_object(obj);
1869 if (obj->has_aliasing_ppgtt_mapping) {
1870 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
1871 obj->has_aliasing_ppgtt_mapping = 0;
1873 i915_gem_gtt_finish_object(obj);
1875 i915_gem_object_put_pages_gtt(obj);
1877 list_del_init(&obj->gtt_list);
1878 list_del_init(&obj->mm_list);
1879 /* Avoid an unnecessary call to unbind on rebind. */
1880 obj->map_and_fenceable = true;
1882 drm_mm_put_block(obj->gtt_space);
1883 obj->gtt_space = NULL;
1884 obj->gtt_offset = 0;
1886 if (i915_gem_object_is_purgeable(obj))
1887 i915_gem_object_truncate(obj);
1892 int i915_gpu_idle(struct drm_device *dev)
1894 drm_i915_private_t *dev_priv = dev->dev_private;
1895 struct intel_ring_buffer *ring;
1898 /* Flush everything onto the inactive list. */
1899 for_each_ring(ring, dev_priv, i) {
1900 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
1904 ret = intel_ring_idle(ring);
1912 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
1913 struct drm_i915_gem_object *obj)
1915 drm_i915_private_t *dev_priv = dev->dev_private;
1919 u32 size = obj->gtt_space->size;
1921 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1923 val |= obj->gtt_offset & 0xfffff000;
1924 val |= (uint64_t)((obj->stride / 128) - 1) <<
1925 SANDYBRIDGE_FENCE_PITCH_SHIFT;
1927 if (obj->tiling_mode == I915_TILING_Y)
1928 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1929 val |= I965_FENCE_REG_VALID;
1933 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
1934 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
1937 static void i965_write_fence_reg(struct drm_device *dev, int reg,
1938 struct drm_i915_gem_object *obj)
1940 drm_i915_private_t *dev_priv = dev->dev_private;
1944 u32 size = obj->gtt_space->size;
1946 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1948 val |= obj->gtt_offset & 0xfffff000;
1949 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1950 if (obj->tiling_mode == I915_TILING_Y)
1951 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1952 val |= I965_FENCE_REG_VALID;
1956 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
1957 POSTING_READ(FENCE_REG_965_0 + reg * 8);
1960 static void i915_write_fence_reg(struct drm_device *dev, int reg,
1961 struct drm_i915_gem_object *obj)
1963 drm_i915_private_t *dev_priv = dev->dev_private;
1967 u32 size = obj->gtt_space->size;
1971 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
1972 (size & -size) != size ||
1973 (obj->gtt_offset & (size - 1)),
1974 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
1975 obj->gtt_offset, obj->map_and_fenceable, size);
1977 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1982 /* Note: pitch better be a power of two tile widths */
1983 pitch_val = obj->stride / tile_width;
1984 pitch_val = ffs(pitch_val) - 1;
1986 val = obj->gtt_offset;
1987 if (obj->tiling_mode == I915_TILING_Y)
1988 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1989 val |= I915_FENCE_SIZE_BITS(size);
1990 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1991 val |= I830_FENCE_REG_VALID;
1996 reg = FENCE_REG_830_0 + reg * 4;
1998 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2000 I915_WRITE(reg, val);
2004 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2005 struct drm_i915_gem_object *obj)
2007 drm_i915_private_t *dev_priv = dev->dev_private;
2011 u32 size = obj->gtt_space->size;
2014 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2015 (size & -size) != size ||
2016 (obj->gtt_offset & (size - 1)),
2017 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2018 obj->gtt_offset, size);
2020 pitch_val = obj->stride / 128;
2021 pitch_val = ffs(pitch_val) - 1;
2023 val = obj->gtt_offset;
2024 if (obj->tiling_mode == I915_TILING_Y)
2025 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2026 val |= I830_FENCE_SIZE_BITS(size);
2027 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2028 val |= I830_FENCE_REG_VALID;
2032 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2033 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2036 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2037 struct drm_i915_gem_object *obj)
2039 switch (INTEL_INFO(dev)->gen) {
2041 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2043 case 4: i965_write_fence_reg(dev, reg, obj); break;
2044 case 3: i915_write_fence_reg(dev, reg, obj); break;
2045 case 2: i830_write_fence_reg(dev, reg, obj); break;
2050 static inline int fence_number(struct drm_i915_private *dev_priv,
2051 struct drm_i915_fence_reg *fence)
2053 return fence - dev_priv->fence_regs;
2056 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2057 struct drm_i915_fence_reg *fence,
2060 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2061 int reg = fence_number(dev_priv, fence);
2063 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2066 obj->fence_reg = reg;
2068 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2070 obj->fence_reg = I915_FENCE_REG_NONE;
2072 list_del_init(&fence->lru_list);
2077 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2079 if (obj->last_fenced_seqno) {
2080 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2084 obj->last_fenced_seqno = 0;
2087 /* Ensure that all CPU reads are completed before installing a fence
2088 * and all writes before removing the fence.
2090 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2093 obj->fenced_gpu_access = false;
2098 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2100 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2103 ret = i915_gem_object_flush_fence(obj);
2107 if (obj->fence_reg == I915_FENCE_REG_NONE)
2110 i915_gem_object_update_fence(obj,
2111 &dev_priv->fence_regs[obj->fence_reg],
2113 i915_gem_object_fence_lost(obj);
2118 static struct drm_i915_fence_reg *
2119 i915_find_fence_reg(struct drm_device *dev)
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 struct drm_i915_fence_reg *reg, *avail;
2125 /* First try to find a free reg */
2127 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2128 reg = &dev_priv->fence_regs[i];
2132 if (!reg->pin_count)
2139 /* None available, try to steal one or wait for a user to finish */
2140 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2151 * i915_gem_object_get_fence - set up fencing for an object
2152 * @obj: object to map through a fence reg
2154 * When mapping objects through the GTT, userspace wants to be able to write
2155 * to them without having to worry about swizzling if the object is tiled.
2156 * This function walks the fence regs looking for a free one for @obj,
2157 * stealing one if it can't find any.
2159 * It then sets up the reg based on the object's properties: address, pitch
2160 * and tiling format.
2162 * For an untiled surface, this removes any existing fence.
2165 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2167 struct drm_device *dev = obj->base.dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 bool enable = obj->tiling_mode != I915_TILING_NONE;
2170 struct drm_i915_fence_reg *reg;
2173 /* Have we updated the tiling parameters upon the object and so
2174 * will need to serialise the write to the associated fence register?
2176 if (obj->fence_dirty) {
2177 ret = i915_gem_object_flush_fence(obj);
2182 /* Just update our place in the LRU if our fence is getting reused. */
2183 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2184 reg = &dev_priv->fence_regs[obj->fence_reg];
2185 if (!obj->fence_dirty) {
2186 list_move_tail(®->lru_list,
2187 &dev_priv->mm.fence_list);
2190 } else if (enable) {
2191 reg = i915_find_fence_reg(dev);
2196 struct drm_i915_gem_object *old = reg->obj;
2198 ret = i915_gem_object_flush_fence(old);
2202 i915_gem_object_fence_lost(old);
2207 i915_gem_object_update_fence(obj, reg, enable);
2208 obj->fence_dirty = false;
2213 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2214 struct drm_mm_node *gtt_space,
2215 unsigned long cache_level)
2217 struct drm_mm_node *other;
2219 /* On non-LLC machines we have to be careful when putting differing
2220 * types of snoopable memory together to avoid the prefetcher
2221 * crossing memory domains and dieing.
2226 if (gtt_space == NULL)
2229 if (list_empty(>t_space->node_list))
2232 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2233 if (other->allocated && !other->hole_follows && other->color != cache_level)
2236 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2237 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2243 static void i915_gem_verify_gtt(struct drm_device *dev)
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247 struct drm_i915_gem_object *obj;
2250 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2251 if (obj->gtt_space == NULL) {
2252 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2257 if (obj->cache_level != obj->gtt_space->color) {
2258 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2259 obj->gtt_space->start,
2260 obj->gtt_space->start + obj->gtt_space->size,
2262 obj->gtt_space->color);
2267 if (!i915_gem_valid_gtt_space(dev,
2269 obj->cache_level)) {
2270 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2271 obj->gtt_space->start,
2272 obj->gtt_space->start + obj->gtt_space->size,
2284 * Finds free space in the GTT aperture and binds the object there.
2287 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2289 bool map_and_fenceable,
2292 struct drm_device *dev = obj->base.dev;
2293 drm_i915_private_t *dev_priv = dev->dev_private;
2294 struct drm_mm_node *free_space;
2295 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
2296 bool mappable, fenceable;
2299 if (obj->madv != I915_MADV_WILLNEED) {
2300 DRM_ERROR("Attempting to bind a purgeable object\n");
2304 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
2306 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
2308 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
2309 obj->base.size, obj->tiling_mode);
2311 alignment = map_and_fenceable ? fence_alignment :
2313 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
2314 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2318 size = map_and_fenceable ? fence_size : obj->base.size;
2320 /* If the object is bigger than the entire aperture, reject it early
2321 * before evicting everything in a vain attempt to find space.
2323 if (obj->base.size > (map_and_fenceable ?
2324 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2326 "Attempting to bind an object larger than the aperture\n");
2331 if (map_and_fenceable)
2333 drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2334 size, alignment, obj->cache_level,
2335 0, dev_priv->mm.gtt_mappable_end,
2338 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2339 size, alignment, obj->cache_level,
2342 if (free_space != NULL) {
2343 if (map_and_fenceable)
2345 drm_mm_get_block_range_generic(free_space,
2346 size, alignment, obj->cache_level,
2347 0, dev_priv->mm.gtt_mappable_end,
2351 drm_mm_get_block_generic(free_space,
2352 size, alignment, obj->cache_level,
2355 if (obj->gtt_space == NULL) {
2356 ret = i915_gem_evict_something(dev, size, alignment,
2367 * NOTE: i915_gem_object_get_pages_gtt() cannot
2368 * return ENOMEM, since we used VM_ALLOC_RETRY.
2370 ret = i915_gem_object_get_pages_gtt(obj);
2372 drm_mm_put_block(obj->gtt_space);
2373 obj->gtt_space = NULL;
2377 i915_gem_gtt_bind_object(obj, obj->cache_level);
2379 i915_gem_object_put_pages_gtt(obj);
2380 drm_mm_put_block(obj->gtt_space);
2381 obj->gtt_space = NULL;
2382 if (i915_gem_evict_everything(dev))
2387 list_add_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2388 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2390 obj->gtt_offset = obj->gtt_space->start;
2393 obj->gtt_space->size == fence_size &&
2394 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2397 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2398 obj->map_and_fenceable = mappable && fenceable;
2400 i915_gem_verify_gtt(dev);
2405 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2408 /* If we don't have a page list set up, then we're not pinned
2409 * to GPU, and we can ignore the cache flush because it'll happen
2410 * again at bind time.
2412 if (obj->pages == NULL)
2415 /* If the GPU is snooping the contents of the CPU cache,
2416 * we do not need to manually clear the CPU cache lines. However,
2417 * the caches are only snooped when the render cache is
2418 * flushed/invalidated. As we always have to emit invalidations
2419 * and flushes when moving into and out of the RENDER domain, correct
2420 * snooping behaviour occurs naturally as the result of our domain
2423 if (obj->cache_level != I915_CACHE_NONE)
2426 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2429 /** Flushes the GTT write domain for the object if it's dirty. */
2431 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2433 uint32_t old_write_domain;
2435 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2438 /* No actual flushing is required for the GTT write domain. Writes
2439 * to it immediately go to main memory as far as we know, so there's
2440 * no chipset flush. It also doesn't land in render cache.
2442 * However, we do have to enforce the order so that all writes through
2443 * the GTT land before any writes to the device, such as updates to
2448 old_write_domain = obj->base.write_domain;
2449 obj->base.write_domain = 0;
2452 /** Flushes the CPU write domain for the object if it's dirty. */
2454 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2456 uint32_t old_write_domain;
2458 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2461 i915_gem_clflush_object(obj);
2462 intel_gtt_chipset_flush();
2463 old_write_domain = obj->base.write_domain;
2464 obj->base.write_domain = 0;
2468 * Moves a single object to the GTT read, and possibly write domain.
2470 * This function returns when the move is complete, including waiting on
2474 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2476 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2477 uint32_t old_write_domain, old_read_domains;
2480 /* Not valid to be called on unbound objects. */
2481 if (obj->gtt_space == NULL)
2484 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2487 ret = i915_gem_object_wait_rendering(obj, !write);
2491 i915_gem_object_flush_cpu_write_domain(obj);
2493 old_write_domain = obj->base.write_domain;
2494 old_read_domains = obj->base.read_domains;
2496 /* It should now be out of any other write domains, and we can update
2497 * the domain values for our changes.
2499 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2500 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2502 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2503 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2507 /* And bump the LRU for this access */
2508 if (i915_gem_object_is_inactive(obj))
2509 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2514 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2515 enum i915_cache_level cache_level)
2517 struct drm_device *dev = obj->base.dev;
2518 drm_i915_private_t *dev_priv = dev->dev_private;
2521 if (obj->cache_level == cache_level)
2524 if (obj->pin_count) {
2525 DRM_DEBUG("can not change the cache level of pinned objects\n");
2529 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
2530 ret = i915_gem_object_unbind(obj);
2535 if (obj->gtt_space) {
2536 ret = i915_gem_object_finish_gpu(obj);
2540 i915_gem_object_finish_gtt(obj);
2542 /* Before SandyBridge, you could not use tiling or fence
2543 * registers with snooped memory, so relinquish any fences
2544 * currently pointing to our region in the aperture.
2546 if (INTEL_INFO(dev)->gen < 6) {
2547 ret = i915_gem_object_put_fence(obj);
2552 if (obj->has_global_gtt_mapping)
2553 i915_gem_gtt_bind_object(obj, cache_level);
2554 if (obj->has_aliasing_ppgtt_mapping)
2555 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2558 obj->gtt_space->color = cache_level;
2561 if (cache_level == I915_CACHE_NONE) {
2562 u32 old_read_domains, old_write_domain;
2564 /* If we're coming from LLC cached, then we haven't
2565 * actually been tracking whether the data is in the
2566 * CPU cache or not, since we only allow one bit set
2567 * in obj->write_domain and have been skipping the clflushes.
2568 * Just set it to the CPU cache for now.
2570 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2571 ("obj %p in CPU write domain", obj));
2572 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
2573 ("obj %p in CPU read domain", obj));
2575 old_read_domains = obj->base.read_domains;
2576 old_write_domain = obj->base.write_domain;
2578 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2579 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2583 obj->cache_level = cache_level;
2584 i915_gem_verify_gtt(dev);
2588 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2589 struct drm_file *file)
2591 struct drm_i915_gem_caching *args = data;
2592 struct drm_i915_gem_object *obj;
2595 ret = i915_mutex_lock_interruptible(dev);
2599 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2600 if (&obj->base == NULL) {
2605 args->caching = obj->cache_level != I915_CACHE_NONE;
2607 drm_gem_object_unreference(&obj->base);
2613 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2614 struct drm_file *file)
2616 struct drm_i915_gem_caching *args = data;
2617 struct drm_i915_gem_object *obj;
2618 enum i915_cache_level level;
2621 switch (args->caching) {
2622 case I915_CACHING_NONE:
2623 level = I915_CACHE_NONE;
2625 case I915_CACHING_CACHED:
2626 level = I915_CACHE_LLC;
2632 ret = i915_mutex_lock_interruptible(dev);
2636 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2637 if (&obj->base == NULL) {
2642 ret = i915_gem_object_set_cache_level(obj, level);
2644 drm_gem_object_unreference(&obj->base);
2651 * Prepare buffer for display plane (scanout, cursors, etc).
2652 * Can be called from an uninterruptible phase (modesetting) and allows
2653 * any flushes to be pipelined (for pageflips).
2656 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2658 struct intel_ring_buffer *pipelined)
2660 u32 old_read_domains, old_write_domain;
2663 if (pipelined != obj->ring) {
2664 ret = i915_gem_object_sync(obj, pipelined);
2669 /* The display engine is not coherent with the LLC cache on gen6. As
2670 * a result, we make sure that the pinning that is about to occur is
2671 * done with uncached PTEs. This is lowest common denominator for all
2674 * However for gen6+, we could do better by using the GFDT bit instead
2675 * of uncaching, which would allow us to flush all the LLC-cached data
2676 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2678 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2682 /* As the user may map the buffer once pinned in the display plane
2683 * (e.g. libkms for the bootup splash), we have to ensure that we
2684 * always use map_and_fenceable for all scanout buffers.
2686 ret = i915_gem_object_pin(obj, alignment, true, false);
2690 i915_gem_object_flush_cpu_write_domain(obj);
2692 old_write_domain = obj->base.write_domain;
2693 old_read_domains = obj->base.read_domains;
2695 /* It should now be out of any other write domains, and we can update
2696 * the domain values for our changes.
2698 obj->base.write_domain = 0;
2699 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2705 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2709 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2712 ret = i915_gem_object_wait_rendering(obj, false);
2716 /* Ensure that we invalidate the GPU's caches and TLBs. */
2717 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2722 * Moves a single object to the CPU read, and possibly write domain.
2724 * This function returns when the move is complete, including waiting on
2728 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2730 uint32_t old_write_domain, old_read_domains;
2733 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2736 ret = i915_gem_object_wait_rendering(obj, !write);
2740 i915_gem_object_flush_gtt_write_domain(obj);
2742 old_write_domain = obj->base.write_domain;
2743 old_read_domains = obj->base.read_domains;
2745 /* Flush the CPU cache if it's still invalid. */
2746 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2747 i915_gem_clflush_object(obj);
2749 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2752 /* It should now be out of any other write domains, and we can update
2753 * the domain values for our changes.
2755 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2757 /* If we're writing through the CPU, then the GPU read domains will
2758 * need to be invalidated at next use.
2761 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2762 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2768 /* Throttle our rendering by waiting until the ring has completed our requests
2769 * emitted over 20 msec ago.
2771 * Note that if we were to use the current jiffies each time around the loop,
2772 * we wouldn't escape the function with any frames outstanding if the time to
2773 * render a frame was over 20ms.
2775 * This should get us reasonable parallelism between CPU and GPU but also
2776 * relatively low latency when blocking on a particular request to finish.
2779 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct drm_i915_file_private *file_priv = file->driver_priv;
2783 unsigned long recent_enough = ticks - (20 * hz / 1000);
2784 struct drm_i915_gem_request *request;
2785 struct intel_ring_buffer *ring = NULL;
2789 if (atomic_read(&dev_priv->mm.wedged))
2792 spin_lock(&file_priv->mm.lock);
2793 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
2794 if (time_after_eq(request->emitted_jiffies, recent_enough))
2797 ring = request->ring;
2798 seqno = request->seqno;
2800 spin_unlock(&file_priv->mm.lock);
2805 ret = __wait_seqno(ring, seqno, true, NULL);
2808 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
2814 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2816 bool map_and_fenceable,
2821 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
2824 if (obj->gtt_space != NULL) {
2825 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
2826 (map_and_fenceable && !obj->map_and_fenceable)) {
2827 WARN(obj->pin_count,
2828 "bo is already pinned with incorrect alignment:"
2829 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
2830 " obj->map_and_fenceable=%d\n",
2831 obj->gtt_offset, alignment,
2833 obj->map_and_fenceable);
2834 ret = i915_gem_object_unbind(obj);
2840 if (obj->gtt_space == NULL) {
2841 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2843 ret = i915_gem_object_bind_to_gtt(obj, alignment,
2849 if (!dev_priv->mm.aliasing_ppgtt)
2850 i915_gem_gtt_bind_object(obj, obj->cache_level);
2853 if (!obj->has_global_gtt_mapping && map_and_fenceable)
2854 i915_gem_gtt_bind_object(obj, obj->cache_level);
2857 obj->pin_mappable |= map_and_fenceable;
2863 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
2865 BUG_ON(obj->pin_count == 0);
2866 BUG_ON(obj->gtt_space == NULL);
2868 if (--obj->pin_count == 0)
2869 obj->pin_mappable = false;
2873 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2874 struct drm_file *file)
2876 struct drm_i915_gem_pin *args = data;
2877 struct drm_i915_gem_object *obj;
2880 ret = i915_mutex_lock_interruptible(dev);
2884 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2885 if (&obj->base == NULL) {
2890 if (obj->madv != I915_MADV_WILLNEED) {
2891 DRM_ERROR("Attempting to pin a purgeable buffer\n");
2896 if (obj->pin_filp != NULL && obj->pin_filp != file) {
2897 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2903 if (obj->user_pin_count == 0) {
2904 ret = i915_gem_object_pin(obj, args->alignment, true, false);
2909 obj->user_pin_count++;
2910 obj->pin_filp = file;
2912 /* XXX - flush the CPU caches for pinned objects
2913 * as the X server doesn't manage domains yet
2915 i915_gem_object_flush_cpu_write_domain(obj);
2916 args->offset = obj->gtt_offset;
2918 drm_gem_object_unreference(&obj->base);
2925 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2926 struct drm_file *file)
2928 struct drm_i915_gem_pin *args = data;
2929 struct drm_i915_gem_object *obj;
2932 ret = i915_mutex_lock_interruptible(dev);
2936 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2937 if (&obj->base == NULL) {
2942 if (obj->pin_filp != file) {
2943 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2948 obj->user_pin_count--;
2949 if (obj->user_pin_count == 0) {
2950 obj->pin_filp = NULL;
2951 i915_gem_object_unpin(obj);
2955 drm_gem_object_unreference(&obj->base);
2962 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2963 struct drm_file *file)
2965 struct drm_i915_gem_busy *args = data;
2966 struct drm_i915_gem_object *obj;
2969 ret = i915_mutex_lock_interruptible(dev);
2973 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2974 if (&obj->base == NULL) {
2979 /* Count all active objects as busy, even if they are currently not used
2980 * by the gpu. Users of this interface expect objects to eventually
2981 * become non-busy without any further actions, therefore emit any
2982 * necessary flushes here.
2984 ret = i915_gem_object_flush_active(obj);
2986 args->busy = obj->active;
2988 args->busy |= intel_ring_flag(obj->ring) << 17;
2991 drm_gem_object_unreference(&obj->base);
2998 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2999 struct drm_file *file_priv)
3001 return i915_gem_ring_throttle(dev, file_priv);
3005 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3006 struct drm_file *file_priv)
3008 struct drm_i915_gem_madvise *args = data;
3009 struct drm_i915_gem_object *obj;
3012 switch (args->madv) {
3013 case I915_MADV_DONTNEED:
3014 case I915_MADV_WILLNEED:
3020 ret = i915_mutex_lock_interruptible(dev);
3024 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3025 if (&obj->base == NULL) {
3030 if (obj->pin_count) {
3035 if (obj->madv != __I915_MADV_PURGED)
3036 obj->madv = args->madv;
3038 /* if the object is no longer attached, discard its backing storage */
3039 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3040 i915_gem_object_truncate(obj);
3042 args->retained = obj->madv != __I915_MADV_PURGED;
3045 drm_gem_object_unreference(&obj->base);
3051 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3052 const struct drm_i915_gem_object_ops *ops)
3054 INIT_LIST_HEAD(&obj->mm_list);
3055 INIT_LIST_HEAD(&obj->gtt_list);
3056 INIT_LIST_HEAD(&obj->ring_list);
3057 INIT_LIST_HEAD(&obj->exec_list);
3061 obj->fence_reg = I915_FENCE_REG_NONE;
3062 obj->madv = I915_MADV_WILLNEED;
3063 /* Avoid an unnecessary call to unbind on the first bind. */
3064 obj->map_and_fenceable = true;
3066 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3069 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3070 .get_pages = i915_gem_object_get_pages_gtt,
3071 .put_pages = i915_gem_object_put_pages_gtt,
3074 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3077 struct drm_i915_gem_object *obj;
3079 struct address_space *mapping;
3083 obj = kmalloc(sizeof(*obj), M_DRM, M_WAITOK | M_ZERO);
3087 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3093 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3094 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3095 /* 965gm cannot relocate objects above 4GiB. */
3096 mask &= ~__GFP_HIGHMEM;
3097 mask |= __GFP_DMA32;
3100 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3101 mapping_set_gfp_mask(mapping, mask);
3104 i915_gem_object_init(obj, &i915_gem_object_ops);
3106 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3107 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3110 /* On some devices, we can have the GPU use the LLC (the CPU
3111 * cache) for about a 10% performance improvement
3112 * compared to uncached. Graphics requests other than
3113 * display scanout are coherent with the CPU in
3114 * accessing this cache. This means in this mode we
3115 * don't need to clflush on the CPU side, and on the
3116 * GPU side we only need to flush internal caches to
3117 * get data visible to the CPU.
3119 * However, we maintain the display planes as UC, and so
3120 * need to rebind when first used as such.
3122 obj->cache_level = I915_CACHE_LLC;
3124 obj->cache_level = I915_CACHE_NONE;
3129 int i915_gem_init_object(struct drm_gem_object *obj)
3136 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3138 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3139 struct drm_device *dev = obj->base.dev;
3140 drm_i915_private_t *dev_priv = dev->dev_private;
3143 i915_gem_detach_phys_object(dev, obj);
3146 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3147 bool was_interruptible;
3149 was_interruptible = dev_priv->mm.interruptible;
3150 dev_priv->mm.interruptible = false;
3152 WARN_ON(i915_gem_object_unbind(obj));
3154 dev_priv->mm.interruptible = was_interruptible;
3157 drm_gem_free_mmap_offset(&obj->base);
3159 drm_gem_object_release(&obj->base);
3160 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3162 drm_free(obj->bit_17, M_DRM);
3163 drm_free(obj, M_DRM);
3167 i915_gem_do_init(struct drm_device *dev, unsigned long start,
3168 unsigned long mappable_end, unsigned long end)
3170 drm_i915_private_t *dev_priv;
3171 unsigned long mappable;
3174 dev_priv = dev->dev_private;
3175 mappable = min(end, mappable_end) - start;
3177 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
3179 dev_priv->mm.gtt_start = start;
3180 dev_priv->mm.gtt_mappable_end = mappable_end;
3181 dev_priv->mm.gtt_end = end;
3182 dev_priv->mm.gtt_total = end - start;
3183 dev_priv->mm.mappable_gtt_total = mappable;
3185 /* Take over this portion of the GTT */
3186 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
3187 device_printf(dev->dev,
3188 "taking over the fictitious range 0x%lx-0x%lx\n",
3189 dev->agp->base + start, dev->agp->base + start + mappable);
3190 error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
3191 dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
3196 i915_gem_idle(struct drm_device *dev)
3198 drm_i915_private_t *dev_priv = dev->dev_private;
3203 if (dev_priv->mm.suspended) {
3208 ret = i915_gpu_idle(dev);
3213 i915_gem_retire_requests(dev);
3215 /* Under UMS, be paranoid and evict. */
3216 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3217 i915_gem_evict_everything(dev);
3219 i915_gem_reset_fences(dev);
3221 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3222 * We need to replace this with a semaphore, or something.
3223 * And not confound mm.suspended!
3225 dev_priv->mm.suspended = 1;
3226 del_timer_sync(&dev_priv->hangcheck_timer);
3228 i915_kernel_lost_context(dev);
3229 i915_gem_cleanup_ringbuffer(dev);
3233 /* Cancel the retire work handler, which should be idle now. */
3234 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3239 void i915_gem_l3_remap(struct drm_device *dev)
3241 drm_i915_private_t *dev_priv = dev->dev_private;
3245 if (!HAS_L3_GPU_CACHE(dev))
3248 if (!dev_priv->l3_parity.remap_info)
3251 misccpctl = I915_READ(GEN7_MISCCPCTL);
3252 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3253 POSTING_READ(GEN7_MISCCPCTL);
3255 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3256 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3257 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3258 DRM_DEBUG("0x%x was already programmed to %x\n",
3259 GEN7_L3LOG_BASE + i, remap);
3260 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3261 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3262 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3265 /* Make sure all the writes land before disabling dop clock gating */
3266 POSTING_READ(GEN7_L3LOG_BASE);
3268 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3271 void i915_gem_init_swizzling(struct drm_device *dev)
3273 drm_i915_private_t *dev_priv = dev->dev_private;
3275 if (INTEL_INFO(dev)->gen < 5 ||
3276 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3279 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3280 DISP_TILE_SURFACE_SWIZZLING);
3285 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3287 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3289 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3293 intel_enable_blt(struct drm_device *dev)
3300 /* The blitter was dysfunctional on early prototypes */
3301 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
3302 if (IS_GEN6(dev) && revision < 8) {
3303 DRM_INFO("BLT not supported on this pre-production hardware;"
3304 " graphics performance will be degraded.\n");
3312 i915_gem_init_hw(struct drm_device *dev)
3314 drm_i915_private_t *dev_priv = dev->dev_private;
3317 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3318 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3320 i915_gem_l3_remap(dev);
3322 i915_gem_init_swizzling(dev);
3324 ret = intel_init_render_ring_buffer(dev);
3329 ret = intel_init_bsd_ring_buffer(dev);
3331 goto cleanup_render_ring;
3334 if (intel_enable_blt(dev)) {
3335 ret = intel_init_blt_ring_buffer(dev);
3337 goto cleanup_bsd_ring;
3340 dev_priv->next_seqno = 1;
3343 * XXX: There was some w/a described somewhere suggesting loading
3344 * contexts before PPGTT.
3346 i915_gem_context_init(dev);
3347 i915_gem_init_ppgtt(dev);
3352 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3353 cleanup_render_ring:
3354 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3359 intel_enable_ppgtt(struct drm_device *dev)
3361 if (i915_enable_ppgtt >= 0)
3362 return i915_enable_ppgtt;
3364 /* Disable ppgtt on SNB if VT-d is on. */
3365 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
3371 int i915_gem_init(struct drm_device *dev)
3373 struct drm_i915_private *dev_priv = dev->dev_private;
3374 unsigned long prealloc_size, gtt_size, mappable_size;
3377 prealloc_size = dev_priv->mm.gtt->stolen_size;
3378 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3379 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3381 /* Basic memrange allocator for stolen space */
3382 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
3385 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3386 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3387 * aperture accordingly when using aliasing ppgtt. */
3388 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3389 /* For paranoia keep the guard page in between. */
3390 gtt_size -= PAGE_SIZE;
3392 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
3394 ret = i915_gem_init_aliasing_ppgtt(dev);
3400 /* Let GEM Manage all of the aperture.
3402 * However, leave one page at the end still bound to the scratch
3403 * page. There are a number of places where the hardware
3404 * apparently prefetches past the end of the object, and we've
3405 * seen multiple hangs with the GPU head pointer stuck in a
3406 * batchbuffer bound at the last page of the aperture. One page
3407 * should be enough to keep any prefetching inside of the
3410 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
3413 ret = i915_gem_init_hw(dev);
3416 i915_gem_cleanup_aliasing_ppgtt(dev);
3421 /* Try to set up FBC with a reasonable compressed buffer size */
3422 if (I915_HAS_FBC(dev) && i915_powersave) {
3425 /* Leave 1M for line length buffer & misc. */
3427 /* Try to get a 32M buffer... */
3428 if (prealloc_size > (36*1024*1024))
3429 cfb_size = 32*1024*1024;
3430 else /* fall back to 7/8 of the stolen space */
3431 cfb_size = prealloc_size * 7 / 8;
3432 i915_setup_compression(dev, cfb_size);
3436 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3437 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3438 dev_priv->dri1.allow_batchbuffer = 1;
3443 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3445 drm_i915_private_t *dev_priv = dev->dev_private;
3446 struct intel_ring_buffer *ring;
3449 for_each_ring(ring, dev_priv, i)
3450 intel_cleanup_ring_buffer(ring);
3454 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3455 struct drm_file *file_priv)
3457 drm_i915_private_t *dev_priv = dev->dev_private;
3460 if (drm_core_check_feature(dev, DRIVER_MODESET))
3463 if (atomic_read(&dev_priv->mm.wedged)) {
3464 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3465 atomic_set(&dev_priv->mm.wedged, 0);
3469 dev_priv->mm.suspended = 0;
3471 ret = i915_gem_init_hw(dev);
3477 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
3480 ret = drm_irq_install(dev);
3482 goto cleanup_ringbuffer;
3488 i915_gem_cleanup_ringbuffer(dev);
3489 dev_priv->mm.suspended = 1;
3496 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3497 struct drm_file *file_priv)
3499 if (drm_core_check_feature(dev, DRIVER_MODESET))
3502 drm_irq_uninstall(dev);
3503 return i915_gem_idle(dev);
3507 i915_gem_lastclose(struct drm_device *dev)
3511 if (drm_core_check_feature(dev, DRIVER_MODESET))
3514 ret = i915_gem_idle(dev);
3516 DRM_ERROR("failed to idle hardware: %d\n", ret);
3520 init_ring_lists(struct intel_ring_buffer *ring)
3522 INIT_LIST_HEAD(&ring->active_list);
3523 INIT_LIST_HEAD(&ring->request_list);
3527 i915_gem_load(struct drm_device *dev)
3530 drm_i915_private_t *dev_priv = dev->dev_private;
3532 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3533 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3534 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3535 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
3536 for (i = 0; i < I915_NUM_RINGS; i++)
3537 init_ring_lists(&dev_priv->ring[i]);
3538 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3539 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3540 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3541 i915_gem_retire_work_handler);
3542 init_completion(&dev_priv->error_completion);
3544 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3546 I915_WRITE(MI_ARB_STATE,
3547 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3550 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3552 /* Old X drivers will take 0-2 for front, back, depth buffers */
3553 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3554 dev_priv->fence_reg_start = 3;
3556 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3557 dev_priv->num_fence_regs = 16;
3559 dev_priv->num_fence_regs = 8;
3561 /* Initialize fence registers to zero */
3562 i915_gem_reset_fences(dev);
3564 i915_gem_detect_bit_6_swizzle(dev);
3565 init_waitqueue_head(&dev_priv->pending_flip_queue);
3567 dev_priv->mm.interruptible = true;
3570 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3571 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3572 register_shrinker(&dev_priv->mm.inactive_shrinker);
3574 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
3575 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
3580 * Create a physically contiguous memory object for this object
3581 * e.g. for cursor + overlay regs
3583 static int i915_gem_init_phys_object(struct drm_device *dev,
3584 int id, int size, int align)
3586 drm_i915_private_t *dev_priv = dev->dev_private;
3587 struct drm_i915_gem_phys_object *phys_obj;
3590 if (dev_priv->mm.phys_objs[id - 1] || !size)
3593 phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), M_DRM,
3600 phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3601 if (!phys_obj->handle) {
3605 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3606 size / PAGE_SIZE, PAT_WRITE_COMBINING);
3608 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3613 drm_free(phys_obj, M_DRM);
3617 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3619 drm_i915_private_t *dev_priv = dev->dev_private;
3620 struct drm_i915_gem_phys_object *phys_obj;
3622 if (!dev_priv->mm.phys_objs[id - 1])
3625 phys_obj = dev_priv->mm.phys_objs[id - 1];
3626 if (phys_obj->cur_obj) {
3627 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3630 drm_pci_free(dev, phys_obj->handle);
3631 drm_free(phys_obj, M_DRM);
3632 dev_priv->mm.phys_objs[id - 1] = NULL;
3635 void i915_gem_free_all_phys_object(struct drm_device *dev)
3639 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3640 i915_gem_free_phys_object(dev, i);
3643 void i915_gem_detach_phys_object(struct drm_device *dev,
3644 struct drm_i915_gem_object *obj)
3646 struct vm_object *mapping = obj->base.vm_obj;
3653 vaddr = obj->phys_obj->handle->vaddr;
3655 page_count = obj->base.size / PAGE_SIZE;
3656 VM_OBJECT_LOCK(obj->base.vm_obj);
3657 for (i = 0; i < page_count; i++) {
3658 struct vm_page *page = shmem_read_mapping_page(mapping, i);
3659 if (!IS_ERR(page)) {
3660 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3661 char *dst = kmap_atomic(page);
3662 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3665 drm_clflush_pages(&page, 1);
3668 set_page_dirty(page);
3669 mark_page_accessed(page);
3670 page_cache_release(page);
3672 VM_OBJECT_LOCK(obj->base.vm_obj);
3673 vm_page_reference(page);
3674 vm_page_dirty(page);
3675 vm_page_busy_wait(page, FALSE, "i915gem");
3676 vm_page_unwire(page, 0);
3677 vm_page_wakeup(page);
3680 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3681 intel_gtt_chipset_flush();
3683 obj->phys_obj->cur_obj = NULL;
3684 obj->phys_obj = NULL;
3688 i915_gem_attach_phys_object(struct drm_device *dev,
3689 struct drm_i915_gem_object *obj,
3693 struct vm_object *mapping = obj->base.vm_obj;
3694 drm_i915_private_t *dev_priv = dev->dev_private;
3699 if (id > I915_MAX_PHYS_OBJECT)
3702 if (obj->phys_obj) {
3703 if (obj->phys_obj->id == id)
3705 i915_gem_detach_phys_object(dev, obj);
3708 /* create a new object */
3709 if (!dev_priv->mm.phys_objs[id - 1]) {
3710 ret = i915_gem_init_phys_object(dev, id,
3711 obj->base.size, align);
3713 DRM_ERROR("failed to init phys object %d size: %zu\n",
3714 id, obj->base.size);
3719 /* bind to the object */
3720 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3721 obj->phys_obj->cur_obj = obj;
3723 page_count = obj->base.size / PAGE_SIZE;
3725 VM_OBJECT_LOCK(obj->base.vm_obj);
3726 for (i = 0; i < page_count; i++) {
3727 struct vm_page *page;
3730 page = shmem_read_mapping_page(mapping, i);
3731 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3733 return PTR_ERR(page);
3735 src = kmap_atomic(page);
3736 dst = (char*)obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3737 memcpy(dst, src, PAGE_SIZE);
3741 mark_page_accessed(page);
3742 page_cache_release(page);
3744 VM_OBJECT_LOCK(obj->base.vm_obj);
3745 vm_page_reference(page);
3746 vm_page_busy_wait(page, FALSE, "i915gem");
3747 vm_page_unwire(page, 0);
3748 vm_page_wakeup(page);
3750 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3756 i915_gem_phys_pwrite(struct drm_device *dev,
3757 struct drm_i915_gem_object *obj,
3758 struct drm_i915_gem_pwrite *args,
3759 struct drm_file *file_priv)
3761 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
3762 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
3764 if (copyin_nofault(user_data, vaddr, args->size) != 0) {
3765 unsigned long unwritten;
3767 /* The physical object once assigned is fixed for the lifetime
3768 * of the obj, so we can safely drop the lock and continue
3772 unwritten = copy_from_user(vaddr, user_data, args->size);
3778 i915_gem_chipset_flush(dev);
3782 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3784 struct drm_i915_file_private *file_priv = file->driver_priv;
3786 /* Clean up our request list when the client is going away, so that
3787 * later retire_requests won't dereference our soon-to-be-gone
3790 spin_lock(&file_priv->mm.lock);
3791 while (!list_empty(&file_priv->mm.request_list)) {
3792 struct drm_i915_gem_request *request;
3794 request = list_first_entry(&file_priv->mm.request_list,
3795 struct drm_i915_gem_request,
3797 list_del(&request->client_list);
3798 request->file_priv = NULL;
3800 spin_unlock(&file_priv->mm.lock);
3804 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
3805 vm_ooffset_t foff, struct ucred *cred, u_short *color)
3808 *color = 0; /* XXXKIB */
3815 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
3818 struct drm_gem_object *gem_obj;
3819 struct drm_i915_gem_object *obj;
3820 struct drm_device *dev;
3821 drm_i915_private_t *dev_priv;
3826 gem_obj = vm_obj->handle;
3827 obj = to_intel_bo(gem_obj);
3828 dev = obj->base.dev;
3829 dev_priv = dev->dev_private;
3831 write = (prot & VM_PROT_WRITE) != 0;
3835 vm_object_pip_add(vm_obj, 1);
3838 * Remove the placeholder page inserted by vm_fault() from the
3839 * object before dropping the object lock. If
3840 * i915_gem_release_mmap() is active in parallel on this gem
3841 * object, then it owns the drm device sx and might find the
3842 * placeholder already. Then, since the page is busy,
3843 * i915_gem_release_mmap() sleeps waiting for the busy state
3844 * of the page cleared. We will be not able to acquire drm
3845 * device lock until i915_gem_release_mmap() is able to make a
3848 if (*mres != NULL) {
3850 vm_page_remove(oldm);
3855 VM_OBJECT_UNLOCK(vm_obj);
3861 ret = i915_mutex_lock_interruptible(dev);
3870 * Since the object lock was dropped, other thread might have
3871 * faulted on the same GTT address and instantiated the
3872 * mapping for the page. Recheck.
3874 VM_OBJECT_LOCK(vm_obj);
3875 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
3877 if ((m->flags & PG_BUSY) != 0) {
3880 vm_page_sleep(m, "915pee");
3886 VM_OBJECT_UNLOCK(vm_obj);
3888 /* Now bind it into the GTT if needed */
3889 if (!obj->map_and_fenceable) {
3890 ret = i915_gem_object_unbind(obj);
3896 if (!obj->gtt_space) {
3897 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
3903 ret = i915_gem_object_set_to_gtt_domain(obj, write);
3910 if (obj->tiling_mode == I915_TILING_NONE)
3911 ret = i915_gem_object_put_fence(obj);
3913 ret = i915_gem_object_get_fence(obj);
3919 if (i915_gem_object_is_inactive(obj))
3920 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3922 obj->fault_mappable = true;
3923 VM_OBJECT_LOCK(vm_obj);
3924 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
3931 KASSERT((m->flags & PG_FICTITIOUS) != 0,
3932 ("not fictitious %p", m));
3933 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
3935 if ((m->flags & PG_BUSY) != 0) {
3938 vm_page_sleep(m, "915pbs");
3942 m->valid = VM_PAGE_BITS_ALL;
3943 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
3946 vm_page_busy_try(m, false);
3952 vm_object_pip_wakeup(vm_obj);
3953 return (VM_PAGER_OK);
3958 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
3959 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
3960 goto unlocked_vmobj;
3962 VM_OBJECT_LOCK(vm_obj);
3963 vm_object_pip_wakeup(vm_obj);
3964 return (VM_PAGER_ERROR);
3968 i915_gem_pager_dtor(void *handle)
3970 struct drm_gem_object *obj;
3971 struct drm_device *dev;
3977 drm_gem_free_mmap_offset(obj);
3978 i915_gem_release_mmap(to_intel_bo(obj));
3979 drm_gem_object_unreference(obj);
3983 struct cdev_pager_ops i915_gem_pager_ops = {
3984 .cdev_pg_fault = i915_gem_pager_fault,
3985 .cdev_pg_ctor = i915_gem_pager_ctor,
3986 .cdev_pg_dtor = i915_gem_pager_dtor
3989 #define GEM_PARANOID_CHECK_GTT 0
3990 #if GEM_PARANOID_CHECK_GTT
3992 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
3995 struct drm_i915_private *dev_priv;
3997 unsigned long start, end;
4001 dev_priv = dev->dev_private;
4002 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
4003 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
4004 for (i = start; i < end; i++) {
4005 pa = intel_gtt_read_pte_paddr(i);
4006 for (j = 0; j < page_count; j++) {
4007 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
4008 panic("Page %p in GTT pte index %d pte %x",
4009 ma[i], i, intel_gtt_read_pte(i));
4016 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
4019 shmem_read_mapping_page(vm_object_t object, vm_pindex_t pindex)
4024 VM_OBJECT_LOCK_ASSERT_OWNED(object);
4025 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
4026 if (m->valid != VM_PAGE_BITS_ALL) {
4027 if (vm_pager_has_page(object, pindex)) {
4028 rv = vm_pager_get_page(object, &m, 1);
4029 m = vm_page_lookup(object, pindex);
4031 return ERR_PTR(-ENOMEM);
4032 if (rv != VM_PAGER_OK) {
4034 return ERR_PTR(-ENOMEM);
4037 pmap_zero_page(VM_PAGE_TO_PHYS(m));
4038 m->valid = VM_PAGE_BITS_ALL;
4048 i915_gpu_is_active(struct drm_device *dev)
4050 drm_i915_private_t *dev_priv = dev->dev_private;
4052 return !list_empty(&dev_priv->mm.active_list);
4056 i915_gem_lowmem(void *arg)
4058 struct drm_device *dev;
4059 struct drm_i915_private *dev_priv;
4060 struct drm_i915_gem_object *obj, *next;
4061 int cnt, cnt_fail, cnt_total;
4064 dev_priv = dev->dev_private;
4066 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
4070 /* first scan for clean buffers */
4071 i915_gem_retire_requests(dev);
4073 cnt_total = cnt_fail = cnt = 0;
4075 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4077 if (i915_gem_object_is_purgeable(obj)) {
4078 if (i915_gem_object_unbind(obj) != 0)
4084 /* second pass, evict/count anything still on the inactive list */
4085 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4087 if (i915_gem_object_unbind(obj) == 0)
4093 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
4095 * We are desperate for pages, so as a last resort, wait
4096 * for the GPU to finish and discard whatever we can.
4097 * This has a dramatic impact to reduce the number of
4098 * OOM-killer events whilst running the GPU aggressively.
4100 if (i915_gpu_idle(dev) == 0)
4107 i915_gem_unload(struct drm_device *dev)
4109 struct drm_i915_private *dev_priv;
4111 dev_priv = dev->dev_private;
4112 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);