sys/dev/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *
  28  * $FreeBSD: head/sys/dev/drm2/radeon/r420.c 254885 2013-08-25 19:37:15Z dumbbell $
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "atom.h"
  36 #include "r100d.h"
  37 #include "r420d.h"
  38 #include "r420_reg_safe.h"
  39
  40 void r420_pm_init_profile(struct radeon_device *rdev)
  41 {
  42         /* default */
  43         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  44         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  45         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  46         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  47         /* low sh */
  48         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
  49         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
  50         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  51         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  52         /* mid sh */
  53         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
  54         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
  55         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  56         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
  57         /* high sh */
  58         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
  59         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  60         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  61         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
  62         /* low mh */
  63         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
  64         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  65         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  66         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  67         /* mid mh */
  68         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
  69         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  70         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  71         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
  72         /* high mh */
  73         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
  74         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  75         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  76         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
  77 }
  78
  79 static void r420_set_reg_safe(struct radeon_device *rdev)
  80 {
  81         rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
  82         rdev->config.r300.reg_safe_bm_size = DRM_ARRAY_SIZE(r420_reg_safe_bm);
  83 }
  84
  85 void r420_pipes_init(struct radeon_device *rdev)
  86 {
  87         unsigned tmp;
  88         unsigned gb_pipe_select;
  89         unsigned num_pipes;
  90
  91         /* GA_ENHANCE workaround TCL deadlock issue */
  92         WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
  93                (1 << 2) | (1 << 3));
  94         /* add idle wait as per freedesktop.org bug 24041 */
  95         if (r100_gui_wait_for_idle(rdev)) {
  96                 DRM_ERROR("Failed to wait GUI idle while "
  97                        "programming pipes. Bad things might happen.\n");
  98         }
  99         /* get max number of pipes */
 100         gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
 101         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
 102
 103         /* SE chips have 1 pipe */
 104         if ((rdev->ddev->pci_device == 0x5e4c) ||
 105             (rdev->ddev->pci_device == 0x5e4f))
 106                 num_pipes = 1;
 107
 108         rdev->num_gb_pipes = num_pipes;
 109         tmp = 0;
 110         switch (num_pipes) {
 111         default:
 112                 /* force to 1 pipe */
 113                 num_pipes = 1;
 114         case 1:
 115                 tmp = (0 << 1);
 116                 break;
 117         case 2:
 118                 tmp = (3 << 1);
 119                 break;
 120         case 3:
 121                 tmp = (6 << 1);
 122                 break;
 123         case 4:
 124                 tmp = (7 << 1);
 125                 break;
 126         }
 127         WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
 128         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 129         tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
 130         WREG32(R300_GB_TILE_CONFIG, tmp);
 131         if (r100_gui_wait_for_idle(rdev)) {
 132                 DRM_ERROR("Failed to wait GUI idle while "
 133                        "programming pipes. Bad things might happen.\n");
 134         }
 135
 136         tmp = RREG32(R300_DST_PIPE_CONFIG);
 137         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 138
 139         WREG32(R300_RB2D_DSTCACHE_MODE,
 140                RREG32(R300_RB2D_DSTCACHE_MODE) |
 141                R300_DC_AUTOFLUSH_ENABLE |
 142                R300_DC_DC_DISABLE_IGNORE_PE);
 143
 144         if (r100_gui_wait_for_idle(rdev)) {
 145                 DRM_ERROR("Failed to wait GUI idle while "
 146                        "programming pipes. Bad things might happen.\n");
 147         }
 148
 149         if (rdev->family == CHIP_RV530) {
 150                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 151                 if ((tmp & 3) == 3)
 152                         rdev->num_z_pipes = 2;
 153                 else
 154                         rdev->num_z_pipes = 1;
 155         } else
 156                 rdev->num_z_pipes = 1;
 157
 158         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 159                  rdev->num_gb_pipes, rdev->num_z_pipes);
 160 }
 161
 162 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 163 {
 164         u32 r;
 165
 166         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 167         r = RREG32(R_0001FC_MC_IND_DATA);
 168         return r;
 169 }
 170
 171 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 172 {
 173         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 174                 S_0001F8_MC_IND_WR_EN(1));
 175         WREG32(R_0001FC_MC_IND_DATA, v);
 176 }
 177
 178 static void r420_debugfs(struct radeon_device *rdev)
 179 {
 180         if (r100_debugfs_rbbm_init(rdev)) {
 181                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 182         }
 183         if (r420_debugfs_pipes_info_init(rdev)) {
 184                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 185         }
 186 }
 187
 188 static void r420_clock_resume(struct radeon_device *rdev)
 189 {
 190         u32 sclk_cntl;
 191
 192         if (radeon_dynclks != -1 && radeon_dynclks)
 193                 radeon_atom_set_clock_gating(rdev, 1);
 194         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 195         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 196         if (rdev->family == CHIP_R420)
 197                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 198         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 199 }
 200
 201 static void r420_cp_errata_init(struct radeon_device *rdev)
 202 {
 203         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 204
 205         /* RV410 and R420 can lock up if CP DMA to host memory happens
 206          * while the 2D engine is busy.
 207          *
 208          * The proper workaround is to queue a RESYNC at the beginning
 209          * of the CP init, apparently.
 210          */
 211         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
 212         radeon_ring_lock(rdev, ring, 8);
 213         radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
 214         radeon_ring_write(ring, rdev->config.r300.resync_scratch);
 215         radeon_ring_write(ring, 0xDEADBEEF);
 216         radeon_ring_unlock_commit(rdev, ring);
 217 }
 218
 219 static void r420_cp_errata_fini(struct radeon_device *rdev)
 220 {
 221         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 222
 223         /* Catch the RESYNC we dispatched all the way back,
 224          * at the very beginning of the CP init.
 225          */
 226         radeon_ring_lock(rdev, ring, 8);
 227         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 228         radeon_ring_write(ring, R300_RB3D_DC_FINISH);
 229         radeon_ring_unlock_commit(rdev, ring);
 230         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 231 }
 232
 233 static int r420_startup(struct radeon_device *rdev)
 234 {
 235         int r;
 236
 237         /* set common regs */
 238         r100_set_common_regs(rdev);
 239         /* program mc */
 240         r300_mc_program(rdev);
 241         /* Resume clock */
 242         r420_clock_resume(rdev);
 243         /* Initialize GART (initialize after TTM so we can allocate
 244          * memory through TTM but finalize after TTM) */
 245         if (rdev->flags & RADEON_IS_PCIE) {
 246                 r = rv370_pcie_gart_enable(rdev);
 247                 if (r)
 248                         return r;
 249         }
 250         if (rdev->flags & RADEON_IS_PCI) {
 251                 r = r100_pci_gart_enable(rdev);
 252                 if (r)
 253                         return r;
 254         }
 255         r420_pipes_init(rdev);
 256
 257         /* allocate wb buffer */
 258         r = radeon_wb_init(rdev);
 259         if (r)
 260                 return r;
 261
 262         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 263         if (r) {
 264                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 265                 return r;
 266         }
 267
 268         /* Enable IRQ */
 269         if (!rdev->irq.installed) {
 270                 r = radeon_irq_kms_init(rdev);
 271                 if (r)
 272                         return r;
 273         }
 274
 275         r100_irq_set(rdev);
 276         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 277         /* 1M ring buffer */
 278         r = r100_cp_init(rdev, 1024 * 1024);
 279         if (r) {
 280                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 281                 return r;
 282         }
 283         r420_cp_errata_init(rdev);
 284
 285         r = radeon_ib_pool_init(rdev);
 286         if (r) {
 287                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 288                 return r;
 289         }
 290
 291         return 0;
 292 }
 293
 294 int r420_resume(struct radeon_device *rdev)
 295 {
 296         int r;
 297
 298         /* Make sur GART are not working */
 299         if (rdev->flags & RADEON_IS_PCIE)
 300                 rv370_pcie_gart_disable(rdev);
 301         if (rdev->flags & RADEON_IS_PCI)
 302                 r100_pci_gart_disable(rdev);
 303         /* Resume clock before doing reset */
 304         r420_clock_resume(rdev);
 305         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 306         if (radeon_asic_reset(rdev)) {
 307                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 308                         RREG32(R_000E40_RBBM_STATUS),
 309                         RREG32(R_0007C0_CP_STAT));
 310         }
 311         /* check if cards are posted or not */
 312         if (rdev->is_atom_bios) {
 313                 atom_asic_init(rdev->mode_info.atom_context);
 314         } else {
 315                 radeon_combios_asic_init(rdev->ddev);
 316         }
 317         /* Resume clock after posting */
 318         r420_clock_resume(rdev);
 319         /* Initialize surface registers */
 320         radeon_surface_init(rdev);
 321
 322         rdev->accel_working = true;
 323         r = r420_startup(rdev);
 324         if (r) {
 325                 rdev->accel_working = false;
 326         }
 327         return r;
 328 }
 329
 330 int r420_suspend(struct radeon_device *rdev)
 331 {
 332         r420_cp_errata_fini(rdev);
 333         r100_cp_disable(rdev);
 334         radeon_wb_disable(rdev);
 335         r100_irq_disable(rdev);
 336         if (rdev->flags & RADEON_IS_PCIE)
 337                 rv370_pcie_gart_disable(rdev);
 338         if (rdev->flags & RADEON_IS_PCI)
 339                 r100_pci_gart_disable(rdev);
 340         return 0;
 341 }
 342
 343 void r420_fini(struct radeon_device *rdev)
 344 {
 345         r100_cp_fini(rdev);
 346         radeon_wb_fini(rdev);
 347         radeon_ib_pool_fini(rdev);
 348         radeon_gem_fini(rdev);
 349         if (rdev->flags & RADEON_IS_PCIE)
 350                 rv370_pcie_gart_fini(rdev);
 351         if (rdev->flags & RADEON_IS_PCI)
 352                 r100_pci_gart_fini(rdev);
 353         radeon_agp_fini(rdev);
 354         radeon_irq_kms_fini(rdev);
 355         radeon_fence_driver_fini(rdev);
 356         radeon_bo_fini(rdev);
 357         if (rdev->is_atom_bios) {
 358                 radeon_atombios_fini(rdev);
 359         } else {
 360                 radeon_combios_fini(rdev);
 361         }
 362         drm_free(rdev->bios, M_DRM);
 363         rdev->bios = NULL;
 364 }
 365
 366 int r420_init(struct radeon_device *rdev)
 367 {
 368         int r;
 369
 370         /* Initialize scratch registers */
 371         radeon_scratch_init(rdev);
 372         /* Initialize surface registers */
 373         radeon_surface_init(rdev);
 374         /* TODO: disable VGA need to use VGA request */
 375         /* restore some register to sane defaults */
 376         r100_restore_sanity(rdev);
 377         /* BIOS*/
 378         if (!radeon_get_bios(rdev)) {
 379                 if (ASIC_IS_AVIVO(rdev))
 380                         return -EINVAL;
 381         }
 382         if (rdev->is_atom_bios) {
 383                 r = radeon_atombios_init(rdev);
 384                 if (r) {
 385                         return r;
 386                 }
 387         } else {
 388                 r = radeon_combios_init(rdev);
 389                 if (r) {
 390                         return r;
 391                 }
 392         }
 393         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 394         if (radeon_asic_reset(rdev)) {
 395                 dev_warn(rdev->dev,
 396                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 397                         RREG32(R_000E40_RBBM_STATUS),
 398                         RREG32(R_0007C0_CP_STAT));
 399         }
 400         /* check if cards are posted or not */
 401         if (radeon_boot_test_post_card(rdev) == false)
 402                 return -EINVAL;
 403
 404         /* Initialize clocks */
 405         radeon_get_clock_info(rdev->ddev);
 406         /* initialize AGP */
 407         if (rdev->flags & RADEON_IS_AGP) {
 408                 r = radeon_agp_init(rdev);
 409                 if (r) {
 410                         radeon_agp_disable(rdev);
 411                 }
 412         }
 413         /* initialize memory controller */
 414         r300_mc_init(rdev);
 415         r420_debugfs(rdev);
 416         /* Fence driver */
 417         r = radeon_fence_driver_init(rdev);
 418         if (r) {
 419                 return r;
 420         }
 421         /* Memory manager */
 422         r = radeon_bo_init(rdev);
 423         if (r) {
 424                 return r;
 425         }
 426         if (rdev->family == CHIP_R420)
 427                 r100_enable_bm(rdev);
 428
 429         if (rdev->flags & RADEON_IS_PCIE) {
 430                 r = rv370_pcie_gart_init(rdev);
 431                 if (r)
 432                         return r;
 433         }
 434         if (rdev->flags & RADEON_IS_PCI) {
 435                 r = r100_pci_gart_init(rdev);
 436                 if (r)
 437                         return r;
 438         }
 439         r420_set_reg_safe(rdev);
 440
 441         rdev->accel_working = true;
 442         r = r420_startup(rdev);
 443         if (r) {
 444                 /* Somethings want wront with the accel init stop accel */
 445                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 446                 r100_cp_fini(rdev);
 447                 radeon_wb_fini(rdev);
 448                 radeon_ib_pool_fini(rdev);
 449                 radeon_irq_kms_fini(rdev);
 450                 if (rdev->flags & RADEON_IS_PCIE)
 451                         rv370_pcie_gart_fini(rdev);
 452                 if (rdev->flags & RADEON_IS_PCI)
 453                         r100_pci_gart_fini(rdev);
 454                 radeon_agp_fini(rdev);
 455                 rdev->accel_working = false;
 456         }
 457         return 0;
 458 }
 459
 460 /*
 461  * Debugfs info
 462  */
 463 #if defined(CONFIG_DEBUG_FS)
 464 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 465 {
 466         struct drm_info_node *node = (struct drm_info_node *) m->private;
 467         struct drm_device *dev = node->minor->dev;
 468         struct radeon_device *rdev = dev->dev_private;
 469         uint32_t tmp;
 470
 471         tmp = RREG32(R400_GB_PIPE_SELECT);
 472         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 473         tmp = RREG32(R300_GB_TILE_CONFIG);
 474         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 475         tmp = RREG32(R300_DST_PIPE_CONFIG);
 476         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 477         return 0;
 478 }
 479
 480 static struct drm_info_list r420_pipes_info_list[] = {
 481         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 482 };
 483 #endif
 484
 485 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 486 {
 487 #if defined(CONFIG_DEBUG_FS)
 488         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 489 #else
 490         return 0;
 491 #endif
 492 }