sys/dev/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include <drm/drm_dp_helper.h>
  34
  35 /* move these to drm_dp_helper.c/h */
  36 #define DP_LINK_CONFIGURATION_SIZE 9
  37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  38
  39 static char *voltage_names[] = {
  40         "0.4V", "0.6V", "0.8V", "1.2V"
  41 };
  42 static char *pre_emph_names[] = {
  43         "0dB", "3.5dB", "6dB", "9.5dB"
  44 };
  45
  46 /***** radeon AUX functions *****/
  47
  48 /* Atom needs data in little endian format
  49  * so swap as appropriate when copying data to
  50  * or from atom. Note that atom operates on
  51  * dw units.
  52  */
  53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
  54 {
  55 #ifdef __BIG_ENDIAN
  56         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
  57         u32 *dst32, *src32;
  58         int i;
  59
  60         memcpy(src_tmp, src, num_bytes);
  61         src32 = (u32 *)src_tmp;
  62         dst32 = (u32 *)dst_tmp;
  63         if (to_le) {
  64                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  65                         dst32[i] = cpu_to_le32(src32[i]);
  66                 memcpy(dst, dst_tmp, num_bytes);
  67         } else {
  68                 u8 dws = num_bytes & ~3;
  69                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  70                         dst32[i] = le32_to_cpu(src32[i]);
  71                 memcpy(dst, dst_tmp, dws);
  72                 if (num_bytes % 4) {
  73                         for (i = 0; i < (num_bytes % 4); i++)
  74                                 dst[dws+i] = dst_tmp[dws+i];
  75                 }
  76         }
  77 #else
  78         memcpy(dst, src, num_bytes);
  79 #endif
  80 }
  81
  82 union aux_channel_transaction {
  83         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  84         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  85 };
  86
  87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  88                                  u8 *send, int send_bytes,
  89                                  u8 *recv, int recv_size,
  90                                  u8 delay, u8 *ack)
  91 {
  92         struct drm_device *dev = chan->dev;
  93         struct radeon_device *rdev = dev->dev_private;
  94         union aux_channel_transaction args;
  95         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  96         unsigned char *base;
  97         int recv_bytes;
  98         int r = 0;
  99
 100         memset(&args, 0, sizeof(args));
 101
 102         mutex_lock(&chan->mutex);
 103         mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
 104
 105         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
 106
 107         radeon_atom_copy_swap(base, send, send_bytes, true);
 108
 109         args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
 110         args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
 111         args.v1.ucDataOutLen = 0;
 112         args.v1.ucChannelID = chan->rec.i2c_id;
 113         args.v1.ucDelay = delay / 10;
 114         if (ASIC_IS_DCE4(rdev))
 115                 args.v2.ucHPD_ID = chan->rec.hpd;
 116
 117         atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 118
 119         *ack = args.v1.ucReplyStatus;
 120
 121         /* timeout */
 122         if (args.v1.ucReplyStatus == 1) {
 123                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 124                 r = -ETIMEDOUT;
 125                 goto done;
 126         }
 127
 128         /* flags not zero */
 129         if (args.v1.ucReplyStatus == 2) {
 130                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 131                 r = -EIO;
 132                 goto done;
 133         }
 134
 135         /* error */
 136         if (args.v1.ucReplyStatus == 3) {
 137                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 138                 r = -EIO;
 139                 goto done;
 140         }
 141
 142         recv_bytes = args.v1.ucDataOutLen;
 143         if (recv_bytes > recv_size)
 144                 recv_bytes = recv_size;
 145
 146         if (recv && recv_size)
 147                 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
 148
 149         r = recv_bytes;
 150 done:
 151         mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
 152         mutex_unlock(&chan->mutex);
 153
 154         return r;
 155 }
 156
 157 #define BARE_ADDRESS_SIZE 3
 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 159
 160 static ssize_t
 161 radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 162 {
 163         struct radeon_i2c_chan *chan =
 164                 container_of(aux, struct radeon_i2c_chan, aux);
 165         int ret;
 166         u8 tx_buf[20];
 167         size_t tx_size;
 168         u8 ack, delay = 0;
 169
 170         if (WARN_ON(msg->size > 16))
 171                 return -E2BIG;
 172
 173         tx_buf[0] = msg->address & 0xff;
 174         tx_buf[1] = msg->address >> 8;
 175         tx_buf[2] = msg->request << 4;
 176         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
 177
 178         switch (msg->request & ~DP_AUX_I2C_MOT) {
 179         case DP_AUX_NATIVE_WRITE:
 180         case DP_AUX_I2C_WRITE:
 181                 /* tx_size needs to be 4 even for bare address packets since the atom
 182                  * table needs the info in tx_buf[3].
 183                  */
 184                 tx_size = HEADER_SIZE + msg->size;
 185                 if (msg->size == 0)
 186                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 187                 else
 188                         tx_buf[3] |= tx_size << 4;
 189                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
 190                 ret = radeon_process_aux_ch(chan,
 191                                             tx_buf, tx_size, NULL, 0, delay, &ack);
 192                 if (ret >= 0)
 193                         /* Return payload size. */
 194                         ret = msg->size;
 195                 break;
 196         case DP_AUX_NATIVE_READ:
 197         case DP_AUX_I2C_READ:
 198                 /* tx_size needs to be 4 even for bare address packets since the atom
 199                  * table needs the info in tx_buf[3].
 200                  */
 201                 tx_size = HEADER_SIZE;
 202                 if (msg->size == 0)
 203                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 204                 else
 205                         tx_buf[3] |= tx_size << 4;
 206                 ret = radeon_process_aux_ch(chan,
 207                                             tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 208                 break;
 209         default:
 210                 ret = -EINVAL;
 211                 break;
 212         }
 213
 214         if (ret >= 0)
 215                 msg->reply = ack >> 4;
 216
 217         return ret;
 218 }
 219
 220 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
 221 {
 222         int ret;
 223
 224         radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
 225         radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
 226         radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
 227
 228         ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
 229         if (!ret)
 230                 radeon_connector->ddc_bus->has_aux = true;
 231
 232         WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
 233 }
 234
 235 /***** general DP utility functions *****/
 236
 237 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 238 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
 239
 240 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 241                                 int lane_count,
 242                                 u8 train_set[4])
 243 {
 244         u8 v = 0;
 245         u8 p = 0;
 246         int lane;
 247
 248         for (lane = 0; lane < lane_count; lane++) {
 249                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 250                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 251
 252                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 253                           lane,
 254                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 255                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 256
 257                 if (this_v > v)
 258                         v = this_v;
 259                 if (this_p > p)
 260                         p = this_p;
 261         }
 262
 263         if (v >= DP_VOLTAGE_MAX)
 264                 v |= DP_TRAIN_MAX_SWING_REACHED;
 265
 266         if (p >= DP_PRE_EMPHASIS_MAX)
 267                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 268
 269         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 270                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 271                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 272
 273         for (lane = 0; lane < 4; lane++)
 274                 train_set[lane] = v | p;
 275 }
 276
 277 /* convert bits per color to bits per pixel */
 278 /* get bpc from the EDID */
 279 static int convert_bpc_to_bpp(int bpc)
 280 {
 281         if (bpc == 0)
 282                 return 24;
 283         else
 284                 return bpc * 3;
 285 }
 286
 287 /* get the max pix clock supported by the link rate and lane num */
 288 static int dp_get_max_dp_pix_clock(int link_rate,
 289                                    int lane_num,
 290                                    int bpp)
 291 {
 292         return (link_rate * lane_num * 8) / bpp;
 293 }
 294
 295 /***** radeon specific DP functions *****/
 296
 297 static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
 298                                        u8 dpcd[DP_DPCD_SIZE])
 299 {
 300         int max_link_rate;
 301
 302         if (radeon_connector_is_dp12_capable(connector))
 303                 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
 304         else
 305                 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
 306
 307         return max_link_rate;
 308 }
 309
 310 /* First get the min lane# when low rate is used according to pixel clock
 311  * (prefer low rate), second check max lane# supported by DP panel,
 312  * if the max lane# < low rate lane# then use max lane# instead.
 313  */
 314 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 315                                         u8 dpcd[DP_DPCD_SIZE],
 316                                         int pix_clock)
 317 {
 318         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 319         int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
 320         int max_lane_num = drm_dp_max_lane_count(dpcd);
 321         int lane_num;
 322         int max_dp_pix_clock;
 323
 324         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 325                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 326                 if (pix_clock <= max_dp_pix_clock)
 327                         break;
 328         }
 329
 330         return lane_num;
 331 }
 332
 333 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 334                                        u8 dpcd[DP_DPCD_SIZE],
 335                                        int pix_clock)
 336 {
 337         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 338         int lane_num, max_pix_clock;
 339
 340         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 341             ENCODER_OBJECT_ID_NUTMEG)
 342                 return 270000;
 343
 344         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 345         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 346         if (pix_clock <= max_pix_clock)
 347                 return 162000;
 348         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 349         if (pix_clock <= max_pix_clock)
 350                 return 270000;
 351         if (radeon_connector_is_dp12_capable(connector)) {
 352                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 353                 if (pix_clock <= max_pix_clock)
 354                         return 540000;
 355         }
 356
 357         return radeon_dp_get_max_link_rate(connector, dpcd);
 358 }
 359
 360 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 361                                     int action, int dp_clock,
 362                                     u8 ucconfig, u8 lane_num)
 363 {
 364         DP_ENCODER_SERVICE_PARAMETERS args;
 365         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 366
 367         memset(&args, 0, sizeof(args));
 368         args.ucLinkClock = dp_clock / 10;
 369         args.ucConfig = ucconfig;
 370         args.ucAction = action;
 371         args.ucLaneNum = lane_num;
 372         args.ucStatus = 0;
 373
 374         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 375         return args.ucStatus;
 376 }
 377
 378 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 379 {
 380         struct drm_device *dev = radeon_connector->base.dev;
 381         struct radeon_device *rdev = dev->dev_private;
 382
 383         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 384                                          radeon_connector->ddc_bus->rec.i2c_id, 0);
 385 }
 386
 387 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 388 {
 389         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 390         u8 buf[3];
 391
 392         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 393                 return;
 394
 395         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
 396                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
 397                               buf[0], buf[1], buf[2]);
 398
 399         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
 400                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 401                               buf[0], buf[1], buf[2]);
 402 }
 403
 404 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 405 {
 406         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 407         u8 msg[DP_DPCD_SIZE];
 408         int ret;
 409
 410         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
 411                                DP_DPCD_SIZE);
 412         if (ret > 0) {
 413                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 414
 415                 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
 416                               dig_connector->dpcd);
 417
 418                 radeon_dp_probe_oui(radeon_connector);
 419
 420                 return true;
 421         }
 422         dig_connector->dpcd[0] = 0;
 423         return false;
 424 }
 425
 426 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 427                              struct drm_connector *connector)
 428 {
 429         struct drm_device *dev = encoder->dev;
 430         struct radeon_device *rdev = dev->dev_private;
 431         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 432         struct radeon_connector_atom_dig *dig_connector;
 433         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 434         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 435         u8 tmp;
 436
 437         if (!ASIC_IS_DCE4(rdev))
 438                 return panel_mode;
 439
 440         if (!radeon_connector->con_priv)
 441                 return panel_mode;
 442
 443         dig_connector = radeon_connector->con_priv;
 444
 445         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 446                 /* DP bridge chips */
 447                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 448                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 449                         if (tmp & 1)
 450                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 451                         else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 452                                  (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 453                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 454                         else
 455                                 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 456                 }
 457         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 458                 /* eDP */
 459                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
 460                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 461                         if (tmp & 1)
 462                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 463                 }
 464         }
 465
 466         return panel_mode;
 467 }
 468
 469 void radeon_dp_set_link_config(struct drm_connector *connector,
 470                                const struct drm_display_mode *mode)
 471 {
 472         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 473         struct radeon_connector_atom_dig *dig_connector;
 474
 475         if (!radeon_connector->con_priv)
 476                 return;
 477         dig_connector = radeon_connector->con_priv;
 478
 479         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 480             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 481                 dig_connector->dp_clock =
 482                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 483                 dig_connector->dp_lane_count =
 484                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 485         }
 486 }
 487
 488 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 489                                 struct drm_display_mode *mode)
 490 {
 491         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 492         struct radeon_connector_atom_dig *dig_connector;
 493         int dp_clock;
 494
 495         if ((mode->clock > 340000) &&
 496             (!radeon_connector_is_dp12_capable(connector)))
 497                 return MODE_CLOCK_HIGH;
 498
 499         if (!radeon_connector->con_priv)
 500                 return MODE_CLOCK_HIGH;
 501         dig_connector = radeon_connector->con_priv;
 502
 503         dp_clock =
 504                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 505
 506         if ((dp_clock == 540000) &&
 507             (!radeon_connector_is_dp12_capable(connector)))
 508                 return MODE_CLOCK_HIGH;
 509
 510         return MODE_OK;
 511 }
 512
 513 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 514 {
 515         u8 link_status[DP_LINK_STATUS_SIZE];
 516         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 517
 518         if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
 519             <= 0)
 520                 return false;
 521         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 522                 return false;
 523         return true;
 524 }
 525
 526 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
 527                                   u8 power_state)
 528 {
 529         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 530         struct radeon_connector_atom_dig *dig_connector;
 531
 532         if (!radeon_connector->con_priv)
 533                 return;
 534
 535         dig_connector = radeon_connector->con_priv;
 536
 537         /* power up/down the sink */
 538         if (dig_connector->dpcd[0] >= 0x11) {
 539                 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
 540                                    DP_SET_POWER, power_state);
 541                 usleep_range(1000, 2000);
 542         }
 543 }
 544
 545
 546 struct radeon_dp_link_train_info {
 547         struct radeon_device *rdev;
 548         struct drm_encoder *encoder;
 549         struct drm_connector *connector;
 550         int enc_id;
 551         int dp_clock;
 552         int dp_lane_count;
 553         bool tp3_supported;
 554         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 555         u8 train_set[4];
 556         u8 link_status[DP_LINK_STATUS_SIZE];
 557         u8 tries;
 558         bool use_dpencoder;
 559         struct drm_dp_aux *aux;
 560 };
 561
 562 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 563 {
 564         /* set the initial vs/emph on the source */
 565         atombios_dig_transmitter_setup(dp_info->encoder,
 566                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 567                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 568
 569         /* set the vs/emph on the sink */
 570         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
 571                           dp_info->train_set, dp_info->dp_lane_count);
 572 }
 573
 574 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 575 {
 576         int rtp = 0;
 577
 578         /* set training pattern on the source */
 579         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 580                 switch (tp) {
 581                 case DP_TRAINING_PATTERN_1:
 582                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 583                         break;
 584                 case DP_TRAINING_PATTERN_2:
 585                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 586                         break;
 587                 case DP_TRAINING_PATTERN_3:
 588                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 589                         break;
 590                 }
 591                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 592         } else {
 593                 switch (tp) {
 594                 case DP_TRAINING_PATTERN_1:
 595                         rtp = 0;
 596                         break;
 597                 case DP_TRAINING_PATTERN_2:
 598                         rtp = 1;
 599                         break;
 600                 }
 601                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 602                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 603         }
 604
 605         /* enable training pattern on the sink */
 606         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
 607 }
 608
 609 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 610 {
 611         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 612         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 613         u8 tmp;
 614
 615         /* power up the sink */
 616         radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 617
 618         /* possibly enable downspread on the sink */
 619         if (dp_info->dpcd[3] & 0x1)
 620                 drm_dp_dpcd_writeb(dp_info->aux,
 621                                    DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 622         else
 623                 drm_dp_dpcd_writeb(dp_info->aux,
 624                                    DP_DOWNSPREAD_CTRL, 0);
 625
 626         if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
 627                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 628
 629         /* set the lane count on the sink */
 630         tmp = dp_info->dp_lane_count;
 631         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
 632                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 633         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
 634
 635         /* set the link rate on the sink */
 636         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 637         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
 638
 639         /* start training on the source */
 640         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 641                 atombios_dig_encoder_setup(dp_info->encoder,
 642                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 643         else
 644                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 645                                           dp_info->dp_clock, dp_info->enc_id, 0);
 646
 647         /* disable the training pattern on the sink */
 648         drm_dp_dpcd_writeb(dp_info->aux,
 649                            DP_TRAINING_PATTERN_SET,
 650                            DP_TRAINING_PATTERN_DISABLE);
 651
 652         return 0;
 653 }
 654
 655 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 656 {
 657         udelay(400);
 658
 659         /* disable the training pattern on the sink */
 660         drm_dp_dpcd_writeb(dp_info->aux,
 661                            DP_TRAINING_PATTERN_SET,
 662                            DP_TRAINING_PATTERN_DISABLE);
 663
 664         /* disable the training pattern on the source */
 665         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 666                 atombios_dig_encoder_setup(dp_info->encoder,
 667                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 668         else
 669                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 670                                           dp_info->dp_clock, dp_info->enc_id, 0);
 671
 672         return 0;
 673 }
 674
 675 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 676 {
 677         bool clock_recovery;
 678         u8 voltage;
 679         int i;
 680
 681         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 682         memset(dp_info->train_set, 0, 4);
 683         radeon_dp_update_vs_emph(dp_info);
 684
 685         udelay(400);
 686
 687         /* clock recovery loop */
 688         clock_recovery = false;
 689         dp_info->tries = 0;
 690         voltage = 0xff;
 691         while (1) {
 692                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 693
 694                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 695                                                  dp_info->link_status) <= 0) {
 696                         DRM_ERROR("displayport link status failed\n");
 697                         break;
 698                 }
 699
 700                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 701                         clock_recovery = true;
 702                         break;
 703                 }
 704
 705                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 706                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 707                                 break;
 708                 }
 709                 if (i == dp_info->dp_lane_count) {
 710                         DRM_ERROR("clock recovery reached max voltage\n");
 711                         break;
 712                 }
 713
 714                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 715                         ++dp_info->tries;
 716                         if (dp_info->tries == 5) {
 717                                 DRM_ERROR("clock recovery tried 5 times\n");
 718                                 break;
 719                         }
 720                 } else
 721                         dp_info->tries = 0;
 722
 723                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 724
 725                 /* Compute new train_set as requested by sink */
 726                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 727
 728                 radeon_dp_update_vs_emph(dp_info);
 729         }
 730         if (!clock_recovery) {
 731                 DRM_ERROR("clock recovery failed\n");
 732                 return -1;
 733         } else {
 734                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 735                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 736                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 737                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 738                 return 0;
 739         }
 740 }
 741
 742 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 743 {
 744         bool channel_eq;
 745
 746         if (dp_info->tp3_supported)
 747                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 748         else
 749                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 750
 751         /* channel equalization loop */
 752         dp_info->tries = 0;
 753         channel_eq = false;
 754         while (1) {
 755                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 756
 757                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 758                                                  dp_info->link_status) <= 0) {
 759                         DRM_ERROR("displayport link status failed\n");
 760                         break;
 761                 }
 762
 763                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 764                         channel_eq = true;
 765                         break;
 766                 }
 767
 768                 /* Try 5 times */
 769                 if (dp_info->tries > 5) {
 770                         DRM_ERROR("channel eq failed: 5 tries\n");
 771                         break;
 772                 }
 773
 774                 /* Compute new train_set as requested by sink */
 775                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 776
 777                 radeon_dp_update_vs_emph(dp_info);
 778                 dp_info->tries++;
 779         }
 780
 781         if (!channel_eq) {
 782                 DRM_ERROR("channel eq failed\n");
 783                 return -1;
 784         } else {
 785                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 786                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 787                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 788                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 789                 return 0;
 790         }
 791 }
 792
 793 void radeon_dp_link_train(struct drm_encoder *encoder,
 794                           struct drm_connector *connector)
 795 {
 796         struct drm_device *dev = encoder->dev;
 797         struct radeon_device *rdev = dev->dev_private;
 798         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 799         struct radeon_encoder_atom_dig *dig;
 800         struct radeon_connector *radeon_connector;
 801         struct radeon_connector_atom_dig *dig_connector;
 802         struct radeon_dp_link_train_info dp_info;
 803         int index;
 804         u8 tmp, frev, crev;
 805
 806         if (!radeon_encoder->enc_priv)
 807                 return;
 808         dig = radeon_encoder->enc_priv;
 809
 810         radeon_connector = to_radeon_connector(connector);
 811         if (!radeon_connector->con_priv)
 812                 return;
 813         dig_connector = radeon_connector->con_priv;
 814
 815         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 816             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 817                 return;
 818
 819         /* DPEncoderService newer than 1.1 can't program properly the
 820          * training pattern. When facing such version use the
 821          * DIGXEncoderControl (X== 1 | 2)
 822          */
 823         dp_info.use_dpencoder = true;
 824         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 825         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 826                 if (crev > 1) {
 827                         dp_info.use_dpencoder = false;
 828                 }
 829         }
 830
 831         dp_info.enc_id = 0;
 832         if (dig->dig_encoder)
 833                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 834         else
 835                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 836         if (dig->linkb)
 837                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 838         else
 839                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 840
 841         if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
 842             == 1) {
 843                 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 844                         dp_info.tp3_supported = true;
 845                 else
 846                         dp_info.tp3_supported = false;
 847         } else {
 848                 dp_info.tp3_supported = false;
 849         }
 850
 851         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 852         dp_info.rdev = rdev;
 853         dp_info.encoder = encoder;
 854         dp_info.connector = connector;
 855         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 856         dp_info.dp_clock = dig_connector->dp_clock;
 857         dp_info.aux = &radeon_connector->ddc_bus->aux;
 858
 859         if (radeon_dp_link_train_init(&dp_info))
 860                 goto done;
 861         if (radeon_dp_link_train_cr(&dp_info))
 862                 goto done;
 863         if (radeon_dp_link_train_ce(&dp_info))
 864                 goto done;
 865 done:
 866         if (radeon_dp_link_train_finish(&dp_info))
 867                 return;
 868 }