2 * Copyright (c) 2000-2004 Taku YAMAMOTO <taku@tackymt.homeip.net>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * maestro.c,v 1.23.2.1 2003/10/03 18:21:38 taku Exp
32 * Part of this code (especially in many magic numbers) was heavily inspired
33 * by the Linux driver originally written by
34 * Alan Cox <alan.cox@linux.org>, modified heavily by
35 * Zach Brown <zab@zabbo.net>.
37 * busdma()-ize and buffer size reduction were suggested by
38 * Cameron Grant <cg@freebsd.org>.
39 * Also he showed me the way to use busdma() suite.
41 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
43 * Munehiro Matsuda <haro@tk.kubota.co.jp>,
44 * who brought patches based on the Linux driver with some simplification.
46 * Hardware volume controller was implemented by
47 * John Baldwin <jhb@freebsd.org>.
50 #ifdef HAVE_KERNEL_OPTION_HEADERS
54 #include <dev/sound/pcm/sound.h>
55 #include <dev/sound/pcm/ac97.h>
56 #include <bus/pci/pcireg.h>
57 #include <bus/pci/pcivar.h>
58 #include <sys/thread2.h>
60 #include <dev/sound/pci/maestro_reg.h>
62 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/maestro.c 274035 2014-11-03 11:11:45Z bapt $");
65 * PCI IDs of supported chips:
67 * MAESTRO-1 0x01001285
68 * MAESTRO-2 0x1968125d
69 * MAESTRO-2E 0x1978125d
72 #define MAESTRO_1_PCI_ID 0x01001285
73 #define MAESTRO_2_PCI_ID 0x1968125d
74 #define MAESTRO_2E_PCI_ID 0x1978125d
76 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
77 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
80 # if AGG_MAXPLAYCH > 4
82 # define AGG_MAXPLAYCH 4
85 # define AGG_MAXPLAYCH 4
88 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
92 # define critical_enter() crit_enter()
93 # define critical_exit() crit_exit()
96 #define PCIR_BAR(x) (PCIR_MAPS + (x) * 4)
100 /* -----------------------------
105 struct agg_info *parent;
107 /* FreeBSD newpcm related */
108 struct pcm_channel *channel;
109 struct snd_dbuf *buffer;
113 bus_addr_t phys; /* channel buffer physical address */
114 bus_addr_t base; /* channel buffer segment base */
115 u_int32_t blklen; /* DMA block length in WORDs */
116 u_int32_t buflen; /* channel buffer length in WORDs */
120 unsigned qs16 : 1; /* quantum size is 16bit */
121 unsigned us : 1; /* in unsigned format */
126 struct agg_info *parent;
128 /* FreeBSD newpcm related */
129 struct pcm_channel *channel;
130 struct snd_dbuf *buffer;
134 bus_addr_t phys; /* channel buffer physical address */
135 bus_addr_t base; /* channel buffer segment base */
136 u_int32_t blklen; /* DMA block length in WORDs */
137 u_int32_t buflen; /* channel buffer length in WORDs */
142 int16_t *src; /* stereo peer buffer */
143 int16_t *sink; /* channel buffer pointer */
144 volatile u_int32_t hwptr; /* ready point in 16bit sample */
148 /* FreeBSD newbus related */
151 /* I wonder whether bus_space_* are in common in *BSD... */
152 struct resource *reg;
155 bus_space_handle_t sh;
157 struct resource *irq;
161 bus_dma_tag_t buf_dmat;
162 bus_dma_tag_t stat_dmat;
164 /* FreeBSD SMPng related */
165 struct lock lock; /* mutual exclusion */
166 /* FreeBSD newpcm related */
167 struct ac97_info *codec;
170 bus_dmamap_t stat_map;
171 u_int8_t *stat; /* status buffer pointer */
172 bus_addr_t phys; /* status buffer physical address */
173 unsigned int bufsz; /* channel buffer size in bytes */
175 volatile u_int active;
176 struct agg_chinfo pch[AGG_MAXPLAYCH];
177 struct agg_rchinfo rch;
178 volatile u_int8_t curpwr; /* current power status: D[0-3] */
182 /* -----------------------------
185 static unsigned int powerstate_active = PCI_POWERSTATE_D1;
186 #ifdef MAESTRO_AGGRESSIVE_POWERSAVE
187 static unsigned int powerstate_idle = PCI_POWERSTATE_D2;
189 static unsigned int powerstate_idle = PCI_POWERSTATE_D1;
191 static unsigned int powerstate_init = PCI_POWERSTATE_D2;
193 /* XXX: this should move to a device specific sysctl dev.pcm.X.debug.Y via
194 device_get_sysctl_*() as discussed on multimedia@ in msg-id
195 <861wujij2q.fsf@xps.des.no> */
196 static SYSCTL_NODE(_debug, OID_AUTO, maestro, CTLFLAG_RD, 0, "");
197 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_active, CTLFLAG_RW,
198 &powerstate_active, 0, "The Dx power state when active (0-1)");
199 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_idle, CTLFLAG_RW,
200 &powerstate_idle, 0, "The Dx power state when idle (0-2)");
201 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_init, CTLFLAG_RW,
203 "The Dx power state prior to the first use (0-2)");
206 /* -----------------------------
210 static void agg_sleep(struct agg_info*, const char *wmesg, int msec);
213 static __inline u_int32_t agg_rd(struct agg_info*, int, int size);
214 static __inline void agg_wr(struct agg_info*, int, u_int32_t data,
217 static int agg_rdcodec(struct agg_info*, int);
218 static int agg_wrcodec(struct agg_info*, int, u_int32_t);
220 static void ringbus_setdest(struct agg_info*, int, int);
222 static u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
223 static void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
224 static u_int16_t wp_rdapu(struct agg_info*, unsigned, u_int16_t);
225 static void wp_wrapu(struct agg_info*, unsigned, u_int16_t, u_int16_t);
226 static void wp_settimer(struct agg_info*, u_int);
227 static void wp_starttimer(struct agg_info*);
228 static void wp_stoptimer(struct agg_info*);
231 static u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
233 static void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
235 static u_int16_t wc_rdchctl(struct agg_info*, int);
237 static void wc_wrchctl(struct agg_info*, int, u_int16_t);
239 static void agg_stopclock(struct agg_info*, int part, int st);
241 static void agg_initcodec(struct agg_info*);
242 static void agg_init(struct agg_info*);
243 static void agg_power(struct agg_info*, int);
245 static void aggch_start_dac(struct agg_chinfo*);
246 static void aggch_stop_dac(struct agg_chinfo*);
247 static void aggch_start_adc(struct agg_rchinfo*);
248 static void aggch_stop_adc(struct agg_rchinfo*);
249 static void aggch_feed_adc_stereo(struct agg_rchinfo*);
250 static void aggch_feed_adc_mono(struct agg_rchinfo*);
252 #ifdef AGG_JITTER_CORRECTION
253 static void suppress_jitter(struct agg_chinfo*);
254 static void suppress_rec_jitter(struct agg_rchinfo*);
257 static void set_timer(struct agg_info*);
259 static void agg_intr(void *);
260 static int agg_probe(device_t);
261 static int agg_attach(device_t);
262 static int agg_detach(device_t);
263 static int agg_suspend(device_t);
264 static int agg_resume(device_t);
265 static int agg_shutdown(device_t);
267 static void *dma_malloc(bus_dma_tag_t, u_int32_t, bus_addr_t*,
269 static void dma_free(bus_dma_tag_t, void *, bus_dmamap_t);
272 /* -----------------------------
277 #define agg_lock(sc) snd_mtxlock(&((sc)->lock))
278 #define agg_unlock(sc) snd_mtxunlock(&((sc)->lock))
281 agg_sleep(struct agg_info *sc, const char *wmesg, int msec)
285 timo = msec * hz / 1000;
288 lksleep(sc, &sc->lock, 0, wmesg, timo);
295 static __inline u_int32_t
296 agg_rd(struct agg_info *sc, int regno, int size)
300 return bus_space_read_1(sc->st, sc->sh, regno);
302 return bus_space_read_2(sc->st, sc->sh, regno);
304 return bus_space_read_4(sc->st, sc->sh, regno);
306 return ~(u_int32_t)0;
311 #define AGG_RD(sc, regno, size) \
312 bus_space_read_##size( \
313 ((struct agg_info*)(sc))->st, \
314 ((struct agg_info*)(sc))->sh, (regno))
318 agg_wr(struct agg_info *sc, int regno, u_int32_t data, int size)
322 bus_space_write_1(sc->st, sc->sh, regno, data);
325 bus_space_write_2(sc->st, sc->sh, regno, data);
328 bus_space_write_4(sc->st, sc->sh, regno, data);
334 #define AGG_WR(sc, regno, data, size) \
335 bus_space_write_##size( \
336 ((struct agg_info*)(sc))->st, \
337 ((struct agg_info*)(sc))->sh, (regno), (data))
339 /* -------------------------------------------------------------------- */
344 agg_codec_wait4idle(struct agg_info *ess)
348 while (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) {
351 DELAY(2); /* 20.8us / 13 */
358 agg_rdcodec(struct agg_info *ess, int regno)
362 /* We have to wait for a SAFE time to write addr/data */
363 if (agg_codec_wait4idle(ess)) {
364 /* Timed out. No read performed. */
365 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
369 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
370 /*DELAY(21); * AC97 cycle = 20.8usec */
372 /* Wait for data retrieve */
373 if (!agg_codec_wait4idle(ess)) {
374 ret = AGG_RD(ess, PORT_CODEC_REG, 2);
376 /* Timed out. No read performed. */
377 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
385 agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data)
387 /* We have to wait for a SAFE time to write addr/data */
388 if (agg_codec_wait4idle(ess)) {
389 /* Timed out. Abort writing. */
390 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
394 AGG_WR(ess, PORT_CODEC_REG, data, 2);
395 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
397 /* Wait for write completion */
398 if (agg_codec_wait4idle(ess)) {
400 device_printf(ess->dev, "agg_wrcodec() RW_DONE timed out.\n");
408 ringbus_setdest(struct agg_info *ess, int src, int dest)
412 data = AGG_RD(ess, PORT_RINGBUS_CTRL, 4);
413 data &= ~(0xfU << src);
414 data |= (0xfU & dest) << src;
415 AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
418 /* -------------------------------------------------------------------- */
423 wp_rdreg(struct agg_info *ess, u_int16_t reg)
425 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
426 return AGG_RD(ess, PORT_DSP_DATA, 2);
430 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
432 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
433 AGG_WR(ess, PORT_DSP_DATA, data, 2);
437 wp_wait_data(struct agg_info *ess, u_int16_t data)
441 while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
445 AGG_WR(ess, PORT_DSP_DATA, data, 2);
452 wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)
454 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
455 if (wp_wait_data(ess, reg | (ch << 4)) != 0)
456 device_printf(ess->dev, "wp_rdapu() indexing timed out.\n");
457 return wp_rdreg(ess, WPREG_DATA_PORT);
461 wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)
463 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
464 if (wp_wait_data(ess, reg | (ch << 4)) == 0) {
465 wp_wrreg(ess, WPREG_DATA_PORT, data);
466 if (wp_wait_data(ess, data) != 0)
467 device_printf(ess->dev,
468 "wp_wrapu() write timed out.\n");
470 device_printf(ess->dev, "wp_wrapu() indexing timed out.\n");
475 apu_setparam(struct agg_info *ess, int apuch,
476 u_int32_t wpwa, u_int16_t size, int16_t pan, u_int dv)
478 wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK);
479 wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa);
480 wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size);
481 wp_wrapu(ess, apuch, APUREG_LOOPLEN, size);
482 wp_wrapu(ess, apuch, APUREG_ROUTING, 0);
483 wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000);
484 wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00
485 | (APU_RADIUS_MASK & (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT))
486 | (APU_PAN_MASK & ((pan + PAN_FRONT) << APU_PAN_SHIFT)));
487 wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE,
488 APU_plus6dB | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
489 wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8);
493 wp_settimer(struct agg_info *ess, u_int divide)
497 RANGE(divide, 2, 32 << 7);
499 for (; divide > 32; divide >>= 1) {
504 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
507 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
508 wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 |
509 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
510 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
514 wp_starttimer(struct agg_info *ess)
516 AGG_WR(ess, PORT_INT_STAT, 1, 2);
517 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
518 | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
519 wp_wrreg(ess, WPREG_TIMER_START, 1);
523 wp_stoptimer(struct agg_info *ess)
525 AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
526 & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
527 AGG_WR(ess, PORT_INT_STAT, 1, 2);
528 wp_wrreg(ess, WPREG_TIMER_START, 0);
531 /* -------------------------------------------------------------------- */
537 wc_rdreg(struct agg_info *ess, u_int16_t reg)
539 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
540 return AGG_RD(ess, PORT_WAVCACHE_DATA, 2);
545 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
547 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
548 AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
553 wc_rdchctl(struct agg_info *ess, int ch)
555 return wc_rdreg(ess, ch << 3);
560 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
562 wc_wrreg(ess, ch << 3, data);
565 /* -------------------------------------------------------------------- */
567 /* Power management */
569 agg_stopclock(struct agg_info *ess, int part, int st)
573 data = pci_read_config(ess->dev, CONF_ACPI_STOPCLOCK, 4);
575 if (st == PCI_POWERSTATE_D1)
576 data &= ~(1 << part);
579 if (st == PCI_POWERSTATE_D1 || st == PCI_POWERSTATE_D2)
580 data |= (0x10000 << part);
582 data &= ~(0x10000 << part);
583 pci_write_config(ess->dev, CONF_ACPI_STOPCLOCK, data, 4);
588 /* -----------------------------
593 agg_initcodec(struct agg_info* ess)
597 if (AGG_RD(ess, PORT_RINGBUS_CTRL, 4) & RINGBUS_CTRL_ACLINK_ENABLED) {
598 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
599 DELAY(104); /* 20.8us * (4 + 1) */
601 /* XXX - 2nd codec should be looked at. */
602 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
604 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
607 if (agg_rdcodec(ess, 0) < 0) {
608 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
611 /* Try cold reset. */
612 device_printf(ess->dev, "will perform cold reset.\n");
613 data = AGG_RD(ess, PORT_GPIO_DIR, 2);
614 if (pci_read_config(ess->dev, 0x58, 2) & 1)
616 data |= 0x009 & ~AGG_RD(ess, PORT_GPIO_DATA, 2);
617 AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
618 AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
619 AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
621 AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
623 AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
624 agg_sleep(ess, "agginicd", 500);
625 AGG_WR(ess, PORT_GPIO_DIR, data, 2);
626 DELAY(84); /* 20.8us * 4 */
627 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
633 agg_init(struct agg_info* ess)
637 /* Setup PCI config registers. */
639 /* Disable all legacy emulations. */
640 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
641 data |= LEGACY_DISABLED;
642 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
644 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
645 * Enable posted write.
646 * Prefer PCI timing rather than that of ISA.
648 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
650 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
651 data &= ~MAESTRO_SWAP_LR;
652 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
654 /* Turn off unused parts if necessary. */
655 /* consult CONF_MAESTRO. */
656 if (data & MAESTRO_SPDIF)
657 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D2);
659 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D1);
660 if (data & MAESTRO_HWVOL)
661 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D3);
663 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D1);
665 /* parts that never be used */
666 agg_stopclock(ess, ACPI_PART_978, PCI_POWERSTATE_D1);
667 agg_stopclock(ess, ACPI_PART_DAA, PCI_POWERSTATE_D1);
668 agg_stopclock(ess, ACPI_PART_GPIO, PCI_POWERSTATE_D1);
669 agg_stopclock(ess, ACPI_PART_SB, PCI_POWERSTATE_D1);
670 agg_stopclock(ess, ACPI_PART_FM, PCI_POWERSTATE_D1);
671 agg_stopclock(ess, ACPI_PART_MIDI, PCI_POWERSTATE_D1);
672 agg_stopclock(ess, ACPI_PART_GAME_PORT, PCI_POWERSTATE_D1);
674 /* parts that will be used only when play/recording */
675 agg_stopclock(ess, ACPI_PART_WP, PCI_POWERSTATE_D2);
677 /* parts that should always be turned on */
678 agg_stopclock(ess, ACPI_PART_CODEC_CLOCK, PCI_POWERSTATE_D3);
679 agg_stopclock(ess, ACPI_PART_GLUE, PCI_POWERSTATE_D3);
680 agg_stopclock(ess, ACPI_PART_PCI_IF, PCI_POWERSTATE_D3);
681 agg_stopclock(ess, ACPI_PART_RINGBUS, PCI_POWERSTATE_D3);
683 /* Reset direct sound. */
684 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
686 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
688 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
690 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
693 /* Enable hardware volume control interruption. */
694 if (data & MAESTRO_HWVOL) /* XXX - why not use device flags? */
695 AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
697 /* Setup Wave Processor. */
699 /* Enable WaveCache, set DMA base address. */
700 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
701 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
702 wp_wrreg(ess, WPREG_CRAM_DATA, 0);
704 AGG_WR(ess, PORT_WAVCACHE_CTRL,
705 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_2MB | WAVCACHE_SGC_32_47, 2);
707 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
708 wc_wrreg(ess, data, ess->phys >> WAVCACHE_BASEADDR_SHIFT);
710 /* Setup Codec/Ringbus. */
712 AGG_WR(ess, PORT_RINGBUS_CTRL,
713 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED, 4);
715 wp_wrreg(ess, 0x08, 0xB004);
716 wp_wrreg(ess, 0x09, 0x001B);
717 wp_wrreg(ess, 0x0A, 0x8000);
718 wp_wrreg(ess, 0x0B, 0x3F37);
719 wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
720 wp_wrreg(ess, WPREG_BASE + 1, 0x7632);
721 ringbus_setdest(ess, RINGBUS_SRC_ADC,
722 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
723 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
724 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
726 /* Enable S/PDIF if necessary. */
727 if (pci_read_config(ess->dev, CONF_MAESTRO, 4) & MAESTRO_SPDIF)
728 /* XXX - why not use device flags? */
729 AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
730 AGG_RD(ess, PORT_RINGBUS_CTRL_B, 1), 1);
732 /* Setup ASSP. Needed for Dell Inspiron 7500? */
733 AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
734 AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
735 AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
739 * There seems to be speciality with NEC systems.
741 switch (pci_get_subvendor(ess->dev)
742 | (pci_get_subdevice(ess->dev) << 16)) {
745 /* Matthew Braithwaite <matt@braithwaite.net> reported that
746 * NEC Versa LX doesn't need GPIO operation. */
747 AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
748 AGG_WR(ess, PORT_GPIO_DIR,
749 AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2);
750 AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
755 /* Deals power state transition. Must be called with softc->lock held. */
757 agg_power(struct agg_info *ess, int status)
761 lastpwr = ess->curpwr;
762 if (lastpwr == status)
766 case PCI_POWERSTATE_D0:
767 case PCI_POWERSTATE_D1:
769 case PCI_POWERSTATE_D2:
770 pci_set_powerstate(ess->dev, status);
771 /* Turn on PCM-related parts. */
772 agg_wrcodec(ess, AC97_REG_POWER, 0);
775 if ((agg_rdcodec(ess, AC97_REG_POWER) & 3) != 3)
776 device_printf(ess->dev,
777 "warning: codec not ready.\n");
779 AGG_WR(ess, PORT_RINGBUS_CTRL,
780 (AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
781 & ~RINGBUS_CTRL_ACLINK_ENABLED)
782 | RINGBUS_CTRL_RINGBUS_ENABLED, 4);
784 AGG_WR(ess, PORT_RINGBUS_CTRL,
785 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
786 | RINGBUS_CTRL_ACLINK_ENABLED, 4);
788 case PCI_POWERSTATE_D3:
790 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
794 case PCI_POWERSTATE_D0:
795 case PCI_POWERSTATE_D1:
796 pci_set_powerstate(ess->dev, status);
800 case PCI_POWERSTATE_D2:
802 case PCI_POWERSTATE_D3:
804 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
808 case PCI_POWERSTATE_D0:
809 case PCI_POWERSTATE_D1:
810 /* Turn off PCM-related parts. */
811 AGG_WR(ess, PORT_RINGBUS_CTRL,
812 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
813 & ~RINGBUS_CTRL_RINGBUS_ENABLED, 4);
815 agg_wrcodec(ess, AC97_REG_POWER, 0x300);
819 pci_set_powerstate(ess->dev, status);
821 case PCI_POWERSTATE_D3:
822 /* Entirely power down. */
823 agg_wrcodec(ess, AC97_REG_POWER, 0xdf00);
825 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
827 if (lastpwr != PCI_POWERSTATE_D2)
829 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
830 AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);
831 pci_set_powerstate(ess->dev, status);
834 /* Invalid power state; let it ignored. */
839 ess->curpwr = status;
842 /* -------------------------------------------------------------------- */
844 /* Channel controller. */
847 aggch_start_dac(struct agg_chinfo *ch)
851 u_int16_t size, apuch, wtbar, wcreg, aputype;
856 wpwa = (ch->phys - ch->base) >> 1;
857 wtbar = 0xc & (wpwa >> WPWA_WTBAR_SHIFT(2));
858 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
860 apuch = (ch->num << 1) | 32;
861 pan = PAN_RIGHT - PAN_FRONT;
864 wcreg |= WAVCACHE_CHCTL_STEREO;
866 aputype = APUTYPE_16BITSTEREO;
871 aputype = APUTYPE_8BITSTEREO;
875 aputype = APUTYPE_16BITLINEAR;
877 aputype = APUTYPE_8BITLINEAR;
882 wcreg |= WAVCACHE_CHCTL_U8;
885 wtbar = (wtbar >> 1) + 4;
887 dv = (((speed % 48000) << 16) + 24000) / 48000
888 + ((speed / 48000) << 16);
890 agg_lock(ch->parent);
891 agg_power(ch->parent, powerstate_active);
893 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar,
894 ch->base >> WAVCACHE_BASEADDR_SHIFT);
895 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 1,
896 ch->base >> WAVCACHE_BASEADDR_SHIFT);
898 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 2,
899 ch->base >> WAVCACHE_BASEADDR_SHIFT);
900 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 3,
901 ch->base >> WAVCACHE_BASEADDR_SHIFT);
903 wc_wrchctl(ch->parent, apuch, wcreg);
904 wc_wrchctl(ch->parent, apuch + 1, wcreg);
906 apu_setparam(ch->parent, apuch, wpwa, size, pan, dv);
909 wpwa |= (WPWA_STEREO >> 1);
910 apu_setparam(ch->parent, apuch + 1, wpwa, size, -pan, dv);
913 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
914 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
915 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
916 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
919 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
920 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
923 /* to mark that this channel is ready for intr. */
924 ch->parent->active |= (1 << ch->num);
926 set_timer(ch->parent);
927 wp_starttimer(ch->parent);
928 agg_unlock(ch->parent);
932 aggch_stop_dac(struct agg_chinfo *ch)
934 agg_lock(ch->parent);
936 /* to mark that this channel no longer needs further intrs. */
937 ch->parent->active &= ~(1 << ch->num);
939 wp_wrapu(ch->parent, (ch->num << 1) | 32, APUREG_APUTYPE,
940 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
941 wp_wrapu(ch->parent, (ch->num << 1) | 33, APUREG_APUTYPE,
942 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
944 if (ch->parent->active) {
945 set_timer(ch->parent);
946 wp_starttimer(ch->parent);
948 wp_stoptimer(ch->parent);
949 agg_power(ch->parent, powerstate_idle);
951 agg_unlock(ch->parent);
955 aggch_start_adc(struct agg_rchinfo *ch)
957 bus_addr_t wpwa, wpwa2;
958 u_int16_t wcreg, wcreg2;
962 /* speed > 48000 not cared */
963 dv = ((ch->speed << 16) + 24000) / 48000;
965 /* RATECONV doesn't seem to like dv == 0x10000. */
970 wpwa = (ch->srcphys - ch->base) >> 1;
971 wpwa2 = (ch->srcphys + ch->parent->bufsz/2 - ch->base) >> 1;
972 wcreg = (ch->srcphys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
973 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
974 pan = PAN_LEFT - PAN_FRONT;
976 wpwa = (ch->phys - ch->base) >> 1;
977 wpwa2 = (ch->srcphys - ch->base) >> 1;
978 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
979 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
983 agg_lock(ch->parent);
986 agg_power(ch->parent, powerstate_active);
988 /* Invalidate WaveCache. */
989 wc_wrchctl(ch->parent, 0, wcreg | WAVCACHE_CHCTL_STEREO);
990 wc_wrchctl(ch->parent, 1, wcreg | WAVCACHE_CHCTL_STEREO);
991 wc_wrchctl(ch->parent, 2, wcreg2 | WAVCACHE_CHCTL_STEREO);
992 wc_wrchctl(ch->parent, 3, wcreg2 | WAVCACHE_CHCTL_STEREO);
994 /* Load APU registers. */
995 /* APU #0 : Sample rate converter for left/center. */
996 apu_setparam(ch->parent, 0, WPWA_USE_SYSMEM | wpwa,
997 ch->buflen >> ch->stereo, 0, dv);
998 wp_wrapu(ch->parent, 0, APUREG_AMPLITUDE, 0);
999 wp_wrapu(ch->parent, 0, APUREG_ROUTING, 2 << APU_DATASRC_A_SHIFT);
1001 /* APU #1 : Sample rate converter for right. */
1002 apu_setparam(ch->parent, 1, WPWA_USE_SYSMEM | wpwa2,
1003 ch->buflen >> ch->stereo, 0, dv);
1004 wp_wrapu(ch->parent, 1, APUREG_AMPLITUDE, 0);
1005 wp_wrapu(ch->parent, 1, APUREG_ROUTING, 3 << APU_DATASRC_A_SHIFT);
1007 /* APU #2 : Input mixer for left. */
1008 apu_setparam(ch->parent, 2, WPWA_USE_SYSMEM | 0,
1009 ch->parent->bufsz >> 2, pan, 0x10000);
1010 wp_wrapu(ch->parent, 2, APUREG_AMPLITUDE, 0);
1011 wp_wrapu(ch->parent, 2, APUREG_EFFECT_GAIN, 0xf0);
1012 wp_wrapu(ch->parent, 2, APUREG_ROUTING, 0x15 << APU_DATASRC_A_SHIFT);
1014 /* APU #3 : Input mixer for right. */
1015 apu_setparam(ch->parent, 3, WPWA_USE_SYSMEM | (ch->parent->bufsz >> 2),
1016 ch->parent->bufsz >> 2, -pan, 0x10000);
1017 wp_wrapu(ch->parent, 3, APUREG_AMPLITUDE, 0);
1018 wp_wrapu(ch->parent, 3, APUREG_EFFECT_GAIN, 0xf0);
1019 wp_wrapu(ch->parent, 3, APUREG_ROUTING, 0x14 << APU_DATASRC_A_SHIFT);
1021 /* to mark this channel ready for intr. */
1022 ch->parent->active |= (1 << ch->parent->playchns);
1026 wp_wrapu(ch->parent, 0, APUREG_APUTYPE,
1027 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1028 wp_wrapu(ch->parent, 1, APUREG_APUTYPE,
1029 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1030 wp_wrapu(ch->parent, 2, APUREG_APUTYPE,
1031 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1032 wp_wrapu(ch->parent, 3, APUREG_APUTYPE,
1033 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1036 set_timer(ch->parent);
1037 wp_starttimer(ch->parent);
1038 agg_unlock(ch->parent);
1042 aggch_stop_adc(struct agg_rchinfo *ch)
1046 agg_lock(ch->parent);
1048 /* to mark that this channel no longer needs further intrs. */
1049 ch->parent->active &= ~(1 << ch->parent->playchns);
1051 for (apuch = 0; apuch < 4; apuch++)
1052 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
1053 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1055 if (ch->parent->active) {
1056 set_timer(ch->parent);
1057 wp_starttimer(ch->parent);
1059 wp_stoptimer(ch->parent);
1060 agg_power(ch->parent, powerstate_idle);
1062 agg_unlock(ch->parent);
1066 * Feed from L/R channel of ADC to destination with stereo interleaving.
1067 * This function expects n not overwrapping the buffer boundary.
1068 * Note that n is measured in sample unit.
1070 * XXX - this function works in 16bit stereo format only.
1073 interleave(int16_t *l, int16_t *r, int16_t *p, unsigned n)
1077 for (end = l + n; l < end; ) {
1084 aggch_feed_adc_stereo(struct agg_rchinfo *ch)
1089 agg_lock(ch->parent);
1090 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1091 agg_unlock(ch->parent);
1092 cur -= 0xffff & ((ch->srcphys - ch->base) >> 1);
1094 src2 = ch->src + ch->parent->bufsz/4;
1097 interleave(ch->src + last, src2 + last,
1098 ch->sink + 2*last, ch->buflen/2 - last);
1099 interleave(ch->src, src2,
1101 } else if (cur > last)
1102 interleave(ch->src + last, src2 + last,
1103 ch->sink + 2*last, cur - last);
1108 * Feed from R channel of ADC and mixdown to destination L/center.
1109 * This function expects n not overwrapping the buffer boundary.
1110 * Note that n is measured in sample unit.
1112 * XXX - this function works in 16bit monoral format only.
1115 mixdown(int16_t *src, int16_t *dest, unsigned n)
1119 for (end = dest + n; dest < end; dest++)
1120 *dest = (int16_t)(((int)*dest - (int)*src++) / 2);
1124 aggch_feed_adc_mono(struct agg_rchinfo *ch)
1128 agg_lock(ch->parent);
1129 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1130 agg_unlock(ch->parent);
1131 cur -= 0xffff & ((ch->phys - ch->base) >> 1);
1135 mixdown(ch->src + last, ch->sink + last, ch->buflen - last);
1136 mixdown(ch->src, ch->sink, cur);
1137 } else if (cur > last)
1138 mixdown(ch->src + last, ch->sink + last, cur - last);
1142 #ifdef AGG_JITTER_CORRECTION
1144 * Stereo jitter suppressor.
1145 * Sometimes playback pointers differ in stereo-paired channels.
1146 * Calling this routine within intr fixes the problem.
1149 suppress_jitter(struct agg_chinfo *ch)
1152 int cp1, cp2, diff /*, halfsize*/ ;
1154 /*halfsize = (ch->qs16? ch->buflen >> 2 : ch->buflen >> 1);*/
1155 cp1 = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1156 cp2 = wp_rdapu(ch->parent, (ch->num << 1) | 33, APUREG_CURPTR);
1158 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1159 if (diff > 1 /* && diff < halfsize*/ )
1160 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1166 suppress_rec_jitter(struct agg_rchinfo *ch)
1168 int cp1, cp2, diff /*, halfsize*/ ;
1170 /*halfsize = (ch->stereo? ch->buflen >> 2 : ch->buflen >> 1);*/
1171 cp1 = (ch->stereo? ch->parent->bufsz >> 2 : ch->parent->bufsz >> 1)
1172 + wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1173 cp2 = wp_rdapu(ch->parent, 1, APUREG_CURPTR);
1175 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1176 if (diff > 1 /* && diff < halfsize*/ )
1177 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1183 calc_timer_div(struct agg_chinfo *ch)
1190 kprintf("snd_maestro: pch[%d].speed == 0, which shouldn't\n",
1195 return (48000 * (ch->blklen << (!ch->qs16 + !ch->stereo))
1196 + speed - 1) / speed;
1200 calc_timer_div_rch(struct agg_rchinfo *ch)
1207 kprintf("snd_maestro: rch.speed == 0, which shouldn't\n");
1211 return (48000 * (ch->blklen << (!ch->stereo))
1212 + speed - 1) / speed;
1216 set_timer(struct agg_info *ess)
1219 u_int dv = 32 << 7, newdv;
1221 for (i = 0; i < ess->playchns; i++)
1222 if ((ess->active & (1 << i)) &&
1223 (dv > (newdv = calc_timer_div(ess->pch + i))))
1225 if ((ess->active & (1 << i)) &&
1226 (dv > (newdv = calc_timer_div_rch(&ess->rch))))
1229 wp_settimer(ess, dv);
1233 /* -----------------------------
1237 /* AC97 mixer interface. */
1240 agg_ac97_init(kobj_t obj, void *sc)
1242 struct agg_info *ess = sc;
1244 return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1;
1248 agg_ac97_read(kobj_t obj, void *sc, int regno)
1250 struct agg_info *ess = sc;
1253 /* XXX sound locking violation: agg_lock(ess); */
1254 ret = agg_rdcodec(ess, regno);
1255 /* agg_unlock(ess); */
1260 agg_ac97_write(kobj_t obj, void *sc, int regno, u_int32_t data)
1262 struct agg_info *ess = sc;
1265 /* XXX sound locking violation: agg_lock(ess); */
1266 ret = agg_wrcodec(ess, regno, data);
1267 /* agg_unlock(ess); */
1272 static kobj_method_t agg_ac97_methods[] = {
1273 KOBJMETHOD(ac97_init, agg_ac97_init),
1274 KOBJMETHOD(ac97_read, agg_ac97_read),
1275 KOBJMETHOD(ac97_write, agg_ac97_write),
1278 AC97_DECLARE(agg_ac97);
1281 /* -------------------------------------------------------------------- */
1283 /* Playback channel. */
1286 aggpch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1287 struct pcm_channel *c, int dir)
1289 struct agg_info *ess = devinfo;
1290 struct agg_chinfo *ch;
1291 bus_addr_t physaddr;
1294 KASSERT((dir == PCMDIR_PLAY),
1295 ("aggpch_init() called for RECORDING channel!"));
1296 ch = ess->pch + ess->playchns;
1301 ch->num = ess->playchns;
1303 p = dma_malloc(ess->buf_dmat, ess->bufsz, &physaddr, &ch->map);
1306 ch->phys = physaddr;
1307 ch->base = physaddr & ((~(bus_addr_t)0) << WAVCACHE_BASEADDR_SHIFT);
1309 sndbuf_setup(b, p, ess->bufsz);
1310 ch->blklen = sndbuf_getblksz(b) / 2;
1311 ch->buflen = sndbuf_getsize(b) / 2;
1318 adjust_pchbase(struct agg_chinfo *chans, u_int n, u_int size)
1320 struct agg_chinfo *pchs[AGG_MAXPLAYCH];
1324 /* sort pchs by phys address */
1325 for (i = 0; i < n; i++) {
1326 for (j = 0; j < i; j++)
1327 if (chans[i].phys < pchs[j]->phys) {
1328 for (k = i; k > j; k--)
1329 pchs[k] = pchs[k - 1];
1332 pchs[j] = chans + i;
1335 /* use new base register if next buffer can not be addressed
1336 via current base. */
1337 #define BASE_SHIFT (WPWA_WTBAR_SHIFT(2) + 2 + 1)
1338 base = pchs[0]->base;
1339 for (k = 1, i = 1; i < n; i++) {
1340 if (pchs[i]->phys + size - base >= 1 << BASE_SHIFT)
1341 /* not addressable: assign new base */
1342 base = (pchs[i]->base -= k++ << BASE_SHIFT);
1344 pchs[i]->base = base;
1349 kprintf("Total of %d bases are assigned.\n", k);
1350 for (i = 0; i < n; i++) {
1351 kprintf("ch.%d: phys 0x%llx, wpwa 0x%llx\n",
1352 i, (long long)chans[i].phys,
1353 (long long)(chans[i].phys -
1354 chans[i].base) >> 1);
1360 aggpch_free(kobj_t obj, void *data)
1362 struct agg_chinfo *ch = data;
1363 struct agg_info *ess = ch->parent;
1365 /* free up buffer - called after channel stopped */
1366 dma_free(ess->buf_dmat, sndbuf_getbuf(ch->buffer), ch->map);
1368 /* return 0 if ok */
1373 aggpch_setformat(kobj_t obj, void *data, u_int32_t format)
1375 struct agg_chinfo *ch = data;
1377 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE)
1379 ch->stereo = ch->qs16 = ch->us = 0;
1380 if (AFMT_CHANNEL(format) > 1)
1383 if (format & AFMT_U8 || format & AFMT_S8) {
1384 if (format & AFMT_U8)
1392 aggpch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1395 ((struct agg_chinfo*)data)->speed = speed;
1401 aggpch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1403 struct agg_chinfo *ch = data;
1406 /* try to keep at least 20msec DMA space */
1407 blkcnt = (ch->speed << (ch->stereo + ch->qs16)) / (50 * blocksize);
1408 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1410 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1411 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1412 blkcnt = sndbuf_getblkcnt(ch->buffer);
1413 blocksize = sndbuf_getblksz(ch->buffer);
1415 sndbuf_setblkcnt(ch->buffer, blkcnt);
1416 sndbuf_setblksz(ch->buffer, blocksize);
1419 ch->blklen = blocksize / 2;
1420 ch->buflen = blkcnt * blocksize / 2;
1425 aggpch_trigger(kobj_t obj, void *data, int go)
1427 struct agg_chinfo *ch = data;
1430 case PCMTRIG_EMLDMAWR:
1433 aggch_start_dac(ch);
1444 aggpch_getptr(kobj_t obj, void *data)
1446 struct agg_chinfo *ch = data;
1449 agg_lock(ch->parent);
1450 cp = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1451 agg_unlock(ch->parent);
1453 return ch->qs16 && ch->stereo
1454 ? (cp << 2) - ((0xffff << 2) & (ch->phys - ch->base))
1455 : (cp << 1) - ((0xffff << 1) & (ch->phys - ch->base));
1458 static struct pcmchan_caps *
1459 aggpch_getcaps(kobj_t obj, void *data)
1461 static u_int32_t playfmt[] = {
1462 SND_FORMAT(AFMT_U8, 1, 0),
1463 SND_FORMAT(AFMT_U8, 2, 0),
1464 SND_FORMAT(AFMT_S8, 1, 0),
1465 SND_FORMAT(AFMT_S8, 2, 0),
1466 SND_FORMAT(AFMT_S16_LE, 1, 0),
1467 SND_FORMAT(AFMT_S16_LE, 2, 0),
1470 static struct pcmchan_caps playcaps = {8000, 48000, playfmt, 0};
1476 static kobj_method_t aggpch_methods[] = {
1477 KOBJMETHOD(channel_init, aggpch_init),
1478 KOBJMETHOD(channel_free, aggpch_free),
1479 KOBJMETHOD(channel_setformat, aggpch_setformat),
1480 KOBJMETHOD(channel_setspeed, aggpch_setspeed),
1481 KOBJMETHOD(channel_setblocksize, aggpch_setblocksize),
1482 KOBJMETHOD(channel_trigger, aggpch_trigger),
1483 KOBJMETHOD(channel_getptr, aggpch_getptr),
1484 KOBJMETHOD(channel_getcaps, aggpch_getcaps),
1487 CHANNEL_DECLARE(aggpch);
1490 /* -------------------------------------------------------------------- */
1492 /* Recording channel. */
1495 aggrch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1496 struct pcm_channel *c, int dir)
1498 struct agg_info *ess = devinfo;
1499 struct agg_rchinfo *ch;
1502 KASSERT((dir == PCMDIR_REC),
1503 ("aggrch_init() called for PLAYBACK channel!"));
1510 /* Uses the bottom-half of the status buffer. */
1511 p = ess->stat + ess->bufsz;
1512 ch->phys = ess->phys + ess->bufsz;
1513 ch->base = ess->phys;
1514 ch->src = (int16_t *)(p + ess->bufsz);
1515 ch->srcphys = ch->phys + ess->bufsz;
1516 ch->sink = (int16_t *)p;
1518 sndbuf_setup(b, p, ess->bufsz);
1519 ch->blklen = sndbuf_getblksz(b) / 2;
1520 ch->buflen = sndbuf_getsize(b) / 2;
1526 aggrch_setformat(kobj_t obj, void *data, u_int32_t format)
1528 struct agg_rchinfo *ch = data;
1530 if (!(format & AFMT_S16_LE))
1532 if (AFMT_CHANNEL(format) > 1)
1540 aggrch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1543 ((struct agg_rchinfo*)data)->speed = speed;
1549 aggrch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1551 struct agg_rchinfo *ch = data;
1554 /* try to keep at least 20msec DMA space */
1555 blkcnt = (ch->speed << ch->stereo) / (25 * blocksize);
1556 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1558 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1559 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1560 blkcnt = sndbuf_getblkcnt(ch->buffer);
1561 blocksize = sndbuf_getblksz(ch->buffer);
1563 sndbuf_setblkcnt(ch->buffer, blkcnt);
1564 sndbuf_setblksz(ch->buffer, blocksize);
1567 ch->blklen = blocksize / 2;
1568 ch->buflen = blkcnt * blocksize / 2;
1573 aggrch_trigger(kobj_t obj, void *sc, int go)
1575 struct agg_rchinfo *ch = sc;
1578 case PCMTRIG_EMLDMARD:
1580 aggch_feed_adc_stereo(ch);
1582 aggch_feed_adc_mono(ch);
1585 aggch_start_adc(ch);
1596 aggrch_getptr(kobj_t obj, void *sc)
1598 struct agg_rchinfo *ch = sc;
1600 return ch->stereo? ch->hwptr << 2 : ch->hwptr << 1;
1603 static struct pcmchan_caps *
1604 aggrch_getcaps(kobj_t obj, void *sc)
1606 static u_int32_t recfmt[] = {
1607 SND_FORMAT(AFMT_S16_LE, 1, 0),
1608 SND_FORMAT(AFMT_S16_LE, 2, 0),
1611 static struct pcmchan_caps reccaps = {8000, 48000, recfmt, 0};
1616 static kobj_method_t aggrch_methods[] = {
1617 KOBJMETHOD(channel_init, aggrch_init),
1618 /* channel_free: no-op */
1619 KOBJMETHOD(channel_setformat, aggrch_setformat),
1620 KOBJMETHOD(channel_setspeed, aggrch_setspeed),
1621 KOBJMETHOD(channel_setblocksize, aggrch_setblocksize),
1622 KOBJMETHOD(channel_trigger, aggrch_trigger),
1623 KOBJMETHOD(channel_getptr, aggrch_getptr),
1624 KOBJMETHOD(channel_getcaps, aggrch_getcaps),
1627 CHANNEL_DECLARE(aggrch);
1630 /* -----------------------------
1637 struct agg_info* ess = sc;
1638 register u_int8_t status;
1642 status = AGG_RD(ess, PORT_HOSTINT_STAT, 1);
1646 /* Acknowledge intr. */
1647 AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
1649 if (status & HOSTINT_STAT_DSOUND) {
1650 #ifdef AGG_JITTER_CORRECTION
1653 if (ess->curpwr <= PCI_POWERSTATE_D1) {
1654 AGG_WR(ess, PORT_INT_STAT, 1, 2);
1655 #ifdef AGG_JITTER_CORRECTION
1656 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1657 if (ess->active & m)
1658 suppress_jitter(ess->pch + i);
1660 if (ess->active & m)
1661 suppress_rec_jitter(&ess->rch);
1664 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1665 if (ess->active & m) {
1666 if (ess->curpwr <= PCI_POWERSTATE_D1)
1667 chn_intr(ess->pch[i].channel);
1674 if ((ess->active & m)
1675 && ess->curpwr <= PCI_POWERSTATE_D1)
1676 chn_intr(ess->rch.channel);
1678 #ifdef AGG_JITTER_CORRECTION
1684 if (status & HOSTINT_STAT_HWVOL) {
1685 register u_int8_t event;
1688 event = AGG_RD(ess, PORT_HWVOL_MASTER, 1);
1689 AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
1694 mixer_hwvol_step(ess->dev, 1, 1);
1697 mixer_hwvol_step(ess->dev, -1, -1);
1702 if (event & HWVOL_MUTE) {
1703 mixer_hwvol_mute(ess->dev);
1706 device_printf(ess->dev,
1707 "%s: unknown HWVOL event 0x%x\n",
1708 device_get_nameunit(ess->dev), event);
1714 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1716 bus_addr_t *phys = arg;
1718 *phys = error? 0 : segs->ds_addr;
1721 kprintf("setmap (%lx, %lx), nseg=%d, error=%d\n",
1722 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1728 dma_malloc(bus_dma_tag_t dmat, u_int32_t sz, bus_addr_t *phys,
1733 if (bus_dmamem_alloc(dmat, &buf, BUS_DMA_NOWAIT, map))
1735 if (bus_dmamap_load(dmat, *map, buf, sz, setmap, phys, 0) != 0 ||
1737 bus_dmamem_free(dmat, buf, *map);
1744 dma_free(bus_dma_tag_t dmat, void *buf, bus_dmamap_t map)
1746 bus_dmamap_unload(dmat, map);
1747 bus_dmamem_free(dmat, buf, map);
1751 agg_probe(device_t dev)
1755 switch (pci_get_devid(dev)) {
1756 case MAESTRO_1_PCI_ID:
1757 s = "ESS Technology Maestro-1";
1760 case MAESTRO_2_PCI_ID:
1761 s = "ESS Technology Maestro-2";
1764 case MAESTRO_2E_PCI_ID:
1765 s = "ESS Technology Maestro-2E";
1769 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
1770 device_set_desc(dev, s);
1771 return BUS_PROBE_DEFAULT;
1777 agg_attach(device_t dev)
1779 struct agg_info *ess = NULL;
1781 int regid = PCIR_BAR(0);
1782 struct resource *reg = NULL;
1783 struct ac97_info *codec = NULL;
1785 struct resource *irq = NULL;
1787 char status[SND_STATUSLEN];
1790 ess = kmalloc(sizeof(*ess), M_DEVBUF, M_WAITOK | M_ZERO);
1793 lockinit(&ess->lock, device_get_desc(dev), 0, LK_CANRECURSE);
1795 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1796 "dac", &dacn) == 0) {
1799 else if (dacn > AGG_MAXPLAYCH)
1800 dacn = AGG_MAXPLAYCH;
1802 dacn = AGG_MAXPLAYCH;
1804 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
1805 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1806 /*align */ 4, 1 << (16+1),
1807 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1808 /*filter*/ NULL, NULL,
1809 /*size */ ess->bufsz, 1, 0x3ffff,
1811 /*lock */ busdma_lock_mutex, &Giant,
1812 &ess->buf_dmat) != 0) {
1813 device_printf(dev, "unable to create dma tag\n");
1818 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1819 /*align */ 1 << WAVCACHE_BASEADDR_SHIFT,
1821 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1822 /*filter*/ NULL, NULL,
1823 /*size */ 3*ess->bufsz, 1, 0x3ffff,
1825 /*lock */ busdma_lock_mutex, &Giant,
1826 &ess->stat_dmat) != 0) {
1827 device_printf(dev, "unable to create dma tag\n");
1832 /* Allocate the room for brain-damaging status buffer. */
1833 ess->stat = dma_malloc(ess->stat_dmat, 3*ess->bufsz, &ess->phys,
1835 if (ess->stat == NULL) {
1836 device_printf(dev, "cannot allocate status buffer\n");
1841 device_printf(dev, "Maestro status/record buffer: %#llx\n",
1842 (long long)ess->phys);
1844 /* State D0-uninitialized. */
1845 ess->curpwr = PCI_POWERSTATE_D3;
1846 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1848 pci_enable_busmaster(dev);
1850 /* Allocate resources. */
1851 reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, ®id, RF_ACTIVE);
1855 ess->st = rman_get_bustag(reg);
1856 ess->sh = rman_get_bushandle(reg);
1858 device_printf(dev, "unable to map register space\n");
1862 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
1863 RF_ACTIVE | RF_SHAREABLE);
1868 device_printf(dev, "unable to map interrupt\n");
1873 /* Setup resources. */
1874 if (snd_setup_intr(dev, irq, INTR_MPSAFE, agg_intr, ess, &ih)) {
1875 device_printf(dev, "unable to setup interrupt\n");
1881 /* Transition from D0-uninitialized to D0. */
1883 agg_power(ess, PCI_POWERSTATE_D0);
1884 if (agg_rdcodec(ess, 0) == 0x80) {
1885 /* XXX - TODO: PT101 */
1887 device_printf(dev, "PT101 codec detected!\n");
1892 codec = AC97_CREATE(dev, ess, agg_ac97);
1893 if (codec == NULL) {
1894 device_printf(dev, "failed to create AC97 codec softc!\n");
1898 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) {
1899 device_printf(dev, "mixer initialization failed!\n");
1905 ret = pcm_register(dev, ess, dacn, 1);
1909 mixer_hwvol_init(dev);
1911 agg_power(ess, powerstate_init);
1913 for (data = 0; data < dacn; data++)
1914 pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess);
1915 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1916 adjust_pchbase(ess->pch, ess->playchns, ess->bufsz);
1918 ksnprintf(status, SND_STATUSLEN,
1919 "port 0x%lx-0x%lx irq %ld at device %d.%d on pci%d",
1920 rman_get_start(reg), rman_get_end(reg), rman_get_start(irq),
1921 pci_get_slot(dev), pci_get_function(dev), pci_get_bus(dev));
1922 pcm_setstatus(dev, status);
1928 ac97_destroy(codec);
1930 bus_teardown_intr(dev, irq, ih);
1932 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1934 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1936 if (ess->stat != NULL)
1937 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1938 if (ess->stat_dmat != NULL)
1939 bus_dma_tag_destroy(ess->stat_dmat);
1940 if (ess->buf_dmat != NULL)
1941 bus_dma_tag_destroy(ess->buf_dmat);
1942 lockuninit(&ess->lock);
1943 kfree(ess, M_DEVBUF);
1950 agg_detach(device_t dev)
1952 struct agg_info *ess = pcm_getdevinfo(dev);
1956 icr = AGG_RD(ess, PORT_HOSTINT_CTRL, 2);
1957 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1961 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1967 r = pcm_unregister(dev);
1969 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1974 agg_power(ess, PCI_POWERSTATE_D3);
1977 bus_teardown_intr(dev, ess->irq, ess->ih);
1978 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1979 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1980 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1981 bus_dma_tag_destroy(ess->stat_dmat);
1982 bus_dma_tag_destroy(ess->buf_dmat);
1983 lockuninit(&ess->lock);
1984 kfree(ess, M_DEVBUF);
1989 agg_suspend(device_t dev)
1991 struct agg_info *ess = pcm_getdevinfo(dev);
1993 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1995 agg_power(ess, PCI_POWERSTATE_D3);
2002 agg_resume(device_t dev)
2005 struct agg_info *ess = pcm_getdevinfo(dev);
2007 for (i = 0; i < ess->playchns; i++)
2008 if (ess->active & (1 << i))
2009 aggch_start_dac(ess->pch + i);
2010 if (ess->active & (1 << i))
2011 aggch_start_adc(&ess->rch);
2015 agg_power(ess, powerstate_init);
2018 if (mixer_reinit(dev)) {
2019 device_printf(dev, "unable to reinitialize the mixer\n");
2027 agg_shutdown(device_t dev)
2029 struct agg_info *ess = pcm_getdevinfo(dev);
2032 agg_power(ess, PCI_POWERSTATE_D3);
2039 static device_method_t agg_methods[] = {
2040 DEVMETHOD(device_probe, agg_probe),
2041 DEVMETHOD(device_attach, agg_attach),
2042 DEVMETHOD(device_detach, agg_detach),
2043 DEVMETHOD(device_suspend, agg_suspend),
2044 DEVMETHOD(device_resume, agg_resume),
2045 DEVMETHOD(device_shutdown, agg_shutdown),
2050 static driver_t agg_driver = {
2056 /*static devclass_t pcm_devclass;*/
2058 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0);
2059 MODULE_DEPEND(snd_maestro, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2060 MODULE_VERSION(snd_maestro, 1);