2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
35 * Used in the LinkSys USB200M and various other adapters.
37 * Manuals available from:
38 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
39 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
40 * controller) to find the definitions for the RX control register.
41 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
43 * Written by Bill Paul <wpaul@windriver.com>
49 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
50 * It uses an external PHY (reference designs use a RealTek chip),
51 * and has a 64-bit multicast hash filter. There is some information
52 * missing from the manual which one needs to know in order to make
55 * - You must set bit 7 in the RX control register, otherwise the
56 * chip won't receive any packets.
57 * - You must initialize all 3 IPG registers, or you won't be able
58 * to send any packets.
60 * Note that this device appears to only support loading the station
61 * address via autload from the EEPROM (i.e. there's no way to manaully
64 * (Adam Weinberger wanted me to name this driver if_gir.c.)
68 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
69 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
72 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
73 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
76 #include <sys/param.h>
77 #include <sys/systm.h>
79 #include <sys/condvar.h>
80 #include <sys/endian.h>
81 #include <sys/kernel.h>
83 #include <sys/malloc.h>
85 #include <sys/module.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
91 #include <net/ethernet.h>
92 #include <net/if_types.h>
93 #include <net/if_media.h>
94 #include <net/vlan/if_vlan_var.h>
95 #include <net/ifq_var.h>
97 #include <dev/netif/mii_layer/mii.h>
98 #include <dev/netif/mii_layer/miivar.h>
100 #include <bus/u4b/usb.h>
101 #include <bus/u4b/usbdi.h>
102 #include <bus/u4b/usbdi_util.h>
105 #define USB_DEBUG_VAR axe_debug
106 #include <bus/u4b/usb_debug.h>
107 #include <bus/u4b/usb_process.h>
109 #include <bus/u4b/net/usb_ethernet.h>
110 #include <bus/u4b/net/if_axereg.h>
113 * AXE_178_MAX_FRAME_BURST
114 * max frame burst size for Ax88178 and Ax88772
119 * use the largest your system can handle without USB stalling.
121 * NB: 88772 parts appear to generate lots of input errors with
122 * a 2K rx buffer and 8K is only slightly faster than 4K on an
123 * EHCI port on a T42 so change at your own risk.
125 #define AXE_178_MAX_FRAME_BURST 1
127 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
130 static int axe_debug = 0;
132 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe");
133 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0,
138 * Various supported device vendors/products.
140 static const STRUCT_USB_HOST_ID axe_devs[] = {
141 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
142 AXE_DEV(ABOCOM, UF200, 0),
143 AXE_DEV(ACERCM, EP1427X2, 0),
144 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
145 AXE_DEV(ASIX, AX88172, 0),
146 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
147 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
148 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
149 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
150 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B),
151 AXE_DEV(ATEN, UC210T, 0),
152 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
153 AXE_DEV(BILLIONTON, USB2AR, 0),
154 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
155 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
156 AXE_DEV(DLINK, DUBE100, 0),
157 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
158 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B),
159 AXE_DEV(GOODWAY, GWUSB2E, 0),
160 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
161 AXE_DEV(JVC, MP_PRX1, 0),
162 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B),
163 AXE_DEV(LINKSYS2, USB200M, 0),
164 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
165 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
166 AXE_DEV(MELCO, LUAU2KTX, 0),
167 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
168 AXE_DEV(NETGEAR, FA120, 0),
169 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
170 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
171 AXE_DEV(SITECOM, LN029, 0),
172 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
173 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
177 static device_probe_t axe_probe;
178 static device_attach_t axe_attach;
179 static device_detach_t axe_detach;
181 static usb_callback_t axe_bulk_read_callback;
182 static usb_callback_t axe_bulk_write_callback;
184 static miibus_readreg_t axe_miibus_readreg;
185 static miibus_writereg_t axe_miibus_writereg;
186 static miibus_statchg_t axe_miibus_statchg;
188 static uether_fn_t axe_attach_post;
189 static uether_fn_t axe_init;
190 static uether_fn_t axe_stop;
191 static uether_fn_t axe_start;
192 static uether_fn_t axe_tick;
193 static uether_fn_t axe_setmulti;
194 static uether_fn_t axe_setpromisc;
196 static int axe_attach_post_sub(struct usb_ether *);
197 static int axe_ifmedia_upd(struct ifnet *);
198 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
199 static int axe_cmd(struct axe_softc *, int, int, int, void *);
200 static void axe_ax88178_init(struct axe_softc *);
201 static void axe_ax88772_init(struct axe_softc *);
202 static void axe_ax88772_phywake(struct axe_softc *);
203 static void axe_ax88772a_init(struct axe_softc *);
204 static void axe_ax88772b_init(struct axe_softc *);
205 static int axe_get_phyno(struct axe_softc *, int);
206 static int axe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
207 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
208 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *,
209 unsigned int offset, unsigned int, struct axe_csum_hdr *);
210 static void axe_csum_cfg(struct usb_ether *);
212 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
216 .endpoint = UE_ADDR_ANY,
217 .direction = UE_DIR_OUT,
219 .bufsize = 16 * MCLBYTES,
220 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
221 .callback = axe_bulk_write_callback,
222 .timeout = 10000, /* 10 seconds */
227 .endpoint = UE_ADDR_ANY,
228 .direction = UE_DIR_IN,
229 .bufsize = 16384, /* bytes */
230 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
231 .callback = axe_bulk_read_callback,
232 .timeout = 0, /* no timeout */
236 static const struct ax88772b_mfb ax88772b_mfb_table[] = {
237 { 0x8000, 0x8001, 2048 },
238 { 0x8100, 0x8147, 4096},
239 { 0x8200, 0x81EB, 6144},
240 { 0x8300, 0x83D7, 8192},
241 { 0x8400, 0x851E, 16384},
242 { 0x8500, 0x8666, 20480},
243 { 0x8600, 0x87AE, 24576},
244 { 0x8700, 0x8A3D, 32768}
247 static device_method_t axe_methods[] = {
248 /* Device interface */
249 DEVMETHOD(device_probe, axe_probe),
250 DEVMETHOD(device_attach, axe_attach),
251 DEVMETHOD(device_detach, axe_detach),
254 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
255 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
256 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
261 static driver_t axe_driver = {
263 .methods = axe_methods,
264 .size = sizeof(struct axe_softc),
267 static devclass_t axe_devclass;
269 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, NULL);
270 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, NULL, NULL);
271 MODULE_DEPEND(axe, uether, 1, 1, 1);
272 MODULE_DEPEND(axe, usb, 1, 1, 1);
273 MODULE_DEPEND(axe, ether, 1, 1, 1);
274 MODULE_DEPEND(axe, miibus, 1, 1, 1);
275 MODULE_VERSION(axe, 1);
277 static const struct usb_ether_methods axe_ue_methods = {
278 .ue_attach_post = axe_attach_post,
279 .ue_attach_post_sub = axe_attach_post_sub,
280 .ue_start = axe_start,
284 .ue_setmulti = axe_setmulti,
285 .ue_setpromisc = axe_setpromisc,
286 .ue_mii_upd = axe_ifmedia_upd,
287 .ue_mii_sts = axe_ifmedia_sts,
291 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
293 struct usb_device_request req;
298 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
299 UT_WRITE_VENDOR_DEVICE :
300 UT_READ_VENDOR_DEVICE);
301 req.bRequest = AXE_CMD_CMD(cmd);
302 USETW(req.wValue, val);
303 USETW(req.wIndex, index);
304 USETW(req.wLength, AXE_CMD_LEN(cmd));
306 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
312 axe_miibus_readreg(device_t dev, int phy, int reg)
314 struct axe_softc *sc = device_get_softc(dev);
318 locked = lockowned(&sc->sc_lock);
322 if(phy != sc->sc_phyno){
328 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
329 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
330 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
333 if (AXE_IS_772(sc) && reg == MII_BMSR) {
335 * BMSR of AX88772 indicates that it supports extended
336 * capability but the extended status register is
337 * revered for embedded ethernet PHY. So clear the
338 * extended capability bit of BMSR.
349 axe_miibus_writereg(device_t dev, int phy, int reg, int val)
351 struct axe_softc *sc = device_get_softc(dev);
355 locked = lockowned(&sc->sc_lock);
359 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
360 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
361 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
369 axe_miibus_statchg(device_t dev)
371 struct axe_softc *sc = device_get_softc(dev);
372 struct mii_data *mii = GET_MII(sc);
377 locked = lockowned(&sc->sc_lock);
381 ifp = uether_getifp(&sc->sc_ue);
382 if (mii == NULL || ifp == NULL ||
383 (ifp->if_flags & IFF_RUNNING) == 0)
386 sc->sc_flags &= ~AXE_FLAG_LINK;
387 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
388 (IFM_ACTIVE | IFM_AVALID)) {
389 switch (IFM_SUBTYPE(mii->mii_media_active)) {
392 sc->sc_flags |= AXE_FLAG_LINK;
395 if ((sc->sc_flags & AXE_FLAG_178) == 0)
397 sc->sc_flags |= AXE_FLAG_LINK;
398 DPRINTFN(11, "miibus_statchg: link should be up\n");
404 DPRINTFN(11, "miibus_statchg: not active or not valid: %x\n", mii->mii_media_status);
407 /* Lost link, do nothing. */
408 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
413 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
414 val |= AXE_MEDIA_FULL_DUPLEX;
415 if (AXE_IS_178_FAMILY(sc)) {
416 if ((IFM_OPTIONS(mii->mii_media_active) &
417 IFM_ETH_TXPAUSE) != 0)
418 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN;
419 if ((IFM_OPTIONS(mii->mii_media_active) &
420 IFM_ETH_RXPAUSE) != 0)
421 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN;
424 if (AXE_IS_178_FAMILY(sc)) {
425 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
426 if ((sc->sc_flags & AXE_FLAG_178) != 0)
427 val |= AXE_178_MEDIA_ENCK;
428 switch (IFM_SUBTYPE(mii->mii_media_active)) {
430 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
433 val |= AXE_178_MEDIA_100TX;
436 /* doesn't need to be handled */
440 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
442 device_printf(dev, "media change failed, error %d\n", err);
452 axe_ifmedia_upd(struct ifnet *ifp)
454 struct axe_softc *sc = ifp->if_softc;
455 struct mii_data *mii = GET_MII(sc);
456 struct mii_softc *miisc;
461 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
462 mii_phy_reset(miisc);
463 error = mii_mediachg(mii);
468 * Report current media status.
471 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
473 struct axe_softc *sc = ifp->if_softc;
474 struct mii_data *mii = GET_MII(sc);
478 ifmr->ifm_active = mii->mii_media_active;
479 ifmr->ifm_status = mii->mii_media_status;
484 axe_setmulti(struct usb_ether *ue)
486 struct axe_softc *sc = uether_getsc(ue);
487 struct ifnet *ifp = uether_getifp(ue);
488 struct ifmultiaddr *ifma;
491 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
495 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
496 rxmode = le16toh(rxmode);
498 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
499 rxmode |= AXE_RXCMD_ALLMULTI;
500 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
503 rxmode &= ~AXE_RXCMD_ALLMULTI;
505 /* if_maddr_rlock(ifp); */
506 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
508 if (ifma->ifma_addr->sa_family != AF_LINK)
510 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
511 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
512 hashtbl[h / 8] |= 1 << (h % 8);
514 /* if_maddr_runlock(ifp); */
516 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
517 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
521 axe_get_phyno(struct axe_softc *sc, int sel)
525 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
526 case PHY_TYPE_100_HOME:
528 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
530 case PHY_TYPE_SPECIAL:
534 case PHY_TYPE_NON_SUP:
544 #define AXE_GPIO_WRITE(x, y) do { \
545 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
546 uether_pause(ue, (y)); \
550 axe_ax88178_init(struct axe_softc *sc)
552 struct usb_ether *ue;
553 int gpio0, ledmode, phymode;
554 uint16_t eeprom, val;
557 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
559 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
560 eeprom = le16toh(eeprom);
561 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
563 /* if EEPROM is invalid we have to use to GPIO0 */
564 if (eeprom == 0xffff) {
565 phymode = AXE_PHY_MODE_MARVELL;
569 phymode = eeprom & 0x7f;
570 gpio0 = (eeprom & 0x80) ? 0 : 1;
571 ledmode = eeprom >> 8;
575 device_printf(sc->sc_ue.ue_dev,
576 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
578 /* Program GPIOs depending on PHY hardware. */
580 case AXE_PHY_MODE_MARVELL:
582 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
584 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
586 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
587 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
590 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
591 AXE_GPIO1_EN, hz / 3);
593 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
594 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
597 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
598 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
599 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
600 AXE_GPIO2_EN, hz / 4);
601 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
602 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
606 case AXE_PHY_MODE_CICADA:
607 case AXE_PHY_MODE_CICADA_V2:
608 case AXE_PHY_MODE_CICADA_V2_ASIX:
610 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
611 AXE_GPIO0_EN, hz / 32);
613 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
614 AXE_GPIO1_EN, hz / 32);
616 case AXE_PHY_MODE_AGERE:
617 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
618 AXE_GPIO1_EN, hz / 32);
619 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
620 AXE_GPIO2_EN, hz / 32);
621 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
622 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
623 AXE_GPIO2_EN, hz / 32);
625 case AXE_PHY_MODE_REALTEK_8211CL:
626 case AXE_PHY_MODE_REALTEK_8211BN:
627 case AXE_PHY_MODE_REALTEK_8251CL:
628 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
629 AXE_GPIO1 | AXE_GPIO1_EN;
630 AXE_GPIO_WRITE(val, hz / 32);
631 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
632 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
633 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
634 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
635 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
637 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
639 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
641 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
643 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
648 /* Unknown PHY model or no need to program GPIOs. */
653 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
654 uether_pause(ue, hz / 4);
656 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
657 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
658 uether_pause(ue, hz / 4);
659 /* Enable MII/GMII/RGMII interface to work with external PHY. */
660 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
661 uether_pause(ue, hz / 4);
663 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
667 axe_ax88772_init(struct axe_softc *sc)
669 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
670 uether_pause(&sc->sc_ue, hz / 16);
672 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
673 /* ask for the embedded PHY */
674 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
675 uether_pause(&sc->sc_ue, hz / 64);
677 /* power down and reset state, pin reset state */
678 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
679 AXE_SW_RESET_CLEAR, NULL);
680 uether_pause(&sc->sc_ue, hz / 16);
682 /* power down/reset state, pin operating state */
683 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
684 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
685 uether_pause(&sc->sc_ue, hz / 4);
687 /* power up, reset */
688 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
690 /* power up, operating */
691 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
692 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
694 /* ask for external PHY */
695 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
696 uether_pause(&sc->sc_ue, hz / 64);
698 /* power down internal PHY */
699 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
700 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
703 uether_pause(&sc->sc_ue, hz / 4);
704 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
708 axe_ax88772_phywake(struct axe_softc *sc)
710 struct usb_ether *ue;
713 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
714 /* Manually select internal(embedded) PHY - MAC mode. */
715 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
716 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
718 uether_pause(&sc->sc_ue, hz / 32);
721 * Manually select external PHY - MAC mode.
722 * Reverse MII/RMII is for AX88772A PHY mode.
724 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
725 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
726 uether_pause(&sc->sc_ue, hz / 32);
728 /* Take PHY out of power down. */
729 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
730 AXE_SW_RESET_IPRL, NULL);
731 uether_pause(&sc->sc_ue, hz / 4);
732 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
733 uether_pause(&sc->sc_ue, hz);
734 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
735 uether_pause(&sc->sc_ue, hz / 32);
736 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
737 uether_pause(&sc->sc_ue, hz / 32);
741 axe_ax88772a_init(struct axe_softc *sc)
743 struct usb_ether *ue;
747 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
748 axe_ax88772_phywake(sc);
750 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
754 axe_ax88772b_init(struct axe_softc *sc)
756 struct usb_ether *ue;
763 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
765 * Save PHY power saving configuration(high byte) and
766 * clear EEPROM checksum value(low byte).
768 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
769 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
772 * Auto-loaded default station address from internal ROM is
773 * 00:00:00:00:00:00 such that an explicit access to EEPROM
774 * is required to get real station address.
776 eaddr = ue->ue_eaddr;
777 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
778 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
780 eeprom = le16toh(eeprom);
781 *eaddr++ = (uint8_t)(eeprom & 0xFF);
782 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
785 axe_ax88772_phywake(sc);
787 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
790 #undef AXE_GPIO_WRITE
793 axe_reset(struct axe_softc *sc)
795 struct usb_config_descriptor *cd;
798 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
800 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_lock,
801 cd->bConfigurationValue);
803 DPRINTF("reset failed (ignored)\n");
805 /* Wait a little while for the chip to get its brains in order. */
806 uether_pause(&sc->sc_ue, hz / 100);
808 /* Reinitialize controller to achieve full reset. */
809 if (sc->sc_flags & AXE_FLAG_178)
810 axe_ax88178_init(sc);
811 else if (sc->sc_flags & AXE_FLAG_772)
812 axe_ax88772_init(sc);
813 else if (sc->sc_flags & AXE_FLAG_772A)
814 axe_ax88772a_init(sc);
815 else if (sc->sc_flags & AXE_FLAG_772B)
816 axe_ax88772b_init(sc);
820 axe_attach_post(struct usb_ether *ue)
822 struct axe_softc *sc = uether_getsc(ue);
825 * Load PHY indexes first. Needed by axe_xxx_init().
827 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
829 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
830 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
831 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
832 if (sc->sc_phyno == -1)
833 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
834 if (sc->sc_phyno == -1) {
835 device_printf(sc->sc_ue.ue_dev,
836 "no valid PHY address found, assuming PHY address 0\n");
840 /* Initialize controller and get station address. */
841 if (sc->sc_flags & AXE_FLAG_178) {
842 axe_ax88178_init(sc);
843 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
844 } else if (sc->sc_flags & AXE_FLAG_772) {
845 axe_ax88772_init(sc);
846 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
847 } else if (sc->sc_flags & AXE_FLAG_772A) {
848 axe_ax88772a_init(sc);
849 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
850 } else if (sc->sc_flags & AXE_FLAG_772B) {
851 axe_ax88772b_init(sc);
853 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
858 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
859 /* Set IPG values. */
860 sc->sc_ipgs[0] = 0x15;
861 sc->sc_ipgs[1] = 0x16;
862 sc->sc_ipgs[2] = 0x1A;
864 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
869 axe_attach_post_sub(struct usb_ether *ue)
871 struct axe_softc *sc;
876 sc = uether_getsc(ue);
877 ifp = uether_getifp(ue);
878 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
879 ifp->if_start = uether_start;
880 ifp->if_ioctl = axe_ioctl;
881 ifp->if_init = uether_init;
882 ifq_set_maxlen(&ifp->if_snd, ifqmaxlen);
883 ifq_set_ready(&ifp->if_snd);
885 if (AXE_IS_178_FAMILY(sc))
886 ifp->if_capabilities |= IFCAP_VLAN_MTU;
887 if (sc->sc_flags & AXE_FLAG_772B) {
888 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM;
889 ifp->if_hwassist = AXE_CSUM_FEATURES;
891 * Checksum offloading of AX88772B also works with VLAN
892 * tagged frames but there is no way to take advantage
893 * of the feature because vlan(4) assumes
894 * IFCAP_VLAN_HWTAGGING is prerequisite condition to
895 * support checksum offloading with VLAN. VLAN hardware
896 * tagging support of AX88772B is very limited so it's
897 * not possible to announce IFCAP_VLAN_HWTAGGING.
900 ifp->if_capenable = ifp->if_capabilities;
901 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178))
902 adv_pause = MIIF_DOPAUSE;
906 /* Careful, miibus assumes that the first member of the softc
907 of it's parent is an arpcom structure --mpf */
908 error = mii_phy_probe(ue->ue_dev, &ue->ue_miibus,
909 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts);
915 * Probe for a AX88172 chip.
918 axe_probe(device_t dev)
920 struct usb_attach_arg *uaa = device_get_ivars(dev);
922 if (uaa->usb_mode != USB_MODE_HOST)
924 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
926 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
929 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
933 * Attach the interface. Allocate softc structures, do ifmedia
934 * setup and ethernet/BPF attach.
937 axe_attach(device_t dev)
939 struct usb_attach_arg *uaa = device_get_ivars(dev);
940 struct axe_softc *sc = device_get_softc(dev);
941 struct usb_ether *ue = &sc->sc_ue;
945 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
947 device_set_usb_desc(dev);
949 lockinit(&sc->sc_lock, device_get_nameunit(dev), 0, 0);
951 iface_index = AXE_IFACE_IDX;
952 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
953 axe_config, AXE_N_TRANSFER, sc, &sc->sc_lock);
955 device_printf(dev, "allocating USB transfers failed\n");
961 ue->ue_udev = uaa->device;
962 ue->ue_lock = &sc->sc_lock;
963 ue->ue_methods = &axe_ue_methods;
965 error = uether_ifattach(ue);
967 device_printf(dev, "could not attach interface\n");
970 return (0); /* success */
974 return (ENXIO); /* failure */
978 axe_detach(device_t dev)
980 struct axe_softc *sc = device_get_softc(dev);
981 struct usb_ether *ue = &sc->sc_ue;
983 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
985 lockuninit(&sc->sc_lock);
990 #if (AXE_BULK_BUF_SIZE >= 0x10000)
991 #error "Please update axe_bulk_read_callback()!"
995 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
997 struct axe_softc *sc = usbd_xfer_softc(xfer);
998 struct usb_ether *ue = &sc->sc_ue;
999 struct usb_page_cache *pc;
1002 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
1004 switch (USB_GET_STATE(xfer)) {
1005 case USB_ST_TRANSFERRED:
1006 pc = usbd_xfer_get_frame(xfer, 0);
1007 axe_rx_frame(ue, pc, actlen);
1012 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
1013 usbd_transfer_submit(xfer);
1017 default: /* Error */
1018 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
1020 if (error != USB_ERR_CANCELLED) {
1021 /* try to clear stall first */
1022 usbd_xfer_set_stall(xfer);
1031 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
1033 struct axe_softc *sc;
1034 struct axe_sframe_hdr hdr;
1035 struct axe_csum_hdr csum_hdr;
1036 int error, len, pos;
1038 sc = uether_getsc(ue);
1042 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
1043 while (pos < actlen) {
1044 if ((int)(pos + sizeof(hdr)) > actlen) {
1045 /* too little data */
1049 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
1051 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
1057 len = le16toh(hdr.len);
1058 if (pos + len > actlen) {
1059 /* invalid length */
1063 axe_rxeof(ue, pc, pos, len, NULL);
1064 pos += len + (len % 2);
1066 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
1067 while (pos < actlen) {
1068 if ((int)(pos + sizeof(csum_hdr)) > actlen) {
1069 /* too little data */
1073 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr));
1075 csum_hdr.len = le16toh(csum_hdr.len);
1076 csum_hdr.ilen = le16toh(csum_hdr.ilen);
1077 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
1078 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
1079 AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
1086 * Get total transferred frame length including
1087 * checksum header. The length should be multiple
1090 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len);
1091 len = (len + 3) & ~3;
1092 if (pos + len > actlen) {
1093 /* invalid length */
1097 axe_rxeof(ue, pc, pos + sizeof(csum_hdr),
1098 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr);
1102 axe_rxeof(ue, pc, 0, actlen, NULL);
1105 IFNET_STAT_INC(uether_getifp(ue), ierrors, 1);
1110 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
1111 unsigned int len, struct axe_csum_hdr *csum_hdr)
1113 struct ifnet *ifp = uether_getifp(ue);
1116 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1117 IFNET_STAT_INC(ifp, ierrors, 1);
1121 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1123 IFNET_STAT_INC(ifp, iqdrops, 1);
1126 m->m_len = m->m_pkthdr.len = MCLBYTES;
1127 m_adj(m, ETHER_ALIGN);
1129 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1131 IFNET_STAT_INC(ifp, ipackets, 1);
1132 m->m_pkthdr.rcvif = ifp;
1133 m->m_pkthdr.len = m->m_len = len;
1135 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) {
1136 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR |
1137 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) {
1138 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1140 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1141 AXE_CSUM_HDR_L4_TYPE_TCP ||
1142 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1143 AXE_CSUM_HDR_L4_TYPE_UDP) {
1144 m->m_pkthdr.csum_flags |=
1145 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1146 m->m_pkthdr.csum_data = 0xffff;
1151 IF_ENQUEUE(&ue->ue_rxq, m);
1155 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1156 #error "Please update axe_bulk_write_callback()!"
1160 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1162 struct axe_softc *sc = usbd_xfer_softc(xfer);
1163 struct axe_sframe_hdr hdr;
1164 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
1165 struct usb_page_cache *pc;
1169 DPRINTFN(11, "starting transfer\n");
1171 switch (USB_GET_STATE(xfer)) {
1172 case USB_ST_TRANSFERRED:
1173 DPRINTFN(11, "transfer complete\n");
1175 ifq_clr_oactive(&ifp->if_snd);
1180 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1181 ifq_is_oactive(&ifp->if_snd)) {
1183 * Don't send anything if there is no link or
1184 * controller is busy.
1186 DPRINTFN(11, "controller busy: sc_flags: %x if_flags %x\n",sc->sc_flags, ifp->if_flags);
1190 DPRINTFN(11, "copying frames, 16 at a time\n");
1191 for (nframes = 0; nframes < 16 &&
1192 !ifq_is_empty(&ifp->if_snd); nframes++) {
1193 m = ifq_dequeue(&ifp->if_snd);
1196 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1199 pc = usbd_xfer_get_frame(xfer, nframes);
1200 if (AXE_IS_178_FAMILY(sc)) {
1201 hdr.len = htole16(m->m_pkthdr.len);
1202 hdr.ilen = ~hdr.len;
1204 * If upper stack computed checksum, driver
1205 * should tell controller not to insert
1206 * computed checksum for checksum offloading
1207 * enabled controller.
1209 if (ifp->if_capabilities & IFCAP_TXCSUM) {
1210 if ((m->m_pkthdr.csum_flags &
1211 AXE_CSUM_FEATURES) != 0)
1213 AXE_TX_CSUM_PSEUDO_HDR);
1218 DPRINTFN(11, "usbd copy in\n");
1219 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1221 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1222 pos += m->m_pkthdr.len;
1223 if ((pos % 512) == 0) {
1226 usbd_copy_in(pc, pos, &hdr,
1231 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1232 pos += m->m_pkthdr.len;
1237 * Update TX packet counter here. This is not
1238 * correct way but it seems that there is no way
1239 * to know how many packets are sent at the end
1240 * of transfer because controller combines
1241 * multiple writes into single one if there is
1242 * room in TX buffer of controller.
1244 IFNET_STAT_INC(ifp, opackets, 1);
1247 * if there's a BPF listener, bounce a copy
1248 * of this frame to him:
1254 /* Set frame length. */
1255 usbd_xfer_set_frame_len(xfer, nframes, pos);
1258 usbd_xfer_set_frames(xfer, nframes);
1259 DPRINTFN(5, "submitting transfer\n");
1260 usbd_transfer_submit(xfer);
1261 ifq_set_oactive(&ifp->if_snd);
1265 default: /* Error */
1266 DPRINTFN(11, "transfer error, %s\n",
1267 usbd_errstr(error));
1269 IFNET_STAT_INC(ifp, oerrors, 1);
1270 ifq_clr_oactive(&ifp->if_snd);
1271 if (error != USB_ERR_CANCELLED) {
1272 /* try to clear stall first */
1273 usbd_xfer_set_stall(xfer);
1282 axe_tick(struct usb_ether *ue)
1284 struct axe_softc *sc = uether_getsc(ue);
1285 struct mii_data *mii = GET_MII(sc);
1287 AXE_LOCK_ASSERT(sc);
1290 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1291 axe_miibus_statchg(ue->ue_dev);
1292 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1298 axe_start(struct usb_ether *ue)
1300 struct axe_softc *sc = uether_getsc(ue);
1303 * start the USB transfers, if not already started:
1305 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1306 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1310 axe_csum_cfg(struct usb_ether *ue)
1312 struct axe_softc *sc;
1314 uint16_t csum1, csum2;
1316 sc = uether_getsc(ue);
1317 AXE_LOCK_ASSERT(sc);
1319 if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1320 ifp = uether_getifp(ue);
1323 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1324 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP |
1326 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1329 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1330 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE |
1331 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP |
1333 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1338 axe_init(struct usb_ether *ue)
1340 struct axe_softc *sc = uether_getsc(ue);
1341 struct ifnet *ifp = uether_getifp(ue);
1344 AXE_LOCK_ASSERT(sc);
1347 if ((ifp->if_flags & IFF_RUNNING) != 0)
1350 /* Cancel pending I/O */
1355 /* Set MAC address and transmitter IPG values. */
1356 if (AXE_IS_178_FAMILY(sc)) {
1357 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1358 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1359 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1361 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1362 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1363 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1364 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1367 if (AXE_IS_178_FAMILY(sc)) {
1368 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1369 if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1370 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK;
1371 sc->sc_flags |= AXE_FLAG_CSUM_FRAME;
1373 sc->sc_lenmask = AXE_HDR_LEN_MASK;
1374 sc->sc_flags |= AXE_FLAG_STD_FRAME;
1378 /* Configure TX/RX checksum offloading. */
1381 if (sc->sc_flags & AXE_FLAG_772B) {
1382 /* AX88772B uses different maximum frame burst configuration. */
1383 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1384 ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1385 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1388 /* Enable receiver, set RX mode. */
1389 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1390 if (AXE_IS_178_FAMILY(sc)) {
1391 if (sc->sc_flags & AXE_FLAG_772B) {
1393 * Select RX header format type 1. Aligning IP
1394 * header on 4 byte boundary is not needed when
1395 * checksum offloading feature is not used
1396 * because we always copy the received frame in
1397 * RX handler. When RX checksum offloading is
1398 * active, aligning IP header is required to
1399 * reflect actual frame length including RX
1402 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1403 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1404 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN;
1407 * Default Rx buffer size is too small to get
1408 * maximum performance.
1410 rxmode |= AXE_178_RXCMD_MFB_16384;
1413 rxmode |= AXE_172_RXCMD_UNICAST;
1416 /* If we want promiscuous mode, set the allframes bit. */
1417 if (ifp->if_flags & IFF_PROMISC)
1418 rxmode |= AXE_RXCMD_PROMISC;
1420 if (ifp->if_flags & IFF_BROADCAST)
1421 rxmode |= AXE_RXCMD_BROADCAST;
1423 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1425 /* Load the multicast filter. */
1428 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1431 ifp->if_flags |= IFF_RUNNING;
1433 /* Switch to selected media. */
1434 axe_ifmedia_upd(ifp);
1438 axe_setpromisc(struct usb_ether *ue)
1440 struct axe_softc *sc = uether_getsc(ue);
1441 struct ifnet *ifp = uether_getifp(ue);
1444 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1446 rxmode = le16toh(rxmode);
1448 if (ifp->if_flags & IFF_PROMISC) {
1449 rxmode |= AXE_RXCMD_PROMISC;
1451 rxmode &= ~AXE_RXCMD_PROMISC;
1454 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1460 axe_stop(struct usb_ether *ue)
1462 struct axe_softc *sc = uether_getsc(ue);
1463 struct ifnet *ifp = uether_getifp(ue);
1465 AXE_LOCK_ASSERT(sc);
1468 ifp->if_flags &= ~IFF_RUNNING;
1469 ifq_clr_oactive(&ifp->if_snd);
1471 sc->sc_flags &= ~AXE_FLAG_LINK;
1474 * stop all the transfers, if not already stopped:
1476 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1477 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1481 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *uc)
1483 struct usb_ether *ue = ifp->if_softc;
1484 struct axe_softc *sc;
1486 int error, mask, reinit;
1488 sc = uether_getsc(ue);
1489 ifr = (struct ifreq *)data;
1492 if (cmd == SIOCSIFCAP) {
1494 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1495 if ((mask & IFCAP_TXCSUM) != 0 &&
1496 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1497 ifp->if_capenable ^= IFCAP_TXCSUM;
1498 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1499 ifp->if_hwassist |= AXE_CSUM_FEATURES;
1501 ifp->if_hwassist &= ~AXE_CSUM_FEATURES;
1504 if ((mask & IFCAP_RXCSUM) != 0 &&
1505 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1506 ifp->if_capenable ^= IFCAP_RXCSUM;
1509 if (reinit > 0 && ifp->if_flags & IFF_RUNNING)
1510 ifp->if_flags &= ~IFF_RUNNING;
1517 error = uether_ioctl(ifp, cmd, data, uc);