2 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp $
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/malloc.h>
40 #include <sys/thread2.h>
44 #include <machine/clock.h>
45 #include <machine/vmparam.h>
47 #include <bus/isa/isareg.h>
48 #include <bus/isa/isavar.h>
50 #include <bus/ppbus/ppbconf.h>
51 #include <bus/ppbus/ppb_msq.h>
57 #define LOG_PPC(function, ppc, string) \
58 if (bootverbose) kprintf("%s: %s\n", function, string)
61 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
63 devclass_t ppc_devclass;
65 static int ppc_probe(device_t dev);
66 static int ppc_attach(device_t dev);
67 static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val);
69 static void ppc_reset_epp(device_t);
70 static void ppc_ecp_sync(device_t);
71 static void ppcintr(void *arg);
73 static int ppc_exec_microseq(device_t, struct ppb_microseq **);
74 static int ppc_setmode(device_t, int);
76 static int ppc_read(device_t, char *, int, int);
77 static int ppc_write(device_t, char *, int, int);
79 static u_char ppc_io(device_t, int, u_char *, int, u_char);
81 static int ppc_setup_intr(device_t, device_t, struct resource *, int,
82 void (*)(void *), void *, void **, lwkt_serialize_t);
83 static int ppc_teardown_intr(device_t, device_t, struct resource *, void *);
85 static device_method_t ppc_methods[] = {
86 /* device interface */
87 DEVMETHOD(device_probe, ppc_probe),
88 DEVMETHOD(device_attach, ppc_attach),
91 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
92 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
93 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
94 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
97 DEVMETHOD(ppbus_io, ppc_io),
98 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
99 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
100 DEVMETHOD(ppbus_setmode, ppc_setmode),
101 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
102 DEVMETHOD(ppbus_read, ppc_read),
103 DEVMETHOD(ppbus_write, ppc_write),
108 static driver_t ppc_driver = {
111 sizeof(struct ppc_data),
114 static char *ppc_models[] = {
115 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
116 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
117 "SMC FDC37C935", "PC87303", 0
120 /* list of available modes */
121 static char *ppc_avms[] = {
122 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
123 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
124 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
125 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
128 /* list of current executing modes
129 * Note that few modes do not actually exist.
131 static char *ppc_modes[] = {
132 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
133 "EPP", "EPP", "EPP", "ECP",
134 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
135 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
138 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
142 * BIOS printer list - used by BIOS probe.
144 #define BIOS_PPC_PORTS 0x408
145 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
146 #define BIOS_MAX_PPC 4
153 ppc_ecp_sync(device_t dev)
156 struct ppc_data *ppc = DEVTOSOFTC(dev);
158 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
162 if ((r & 0xe0) != PPC_ECR_EPP)
165 for (i = 0; i < 100; i++) {
172 kprintf("ppc%d: ECP sync failed as data still " \
173 "present in FIFO.\n", ppc->ppc_unit);
181 * Detect parallel port FIFO
184 ppc_detect_fifo(struct ppc_data *ppc)
187 char ctr_sav, ctr, cc;
191 ecr_sav = r_ecr(ppc);
192 ctr_sav = r_ctr(ppc);
194 /* enter ECP configuration mode, no interrupt, no DMA */
197 /* read PWord size - transfers in FIFO mode must be PWord aligned */
198 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
200 /* XXX 16 and 32 bits implementations not supported */
201 if (ppc->ppc_pword != PPC_PWORD_8) {
202 LOG_PPC(__func__, ppc, "PWord not supported");
206 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
208 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
210 /* enter ECP test mode, no interrupt, no DMA */
214 for (i=0; i<1024; i++) {
215 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
221 LOG_PPC(__func__, ppc, "can't flush FIFO");
225 /* enable interrupts, no DMA */
228 /* determine readIntrThreshold
229 * fill the FIFO until serviceIntr is set
231 for (i=0; i<1024; i++) {
232 w_fifo(ppc, (char)i);
233 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
234 /* readThreshold reached */
237 if (r_ecr(ppc) & PPC_FIFO_FULL) {
244 LOG_PPC(__func__, ppc, "can't fill FIFO");
248 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
249 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
250 w_ecr(ppc, 0xd0); /* enable interrupts */
252 /* determine writeIntrThreshold
253 * empty the FIFO until serviceIntr is set
255 for (i=ppc->ppc_fifo; i>0; i--) {
256 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
257 LOG_PPC(__func__, ppc, "invalid data in FIFO");
260 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
261 /* writeIntrThreshold reached */
262 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
264 /* if FIFO empty before the last byte, error */
265 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
266 LOG_PPC(__func__, ppc, "data lost in FIFO");
271 /* FIFO must be empty after the last byte */
272 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
273 LOG_PPC(__func__, ppc, "can't empty the FIFO");
290 ppc_detect_port(struct ppc_data *ppc)
293 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
295 if (r_dtr(ppc) != 0xaa)
302 * EPP timeout, according to the PC87332 manual
303 * Semantics of clearing EPP timeout bit.
304 * PC87332 - reading SPP_STR does it...
305 * SMC - write 1 to EPP timeout bit XXX
306 * Others - (?) write 0 to EPP timeout bit
309 ppc_reset_epp_timeout(struct ppc_data *ppc)
315 w_str(ppc, r & 0xfe);
321 ppc_check_epp_timeout(struct ppc_data *ppc)
323 ppc_reset_epp_timeout(ppc);
325 return (!(r_str(ppc) & TIMEOUT));
329 * Configure current operating mode
332 ppc_generic_setmode(struct ppc_data *ppc, int mode)
336 /* check if mode is available */
337 if (mode && !(ppc->ppc_avm & mode))
340 /* if ECP mode, configure ecr register */
341 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
342 /* return to byte mode (keeping direction bit),
343 * no interrupt, no DMA to be able to change to
346 w_ecr(ppc, PPC_ECR_RESET);
347 ecr = PPC_DISABLE_INTR;
351 else if (mode & PPB_ECP)
352 /* select ECP mode */
354 else if (mode & PPB_PS2)
355 /* select PS2 mode with ECP */
358 /* select COMPATIBLE/NIBBLE mode */
364 ppc->ppc_mode = mode;
370 * The ppc driver is free to choose options like FIFO or DMA
371 * if ECP mode is available.
373 * The 'RAW' option allows the upper drivers to force the ppc mode
374 * even with FIFO, DMA available.
377 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
381 /* check if mode is available */
382 if (mode && !(ppc->ppc_avm & mode))
385 /* if ECP mode, configure ecr register */
386 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
387 /* return to byte mode (keeping direction bit),
388 * no interrupt, no DMA to be able to change to
391 w_ecr(ppc, PPC_ECR_RESET);
392 ecr = PPC_DISABLE_INTR;
395 /* select EPP mode */
397 else if (mode & PPB_ECP)
398 /* select ECP mode */
400 else if (mode & PPB_PS2)
401 /* select PS2 mode with ECP */
404 /* select COMPATIBLE/NIBBLE mode */
410 ppc->ppc_mode = mode;
415 #ifdef PPC_PROBE_CHIPSET
419 * Probe for a Natsemi PC873xx-family part.
421 * References in this function are to the National Semiconductor
422 * PC87332 datasheet TL/C/11930, May 1995 revision.
424 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
425 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
426 static int pc873xx_irqtab[] = {5, 7, 5, 0};
428 static int pc873xx_regstab[] = {
429 PC873_FER, PC873_FAR, PC873_PTR,
430 PC873_FCR, PC873_PCR, PC873_PMC,
431 PC873_TUP, PC873_SID, PC873_PNP0,
432 PC873_PNP1, PC873_LPTBA, -1
435 static char *pc873xx_rnametab[] = {
436 "FER", "FAR", "PTR", "FCR", "PCR",
437 "PMC", "TUP", "SID", "PNP0", "PNP1",
442 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
444 static int index = 0;
446 int ptr, pcr, val, i;
448 while ((idport = pc873xx_basetab[index++])) {
450 /* XXX should check first to see if this location is already claimed */
453 * Pull the 873xx through the power-on ID cycle (2.2,1.).
454 * We can't use this to locate the chip as it may already have
455 * been used by the BIOS.
457 (void)inb(idport); (void)inb(idport);
458 (void)inb(idport); (void)inb(idport);
461 * Read the SID byte. Possible values are :
468 outb(idport, PC873_SID);
469 val = inb(idport + 1);
470 if ((val & 0xf0) == 0x10) {
471 ppc->ppc_model = NS_PC87332;
472 } else if ((val & 0xf8) == 0x70) {
473 ppc->ppc_model = NS_PC87306;
474 } else if ((val & 0xf8) == 0x50) {
475 ppc->ppc_model = NS_PC87334;
476 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
477 documentation, but probing
479 ppc->ppc_model = NS_PC87303;
481 if (bootverbose && (val != 0xff))
482 kprintf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
483 continue ; /* not recognised */
486 /* print registers */
489 for (i=0; pc873xx_regstab[i] != -1; i++) {
490 outb(idport, pc873xx_regstab[i]);
491 kprintf(" %s=0x%x", pc873xx_rnametab[i],
492 inb(idport + 1) & 0xff);
498 * We think we have one. Is it enabled and where we want it to be?
500 outb(idport, PC873_FER);
501 val = inb(idport + 1);
502 if (!(val & PC873_PPENABLE)) {
504 kprintf("PC873xx parallel port disabled\n");
507 outb(idport, PC873_FAR);
508 val = inb(idport + 1);
509 /* XXX we should create a driver instance for every port found */
510 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
512 /* First try to change the port address to that requested... */
514 switch(ppc->ppc_base) {
532 outb(idport, PC873_FAR);
533 outb(idport + 1, val);
534 outb(idport + 1, val);
536 /* Check for success by reading back the value we supposedly
537 wrote and comparing...*/
539 outb(idport, PC873_FAR);
540 val = inb(idport + 1) & 0x3;
542 /* If we fail, report the failure... */
544 if (pc873xx_porttab[val] != ppc->ppc_base) {
546 kprintf("PC873xx at 0x%x not for driver at port 0x%x\n",
547 pc873xx_porttab[val], ppc->ppc_base);
552 outb(idport, PC873_PTR);
553 ptr = inb(idport + 1);
555 /* get irq settings */
556 if (ppc->ppc_base == 0x378)
557 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
559 irq = pc873xx_irqtab[val];
562 kprintf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
565 * Check if irq settings are correct
567 if (irq != ppc->ppc_irq) {
569 * If the chipset is not locked and base address is 0x378,
570 * we have another chance
572 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
573 if (ppc->ppc_irq == 7) {
574 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
575 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
577 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
578 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
581 kprintf("PC873xx irq set to %d\n", ppc->ppc_irq);
584 kprintf("PC873xx sorry, can't change irq setting\n");
588 kprintf("PC873xx irq settings are correct\n");
591 outb(idport, PC873_PCR);
592 pcr = inb(idport + 1);
594 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
596 kprintf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
598 ppc->ppc_avm |= PPB_NIBBLE;
602 if (pcr & PC873_EPPEN) {
603 ppc->ppc_avm |= PPB_EPP;
608 if (pcr & PC873_EPP19)
609 ppc->ppc_epp = EPP_1_9;
611 ppc->ppc_epp = EPP_1_7;
613 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
614 outb(idport, PC873_PTR);
615 ptr = inb(idport + 1);
616 if (ptr & PC873_EPPRDIR)
617 kprintf(", Regular mode");
619 kprintf(", Automatic mode");
621 } else if (pcr & PC873_ECPEN) {
622 ppc->ppc_avm |= PPB_ECP;
626 if (pcr & PC873_ECPCLK) { /* XXX */
627 ppc->ppc_avm |= PPB_PS2;
632 outb(idport, PC873_PTR);
633 ptr = inb(idport + 1);
634 if (ptr & PC873_EXTENDED) {
635 ppc->ppc_avm |= PPB_SPP;
642 kprintf("PC873xx unlocked");
644 if (chipset_mode & PPB_ECP) {
645 if ((chipset_mode & PPB_EPP) && bootverbose)
646 kprintf(", ECP+EPP not supported");
649 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
650 outb(idport + 1, pcr);
651 outb(idport + 1, pcr);
656 } else if (chipset_mode & PPB_EPP) {
657 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
658 pcr |= (PC873_EPPEN | PC873_EPP19);
659 outb(idport + 1, pcr);
660 outb(idport + 1, pcr);
662 ppc->ppc_epp = EPP_1_9; /* XXX */
667 /* enable automatic direction turnover */
668 if (ppc->ppc_model == NS_PC87332) {
669 outb(idport, PC873_PTR);
670 ptr = inb(idport + 1);
671 ptr &= ~PC873_EPPRDIR;
672 outb(idport + 1, ptr);
673 outb(idport + 1, ptr);
676 kprintf(", Automatic mode");
679 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
680 outb(idport + 1, pcr);
681 outb(idport + 1, pcr);
683 /* configure extended bit in PTR */
684 outb(idport, PC873_PTR);
685 ptr = inb(idport + 1);
687 if (chipset_mode & PPB_PS2) {
688 ptr |= PC873_EXTENDED;
694 /* default to NIBBLE mode */
695 ptr &= ~PC873_EXTENDED;
700 outb(idport + 1, ptr);
701 outb(idport + 1, ptr);
704 ppc->ppc_avm = chipset_mode;
710 ppc->ppc_type = PPC_TYPE_GENERIC;
711 ppc_generic_setmode(ppc, chipset_mode);
713 return(chipset_mode);
719 * ppc_smc37c66xgt_detect
721 * SMC FDC37C66xGT configuration.
724 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
729 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
731 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
734 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
737 * Detection: enter configuration mode and read CRD register.
741 outb(csr, SMC665_iCODE);
742 outb(csr, SMC665_iCODE);
746 if (inb(cio) == 0x65) {
751 for (i = 0; i < 2; i++) {
753 outb(csr, SMC666_iCODE);
754 outb(csr, SMC666_iCODE);
758 if (inb(cio) == 0x66) {
763 /* Another chance, CSR may be hard-configured to be at 0x370 */
769 * If chipset not found, do not continue.
777 /* read the port's address: bits 0 and 1 of CR1 */
778 r = inb(cio) & SMC_CR1_ADDR;
779 if (port_address[(int)r] != ppc->ppc_base)
782 ppc->ppc_model = type;
785 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
786 * If SPP mode is detected, try to set ECP+EPP mode
791 kprintf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
795 kprintf(" CR4=0x%x", inb(cio) & 0xff);
802 /* autodetect mode */
804 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
805 if (type == SMC_37C666GT) {
806 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
808 kprintf(" configuration hardwired, supposing " \
812 if ((inb(cio) & SMC_CR1_MODE) == 0) {
813 /* already in extended parallel port mode, read CR4 */
815 r = (inb(cio) & SMC_CR4_EMODE);
819 ppc->ppc_avm |= PPB_SPP;
825 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
831 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
837 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
839 kprintf(" ECP+EPP SPP");
843 /* not an extended port mode */
844 ppc->ppc_avm |= PPB_SPP;
851 ppc->ppc_avm = chipset_mode;
853 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
854 if (type == SMC_37C666GT)
858 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
859 /* do not use ECP when the mode is not forced to */
860 outb(cio, r | SMC_CR1_MODE);
864 /* an extended mode is selected */
865 outb(cio, r & ~SMC_CR1_MODE);
867 /* read CR4 register and reset mode field */
869 r = inb(cio) & ~SMC_CR4_EMODE;
871 if (chipset_mode & PPB_ECP) {
872 if (chipset_mode & PPB_EPP) {
873 outb(cio, r | SMC_ECPEPP);
877 outb(cio, r | SMC_ECP);
883 outb(cio, r | SMC_EPPSPP);
888 ppc->ppc_avm = chipset_mode;
891 /* set FIFO threshold to 16 */
892 if (ppc->ppc_avm & PPB_ECP) {
903 if (ppc->ppc_avm & PPB_EPP) {
909 * Set the EPP protocol...
910 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
912 if (ppc->ppc_epp == EPP_1_9)
913 outb(cio, (r & ~SMC_CR4_EPPTYPE));
915 outb(cio, (r | SMC_CR4_EPPTYPE));
918 /* end config mode */
921 ppc->ppc_type = PPC_TYPE_SMCLIKE;
922 ppc_smclike_setmode(ppc, chipset_mode);
924 return (chipset_mode);
928 * SMC FDC37C935 configuration
929 * Found on many Alpha machines
932 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
937 outb(SMC935_CFG, 0x55); /* enter config mode */
938 outb(SMC935_CFG, 0x55);
941 outb(SMC935_IND, SMC935_ID); /* check device id */
942 if (inb(SMC935_DAT) == 0x2)
946 outb(SMC935_CFG, 0xaa); /* exit config mode */
950 ppc->ppc_model = type;
952 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
953 outb(SMC935_DAT, 3); /* which is logical device 3 */
955 /* set io port base */
956 outb(SMC935_IND, SMC935_PORTHI);
957 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
958 outb(SMC935_IND, SMC935_PORTLO);
959 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
962 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
964 ppc->ppc_avm = chipset_mode;
965 outb(SMC935_IND, SMC935_PPMODE);
966 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
968 /* SPP + EPP or just plain SPP */
969 if (chipset_mode & (PPB_SPP)) {
970 if (chipset_mode & PPB_EPP) {
971 if (ppc->ppc_epp == EPP_1_9) {
972 outb(SMC935_IND, SMC935_PPMODE);
973 outb(SMC935_DAT, SMC935_EPP19SPP);
975 if (ppc->ppc_epp == EPP_1_7) {
976 outb(SMC935_IND, SMC935_PPMODE);
977 outb(SMC935_DAT, SMC935_EPP17SPP);
980 outb(SMC935_IND, SMC935_PPMODE);
981 outb(SMC935_DAT, SMC935_SPP);
985 /* ECP + EPP or just plain ECP */
986 if (chipset_mode & PPB_ECP) {
987 if (chipset_mode & PPB_EPP) {
988 if (ppc->ppc_epp == EPP_1_9) {
989 outb(SMC935_IND, SMC935_PPMODE);
990 outb(SMC935_DAT, SMC935_ECPEPP19);
992 if (ppc->ppc_epp == EPP_1_7) {
993 outb(SMC935_IND, SMC935_PPMODE);
994 outb(SMC935_DAT, SMC935_ECPEPP17);
997 outb(SMC935_IND, SMC935_PPMODE);
998 outb(SMC935_DAT, SMC935_ECP);
1003 outb(SMC935_CFG, 0xaa); /* exit config mode */
1005 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1006 ppc_smclike_setmode(ppc, chipset_mode);
1008 return (chipset_mode);
1012 * Winbond W83877F stuff
1014 * EFER: extended function enable register
1015 * EFIR: extended function index register
1016 * EFDR: extended function data register
1018 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1019 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1021 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1022 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1023 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1024 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1027 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1030 unsigned char r, hefere, hefras;
1032 for (i = 0; i < 4; i ++) {
1033 /* first try to enable configuration registers */
1034 efer = w83877f_efers[i];
1036 /* write the key to the EFER */
1037 for (j = 0; j < w83877f_keyiter[i]; j ++)
1038 outb (efer, w83877f_keys[i]);
1040 /* then check HEFERE and HEFRAS bits */
1042 hefere = inb(efdr) & WINB_HEFERE;
1045 hefras = inb(efdr) & WINB_HEFRAS;
1049 * 0 1 write 89h to 250h (power-on default)
1050 * 1 0 write 86h twice to 3f0h
1051 * 1 1 write 87h twice to 3f0h
1052 * 0 0 write 88h to 250h
1054 if ((hefere | hefras) == w83877f_hefs[i])
1058 return (-1); /* failed */
1061 /* check base port address - read from CR23 */
1063 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1066 /* read CHIP ID from CR9/bits0-3 */
1069 switch (inb(efdr) & WINB_CHIPID) {
1070 case WINB_W83877F_ID:
1071 ppc->ppc_model = WINB_W83877F;
1074 case WINB_W83877AF_ID:
1075 ppc->ppc_model = WINB_W83877AF;
1079 ppc->ppc_model = WINB_UNKNOWN;
1083 /* dump of registers */
1084 kprintf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1085 for (i = 0; i <= 0xd; i ++) {
1087 kprintf("0x%x ", inb(efdr));
1089 for (i = 0x10; i <= 0x17; i ++) {
1091 kprintf("0x%x ", inb(efdr));
1094 kprintf("0x%x ", inb(efdr));
1095 for (i = 0x20; i <= 0x29; i ++) {
1097 kprintf("0x%x ", inb(efdr));
1100 kprintf("ppc%d:", ppc->ppc_unit);
1103 ppc->ppc_type = PPC_TYPE_GENERIC;
1105 if (!chipset_mode) {
1106 /* autodetect mode */
1110 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1114 r |= (inb(efdr) & WINB_PRTMODS2);
1119 kprintf("ppc%d: W83757 compatible mode\n",
1121 return (-1); /* generic or SMC-like */
1128 kprintf(" not in parallel port mode\n");
1131 case (WINB_PARALLEL | WINB_EPP_SPP):
1132 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1134 kprintf(" EPP SPP");
1137 case (WINB_PARALLEL | WINB_ECP):
1138 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1140 kprintf(" ECP SPP");
1143 case (WINB_PARALLEL | WINB_ECP_EPP):
1144 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1145 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1148 kprintf(" ECP+EPP SPP");
1151 kprintf("%s: unknown case (0x%x)!\n", __func__, r);
1157 /* select CR9 and set PRTMODS2 bit */
1159 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1161 /* select CR0 and reset PRTMODSx bits */
1163 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1165 if (chipset_mode & PPB_ECP) {
1166 if (chipset_mode & PPB_EPP) {
1167 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1169 kprintf(" ECP+EPP");
1171 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1174 outb(efdr, inb(efdr) | WINB_ECP);
1179 /* select EPP_SPP otherwise */
1180 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1182 kprintf(" EPP SPP");
1184 ppc->ppc_avm = chipset_mode;
1190 /* exit configuration mode */
1193 switch (ppc->ppc_type) {
1194 case PPC_TYPE_SMCLIKE:
1195 ppc_smclike_setmode(ppc, chipset_mode);
1198 ppc_generic_setmode(ppc, chipset_mode);
1202 return (chipset_mode);
1207 * ppc_generic_detect
1210 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1212 /* default to generic */
1213 ppc->ppc_type = PPC_TYPE_GENERIC;
1216 kprintf("ppc%d:", ppc->ppc_unit);
1218 /* first, check for ECP */
1219 w_ecr(ppc, PPC_ECR_PS2);
1220 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1221 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1223 kprintf(" ECP SPP");
1225 /* search for SMC style ECP+EPP mode */
1226 w_ecr(ppc, PPC_ECR_EPP);
1229 /* try to reset EPP timeout bit */
1230 if (ppc_check_epp_timeout(ppc)) {
1231 ppc->ppc_dtm |= PPB_EPP;
1233 if (ppc->ppc_dtm & PPB_ECP) {
1234 /* SMC like chipset found */
1235 ppc->ppc_model = SMC_LIKE;
1236 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1239 kprintf(" ECP+EPP");
1245 /* restore to standard mode */
1246 w_ecr(ppc, PPC_ECR_STD);
1249 /* XXX try to detect NIBBLE and PS2 modes */
1250 ppc->ppc_dtm |= PPB_NIBBLE;
1256 ppc->ppc_avm = chipset_mode;
1258 ppc->ppc_avm = ppc->ppc_dtm;
1263 switch (ppc->ppc_type) {
1264 case PPC_TYPE_SMCLIKE:
1265 ppc_smclike_setmode(ppc, chipset_mode);
1268 ppc_generic_setmode(ppc, chipset_mode);
1272 return (chipset_mode);
1278 * mode is the mode suggested at boot
1281 ppc_detect(struct ppc_data *ppc, int chipset_mode)
1283 #ifdef PPC_PROBE_CHIPSET
1286 /* list of supported chipsets */
1287 int (*chipset_detect[])(struct ppc_data *, int) = {
1289 ppc_smc37c66xgt_detect,
1291 ppc_smc37c935_detect,
1297 /* if can't find the port and mode not forced return error */
1298 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1299 return (EIO); /* failed, port not present */
1301 /* assume centronics compatible mode is supported */
1302 ppc->ppc_avm = PPB_COMPATIBLE;
1304 #ifdef PPC_PROBE_CHIPSET
1305 /* we have to differenciate available chipset modes,
1306 * chipset running modes and IEEE-1284 operating modes
1308 * after detection, the port must support running in compatible mode
1310 if (ppc->ppc_flags & 0x40) {
1312 kprintf("ppc: chipset forced to generic\n");
1315 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1317 #ifdef PPC_PROBE_CHIPSET
1319 for (i=0; chipset_detect[i] != NULL; i++) {
1320 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1321 ppc->ppc_mode = mode;
1328 /* configure/detect ECP FIFO */
1329 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1330 ppc_detect_fifo(ppc);
1336 * ppc_exec_microseq()
1338 * Execute a microsequence.
1339 * Microsequence mechanism is supposed to handle fast I/O operations.
1342 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1344 struct ppc_data *ppc = DEVTOSOFTC(dev);
1345 struct ppb_microseq *mi;
1355 struct ppb_microseq *stack = NULL;
1357 /* microsequence registers are equivalent to PC-like port registers */
1359 #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register))
1360 #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte))
1362 #define INCR_PC (mi ++) /* increment program counter */
1366 switch (mi->opcode) {
1368 cc = r_reg(mi->arg[0].i, ppc);
1369 cc &= (char)mi->arg[2].i; /* clear mask */
1370 cc |= (char)mi->arg[1].i; /* assert mask */
1371 w_reg(mi->arg[0].i, ppc, cc);
1375 case MS_OP_RASSERT_P:
1379 if ((len = mi->arg[0].i) == MS_ACCUM) {
1380 accum = ppc->ppc_accum;
1381 for (; accum; accum--)
1382 w_reg(reg, ppc, *ptr++);
1383 ppc->ppc_accum = accum;
1385 for (i=0; i<len; i++)
1386 w_reg(reg, ppc, *ptr++);
1392 case MS_OP_RFETCH_P:
1394 mask = (char)mi->arg[2].i;
1397 if ((len = mi->arg[0].i) == MS_ACCUM) {
1398 accum = ppc->ppc_accum;
1399 for (; accum; accum--)
1400 *ptr++ = r_reg(reg, ppc) & mask;
1401 ppc->ppc_accum = accum;
1403 for (i=0; i<len; i++)
1404 *ptr++ = r_reg(reg, ppc) & mask;
1411 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1419 /* let's suppose the next instr. is the same */
1421 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1422 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1424 if (mi->opcode == MS_OP_DELAY) {
1425 DELAY(mi->arg[0].i);
1433 tsleep(ppc_exec_microseq, 0, "ppbdelay",
1434 mi->arg[0].i * (hz/1000));
1440 iter = mi->arg[1].i;
1441 p = (char *)mi->arg[2].p;
1443 /* XXX delay limited to 255 us */
1444 for (i=0; i<iter; i++) {
1445 w_reg(reg, ppc, *p++);
1446 DELAY((unsigned char)*p++);
1452 ppc->ppc_accum = mi->arg[0].i;
1457 if (--ppc->ppc_accum > 0)
1464 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1471 if ((cc & (char)mi->arg[0].i) == 0)
1478 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1486 * If the C call returns !0 then end the microseq.
1487 * The current state of ptr is passed to the C function
1489 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1496 ppc->ppc_ptr = (char *)mi->arg[0].p;
1502 panic("%s: too much calls", __func__);
1505 /* store the state of the actual
1510 /* jump to the new microsequence */
1511 mi = (struct ppb_microseq *)mi->arg[0].p;
1518 /* retrieve microseq and pc state before the call */
1521 /* reset the stack */
1524 /* XXX return code */
1532 /* can't return to ppb level during the execution
1533 * of a submicrosequence */
1535 panic("%s: can't return to ppb level",
1538 /* update pc for ppb level of execution */
1541 /* return to ppb level of execution */
1545 panic("%s: unknown microsequence opcode 0x%x",
1546 __func__, mi->opcode);
1556 device_t dev = (device_t)arg;
1557 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1558 u_char ctr, ecr, str;
1565 kprintf("![%x/%x/%x]", ctr, ecr, str);
1568 /* don't use ecp mode with IRQENABLE set */
1569 if (ctr & IRQENABLE) {
1573 /* interrupts are generated by nFault signal
1574 * only in ECP mode */
1575 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1576 /* check if ppc driver has programmed the
1577 * nFault interrupt */
1578 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1580 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1581 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1583 /* shall be handled by underlying layers XXX */
1588 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1589 /* disable interrupts (should be done by hardware though) */
1590 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1591 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1594 /* check if DMA completed */
1595 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1600 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1603 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1613 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1615 /* wakeup the waiting process */
1616 wakeup((caddr_t)ppc);
1619 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1621 /* classic interrupt I/O */
1622 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1629 ppc_read(device_t dev, char *buf, int len, int mode)
1635 * Call this function if you want to send data in any advanced mode
1636 * of your parallel port: FIFO, DMA
1638 * If what you want is not possible (no ECP, no DMA...),
1639 * EINVAL is returned
1642 ppc_write(device_t dev, char *buf, int len, int how)
1644 struct ppc_data *ppc = DEVTOSOFTC(dev);
1645 char ecr, ecr_sav, ctr, ctr_sav;
1653 ecr_sav = r_ecr(ppc);
1654 ctr_sav = r_ctr(ppc);
1657 * Send buffer with DMA, FIFO and interrupts
1659 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1661 if (ppc->ppc_dmachan > 0) {
1663 /* byte mode, no intr, no DMA, dir=0, flush fifo
1665 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1668 /* disable nAck interrupts */
1673 ppc->ppc_dmaflags = ISADMA_WRITE;
1674 ppc->ppc_dmaddr = (caddr_t)buf;
1675 ppc->ppc_dmacnt = (u_int)len;
1677 switch (ppc->ppc_mode) {
1678 case PPB_COMPATIBLE:
1679 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1680 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1683 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1693 /* enter splhigh() not to be preempted
1694 * by the dma interrupt, we may miss
1695 * the wakeup otherwise
1699 ppc->ppc_dmastat = PPC_DMA_INIT;
1701 /* enable interrupts */
1702 ecr &= ~PPC_SERVICE_INTR;
1703 ppc->ppc_irqstat = PPC_IRQ_DMA;
1712 kprintf("s%d", ppc->ppc_dmacnt);
1714 ppc->ppc_dmastat = PPC_DMA_STARTED;
1716 /* Wait for the DMA completed interrupt. We hope we won't
1717 * miss it, otherwise a signal will be necessary to unlock the
1722 error = tsleep((caddr_t)ppc, PCATCH, "ppcdma", 0);
1724 } while (error == EWOULDBLOCK);
1735 ppc->ppc_dmaddr, ppc->ppc_dmacnt,
1738 /* no dma, no interrupt, flush the fifo */
1739 w_ecr(ppc, PPC_ECR_RESET);
1741 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1745 /* wait for an empty fifo */
1746 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1748 for (spin=100; spin; spin--)
1749 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1754 error = tsleep((caddr_t)ppc, PCATCH, "ppcfifo", hz/100);
1755 if (error != EWOULDBLOCK) {
1759 /* no dma, no interrupt, flush the fifo */
1760 w_ecr(ppc, PPC_ECR_RESET);
1762 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1769 /* no dma, no interrupt, flush the fifo */
1770 w_ecr(ppc, PPC_ECR_RESET);
1773 error = EINVAL; /* XXX we should FIFO and
1780 /* PDRQ must be kept unasserted until nPDACK is
1781 * deasserted for a minimum of 350ns (SMC datasheet)
1783 * Consequence may be a FIFO that never empty
1787 w_ecr(ppc, ecr_sav);
1788 w_ctr(ppc, ctr_sav);
1794 ppc_reset_epp(device_t dev)
1796 struct ppc_data *ppc = DEVTOSOFTC(dev);
1798 ppc_reset_epp_timeout(ppc);
1804 ppc_setmode(device_t dev, int mode)
1806 struct ppc_data *ppc = DEVTOSOFTC(dev);
1808 switch (ppc->ppc_type) {
1809 case PPC_TYPE_SMCLIKE:
1810 return (ppc_smclike_setmode(ppc, mode));
1813 case PPC_TYPE_GENERIC:
1815 return (ppc_generic_setmode(ppc, mode));
1823 static struct isa_pnp_id lpc_ids[] = {
1824 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */
1825 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */
1830 ppc_probe(device_t dev)
1833 static short next_bios_ppc = 0;
1835 struct ppc_data *ppc;
1840 parent = device_get_parent(dev);
1842 error = ISA_PNP_PROBE(parent, dev, lpc_ids);
1845 else if (error != 0) /* XXX shall be set after detection */
1846 device_set_desc(dev, "Parallel port");
1849 * Allocate the ppc_data structure.
1851 ppc = DEVTOSOFTC(dev);
1852 bzero(ppc, sizeof(struct ppc_data));
1854 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1855 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1857 /* retrieve ISA parameters */
1858 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL);
1862 * If port not specified, use bios list.
1865 if((next_bios_ppc < BIOS_MAX_PPC) &&
1866 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1867 port = *(BIOS_PORTS+next_bios_ppc++);
1869 device_printf(dev, "parallel port found at 0x%x\n",
1872 device_printf(dev, "parallel port not found.\n");
1875 bus_set_resource(dev, SYS_RES_IOPORT, 0, port,
1876 IO_LPTSIZE_EXTENDED, -1);
1880 /* IO port is mandatory */
1882 /* Try "extended" IO port range...*/
1883 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1884 &ppc->rid_ioport, 0, ~0,
1885 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1887 if (ppc->res_ioport != 0) {
1889 device_printf(dev, "using extended I/O port range\n");
1891 /* Failed? If so, then try the "normal" IO port range... */
1892 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1893 &ppc->rid_ioport, 0, ~0,
1896 if (ppc->res_ioport != 0) {
1898 device_printf(dev, "using normal I/O port range\n");
1900 device_printf(dev, "cannot reserve I/O port range\n");
1905 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1907 ppc->bsh = rman_get_bushandle(ppc->res_ioport);
1908 ppc->bst = rman_get_bustag(ppc->res_ioport);
1910 ppc->ppc_flags = device_get_flags(dev);
1912 if (!(ppc->ppc_flags & 0x20)) {
1913 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq,
1914 0ul, ~0ul, 1, RF_SHAREABLE);
1915 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq,
1916 0ul, ~0ul, 1, RF_ACTIVE);
1920 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1922 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1924 ppc->ppc_unit = device_get_unit(dev);
1925 ppc->ppc_model = GENERIC;
1927 ppc->ppc_mode = PPB_COMPATIBLE;
1928 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1930 ppc->ppc_type = PPC_TYPE_GENERIC;
1933 * Try to detect the chipset and its mode.
1935 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1941 if (ppc->res_irq != 0) {
1942 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1945 if (ppc->res_ioport != 0) {
1946 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1948 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1951 if (ppc->res_drq != 0) {
1952 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1954 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1961 ppc_attach(device_t dev)
1963 struct ppc_data *ppc = DEVTOSOFTC(dev);
1966 device_t parent = device_get_parent(dev);
1968 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1969 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1970 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1971 ppc_epp_protocol[ppc->ppc_epp] : "");
1974 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1975 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1977 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1978 /* acquire the DMA channel forever */ /* XXX */
1979 isa_dma_acquire(ppc->ppc_dmachan);
1980 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1983 /* add ppbus as a child of this isa to parallel bridge */
1984 ppbus = device_add_child(dev, "ppbus", -1);
1987 * Probe the ppbus and attach devices found.
1989 device_probe_and_attach(ppbus);
1991 /* register the ppc interrupt handler as default */
1993 /* default to the tty mask for registration */ /* XXX */
1994 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, 0,
1996 &ppc->intr_cookie, NULL, NULL) == 0) {
1997 /* remember the ppcintr is registered */
1998 ppc->ppc_registered = 1;
2006 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
2008 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
2011 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2014 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2017 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2020 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2023 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2026 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2029 return (r_dtr(ppc));
2032 return (r_str(ppc));
2035 return (r_ctr(ppc));
2038 return (r_epp_A(ppc));
2041 return (r_epp_D(ppc));
2044 return (r_ecr(ppc));
2047 return (r_fifo(ppc));
2071 panic("%s: unknown I/O operation", __func__);
2075 return (0); /* not significative */
2079 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
2081 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
2084 case PPC_IVAR_EPP_PROTO:
2085 *val = (u_long)ppc->ppc_epp;
2088 *val = (u_long)ppc->ppc_irq;
2098 * Resource is useless here since ppbus devices' interrupt handlers are
2099 * multiplexed to the same resource initially allocated by ppc
2102 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2103 void (*ihand)(void *), void *arg,
2104 void **cookiep, lwkt_serialize_t serializer)
2107 struct ppc_data *ppc = DEVTOSOFTC(bus);
2109 if (ppc->ppc_registered) {
2110 /* XXX refuse registration if DMA is in progress */
2112 /* first, unregister the default interrupt handler */
2113 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2114 bus, ppc->res_irq, ppc->intr_cookie)))
2117 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2118 /* ppc->res_irq); */
2120 /* DMA/FIFO operation won't be possible anymore */
2121 ppc->ppc_registered = 0;
2124 /* pass registration to the upper layer, ignore the incoming resource */
2125 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2126 r, flags, ihand, arg, cookiep,
2131 * When no underlying device has a registered interrupt, register the ppc
2135 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2138 struct ppc_data *ppc = DEVTOSOFTC(bus);
2139 device_t parent = device_get_parent(bus);
2141 /* pass unregistration to the upper layer */
2142 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2145 /* default to the tty mask for registration */ /* XXX */
2147 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2149 &ppc->intr_cookie, NULL, NULL))
2151 /* remember the ppcintr is registered */
2152 ppc->ppc_registered = 1;
2158 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, NULL, NULL);
2159 DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, NULL, NULL);