sys/dev/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27 #include <drm/drmP.h>
  28 #include <uapi_drm/radeon_drm.h>
  29 #include "radeon.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include <drm/drm_dp_helper.h>
  34
  35 /* move these to drm_dp_helper.c/h */
  36 #define DP_LINK_CONFIGURATION_SIZE 9
  37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  38
  39 static char *voltage_names[] = {
  40         "0.4V", "0.6V", "0.8V", "1.2V"
  41 };
  42 static char *pre_emph_names[] = {
  43         "0dB", "3.5dB", "6dB", "9.5dB"
  44 };
  45
  46 /***** radeon AUX functions *****/
  47
  48 /* Atom needs data in little endian format
  49  * so swap as appropriate when copying data to
  50  * or from atom. Note that atom operates on
  51  * dw units.
  52  */
  53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
  54 {
  55 #ifdef __BIG_ENDIAN
  56         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
  57         u32 *dst32, *src32;
  58         int i;
  59
  60         memcpy(src_tmp, src, num_bytes);
  61         src32 = (u32 *)src_tmp;
  62         dst32 = (u32 *)dst_tmp;
  63         if (to_le) {
  64                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  65                         dst32[i] = cpu_to_le32(src32[i]);
  66                 memcpy(dst, dst_tmp, num_bytes);
  67         } else {
  68                 u8 dws = num_bytes & ~3;
  69                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  70                         dst32[i] = le32_to_cpu(src32[i]);
  71                 memcpy(dst, dst_tmp, dws);
  72                 if (num_bytes % 4) {
  73                         for (i = 0; i < (num_bytes % 4); i++)
  74                                 dst[dws+i] = dst_tmp[dws+i];
  75                 }
  76         }
  77 #else
  78         memcpy(dst, src, num_bytes);
  79 #endif
  80 }
  81
  82 union aux_channel_transaction {
  83         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  84         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  85 };
  86
  87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  88                                  u8 *send, int send_bytes,
  89                                  u8 *recv, int recv_size,
  90                                  u8 delay, u8 *ack)
  91 {
  92         struct drm_device *dev = chan->dev;
  93         struct radeon_device *rdev = dev->dev_private;
  94         union aux_channel_transaction args;
  95         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  96         unsigned char *base;
  97         int recv_bytes;
  98         int r = 0;
  99
 100         memset(&args, 0, sizeof(args));
 101
 102         lockmgr(&chan->mutex, LK_EXCLUSIVE);
 103         lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_EXCLUSIVE);
 104
 105         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
 106
 107         radeon_atom_copy_swap(base, send, send_bytes, true);
 108
 109         args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
 110         args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
 111         args.v1.ucDataOutLen = 0;
 112         args.v1.ucChannelID = chan->rec.i2c_id;
 113         args.v1.ucDelay = delay / 10;
 114         if (ASIC_IS_DCE4(rdev))
 115                 args.v2.ucHPD_ID = chan->rec.hpd;
 116
 117         atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 118
 119         *ack = args.v1.ucReplyStatus;
 120
 121         /* timeout */
 122         if (args.v1.ucReplyStatus == 1) {
 123                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 124                 r = -ETIMEDOUT;
 125                 goto done;
 126         }
 127
 128         /* flags not zero */
 129         if (args.v1.ucReplyStatus == 2) {
 130                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 131                 r = -EIO;
 132                 goto done;
 133         }
 134
 135         /* error */
 136         if (args.v1.ucReplyStatus == 3) {
 137                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 138                 r = -EIO;
 139                 goto done;
 140         }
 141
 142         recv_bytes = args.v1.ucDataOutLen;
 143         if (recv_bytes > recv_size)
 144                 recv_bytes = recv_size;
 145
 146         if (recv && recv_size)
 147                 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
 148
 149         r = recv_bytes;
 150 done:
 151         lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_RELEASE);
 152         lockmgr(&chan->mutex, LK_RELEASE);
 153
 154         return r;
 155 }
 156
 157 #define BARE_ADDRESS_SIZE 3
 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 159
 160 static ssize_t
 161 radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 162 {
 163         struct radeon_i2c_chan *chan =
 164                 container_of(aux, struct radeon_i2c_chan, aux);
 165         int ret;
 166         u8 tx_buf[20];
 167         size_t tx_size;
 168         u8 ack, delay = 0;
 169
 170         if (WARN_ON(msg->size > 16))
 171                 return -E2BIG;
 172
 173         tx_buf[0] = msg->address & 0xff;
 174         tx_buf[1] = msg->address >> 8;
 175         tx_buf[2] = msg->request << 4;
 176         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
 177
 178         switch (msg->request & ~DP_AUX_I2C_MOT) {
 179         case DP_AUX_NATIVE_WRITE:
 180         case DP_AUX_I2C_WRITE:
 181                 /* tx_size needs to be 4 even for bare address packets since the atom
 182                  * table needs the info in tx_buf[3].
 183                  */
 184                 tx_size = HEADER_SIZE + msg->size;
 185                 if (msg->size == 0)
 186                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 187                 else
 188                         tx_buf[3] |= tx_size << 4;
 189                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
 190                 ret = radeon_process_aux_ch(chan,
 191                                             tx_buf, tx_size, NULL, 0, delay, &ack);
 192                 if (ret >= 0)
 193                         /* Return payload size. */
 194                         ret = msg->size;
 195                 break;
 196         case DP_AUX_NATIVE_READ:
 197         case DP_AUX_I2C_READ:
 198                 /* tx_size needs to be 4 even for bare address packets since the atom
 199                  * table needs the info in tx_buf[3].
 200                  */
 201                 tx_size = HEADER_SIZE;
 202                 if (msg->size == 0)
 203                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 204                 else
 205                         tx_buf[3] |= tx_size << 4;
 206                 ret = radeon_process_aux_ch(chan,
 207                                             tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 208                 break;
 209         default:
 210                 ret = -EINVAL;
 211                 break;
 212         }
 213
 214         if (ret >= 0)
 215                 msg->reply = ack >> 4;
 216
 217         return ret;
 218 }
 219
 220 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
 221 {
 222         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 223
 224         dig_connector->dp_i2c_bus->aux.dev = radeon_connector->base.kdev;
 225         dig_connector->dp_i2c_bus->aux.transfer = radeon_dp_aux_transfer;
 226 }
 227
 228 int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte)
 229 {
 230         struct i2c_algo_dp_aux_data *algo_data = device_get_softc(dev);
 231         struct radeon_i2c_chan *auxch = algo_data->priv;
 232         u16 address = algo_data->address;
 233         u8 msg[5];
 234         u8 reply[2];
 235         unsigned retry;
 236         int msg_bytes;
 237         int reply_bytes = 1;
 238         int ret;
 239         u8 ack;
 240
 241         /* Set up the address */
 242         msg[0] = address;
 243         msg[1] = address >> 8;
 244
 245         /* Set up the command byte */
 246         if (mode & MODE_I2C_READ) {
 247                 msg[2] = DP_AUX_I2C_READ << 4;
 248                 msg_bytes = 4;
 249                 msg[3] = msg_bytes << 4;
 250         } else {
 251                 msg[2] = DP_AUX_I2C_WRITE << 4;
 252                 msg_bytes = 5;
 253                 msg[3] = msg_bytes << 4;
 254                 msg[4] = write_byte;
 255         }
 256
 257         /* special handling for start/stop */
 258         if (mode & (MODE_I2C_START | MODE_I2C_STOP))
 259                 msg[3] = 3 << 4;
 260
 261         /* Set MOT bit for all but stop */
 262         if ((mode & MODE_I2C_STOP) == 0)
 263                 msg[2] |= DP_AUX_I2C_MOT << 4;
 264
 265         for (retry = 0; retry < 7; retry++) {
 266                 ret = radeon_process_aux_ch(auxch,
 267                                             msg, msg_bytes, reply, reply_bytes, 0, &ack);
 268                 if (ret == -EBUSY)
 269                         continue;
 270                 else if (ret < 0) {
 271                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 272                         return ret;
 273                 }
 274
 275                 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
 276                 case DP_AUX_NATIVE_REPLY_ACK:
 277                         /* I2C-over-AUX Reply field is only valid
 278                          * when paired with AUX ACK.
 279                          */
 280                         break;
 281                 case DP_AUX_NATIVE_REPLY_NACK:
 282                         DRM_DEBUG_KMS("aux_ch native nack\n");
 283                         return -EREMOTEIO;
 284                 case DP_AUX_NATIVE_REPLY_DEFER:
 285                         DRM_DEBUG_KMS("aux_ch native defer\n");
 286                         usleep_range(500, 600);
 287                         continue;
 288                 default:
 289                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
 290                         return -EREMOTEIO;
 291                 }
 292
 293                 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
 294                 case DP_AUX_I2C_REPLY_ACK:
 295                         if (mode == MODE_I2C_READ)
 296                                 *read_byte = reply[0];
 297                         return ret;
 298                 case DP_AUX_I2C_REPLY_NACK:
 299                         DRM_DEBUG_KMS("aux_i2c nack\n");
 300                         return -EREMOTEIO;
 301                 case DP_AUX_I2C_REPLY_DEFER:
 302                         DRM_DEBUG_KMS("aux_i2c defer\n");
 303                         usleep_range(400, 500);
 304                         break;
 305                 default:
 306                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
 307                         return -EREMOTEIO;
 308                 }
 309         }
 310
 311         DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
 312         return -EREMOTEIO;
 313 }
 314
 315 /***** general DP utility functions *****/
 316
 317 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 318 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
 319
 320 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 321                                 int lane_count,
 322                                 u8 train_set[4])
 323 {
 324         u8 v = 0;
 325         u8 p = 0;
 326         int lane;
 327
 328         for (lane = 0; lane < lane_count; lane++) {
 329                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 330                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 331
 332                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 333                           lane,
 334                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 335                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 336
 337                 if (this_v > v)
 338                         v = this_v;
 339                 if (this_p > p)
 340                         p = this_p;
 341         }
 342
 343         if (v >= DP_VOLTAGE_MAX)
 344                 v |= DP_TRAIN_MAX_SWING_REACHED;
 345
 346         if (p >= DP_PRE_EMPHASIS_MAX)
 347                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 348
 349         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 350                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 351                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 352
 353         for (lane = 0; lane < 4; lane++)
 354                 train_set[lane] = v | p;
 355 }
 356
 357 /* convert bits per color to bits per pixel */
 358 /* get bpc from the EDID */
 359 static int convert_bpc_to_bpp(int bpc)
 360 {
 361         if (bpc == 0)
 362                 return 24;
 363         else
 364                 return bpc * 3;
 365 }
 366
 367 /* get the max pix clock supported by the link rate and lane num */
 368 static int dp_get_max_dp_pix_clock(int link_rate,
 369                                    int lane_num,
 370                                    int bpp)
 371 {
 372         return (link_rate * lane_num * 8) / bpp;
 373 }
 374
 375 /***** radeon specific DP functions *****/
 376
 377 static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
 378                                        u8 dpcd[DP_DPCD_SIZE])
 379 {
 380         int max_link_rate;
 381
 382         if (radeon_connector_is_dp12_capable(connector))
 383                 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
 384         else
 385                 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
 386
 387         return max_link_rate;
 388 }
 389
 390 /* First get the min lane# when low rate is used according to pixel clock
 391  * (prefer low rate), second check max lane# supported by DP panel,
 392  * if the max lane# < low rate lane# then use max lane# instead.
 393  */
 394 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 395                                         u8 dpcd[DP_DPCD_SIZE],
 396                                         int pix_clock)
 397 {
 398         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 399         int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
 400         int max_lane_num = drm_dp_max_lane_count(dpcd);
 401         int lane_num;
 402         int max_dp_pix_clock;
 403
 404         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 405                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 406                 if (pix_clock <= max_dp_pix_clock)
 407                         break;
 408         }
 409
 410         return lane_num;
 411 }
 412
 413 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 414                                        u8 dpcd[DP_DPCD_SIZE],
 415                                        int pix_clock)
 416 {
 417         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 418         int lane_num, max_pix_clock;
 419
 420         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 421             ENCODER_OBJECT_ID_NUTMEG)
 422                 return 270000;
 423
 424         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 425         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 426         if (pix_clock <= max_pix_clock)
 427                 return 162000;
 428         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 429         if (pix_clock <= max_pix_clock)
 430                 return 270000;
 431         if (radeon_connector_is_dp12_capable(connector)) {
 432                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 433                 if (pix_clock <= max_pix_clock)
 434                         return 540000;
 435         }
 436
 437         return radeon_dp_get_max_link_rate(connector, dpcd);
 438 }
 439
 440 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 441                                     int action, int dp_clock,
 442                                     u8 ucconfig, u8 lane_num)
 443 {
 444         DP_ENCODER_SERVICE_PARAMETERS args;
 445         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 446
 447         memset(&args, 0, sizeof(args));
 448         args.ucLinkClock = dp_clock / 10;
 449         args.ucConfig = ucconfig;
 450         args.ucAction = action;
 451         args.ucLaneNum = lane_num;
 452         args.ucStatus = 0;
 453
 454         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 455         return args.ucStatus;
 456 }
 457
 458 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 459 {
 460         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 461         struct drm_device *dev = radeon_connector->base.dev;
 462         struct radeon_device *rdev = dev->dev_private;
 463
 464         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 465                                          dig_connector->dp_i2c_bus->rec.i2c_id, 0);
 466 }
 467
 468 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 469 {
 470         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 471         u8 buf[3];
 472
 473         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 474                 return;
 475
 476         if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_SINK_OUI, buf, 3) == 3)
 477                 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n",
 478                               buf[0], buf[1], buf[2]);
 479
 480         if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
 481                 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n",
 482                               buf[0], buf[1], buf[2]);
 483 }
 484
 485 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 486 {
 487         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 488         u8 msg[DP_DPCD_SIZE];
 489         int ret;
 490
 491         char dpcd_hex_dump[DP_DPCD_SIZE * 3];
 492
 493         ret = drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_DPCD_REV, msg,
 494                                DP_DPCD_SIZE);
 495         if (ret > 0) {
 496                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 497                 DRM_DEBUG_KMS("DPCD: %s\n", hexncpy(dig_connector->dpcd,
 498                               sizeof(dig_connector->dpcd),
 499                               dpcd_hex_dump, sizeof(dpcd_hex_dump), " "));
 500
 501                 radeon_dp_probe_oui(radeon_connector);
 502
 503                 return true;
 504         }
 505         dig_connector->dpcd[0] = 0;
 506         return false;
 507 }
 508
 509 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 510                              struct drm_connector *connector)
 511 {
 512         struct drm_device *dev = encoder->dev;
 513         struct radeon_device *rdev = dev->dev_private;
 514         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 515         struct radeon_connector_atom_dig *dig_connector;
 516         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 517         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 518         u8 tmp;
 519
 520         if (!ASIC_IS_DCE4(rdev))
 521                 return panel_mode;
 522
 523         if (!radeon_connector->con_priv)
 524                 return panel_mode;
 525
 526         dig_connector = radeon_connector->con_priv;
 527
 528         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 529                 /* DP bridge chips */
 530                 if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
 531                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 532                         if (tmp & 1)
 533                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 534                         else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 535                                  (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 536                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 537                         else
 538                                 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 539                 }
 540         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 541                 /* eDP */
 542                 if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
 543                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 544                         if (tmp & 1)
 545                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 546                 }
 547         }
 548
 549         return panel_mode;
 550 }
 551
 552 void radeon_dp_set_link_config(struct drm_connector *connector,
 553                                const struct drm_display_mode *mode)
 554 {
 555         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 556         struct radeon_connector_atom_dig *dig_connector;
 557
 558         if (!radeon_connector->con_priv)
 559                 return;
 560         dig_connector = radeon_connector->con_priv;
 561
 562         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 563             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 564                 dig_connector->dp_clock =
 565                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 566                 dig_connector->dp_lane_count =
 567                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 568         }
 569 }
 570
 571 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 572                                 struct drm_display_mode *mode)
 573 {
 574         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 575         struct radeon_connector_atom_dig *dig_connector;
 576         int dp_clock;
 577
 578         if ((mode->clock > 340000) &&
 579             (!radeon_connector_is_dp12_capable(connector)))
 580                 return MODE_CLOCK_HIGH;
 581
 582         if (!radeon_connector->con_priv)
 583                 return MODE_CLOCK_HIGH;
 584         dig_connector = radeon_connector->con_priv;
 585
 586         dp_clock =
 587                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 588
 589         if ((dp_clock == 540000) &&
 590             (!radeon_connector_is_dp12_capable(connector)))
 591                 return MODE_CLOCK_HIGH;
 592
 593         return MODE_OK;
 594 }
 595
 596 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 597 {
 598         u8 link_status[DP_LINK_STATUS_SIZE];
 599         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 600
 601         if (drm_dp_dpcd_read_link_status(&dig->dp_i2c_bus->aux, link_status) <= 0)
 602                 return false;
 603         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 604                 return false;
 605         return true;
 606 }
 607
 608 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
 609                                   u8 power_state)
 610 {
 611         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 612         struct radeon_connector_atom_dig *dig_connector;
 613
 614         if (!radeon_connector->con_priv)
 615                 return;
 616
 617         dig_connector = radeon_connector->con_priv;
 618
 619         /* power up/down the sink */
 620         if (dig_connector->dpcd[0] >= 0x11) {
 621                 drm_dp_dpcd_writeb(&dig_connector->dp_i2c_bus->aux,
 622                                    DP_SET_POWER, power_state);
 623                 usleep_range(1000, 2000);
 624         }
 625 }
 626
 627
 628 struct radeon_dp_link_train_info {
 629         struct radeon_device *rdev;
 630         struct drm_encoder *encoder;
 631         struct drm_connector *connector;
 632         int enc_id;
 633         int dp_clock;
 634         int dp_lane_count;
 635         bool tp3_supported;
 636         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 637         u8 train_set[4];
 638         u8 link_status[DP_LINK_STATUS_SIZE];
 639         u8 tries;
 640         bool use_dpencoder;
 641         struct drm_dp_aux *aux;
 642 };
 643
 644 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 645 {
 646         /* set the initial vs/emph on the source */
 647         atombios_dig_transmitter_setup(dp_info->encoder,
 648                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 649                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 650
 651         /* set the vs/emph on the sink */
 652         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
 653                           dp_info->train_set, dp_info->dp_lane_count);
 654 }
 655
 656 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 657 {
 658         int rtp = 0;
 659
 660         /* set training pattern on the source */
 661         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 662                 switch (tp) {
 663                 case DP_TRAINING_PATTERN_1:
 664                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 665                         break;
 666                 case DP_TRAINING_PATTERN_2:
 667                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 668                         break;
 669                 case DP_TRAINING_PATTERN_3:
 670                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 671                         break;
 672                 }
 673                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 674         } else {
 675                 switch (tp) {
 676                 case DP_TRAINING_PATTERN_1:
 677                         rtp = 0;
 678                         break;
 679                 case DP_TRAINING_PATTERN_2:
 680                         rtp = 1;
 681                         break;
 682                 }
 683                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 684                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 685         }
 686
 687         /* enable training pattern on the sink */
 688         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
 689 }
 690
 691 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 692 {
 693         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 694         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 695         u8 tmp;
 696
 697         /* power up the sink */
 698         radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 699
 700         /* possibly enable downspread on the sink */
 701         if (dp_info->dpcd[3] & 0x1)
 702                 drm_dp_dpcd_writeb(dp_info->aux,
 703                                    DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 704         else
 705                 drm_dp_dpcd_writeb(dp_info->aux,
 706                                    DP_DOWNSPREAD_CTRL, 0);
 707
 708         if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
 709             (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
 710                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 711         }
 712
 713         /* set the lane count on the sink */
 714         tmp = dp_info->dp_lane_count;
 715         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
 716                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 717         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
 718
 719         /* set the link rate on the sink */
 720         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 721         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
 722
 723         /* start training on the source */
 724         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 725                 atombios_dig_encoder_setup(dp_info->encoder,
 726                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 727         else
 728                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 729                                           dp_info->dp_clock, dp_info->enc_id, 0);
 730
 731         /* disable the training pattern on the sink */
 732         drm_dp_dpcd_writeb(dp_info->aux,
 733                            DP_TRAINING_PATTERN_SET,
 734                            DP_TRAINING_PATTERN_DISABLE);
 735
 736         return 0;
 737 }
 738
 739 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 740 {
 741         udelay(400);
 742
 743         /* disable the training pattern on the sink */
 744         drm_dp_dpcd_writeb(dp_info->aux,
 745                            DP_TRAINING_PATTERN_SET,
 746                            DP_TRAINING_PATTERN_DISABLE);
 747
 748         /* disable the training pattern on the source */
 749         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 750                 atombios_dig_encoder_setup(dp_info->encoder,
 751                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 752         else
 753                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 754                                           dp_info->dp_clock, dp_info->enc_id, 0);
 755
 756         return 0;
 757 }
 758
 759 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 760 {
 761         bool clock_recovery;
 762         u8 voltage;
 763         int i;
 764
 765         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 766         memset(dp_info->train_set, 0, 4);
 767         radeon_dp_update_vs_emph(dp_info);
 768
 769         udelay(400);
 770
 771         /* clock recovery loop */
 772         clock_recovery = false;
 773         dp_info->tries = 0;
 774         voltage = 0xff;
 775         while (1) {
 776                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 777
 778                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 779                                                  dp_info->link_status) <= 0) {
 780                         DRM_ERROR("displayport link status failed\n");
 781                         break;
 782                 }
 783
 784                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 785                         clock_recovery = true;
 786                         break;
 787                 }
 788
 789                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 790                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 791                                 break;
 792                 }
 793                 if (i == dp_info->dp_lane_count) {
 794                         DRM_ERROR("clock recovery reached max voltage\n");
 795                         break;
 796                 }
 797
 798                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 799                         ++dp_info->tries;
 800                         if (dp_info->tries == 5) {
 801                                 DRM_ERROR("clock recovery tried 5 times\n");
 802                                 break;
 803                         }
 804                 } else
 805                         dp_info->tries = 0;
 806
 807                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 808
 809                 /* Compute new train_set as requested by sink */
 810                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 811
 812                 radeon_dp_update_vs_emph(dp_info);
 813         }
 814         if (!clock_recovery) {
 815                 DRM_ERROR("clock recovery failed\n");
 816                 return -1;
 817         } else {
 818                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 819                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 820                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 821                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 822                 return 0;
 823         }
 824 }
 825
 826 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 827 {
 828         bool channel_eq;
 829
 830         if (dp_info->tp3_supported)
 831                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 832         else
 833                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 834
 835         /* channel equalization loop */
 836         dp_info->tries = 0;
 837         channel_eq = false;
 838         while (1) {
 839                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 840
 841                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 842                                                  dp_info->link_status) <= 0) {
 843                         DRM_ERROR("displayport link status failed\n");
 844                         break;
 845                 }
 846
 847                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 848                         channel_eq = true;
 849                         break;
 850                 }
 851
 852                 /* Try 5 times */
 853                 if (dp_info->tries > 5) {
 854                         DRM_ERROR("channel eq failed: 5 tries\n");
 855                         break;
 856                 }
 857
 858                 /* Compute new train_set as requested by sink */
 859                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 860
 861                 radeon_dp_update_vs_emph(dp_info);
 862                 dp_info->tries++;
 863         }
 864
 865         if (!channel_eq) {
 866                 DRM_ERROR("channel eq failed\n");
 867                 return -1;
 868         } else {
 869                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 870                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 871                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 872                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 873                 return 0;
 874         }
 875 }
 876
 877 void radeon_dp_link_train(struct drm_encoder *encoder,
 878                           struct drm_connector *connector)
 879 {
 880         struct drm_device *dev = encoder->dev;
 881         struct radeon_device *rdev = dev->dev_private;
 882         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 883         struct radeon_encoder_atom_dig *dig;
 884         struct radeon_connector *radeon_connector;
 885         struct radeon_connector_atom_dig *dig_connector;
 886         struct radeon_dp_link_train_info dp_info;
 887         int index;
 888         u8 tmp, frev, crev;
 889
 890         if (!radeon_encoder->enc_priv)
 891                 return;
 892         dig = radeon_encoder->enc_priv;
 893
 894         radeon_connector = to_radeon_connector(connector);
 895         if (!radeon_connector->con_priv)
 896                 return;
 897         dig_connector = radeon_connector->con_priv;
 898
 899         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 900             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 901                 return;
 902
 903         /* DPEncoderService newer than 1.1 can't program properly the
 904          * training pattern. When facing such version use the
 905          * DIGXEncoderControl (X== 1 | 2)
 906          */
 907         dp_info.use_dpencoder = true;
 908         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 909         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 910                 if (crev > 1) {
 911                         dp_info.use_dpencoder = false;
 912                 }
 913         }
 914
 915         dp_info.enc_id = 0;
 916         if (dig->dig_encoder)
 917                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 918         else
 919                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 920         if (dig->linkb)
 921                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 922         else
 923                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 924
 925         if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, DP_MAX_LANE_COUNT, &tmp)
 926             == 1) {
 927                 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 928                         dp_info.tp3_supported = true;
 929                 else
 930                         dp_info.tp3_supported = false;
 931         } else {
 932                 dp_info.tp3_supported = false;
 933         }
 934
 935         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 936         dp_info.rdev = rdev;
 937         dp_info.encoder = encoder;
 938         dp_info.connector = connector;
 939         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 940         dp_info.dp_clock = dig_connector->dp_clock;
 941         dp_info.aux = &dig_connector->dp_i2c_bus->aux;
 942
 943         if (radeon_dp_link_train_init(&dp_info))
 944                 goto done;
 945         if (radeon_dp_link_train_cr(&dp_info))
 946                 goto done;
 947         if (radeon_dp_link_train_ce(&dp_info))
 948                 goto done;
 949 done:
 950         if (radeon_dp_link_train_finish(&dp_info))
 951                 return;
 952 }