2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $
30 * Device driver for Intel's On Die thermal sensor via MSR.
31 * First introduced in Intel's Core line of processors.
34 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/types.h>
38 #include <sys/module.h>
40 #include <sys/kernel.h>
41 #include <sys/sensors.h>
42 #include <sys/proc.h> /* for curthread */
43 #include <sys/sched.h>
44 #include <sys/thread2.h>
46 #include <machine/specialreg.h>
47 #include <machine/cpufunc.h>
48 #include <machine/cputypes.h>
49 #include <machine/md_var.h>
51 struct coretemp_softc {
52 struct ksensordev sc_sensordev;
53 struct ksensor sc_sensor;
57 struct globaldata *sc_gd;
59 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */
60 volatile uint64_t sc_msr;
63 #define CORETEMP_FLAG_INITED 0x1
64 #define CORETEMP_FLAG_PENDING 0x2
65 #define CORETEMP_FLAG_CRIT 0x4
70 static void coretemp_identify(driver_t *driver, device_t parent);
71 static int coretemp_probe(device_t dev);
72 static int coretemp_attach(device_t dev);
73 static int coretemp_detach(device_t dev);
75 static int coretemp_get_temp(device_t dev);
76 static void coretemp_refresh(void *arg);
78 static device_method_t coretemp_methods[] = {
79 /* Device interface */
80 DEVMETHOD(device_identify, coretemp_identify),
81 DEVMETHOD(device_probe, coretemp_probe),
82 DEVMETHOD(device_attach, coretemp_attach),
83 DEVMETHOD(device_detach, coretemp_detach),
88 static driver_t coretemp_driver = {
91 sizeof(struct coretemp_softc),
94 static devclass_t coretemp_devclass;
95 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL);
96 MODULE_VERSION(coretemp, 1);
99 coretemp_identify(driver_t *driver, device_t parent)
104 /* Make sure we're not being doubly invoked. */
105 if (device_find_child(parent, "coretemp", -1) != NULL)
108 /* Check that CPUID 0x06 is supported and the vendor is Intel.*/
109 if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL)
112 * CPUID 0x06 returns 1 if the processor has on-die thermal
113 * sensors. EBX[0:3] contains the number of sensors.
115 do_cpuid(0x06, regs);
116 if ((regs[0] & 0x1) != 1)
120 * We add a child for each CPU since settings must be performed
121 * on each CPU in the SMP case.
123 child = device_add_child(parent, "coretemp", -1);
125 device_printf(parent, "add coretemp child failed\n");
129 coretemp_probe(device_t dev)
131 if (resource_disabled("coretemp", 0))
134 device_set_desc(dev, "CPU On-Die Thermal Sensors");
136 return (BUS_PROBE_GENERIC);
140 coretemp_attach(device_t dev)
142 struct coretemp_softc *sc = device_get_softc(dev);
145 int cpu_model, cpu_stepping;
149 pdev = device_get_parent(dev);
150 cpu_model = CPUID_TO_MODEL(cpu_id);
151 cpu_stepping = cpu_id & CPUID_STEPPING;
154 * Some CPUs, namely the PIII, don't have thermal sensors, but
155 * report them when the CPUID check is performed in
156 * coretemp_identify(). This leads to a later GPF when the sensor
157 * is queried via a MSR, so we stop here.
163 * XXXrpaulo: I have this CPU model and when it returns from C3
164 * coretemp continues to function properly.
168 * Check for errata AE18.
169 * "Processor Digital Thermal Sensor (DTS) Readout stops
170 * updating upon returning from C3/C4 state."
172 * Adapted from the Linux coretemp driver.
174 if (cpu_model == 0xe && cpu_stepping < 0xc) {
175 msr = rdmsr(MSR_BIOS_SIGN);
178 device_printf(dev, "not supported (Intel errata "
179 "AE18), try updating your BIOS\n");
186 * Use 100C as the initial value.
190 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
192 * On some Core 2 CPUs, there's an undocumented MSR that
193 * can tell us if Tj(max) is 100 or 85.
195 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted
196 * from the Linux coretemp driver.
198 msr = rdmsr(MSR_IA32_EXT_CONFIG);
201 } else if (cpu_model == 0x17) {
202 switch (cpu_stepping) {
203 case 0x6: /* Mobile Core 2 Duo */
206 default: /* Unknown stepping */
209 } else if (cpu_model == 0x1c) {
210 switch (cpu_stepping) {
211 case 0xa: /* 45nm Atom D400, N400 and D500 series */
220 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
222 * This method is described in Intel white paper "CPU
223 * Monitoring With DTS/PECI". (#322683)
225 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
227 tjtarget = (msr >> 16) & 0xff;
230 * On earlier generation of processors, the value
231 * obtained from IA32_TEMPERATURE_TARGET register is
232 * an offset that needs to be summed with a model
233 * specific base. It is however not clear what
234 * these numbers are, with the publicly available
235 * documents from Intel.
237 * For now, we consider [70, 110]C range, as
238 * described in #322683, as "reasonable" and accept
239 * these values whenever the MSR is available for
240 * read, regardless the CPU model.
242 if (tjtarget >= 70 && tjtarget <= 110)
243 sc->sc_tjmax = tjtarget;
245 device_printf(dev, "Tj(target) value %d "
246 "does not seem right.\n", tjtarget);
248 device_printf(dev, "Can not get Tj(target) "
249 "from your CPU, using 100C.\n");
253 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
255 sc->sc_cpu = device_get_unit(device_get_parent(dev));
256 sc->sc_gd = globaldata_find(sc->sc_cpu);
259 * Add hw.sensors.cpuN.temp0 MIB.
261 strlcpy(sc->sc_sensordev.xname, device_get_nameunit(pdev),
262 sizeof(sc->sc_sensordev.xname));
263 ksnprintf(sc->sc_sensor.desc, sizeof(sc->sc_sensor.desc),
264 "node%d core%d", get_chip_ID(sc->sc_cpu),
265 get_core_number_within_chip(sc->sc_cpu));
266 sc->sc_sensor.type = SENSOR_TEMP;
267 sc->sc_sensor.status = SENSOR_S_UNSPEC;
268 sc->sc_sensor.flags |= SENSOR_FINVALID;
269 sc->sc_sensor.value = 0;
270 sensor_attach(&sc->sc_sensordev, &sc->sc_sensor);
271 sensor_task_register(sc, coretemp_refresh, 2);
272 sensordev_install(&sc->sc_sensordev);
278 coretemp_detach(device_t dev)
280 struct coretemp_softc *sc = device_get_softc(dev);
282 sensordev_deinstall(&sc->sc_sensordev);
283 sensor_task_unregister(sc);
285 lwkt_synchronize_ipiqs("coretemp");
291 coretemp_ipifunc(void *xsc)
293 struct coretemp_softc *sc = xsc;
295 sc->sc_msr = rdmsr(MSR_THERM_STATUS);
297 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_PENDING);
301 coretemp_get_temp(device_t dev)
305 struct coretemp_softc *sc = device_get_softc(dev);
310 * Send IPI to the specific CPU to read the correct
311 * temperature. If the IPI does not complete yet,
312 * i.e. CORETEMP_FLAG_PENDING is set, return -1.
314 if (ncpus > 1 && cpu != mycpuid) {
315 if ((sc->sc_flags & CORETEMP_FLAG_INITED) == 0) {
316 /* The first time we are called */
317 KASSERT((sc->sc_flags & CORETEMP_FLAG_PENDING) == 0,
318 ("has pending bit set"));
319 atomic_set_int(&sc->sc_flags,
320 CORETEMP_FLAG_INITED | CORETEMP_FLAG_PENDING);
322 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc);
325 if (sc->sc_flags & CORETEMP_FLAG_PENDING) {
326 /* IPI does not complete yet */
329 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_PENDING);
333 msr = rdmsr(MSR_THERM_STATUS);
337 * Check for Thermal Status and Thermal Status Log.
339 if ((msr & 0x3) == 0x3)
340 device_printf(dev, "PROCHOT asserted\n");
343 * Bit 31 contains "Reading valid"
345 if (((msr >> 31) & 0x1) == 1) {
347 * Starting on bit 16 and ending on bit 22.
349 temp = sc->sc_tjmax - ((msr >> 16) & 0x7f);
354 * Check for Critical Temperature Status and Critical
356 * It doesn't really matter if the current temperature is
357 * invalid because the "Critical Temperature Log" bit will
358 * tell us if the Critical Temperature has been reached in
359 * past. It's not directly related to the current temperature.
361 * If we reach a critical level, allow devctl(4) to catch this
362 * and shutdown the system.
364 if (((msr >> 4) & 0x3) == 0x3) {
365 if ((sc->sc_flags & CORETEMP_FLAG_CRIT) == 0) {
368 device_printf(dev, "critical temperature detected, "
369 "suggest system shutdown\n");
370 ksnprintf(stemp, sizeof(stemp), "%d", temp);
371 devctl_notify("coretemp", "Thermal", stemp,
373 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_CRIT);
375 } else if (sc->sc_flags & CORETEMP_FLAG_CRIT) {
376 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_CRIT);
379 if (sc->sc_flags & CORETEMP_FLAG_PENDING) {
381 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipifunc, sc);
388 coretemp_refresh(void *arg)
390 struct coretemp_softc *sc = arg;
391 device_t dev = sc->sc_dev;
392 struct ksensor *s = &sc->sc_sensor;
395 temp = coretemp_get_temp(dev);
398 /* No updates; keep the previous value */
399 } else if (temp == -1) {
400 s->status = SENSOR_S_UNSPEC;
401 s->flags |= SENSOR_FINVALID;
404 if (sc->sc_flags & CORETEMP_FLAG_CRIT)
405 s->status = SENSOR_S_CRIT;
407 s->status = SENSOR_S_OK;
408 s->flags &= ~SENSOR_FINVALID;
409 s->value = temp * 1000000 + 273150000;