2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
39 static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 /***** radeon AUX functions *****/
48 /* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
78 memcpy(dst, src, num_bytes);
82 union aux_channel_transaction {
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 u8 *send, int send_bytes,
89 u8 *recv, int recv_size,
92 struct drm_device *dev = chan->dev;
93 struct radeon_device *rdev = dev->dev_private;
94 union aux_channel_transaction args;
95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
100 memset(&args, 0, sizeof(args));
102 lockmgr(&chan->mutex, LK_EXCLUSIVE);
103 lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_EXCLUSIVE);
105 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
107 radeon_atom_copy_swap(base, send, send_bytes, true);
109 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
110 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
111 args.v1.ucDataOutLen = 0;
112 args.v1.ucChannelID = chan->rec.i2c_id;
113 args.v1.ucDelay = delay / 10;
114 if (ASIC_IS_DCE4(rdev))
115 args.v2.ucHPD_ID = chan->rec.hpd;
117 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
119 *ack = args.v1.ucReplyStatus;
122 if (args.v1.ucReplyStatus == 1) {
123 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
129 if (args.v1.ucReplyStatus == 2) {
130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
136 if (args.v1.ucReplyStatus == 3) {
137 DRM_DEBUG_KMS("dp_aux_ch error\n");
142 recv_bytes = args.v1.ucDataOutLen;
143 if (recv_bytes > recv_size)
144 recv_bytes = recv_size;
146 if (recv && recv_size)
147 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
151 lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_RELEASE);
152 lockmgr(&chan->mutex, LK_RELEASE);
157 #define BARE_ADDRESS_SIZE 3
158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
161 radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
163 struct radeon_i2c_chan *chan =
164 container_of(aux, struct radeon_i2c_chan, aux);
170 if (WARN_ON(msg->size > 16))
173 tx_buf[0] = msg->address & 0xff;
174 tx_buf[1] = msg->address >> 8;
175 tx_buf[2] = msg->request << 4;
176 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
178 switch (msg->request & ~DP_AUX_I2C_MOT) {
179 case DP_AUX_NATIVE_WRITE:
180 case DP_AUX_I2C_WRITE:
181 /* tx_size needs to be 4 even for bare address packets since the atom
182 * table needs the info in tx_buf[3].
184 tx_size = HEADER_SIZE + msg->size;
186 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
188 tx_buf[3] |= tx_size << 4;
189 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
190 ret = radeon_process_aux_ch(chan,
191 tx_buf, tx_size, NULL, 0, delay, &ack);
193 /* Return payload size. */
196 case DP_AUX_NATIVE_READ:
197 case DP_AUX_I2C_READ:
198 /* tx_size needs to be 4 even for bare address packets since the atom
199 * table needs the info in tx_buf[3].
201 tx_size = HEADER_SIZE;
203 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
205 tx_buf[3] |= tx_size << 4;
206 ret = radeon_process_aux_ch(chan,
207 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
215 msg->reply = ack >> 4;
220 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
222 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
224 dig_connector->dp_i2c_bus->rec.hpd = radeon_connector->hpd.hpd; /* XXX check*/
225 dig_connector->dp_i2c_bus->aux.dev = radeon_connector->base.kdev;
226 dig_connector->dp_i2c_bus->aux.transfer = radeon_dp_aux_transfer;
229 int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte)
231 struct i2c_algo_dp_aux_data *algo_data = device_get_softc(dev);
232 struct radeon_i2c_chan *auxch = algo_data->priv;
233 u16 address = algo_data->address;
242 /* Set up the address */
244 msg[1] = address >> 8;
246 /* Set up the command byte */
247 if (mode & MODE_I2C_READ) {
248 msg[2] = DP_AUX_I2C_READ << 4;
250 msg[3] = msg_bytes << 4;
252 msg[2] = DP_AUX_I2C_WRITE << 4;
254 msg[3] = msg_bytes << 4;
258 /* special handling for start/stop */
259 if (mode & (MODE_I2C_START | MODE_I2C_STOP))
262 /* Set MOT bit for all but stop */
263 if ((mode & MODE_I2C_STOP) == 0)
264 msg[2] |= DP_AUX_I2C_MOT << 4;
266 for (retry = 0; retry < 7; retry++) {
267 ret = radeon_process_aux_ch(auxch,
268 msg, msg_bytes, reply, reply_bytes, 0, &ack);
272 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
276 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
277 case DP_AUX_NATIVE_REPLY_ACK:
278 /* I2C-over-AUX Reply field is only valid
279 * when paired with AUX ACK.
282 case DP_AUX_NATIVE_REPLY_NACK:
283 DRM_DEBUG_KMS("aux_ch native nack\n");
285 case DP_AUX_NATIVE_REPLY_DEFER:
286 DRM_DEBUG_KMS("aux_ch native defer\n");
287 usleep_range(500, 600);
290 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
294 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
295 case DP_AUX_I2C_REPLY_ACK:
296 if (mode == MODE_I2C_READ)
297 *read_byte = reply[0];
298 return (0); /* XXX: why 0 and not msg size? */
299 case DP_AUX_I2C_REPLY_NACK:
300 DRM_DEBUG_KMS("aux_i2c nack\n");
302 case DP_AUX_I2C_REPLY_DEFER:
303 DRM_DEBUG_KMS("aux_i2c defer\n");
304 usleep_range(400, 500);
307 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
312 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
316 /***** general DP utility functions *****/
318 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
319 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
321 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
329 for (lane = 0; lane < lane_count; lane++) {
330 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
331 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
333 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
335 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
336 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
344 if (v >= DP_VOLTAGE_MAX)
345 v |= DP_TRAIN_MAX_SWING_REACHED;
347 if (p >= DP_PRE_EMPHASIS_MAX)
348 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
350 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
351 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
352 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
354 for (lane = 0; lane < 4; lane++)
355 train_set[lane] = v | p;
358 /* convert bits per color to bits per pixel */
359 /* get bpc from the EDID */
360 static int convert_bpc_to_bpp(int bpc)
368 /* get the max pix clock supported by the link rate and lane num */
369 static int dp_get_max_dp_pix_clock(int link_rate,
373 return (link_rate * lane_num * 8) / bpp;
376 /***** radeon specific DP functions *****/
378 static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
379 u8 dpcd[DP_DPCD_SIZE])
383 if (radeon_connector_is_dp12_capable(connector))
384 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
386 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
388 return max_link_rate;
391 /* First get the min lane# when low rate is used according to pixel clock
392 * (prefer low rate), second check max lane# supported by DP panel,
393 * if the max lane# < low rate lane# then use max lane# instead.
395 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
396 u8 dpcd[DP_DPCD_SIZE],
399 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
400 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
401 int max_lane_num = drm_dp_max_lane_count(dpcd);
403 int max_dp_pix_clock;
405 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
406 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
407 if (pix_clock <= max_dp_pix_clock)
414 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
415 u8 dpcd[DP_DPCD_SIZE],
418 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
419 int lane_num, max_pix_clock;
421 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
422 ENCODER_OBJECT_ID_NUTMEG)
425 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
426 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
427 if (pix_clock <= max_pix_clock)
429 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
430 if (pix_clock <= max_pix_clock)
432 if (radeon_connector_is_dp12_capable(connector)) {
433 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
434 if (pix_clock <= max_pix_clock)
438 return radeon_dp_get_max_link_rate(connector, dpcd);
441 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
442 int action, int dp_clock,
443 u8 ucconfig, u8 lane_num)
445 DP_ENCODER_SERVICE_PARAMETERS args;
446 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
448 memset(&args, 0, sizeof(args));
449 args.ucLinkClock = dp_clock / 10;
450 args.ucConfig = ucconfig;
451 args.ucAction = action;
452 args.ucLaneNum = lane_num;
455 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
456 return args.ucStatus;
459 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
461 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
462 struct drm_device *dev = radeon_connector->base.dev;
463 struct radeon_device *rdev = dev->dev_private;
465 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
466 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
469 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
471 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
474 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
477 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_SINK_OUI, buf, 3) == 3)
478 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n",
479 buf[0], buf[1], buf[2]);
481 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
482 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n",
483 buf[0], buf[1], buf[2]);
486 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
488 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
489 u8 msg[DP_DPCD_SIZE];
492 char dpcd_hex_dump[DP_DPCD_SIZE * 3];
494 ret = drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_DPCD_REV, msg,
497 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
498 DRM_DEBUG_KMS("DPCD: %s\n", hexncpy(dig_connector->dpcd,
499 sizeof(dig_connector->dpcd),
500 dpcd_hex_dump, sizeof(dpcd_hex_dump), " "));
502 radeon_dp_probe_oui(radeon_connector);
506 dig_connector->dpcd[0] = 0;
510 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
511 struct drm_connector *connector)
513 struct drm_device *dev = encoder->dev;
514 struct radeon_device *rdev = dev->dev_private;
515 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
516 struct radeon_connector_atom_dig *dig_connector;
517 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
518 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
521 if (!ASIC_IS_DCE4(rdev))
524 if (!radeon_connector->con_priv)
527 dig_connector = radeon_connector->con_priv;
529 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
530 /* DP bridge chips */
531 if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
532 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
534 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
535 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
536 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
537 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
539 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
541 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
543 if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
544 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
546 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
553 void radeon_dp_set_link_config(struct drm_connector *connector,
554 const struct drm_display_mode *mode)
556 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
557 struct radeon_connector_atom_dig *dig_connector;
559 if (!radeon_connector->con_priv)
561 dig_connector = radeon_connector->con_priv;
563 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
564 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
565 dig_connector->dp_clock =
566 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
567 dig_connector->dp_lane_count =
568 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
572 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
573 struct drm_display_mode *mode)
575 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
576 struct radeon_connector_atom_dig *dig_connector;
579 if ((mode->clock > 340000) &&
580 (!radeon_connector_is_dp12_capable(connector)))
581 return MODE_CLOCK_HIGH;
583 if (!radeon_connector->con_priv)
584 return MODE_CLOCK_HIGH;
585 dig_connector = radeon_connector->con_priv;
588 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
590 if ((dp_clock == 540000) &&
591 (!radeon_connector_is_dp12_capable(connector)))
592 return MODE_CLOCK_HIGH;
597 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
599 u8 link_status[DP_LINK_STATUS_SIZE];
600 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
602 if (drm_dp_dpcd_read_link_status(&dig->dp_i2c_bus->aux, link_status) <= 0)
604 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
609 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
612 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
613 struct radeon_connector_atom_dig *dig_connector;
615 if (!radeon_connector->con_priv)
618 dig_connector = radeon_connector->con_priv;
620 /* power up/down the sink */
621 if (dig_connector->dpcd[0] >= 0x11) {
622 drm_dp_dpcd_writeb(&dig_connector->dp_i2c_bus->aux,
623 DP_SET_POWER, power_state);
624 usleep_range(1000, 2000);
629 struct radeon_dp_link_train_info {
630 struct radeon_device *rdev;
631 struct drm_encoder *encoder;
632 struct drm_connector *connector;
637 u8 dpcd[DP_RECEIVER_CAP_SIZE];
639 u8 link_status[DP_LINK_STATUS_SIZE];
642 struct drm_dp_aux *aux;
645 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
647 /* set the initial vs/emph on the source */
648 atombios_dig_transmitter_setup(dp_info->encoder,
649 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
650 0, dp_info->train_set[0]); /* sets all lanes at once */
652 /* set the vs/emph on the sink */
653 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
654 dp_info->train_set, dp_info->dp_lane_count);
657 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
661 /* set training pattern on the source */
662 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
664 case DP_TRAINING_PATTERN_1:
665 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
667 case DP_TRAINING_PATTERN_2:
668 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
670 case DP_TRAINING_PATTERN_3:
671 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
674 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
677 case DP_TRAINING_PATTERN_1:
680 case DP_TRAINING_PATTERN_2:
684 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
685 dp_info->dp_clock, dp_info->enc_id, rtp);
688 /* enable training pattern on the sink */
689 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
692 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
694 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
695 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
698 /* power up the sink */
699 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
701 /* possibly enable downspread on the sink */
702 if (dp_info->dpcd[3] & 0x1)
703 drm_dp_dpcd_writeb(dp_info->aux,
704 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
706 drm_dp_dpcd_writeb(dp_info->aux,
707 DP_DOWNSPREAD_CTRL, 0);
709 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
710 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
711 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
714 /* set the lane count on the sink */
715 tmp = dp_info->dp_lane_count;
716 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
717 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
718 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
720 /* set the link rate on the sink */
721 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
722 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
724 /* start training on the source */
725 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
726 atombios_dig_encoder_setup(dp_info->encoder,
727 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
729 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
730 dp_info->dp_clock, dp_info->enc_id, 0);
732 /* disable the training pattern on the sink */
733 drm_dp_dpcd_writeb(dp_info->aux,
734 DP_TRAINING_PATTERN_SET,
735 DP_TRAINING_PATTERN_DISABLE);
740 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
744 /* disable the training pattern on the sink */
745 drm_dp_dpcd_writeb(dp_info->aux,
746 DP_TRAINING_PATTERN_SET,
747 DP_TRAINING_PATTERN_DISABLE);
749 /* disable the training pattern on the source */
750 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
751 atombios_dig_encoder_setup(dp_info->encoder,
752 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
754 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
755 dp_info->dp_clock, dp_info->enc_id, 0);
760 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
766 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
767 memset(dp_info->train_set, 0, 4);
768 radeon_dp_update_vs_emph(dp_info);
772 /* clock recovery loop */
773 clock_recovery = false;
777 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
779 if (drm_dp_dpcd_read_link_status(dp_info->aux,
780 dp_info->link_status) <= 0) {
781 DRM_ERROR("displayport link status failed\n");
785 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
786 clock_recovery = true;
790 for (i = 0; i < dp_info->dp_lane_count; i++) {
791 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
794 if (i == dp_info->dp_lane_count) {
795 DRM_ERROR("clock recovery reached max voltage\n");
799 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
801 if (dp_info->tries == 5) {
802 DRM_ERROR("clock recovery tried 5 times\n");
808 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
810 /* Compute new train_set as requested by sink */
811 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
813 radeon_dp_update_vs_emph(dp_info);
815 if (!clock_recovery) {
816 DRM_ERROR("clock recovery failed\n");
819 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
820 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
821 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
822 DP_TRAIN_PRE_EMPHASIS_SHIFT);
827 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
831 if (dp_info->tp3_supported)
832 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
834 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
836 /* channel equalization loop */
840 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
842 if (drm_dp_dpcd_read_link_status(dp_info->aux,
843 dp_info->link_status) <= 0) {
844 DRM_ERROR("displayport link status failed\n");
848 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
854 if (dp_info->tries > 5) {
855 DRM_ERROR("channel eq failed: 5 tries\n");
859 /* Compute new train_set as requested by sink */
860 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
862 radeon_dp_update_vs_emph(dp_info);
867 DRM_ERROR("channel eq failed\n");
870 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
871 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
872 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
873 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
878 void radeon_dp_link_train(struct drm_encoder *encoder,
879 struct drm_connector *connector)
881 struct drm_device *dev = encoder->dev;
882 struct radeon_device *rdev = dev->dev_private;
883 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
884 struct radeon_encoder_atom_dig *dig;
885 struct radeon_connector *radeon_connector;
886 struct radeon_connector_atom_dig *dig_connector;
887 struct radeon_dp_link_train_info dp_info;
891 if (!radeon_encoder->enc_priv)
893 dig = radeon_encoder->enc_priv;
895 radeon_connector = to_radeon_connector(connector);
896 if (!radeon_connector->con_priv)
898 dig_connector = radeon_connector->con_priv;
900 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
901 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
904 /* DPEncoderService newer than 1.1 can't program properly the
905 * training pattern. When facing such version use the
906 * DIGXEncoderControl (X== 1 | 2)
908 dp_info.use_dpencoder = true;
909 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
910 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
912 dp_info.use_dpencoder = false;
917 if (dig->dig_encoder)
918 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
920 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
922 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
924 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
926 if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, DP_MAX_LANE_COUNT, &tmp)
928 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
929 dp_info.tp3_supported = true;
931 dp_info.tp3_supported = false;
933 dp_info.tp3_supported = false;
936 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
938 dp_info.encoder = encoder;
939 dp_info.connector = connector;
940 dp_info.dp_lane_count = dig_connector->dp_lane_count;
941 dp_info.dp_clock = dig_connector->dp_clock;
942 dp_info.aux = &dig_connector->dp_i2c_bus->aux;
944 if (radeon_dp_link_train_init(&dp_info))
946 if (radeon_dp_link_train_cr(&dp_info))
948 if (radeon_dp_link_train_ce(&dp_info))
951 if (radeon_dp_link_train_finish(&dp_info))