2 *********************************************************************
4 * BY : C.L. Huang (ching@tekram.com.tw)
5 * Erich Chen (erich@tekram.com.tw)
6 * Description: Device Driver for the amd53c974 PCI Bus Master
7 * SCSI Host adapter found on cards such as
8 * the Tekram DC-390(T).
9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *********************************************************************
33 * $FreeBSD: src/sys/pci/amd.c,v 1.3.2.2 2001/06/02 04:32:50 nyan Exp $
37 *********************************************************************
40 * REV# DATE NAME DESCRIPTION
41 * 1.00 07/02/96 CLH First release for RELEASE-2.1.0
42 * 1.01 08/20/96 CLH Update for RELEASE-2.1.5
43 * 1.02 11/06/96 CLH Fixed more than 1 LUN scanning
44 * 1.03 12/20/96 CLH Modify to support 2.2-ALPHA
45 * 1.04 12/26/97 CLH Modify to support RELEASE-2.2.5
46 * 1.05 01/01/99 ERICH CHEN Modify to support RELEASE-3.0.x (CAM)
47 *********************************************************************
50 /* #define AMD_DEBUG0 */
51 /* #define AMD_DEBUG_SCSI_PHASE */
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/kernel.h>
56 #include <sys/malloc.h>
57 #include <sys/queue.h>
61 #include <sys/thread2.h>
66 #include <machine/clock.h>
68 #include <bus/cam/cam.h>
69 #include <bus/cam/cam_ccb.h>
70 #include <bus/cam/cam_sim.h>
71 #include <bus/cam/cam_xpt_sim.h>
72 #include <bus/cam/cam_debug.h>
74 #include <bus/cam/scsi/scsi_all.h>
75 #include <bus/cam/scsi/scsi_message.h>
77 #include <bus/pci/pcivar.h>
78 #include <bus/pci/pcireg.h>
81 #define PCI_DEVICE_ID_AMD53C974 0x20201022ul
82 #define PCI_BASE_ADDR0 0x10
84 typedef u_int (phase_handler_t)(struct amd_softc *, struct amd_srb *, u_int);
85 typedef phase_handler_t *phase_handler_func_t;
87 static void amd_intr(void *vamd);
88 static int amdstart(struct amd_softc *amd, struct amd_srb * pSRB);
89 static phase_handler_t amd_NopPhase;
91 static phase_handler_t amd_DataOutPhase0;
92 static phase_handler_t amd_DataInPhase0;
93 #define amd_CommandPhase0 amd_NopPhase
94 static phase_handler_t amd_StatusPhase0;
95 static phase_handler_t amd_MsgOutPhase0;
96 static phase_handler_t amd_MsgInPhase0;
97 static phase_handler_t amd_DataOutPhase1;
98 static phase_handler_t amd_DataInPhase1;
99 static phase_handler_t amd_CommandPhase1;
100 static phase_handler_t amd_StatusPhase1;
101 static phase_handler_t amd_MsgOutPhase1;
102 static phase_handler_t amd_MsgInPhase1;
104 static void amdsetupcommand(struct amd_softc *amd, struct amd_srb *srb);
105 static int amdparsemsg(struct amd_softc *amd);
106 static int amdhandlemsgreject(struct amd_softc *amd);
107 static void amdconstructsdtr(struct amd_softc *amd,
108 u_int period, u_int offset);
109 static u_int amdfindclockrate(struct amd_softc *amd, u_int *period);
110 static int amdsentmsg(struct amd_softc *amd, u_int msgtype, int full);
112 static void DataIO_Comm(struct amd_softc *amd, struct amd_srb *pSRB, u_int dir);
113 static void amd_Disconnect(struct amd_softc *amd);
114 static void amd_Reselect(struct amd_softc *amd);
115 static void SRBdone(struct amd_softc *amd, struct amd_srb *pSRB);
116 static void amd_ScsiRstDetect(struct amd_softc *amd);
117 static void amd_ResetSCSIBus(struct amd_softc *amd);
118 static void RequestSense(struct amd_softc *amd, struct amd_srb *pSRB);
119 static void amd_InvalidCmd(struct amd_softc *amd);
122 static void amd_timeout(void *arg1);
123 static void amd_reset(struct amd_softc *amd);
125 static u_int8_t * phystovirt(struct amd_srb *pSRB, u_int32_t xferCnt);
127 void amd_linkSRB(struct amd_softc *amd);
128 static int amd_init(device_t);
129 static void amd_load_defaults(struct amd_softc *amd);
130 static void amd_load_eeprom_or_defaults(struct amd_softc *amd);
131 static int amd_EEpromInDO(struct amd_softc *amd);
132 static u_int16_t EEpromGetData1(struct amd_softc *amd);
133 static void amd_EnDisableCE(struct amd_softc *amd, int mode, int *regval);
134 static void amd_EEpromOutDI(struct amd_softc *amd, int *regval, int Carry);
135 static void amd_Prepare(struct amd_softc *amd, int *regval, u_int8_t EEpromCmd);
136 static void amd_ReadEEprom(struct amd_softc *amd);
138 static int amd_probe(device_t);
139 static int amd_attach(device_t);
140 static void amdcompletematch(struct amd_softc *amd, target_id_t target,
141 lun_id_t lun, u_int tag, struct srb_queue *queue,
143 static void amdsetsync(struct amd_softc *amd, u_int target, u_int clockrate,
144 u_int period, u_int offset, u_int type);
145 static void amdsettags(struct amd_softc *amd, u_int target, int tagenb);
147 static __inline void amd_clear_msg_state(struct amd_softc *amd);
150 amd_clear_msg_state(struct amd_softc *amd)
153 amd->msgout_index = 0;
154 amd->msgin_index = 0;
157 /* CAM SIM entry points */
158 #define ccb_srb_ptr spriv_ptr0
159 #define ccb_amd_ptr spriv_ptr1
160 static void amd_action(struct cam_sim *sim, union ccb *ccb);
161 static void amd_poll(struct cam_sim *sim);
164 * State engine function tables indexed by SCSI phase number
166 phase_handler_func_t amd_SCSI_phase0[] = {
177 phase_handler_func_t amd_SCSI_phase1[] = {
189 * EEProm/BIOS negotiation periods
191 u_int8_t eeprom_period[] = {
203 * chip clock setting to SCSI specified sync parameter table.
205 u_int8_t tinfo_sync_period[] = {
218 static __inline struct amd_srb *
219 amdgetsrb(struct amd_softc * amd)
221 struct amd_srb * pSRB;
224 pSRB = TAILQ_FIRST(&amd->free_srbs);
226 TAILQ_REMOVE(&amd->free_srbs, pSRB, links);
232 amdsetupcommand(struct amd_softc *amd, struct amd_srb *srb)
234 struct scsi_request_sense sense_cmd;
235 struct ccb_scsiio *csio;
239 csio = &srb->pccb->csio;
241 if (srb->SRBFlag & AUTO_REQSENSE) {
242 sense_cmd.opcode = REQUEST_SENSE;
243 sense_cmd.byte2 = srb->pccb->ccb_h.target_lun << 5;
244 sense_cmd.unused[0] = 0;
245 sense_cmd.unused[1] = 0;
246 sense_cmd.length = csio->sense_len;
247 sense_cmd.control = 0;
248 cdb = &sense_cmd.opcode;
249 cdb_len = sizeof(sense_cmd);
251 cdb = &srb->CmdBlock[0];
252 cdb_len = srb->ScsiCmdLen;
254 amd_write8_multi(amd, SCSIFIFOREG, cdb, cdb_len);
258 * Attempt to start a waiting transaction. Interrupts must be disabled
259 * upon entry to this function.
262 amdrunwaiting(struct amd_softc *amd) {
265 if (amd->last_phase != SCSI_BUS_FREE)
268 srb = TAILQ_FIRST(&amd->waiting_srbs);
272 if (amdstart(amd, srb) == 0) {
273 TAILQ_REMOVE(&amd->waiting_srbs, srb, links);
274 TAILQ_INSERT_HEAD(&amd->running_srbs, srb, links);
279 amdexecutesrb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
283 struct amd_softc *amd;
285 srb = (struct amd_srb *)arg;
287 amd = (struct amd_softc *)ccb->ccb_h.ccb_amd_ptr;
291 kprintf("amd%d: Unexpected error 0x%x returned from "
292 "bus_dmamap_load\n", amd->unit, error);
293 if (ccb->ccb_h.status == CAM_REQ_INPROG) {
294 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
295 ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN;
297 TAILQ_INSERT_HEAD(&amd->free_srbs, srb, links);
304 bus_dma_segment_t *end_seg;
307 end_seg = dm_segs + nseg;
309 /* Copy the segments into our SG list */
310 srb->pSGlist = &srb->SGsegment[0];
312 while (dm_segs < end_seg) {
313 sg->SGXLen = dm_segs->ds_len;
314 sg->SGXPtr = dm_segs->ds_addr;
319 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
320 op = BUS_DMASYNC_PREREAD;
322 op = BUS_DMASYNC_PREWRITE;
324 bus_dmamap_sync(amd->buffer_dmat, srb->dmamap, op);
329 srb->AdaptStatus = 0;
330 srb->TargetStatus = 0;
335 srb->TotalXferredLen = 0;
337 srb->SGToBeXferLen = 0;
343 * Last time we need to check if this CCB needs to
346 if (ccb->ccb_h.status != CAM_REQ_INPROG) {
348 bus_dmamap_unload(amd->buffer_dmat, srb->dmamap);
349 TAILQ_INSERT_HEAD(&amd->free_srbs, srb, links);
354 ccb->ccb_h.status |= CAM_SIM_QUEUED;
356 /* XXX Need a timeout handler */
357 callout_reset(&ccb->ccb_h.timeout_ch, (ccb->ccb_h.timeout * hz) / 1000,
360 TAILQ_INSERT_TAIL(&amd->waiting_srbs, srb, links);
366 amd_action(struct cam_sim * psim, union ccb * pccb)
368 struct amd_softc * amd;
371 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("amd_action\n"));
373 amd = (struct amd_softc *) cam_sim_softc(psim);
374 target_id = pccb->ccb_h.target_id;
376 switch (pccb->ccb_h.func_code) {
379 struct amd_srb * pSRB;
380 struct ccb_scsiio *pcsio;
385 * Assign an SRB and connect it with this ccb.
387 pSRB = amdgetsrb(amd);
391 pccb->ccb_h.status = CAM_RESRC_UNAVAIL;
396 pccb->ccb_h.ccb_srb_ptr = pSRB;
397 pccb->ccb_h.ccb_amd_ptr = amd;
398 pSRB->ScsiCmdLen = pcsio->cdb_len;
399 bcopy(pcsio->cdb_io.cdb_bytes, pSRB->CmdBlock, pcsio->cdb_len);
400 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
401 if ((pccb->ccb_h.flags & CAM_SCATTER_VALID) == 0) {
403 * We've been given a pointer
404 * to a single buffer.
406 if ((pccb->ccb_h.flags & CAM_DATA_PHYS) == 0) {
411 bus_dmamap_load(amd->buffer_dmat,
417 if (error == EINPROGRESS) {
420 * ordering, freeze the
422 * until our mapping is
425 xpt_freeze_simq(amd->psim, 1);
426 pccb->ccb_h.status |=
431 struct bus_dma_segment seg;
433 /* Pointer to physical buffer */
435 (bus_addr_t)pcsio->data_ptr;
436 seg.ds_len = pcsio->dxfer_len;
437 amdexecutesrb(pSRB, &seg, 1, 0);
440 struct bus_dma_segment *segs;
442 if ((pccb->ccb_h.flags & CAM_SG_LIST_PHYS) == 0
443 || (pccb->ccb_h.flags & CAM_DATA_PHYS) != 0) {
444 TAILQ_INSERT_HEAD(&amd->free_srbs,
446 pccb->ccb_h.status = CAM_PROVIDE_FAIL;
451 /* Just use the segments provided */
453 (struct bus_dma_segment *)pcsio->data_ptr;
454 amdexecutesrb(pSRB, segs, pcsio->sglist_cnt, 0);
457 amdexecutesrb(pSRB, NULL, 0, 0);
462 struct ccb_pathinq *cpi = &pccb->cpi;
464 cpi->version_num = 1;
465 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
466 cpi->target_sprt = 0;
468 cpi->hba_eng_cnt = 0;
470 cpi->max_lun = amd->max_lun; /* 7 or 0 */
471 cpi->initiator_id = amd->AdaptSCSIID;
472 cpi->bus_id = cam_sim_bus(psim);
473 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
474 strncpy(cpi->hba_vid, "TRM-AMD", HBA_IDLEN);
475 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
476 cpi->unit_number = cam_sim_unit(psim);
477 cpi->transport = XPORT_SPI;
478 cpi->transport_version = 2;
479 cpi->protocol = PROTO_SCSI;
480 cpi->protocol_version = SCSI_REV_2;
481 cpi->ccb_h.status = CAM_REQ_CMP;
486 pccb->ccb_h.status = CAM_REQ_INVALID;
494 amd_ResetSCSIBus(amd);
497 for (i = 0; i < 500; i++) {
498 DELAY(1000); /* Wait until our interrupt
502 pccb->ccb_h.status = CAM_REQ_CMP;
507 pccb->ccb_h.status = CAM_REQ_INVALID;
511 pccb->ccb_h.status = CAM_REQ_INVALID;
514 case XPT_GET_TRAN_SETTINGS:
516 struct ccb_trans_settings *cts = &pccb->cts;
517 struct amd_target_info *targ_info = &amd->tinfo[target_id];
518 struct amd_transinfo *tinfo;
519 struct ccb_trans_settings_scsi *scsi =
520 &cts->proto_specific.scsi;
521 struct ccb_trans_settings_spi *spi =
522 &cts->xport_specific.spi;
524 cts->protocol = PROTO_SCSI;
525 cts->protocol_version = SCSI_REV_2;
526 cts->transport = XPORT_SPI;
527 cts->transport_version = 2;
530 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
531 /* current transfer settings */
532 if (targ_info->disc_tag & AMD_CUR_DISCENB) {
533 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
537 if (targ_info->disc_tag & AMD_CUR_TAGENB) {
538 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
542 tinfo = &targ_info->current;
544 /* default(user) transfer settings */
545 if (targ_info->disc_tag & AMD_USR_DISCENB) {
546 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
550 if (targ_info->disc_tag & AMD_USR_TAGENB) {
551 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
555 tinfo = &targ_info->user;
557 spi->sync_period = tinfo->period;
558 spi->sync_offset = tinfo->offset;
561 spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
562 spi->valid = CTS_SPI_VALID_SYNC_RATE
563 | CTS_SPI_VALID_SYNC_OFFSET
564 | CTS_SPI_VALID_BUS_WIDTH
565 | CTS_SPI_VALID_DISC;
566 scsi->valid = CTS_SCSI_VALID_TQ;
567 pccb->ccb_h.status = CAM_REQ_CMP;
571 #define IS_CURRENT_SETTINGS(c) (c->type == CTS_TYPE_CURRENT_SETTINGS)
572 #define IS_USER_SETTINGS(c) (c->type == CTS_TYPE_USER_SETTINGS)
573 case XPT_SET_TRAN_SETTINGS:
575 struct ccb_trans_settings *cts = &pccb->cts;
576 struct amd_target_info *targ_info;
577 u_int update_type = 0;
580 struct ccb_trans_settings_scsi *scsi =
581 &cts->proto_specific.scsi;
582 struct ccb_trans_settings_spi *spi =
583 &cts->xport_specific.spi;
584 if (IS_CURRENT_SETTINGS(cts)) {
585 update_type |= AMD_TRANS_GOAL;
586 } else if (IS_USER_SETTINGS(cts)) {
587 update_type |= AMD_TRANS_USER;
590 || update_type == (AMD_TRANS_USER|AMD_TRANS_GOAL)) {
591 cts->ccb_h.status = CAM_REQ_INVALID;
596 targ_info = &amd->tinfo[target_id];
598 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) {
599 if (update_type & AMD_TRANS_GOAL) {
600 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
602 targ_info->disc_tag |= AMD_CUR_DISCENB;
604 targ_info->disc_tag &= ~AMD_CUR_DISCENB;
607 if (update_type & AMD_TRANS_USER) {
608 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
610 targ_info->disc_tag |= AMD_USR_DISCENB;
612 targ_info->disc_tag &= ~AMD_USR_DISCENB;
616 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
617 if (update_type & AMD_TRANS_GOAL) {
618 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
620 targ_info->disc_tag |= AMD_CUR_TAGENB;
622 targ_info->disc_tag &= ~AMD_CUR_TAGENB;
625 if (update_type & AMD_TRANS_USER) {
626 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
628 targ_info->disc_tag |= AMD_USR_TAGENB;
630 targ_info->disc_tag &= ~AMD_USR_TAGENB;
635 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) == 0) {
636 if (update_type & AMD_TRANS_GOAL)
637 spi->sync_offset = targ_info->goal.offset;
639 spi->sync_offset = targ_info->user.offset;
642 if (spi->sync_offset > AMD_MAX_SYNC_OFFSET)
643 spi->sync_offset = AMD_MAX_SYNC_OFFSET;
645 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) == 0) {
646 if (update_type & AMD_TRANS_GOAL)
647 spi->sync_period = targ_info->goal.period;
649 spi->sync_period = targ_info->user.period;
652 last_entry = sizeof(tinfo_sync_period) - 1;
653 if ((spi->sync_period != 0)
654 && (spi->sync_period < tinfo_sync_period[0]))
655 spi->sync_period = tinfo_sync_period[0];
656 if (spi->sync_period > tinfo_sync_period[last_entry])
657 spi->sync_period = 0;
658 if (spi->sync_offset == 0)
659 spi->sync_period = 0;
661 if ((update_type & AMD_TRANS_USER) != 0) {
662 targ_info->user.period = spi->sync_period;
663 targ_info->user.offset = spi->sync_offset;
665 if ((update_type & AMD_TRANS_GOAL) != 0) {
666 targ_info->goal.period = spi->sync_period;
667 targ_info->goal.offset = spi->sync_offset;
670 pccb->ccb_h.status = CAM_REQ_CMP;
674 case XPT_CALC_GEOMETRY:
676 struct ccb_calc_geometry *ccg;
678 u_int32_t secs_per_cylinder;
682 size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size);
683 extended = (amd->eepromBuf[EE_MODE2] & GREATER_1G) != 0;
685 if (size_mb > 1024 && extended) {
687 ccg->secs_per_track = 63;
690 ccg->secs_per_track = 32;
692 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
693 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
694 pccb->ccb_h.status = CAM_REQ_CMP;
699 pccb->ccb_h.status = CAM_REQ_INVALID;
706 amd_poll(struct cam_sim * psim)
708 amd_intr(cam_sim_softc(psim));
712 phystovirt(struct amd_srb * pSRB, u_int32_t xferCnt)
715 struct ccb_scsiio *pcsio;
717 struct amd_sg * pseg;
720 pcsio = &pSRB->pccb->csio;
722 dataPtr = (intptr_t) pcsio->data_ptr;
723 pseg = pSRB->SGsegment;
724 for (i = 0; i < pSRB->SGIndex; i++) {
725 dataPtr += (int) pseg->SGXLen;
728 dataPtr += (int) xferCnt;
729 return ((u_int8_t *) dataPtr);
733 ResetDevParam(struct amd_softc * amd)
737 for (target = 0; target <= amd->max_id; target++) {
738 if (amd->AdaptSCSIID != target) {
739 amdsetsync(amd, target, /*clockrate*/0,
740 /*period*/0, /*offset*/0, AMD_TRANS_CUR);
746 amdcompletematch(struct amd_softc *amd, target_id_t target, lun_id_t lun,
747 u_int tag, struct srb_queue *queue, cam_status status)
750 struct amd_srb *next_srb;
752 for (srb = TAILQ_FIRST(queue); srb != NULL; srb = next_srb) {
755 next_srb = TAILQ_NEXT(srb, links);
756 if (srb->pccb->ccb_h.target_id != target
757 && target != CAM_TARGET_WILDCARD)
760 if (srb->pccb->ccb_h.target_lun != lun
761 && lun != CAM_LUN_WILDCARD)
764 if (srb->TagNumber != tag
765 && tag != AMD_TAG_WILDCARD)
769 TAILQ_REMOVE(queue, srb, links);
770 TAILQ_INSERT_HEAD(&amd->free_srbs, srb, links);
771 if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0
772 && (status & CAM_DEV_QFRZN) != 0)
773 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
774 ccb->ccb_h.status = status;
781 amdsetsync(struct amd_softc *amd, u_int target, u_int clockrate,
782 u_int period, u_int offset, u_int type)
784 struct amd_target_info *tinfo;
788 tinfo = &amd->tinfo[target];
789 old_period = tinfo->current.period;
790 old_offset = tinfo->current.offset;
791 if ((type & AMD_TRANS_CUR) != 0
792 && (old_period != period || old_offset != offset)) {
793 struct cam_path *path;
795 tinfo->current.period = period;
796 tinfo->current.offset = offset;
797 tinfo->sync_period_reg = clockrate;
798 tinfo->sync_offset_reg = offset;
799 tinfo->CtrlR3 &= ~FAST_SCSI;
800 tinfo->CtrlR4 &= ~EATER_25NS;
802 tinfo->CtrlR4 |= EATER_25NS;
804 tinfo->CtrlR3 |= FAST_SCSI;
806 if ((type & AMD_TRANS_ACTIVE) == AMD_TRANS_ACTIVE) {
807 amd_write8(amd, SYNCPERIOREG, tinfo->sync_period_reg);
808 amd_write8(amd, SYNCOFFREG, tinfo->sync_offset_reg);
809 amd_write8(amd, CNTLREG3, tinfo->CtrlR3);
810 amd_write8(amd, CNTLREG4, tinfo->CtrlR4);
812 /* If possible, update the XPT's notion of our transfer rate */
813 if (xpt_create_path(&path, /*periph*/NULL,
814 cam_sim_path(amd->psim), target,
815 CAM_LUN_WILDCARD) == CAM_REQ_CMP) {
816 struct ccb_trans_settings neg;
817 struct ccb_trans_settings_spi *spi =
818 &neg.xport_specific.spi;
819 xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1);
820 memset(&neg, 0, sizeof (neg));
821 spi->sync_period = period;
822 spi->sync_offset = offset;
823 spi->valid = CTS_SPI_VALID_SYNC_RATE
824 | CTS_SPI_VALID_SYNC_OFFSET;
825 xpt_async(AC_TRANSFER_NEG, path, &neg);
829 if ((type & AMD_TRANS_GOAL) != 0) {
830 tinfo->goal.period = period;
831 tinfo->goal.offset = offset;
834 if ((type & AMD_TRANS_USER) != 0) {
835 tinfo->user.period = period;
836 tinfo->user.offset = offset;
841 amdsettags(struct amd_softc *amd, u_int target, int tagenb)
843 panic("Implement me!");
849 **********************************************************************
850 * Function : amd_reset (struct amd_softc * amd)
851 * Purpose : perform a hard reset on the SCSI bus( and AMD chip).
852 * Inputs : cmd - command which caused the SCSI RESET
853 **********************************************************************
856 amd_reset(struct amd_softc * amd)
863 kprintf("DC390: RESET");
867 bval = amd_read8(amd, CNTLREG1);
868 bval |= DIS_INT_ON_SCSI_RST;
869 amd_write8(amd, CNTLREG1, bval); /* disable interrupt */
870 amd_ResetSCSIBus(amd);
872 for (i = 0; i < 500; i++) {
876 bval = amd_read8(amd, CNTLREG1);
877 bval &= ~DIS_INT_ON_SCSI_RST;
878 amd_write8(amd, CNTLREG1, bval); /* re-enable interrupt */
880 amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD);
881 amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
884 amdcompletematch(amd, CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD,
885 AMD_TAG_WILDCARD, &amd->running_srbs,
886 CAM_DEV_QFRZN|CAM_SCSI_BUS_RESET);
887 amdcompletematch(amd, CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD,
888 AMD_TAG_WILDCARD, &amd->waiting_srbs,
889 CAM_DEV_QFRZN|CAM_SCSI_BUS_RESET);
890 amd->active_srb = NULL;
897 amd_timeout(void *arg1)
899 struct amd_srb * pSRB;
901 pSRB = (struct amd_srb *) arg1;
906 amdstart(struct amd_softc *amd, struct amd_srb *pSRB)
909 struct ccb_scsiio *pcsio;
910 struct amd_target_info *targ_info;
918 target = pccb->ccb_h.target_id;
919 lun = pccb->ccb_h.target_lun;
920 targ_info = &amd->tinfo[target];
922 amd_clear_msg_state(amd);
923 amd_write8(amd, SCSIDESTIDREG, target);
924 amd_write8(amd, SYNCPERIOREG, targ_info->sync_period_reg);
925 amd_write8(amd, SYNCOFFREG, targ_info->sync_offset_reg);
926 amd_write8(amd, CNTLREG1, targ_info->CtrlR1);
927 amd_write8(amd, CNTLREG3, targ_info->CtrlR3);
928 amd_write8(amd, CNTLREG4, targ_info->CtrlR4);
929 amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
931 identify_msg = MSG_IDENTIFYFLAG | lun;
932 if ((targ_info->disc_tag & AMD_CUR_DISCENB) != 0
933 && (pccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0
934 && (pSRB->CmdBlock[0] != REQUEST_SENSE)
935 && (pSRB->SRBFlag & AUTO_REQSENSE) == 0)
936 identify_msg |= MSG_IDENTIFY_DISCFLAG;
938 amd_write8(amd, SCSIFIFOREG, identify_msg);
939 if ((targ_info->disc_tag & AMD_CUR_TAGENB) == 0
940 || (identify_msg & MSG_IDENTIFY_DISCFLAG) == 0)
941 pccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
942 if (targ_info->current.period != targ_info->goal.period
943 || targ_info->current.offset != targ_info->goal.offset) {
944 command = SEL_W_ATN_STOP;
945 amdconstructsdtr(amd, targ_info->goal.period,
946 targ_info->goal.offset);
947 } else if ((pccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) {
948 command = SEL_W_ATN2;
949 pSRB->SRBState = SRB_START;
950 amd_write8(amd, SCSIFIFOREG, pcsio->tag_action);
951 amd_write8(amd, SCSIFIFOREG, pSRB->TagNumber);
954 pSRB->SRBState = SRB_START;
956 if (command != SEL_W_ATN_STOP)
957 amdsetupcommand(amd, pSRB);
959 if (amd_read8(amd, SCSISTATREG) & INTERRUPT) {
960 pSRB->SRBState = SRB_READY;
963 amd->last_phase = SCSI_ARBITRATING;
964 amd_write8(amd, SCSICMDREG, command);
965 amd->active_srb = pSRB;
966 amd->cur_target = target;
973 * Catch an interrupt from the adapter.
974 * Process pending device interrupts.
979 struct amd_softc *amd;
980 struct amd_srb *pSRB;
981 u_int internstat = 0;
985 amd = (struct amd_softc *)arg;
989 kprintf("amd_intr: amd NULL return......");
994 scsistat = amd_read8(amd, SCSISTATREG);
995 if (!(scsistat & INTERRUPT)) {
997 kprintf("amd_intr: scsistat = NULL ,return......");
1001 #ifdef AMD_DEBUG_SCSI_PHASE
1002 kprintf("scsistat=%2x,", scsistat);
1005 internstat = amd_read8(amd, INTERNSTATREG);
1006 intstat = amd_read8(amd, INTSTATREG);
1008 #ifdef AMD_DEBUG_SCSI_PHASE
1009 kprintf("intstat=%2x,", intstat);
1012 if (intstat & DISCONNECTED) {
1013 amd_Disconnect(amd);
1016 if (intstat & RESELECTED) {
1020 if (intstat & INVALID_CMD) {
1021 amd_InvalidCmd(amd);
1024 if (intstat & SCSI_RESET_) {
1025 amd_ScsiRstDetect(amd);
1028 if (intstat & (SUCCESSFUL_OP + SERVICE_REQUEST)) {
1029 pSRB = amd->active_srb;
1031 * Run our state engine. First perform
1032 * post processing for the last phase we
1033 * were in, followed by any processing
1034 * required to handle the current phase.
1037 amd_SCSI_phase0[amd->last_phase](amd, pSRB, scsistat);
1038 amd->last_phase = scsistat & SCSI_PHASE_MASK;
1039 (void)amd_SCSI_phase1[amd->last_phase](amd, pSRB, scsistat);
1044 amd_DataOutPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1046 struct amd_sg *psgl;
1047 u_int32_t ResidCnt, xferCnt;
1049 if (!(pSRB->SRBState & SRB_XFERPAD)) {
1050 if (scsistat & PARITY_ERR) {
1051 pSRB->SRBStatus |= PARITY_ERROR;
1053 if (scsistat & COUNT_2_ZERO) {
1054 while ((amd_read8(amd, DMA_Status)&DMA_XFER_DONE) == 0)
1056 pSRB->TotalXferredLen += pSRB->SGToBeXferLen;
1058 if (pSRB->SGIndex < pSRB->SGcount) {
1060 psgl = pSRB->pSGlist;
1061 pSRB->SGPhysAddr = psgl->SGXPtr;
1062 pSRB->SGToBeXferLen = psgl->SGXLen;
1064 pSRB->SGToBeXferLen = 0;
1067 ResidCnt = amd_read8(amd, CURRENTFIFOREG) & 0x1f;
1068 ResidCnt += amd_read8(amd, CTCREG_LOW)
1069 | (amd_read8(amd, CTCREG_MID) << 8)
1070 | (amd_read8(amd, CURTXTCNTREG) << 16);
1072 xferCnt = pSRB->SGToBeXferLen - ResidCnt;
1073 pSRB->SGPhysAddr += xferCnt;
1074 pSRB->TotalXferredLen += xferCnt;
1075 pSRB->SGToBeXferLen = ResidCnt;
1078 amd_write8(amd, DMA_Cmd, WRITE_DIRECTION | DMA_IDLE_CMD);
1083 amd_DataInPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1086 u_int16_t i, residual;
1087 struct amd_sg *psgl;
1088 u_int32_t ResidCnt, xferCnt;
1091 if (!(pSRB->SRBState & SRB_XFERPAD)) {
1092 if (scsistat & PARITY_ERR) {
1093 pSRB->SRBStatus |= PARITY_ERROR;
1095 if (scsistat & COUNT_2_ZERO) {
1097 bval = amd_read8(amd, DMA_Status);
1098 if ((bval & DMA_XFER_DONE) != 0)
1101 amd_write8(amd, DMA_Cmd, READ_DIRECTION|DMA_IDLE_CMD);
1103 pSRB->TotalXferredLen += pSRB->SGToBeXferLen;
1105 if (pSRB->SGIndex < pSRB->SGcount) {
1107 psgl = pSRB->pSGlist;
1108 pSRB->SGPhysAddr = psgl->SGXPtr;
1109 pSRB->SGToBeXferLen = psgl->SGXLen;
1111 pSRB->SGToBeXferLen = 0;
1113 } else { /* phase changed */
1115 bval = amd_read8(amd, CURRENTFIFOREG);
1116 while (bval & 0x1f) {
1117 if ((bval & 0x1f) == 1) {
1118 for (i = 0; i < 0x100; i++) {
1119 bval = amd_read8(amd, CURRENTFIFOREG);
1120 if (!(bval & 0x1f)) {
1122 } else if (i == 0x0ff) {
1128 bval = amd_read8(amd, CURRENTFIFOREG);
1132 amd_write8(amd, DMA_Cmd, READ_DIRECTION|DMA_BLAST_CMD);
1133 for (i = 0; i < 0x8000; i++) {
1134 if ((amd_read8(amd, DMA_Status)&BLAST_COMPLETE))
1137 amd_write8(amd, DMA_Cmd, READ_DIRECTION|DMA_IDLE_CMD);
1139 ResidCnt = amd_read8(amd, CTCREG_LOW)
1140 | (amd_read8(amd, CTCREG_MID) << 8)
1141 | (amd_read8(amd, CURTXTCNTREG) << 16);
1142 xferCnt = pSRB->SGToBeXferLen - ResidCnt;
1143 pSRB->SGPhysAddr += xferCnt;
1144 pSRB->TotalXferredLen += xferCnt;
1145 pSRB->SGToBeXferLen = ResidCnt;
1147 /* get residual byte */
1148 bval = amd_read8(amd, SCSIFIFOREG);
1149 ptr = phystovirt(pSRB, xferCnt);
1152 pSRB->TotalXferredLen++;
1153 pSRB->SGToBeXferLen--;
1161 amd_StatusPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1163 pSRB->TargetStatus = amd_read8(amd, SCSIFIFOREG);
1165 pSRB->EndMessage = amd_read8(amd, SCSIFIFOREG);
1166 pSRB->SRBState = SRB_COMPLETED;
1167 amd_write8(amd, SCSICMDREG, MSG_ACCEPTED_CMD);
1172 amd_MsgOutPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1174 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL + SRB_ABORT_SENT)) {
1175 scsistat = SCSI_NOP0;
1181 amd_MsgInPhase0(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1185 amd->msgin_buf[amd->msgin_index] = amd_read8(amd, SCSIFIFOREG);
1187 done = amdparsemsg(amd);
1189 amd->msgin_index = 0;
1196 amdparsemsg(struct amd_softc *amd)
1207 * Parse as much of the message as is availible,
1208 * rejecting it if we don't support it. When
1209 * the entire message is availible and has been
1210 * handled, return TRUE indicating that we have
1211 * parsed an entire message.
1213 switch (amd->msgin_buf[0]) {
1214 case MSG_DISCONNECT:
1215 amd->active_srb->SRBState = SRB_DISCONNECT;
1216 amd->disc_count[amd->cur_target][amd->cur_lun]++;
1219 case MSG_SIMPLE_Q_TAG:
1221 struct amd_srb *disc_srb;
1223 if (amd->msgin_index < 1)
1225 disc_srb = &amd->SRB_array[amd->msgin_buf[1]];
1226 if (amd->active_srb != NULL
1227 || disc_srb->SRBState != SRB_DISCONNECT
1228 || disc_srb->pccb->ccb_h.target_id != amd->cur_target
1229 || disc_srb->pccb->ccb_h.target_lun != amd->cur_lun) {
1230 kprintf("amd%d: Unexpected tagged reselection "
1231 "for target %d, Issuing Abort\n", amd->unit,
1233 amd->msgout_buf[0] = MSG_ABORT;
1234 amd->msgout_len = 1;
1238 amd->active_srb = disc_srb;
1239 amd->disc_count[amd->cur_target][amd->cur_lun]--;
1243 case MSG_MESSAGE_REJECT:
1244 response = amdhandlemsgreject(amd);
1245 if (response == FALSE)
1246 amd_write8(amd, SCSICMDREG, RESET_ATN_CMD);
1258 /* Wait for enough of the message to begin validation */
1259 if (amd->msgin_index < 1)
1261 if (amd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
1266 /* Wait for opcode */
1267 if (amd->msgin_index < 2)
1270 if (amd->msgin_buf[2] != MSG_EXT_SDTR) {
1276 * Wait until we have both args before validating
1277 * and acting on this message.
1279 * Add one to MSG_EXT_SDTR_LEN to account for
1280 * the extended message preamble.
1282 if (amd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
1285 period = amd->msgin_buf[3];
1286 saved_offset = offset = amd->msgin_buf[4];
1287 clockrate = amdfindclockrate(amd, &period);
1288 if (offset > AMD_MAX_SYNC_OFFSET)
1289 offset = AMD_MAX_SYNC_OFFSET;
1290 if (period == 0 || offset == 0) {
1295 amdsetsync(amd, amd->cur_target, clockrate, period, offset,
1296 AMD_TRANS_ACTIVE|AMD_TRANS_GOAL);
1299 * See if we initiated Sync Negotiation
1300 * and didn't have to fall down to async
1303 if (amdsentmsg(amd, MSG_EXT_SDTR, /*full*/TRUE)) {
1305 if (saved_offset != offset) {
1306 /* Went too low - force async */
1311 * Send our own SDTR in reply
1314 kprintf("Sending SDTR!\n");
1315 amd->msgout_index = 0;
1316 amd->msgout_len = 0;
1317 amdconstructsdtr(amd, period, offset);
1318 amd->msgout_index = 0;
1324 case MSG_SAVEDATAPOINTER:
1325 case MSG_RESTOREPOINTERS:
1326 /* XXX Implement!!! */
1335 amd->msgout_index = 0;
1336 amd->msgout_len = 1;
1337 amd->msgout_buf[0] = MSG_MESSAGE_REJECT;
1343 amd_write8(amd, SCSICMDREG, SET_ATN_CMD);
1345 if (done && !response)
1346 /* Clear the outgoing message buffer */
1347 amd->msgout_len = 0;
1350 amd_write8(amd, SCSICMDREG, MSG_ACCEPTED_CMD);
1356 amdfindclockrate(struct amd_softc *amd, u_int *period)
1361 for (i = 0; i < sizeof(tinfo_sync_period); i++) {
1362 u_int8_t *table_entry;
1364 table_entry = &tinfo_sync_period[i];
1365 if (*period <= *table_entry) {
1367 * When responding to a target that requests
1368 * sync, the requested rate may fall between
1369 * two rates that we can output, but still be
1370 * a rate that we can receive. Because of this,
1371 * we want to respond to the target with
1372 * the same rate that it sent to us even
1373 * if the period we use to send data to it
1374 * is lower. Only lower the response period
1378 *period = *table_entry;
1384 if (i == sizeof(tinfo_sync_period)) {
1385 /* Too slow for us. Use asnyc transfers. */
1395 * See if we sent a particular extended message to the target.
1396 * If "full" is true, the target saw the full message.
1397 * If "full" is false, the target saw at least the first
1398 * byte of the message.
1401 amdsentmsg(struct amd_softc *amd, u_int msgtype, int full)
1409 while (index < amd->msgout_len) {
1410 if ((amd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
1411 || amd->msgout_buf[index] == MSG_MESSAGE_REJECT)
1413 else if (amd->msgout_buf[index] >= MSG_SIMPLE_Q_TAG
1414 && amd->msgout_buf[index] < MSG_IGN_WIDE_RESIDUE) {
1415 /* Skip tag type and tag id */
1417 } else if (amd->msgout_buf[index] == MSG_EXTENDED) {
1418 /* Found a candidate */
1419 if (amd->msgout_buf[index+2] == msgtype) {
1422 end_index = index + 1
1423 + amd->msgout_buf[index + 1];
1425 if (amd->msgout_index > end_index)
1427 } else if (amd->msgout_index > index)
1432 panic("amdsentmsg: Inconsistent msg buffer");
1439 amdconstructsdtr(struct amd_softc *amd, u_int period, u_int offset)
1441 amd->msgout_buf[amd->msgout_index++] = MSG_EXTENDED;
1442 amd->msgout_buf[amd->msgout_index++] = MSG_EXT_SDTR_LEN;
1443 amd->msgout_buf[amd->msgout_index++] = MSG_EXT_SDTR;
1444 amd->msgout_buf[amd->msgout_index++] = period;
1445 amd->msgout_buf[amd->msgout_index++] = offset;
1446 amd->msgout_len += 5;
1450 amdhandlemsgreject(struct amd_softc *amd)
1453 * If we had an outstanding SDTR for this
1454 * target, this is a signal that the target
1455 * is refusing negotiation. Also watch out
1456 * for rejected tag messages.
1458 struct amd_srb *srb;
1459 struct amd_target_info *targ_info;
1460 int response = FALSE;
1462 srb = amd->active_srb;
1463 targ_info = &amd->tinfo[amd->cur_target];
1464 if (amdsentmsg(amd, MSG_EXT_SDTR, /*full*/FALSE)) {
1465 /* note asynch xfers and clear flag */
1466 amdsetsync(amd, amd->cur_target, /*clockrate*/0,
1467 /*period*/0, /*offset*/0,
1468 AMD_TRANS_ACTIVE|AMD_TRANS_GOAL);
1469 kprintf("amd%d:%d: refuses synchronous negotiation. "
1470 "Using asynchronous transfers\n",
1471 amd->unit, amd->cur_target);
1472 } else if ((srb != NULL)
1473 && (srb->pccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) {
1474 struct ccb_trans_settings neg;
1475 struct ccb_trans_settings_scsi *scsi = &neg.proto_specific.scsi;
1477 kprintf("amd%d:%d: refuses tagged commands. Performing "
1478 "non-tagged I/O\n", amd->unit, amd->cur_target);
1480 amdsettags(amd, amd->cur_target, FALSE);
1481 memset(&neg, 0, sizeof (neg));
1482 scsi->valid = CTS_SCSI_VALID_TQ;
1483 xpt_setup_ccb(&neg.ccb_h, srb->pccb->ccb_h.path, /*priority*/1);
1484 xpt_async(AC_TRANSFER_NEG, srb->pccb->ccb_h.path, &neg);
1487 * Resend the identify for this CCB as the target
1488 * may believe that the selection is invalid otherwise.
1490 if (amd->msgout_len != 0)
1491 bcopy(&amd->msgout_buf[0], &amd->msgout_buf[1],
1493 amd->msgout_buf[0] = MSG_IDENTIFYFLAG
1494 | srb->pccb->ccb_h.target_lun;
1496 if ((targ_info->disc_tag & AMD_CUR_DISCENB) != 0
1497 && (srb->pccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0)
1498 amd->msgout_buf[0] |= MSG_IDENTIFY_DISCFLAG;
1500 srb->pccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
1503 * Requeue all tagged commands for this target
1504 * currently in our posession so they can be
1505 * converted to untagged commands.
1507 amdcompletematch(amd, amd->cur_target, amd->cur_lun,
1508 AMD_TAG_WILDCARD, &amd->waiting_srbs,
1509 CAM_DEV_QFRZN|CAM_REQUEUE_REQ);
1512 * Otherwise, we ignore it.
1514 kprintf("amd%d:%d: Message reject received -- ignored\n",
1515 amd->unit, amd->cur_target);
1521 if (!(pSRB->SRBState & SRB_MSGIN_MULTI)) {
1522 if (bval == MSG_DISCONNECT) {
1523 pSRB->SRBState = SRB_DISCONNECT;
1524 } else if (bval == MSG_SAVEDATAPOINTER) {
1526 } else if ((bval == MSG_EXTENDED)
1527 || ((bval >= MSG_SIMPLE_Q_TAG)
1528 && (bval <= MSG_ORDERED_Q_TAG))) {
1529 pSRB->SRBState |= SRB_MSGIN_MULTI;
1530 pSRB->MsgInBuf[0] = bval;
1532 pSRB->pMsgPtr = &pSRB->MsgInBuf[1];
1533 } else if (bval == MSG_MESSAGE_REJECT) {
1534 amd_write8(amd, SCSICMDREG, RESET_ATN_CMD);
1536 if (pSRB->SRBState & DO_SYNC_NEGO) {
1539 } else if (bval == MSG_RESTOREPOINTERS) {
1544 } else { /* minx: */
1545 *pSRB->pMsgPtr = bval;
1548 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_Q_TAG)
1549 && (pSRB->MsgInBuf[0] <= MSG_ORDERED_Q_TAG)) {
1550 if (pSRB->MsgCnt == 2) {
1552 pSRB = &amd->SRB_array[pSRB->MsgInBuf[1]];
1553 if (pSRB->SRBState & SRB_DISCONNECT) == 0) {
1554 pSRB = amd->pTmpSRB;
1555 pSRB->SRBState = SRB_UNEXPECT_RESEL;
1556 pDCB->pActiveSRB = pSRB;
1557 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG;
1558 EnableMsgOut2(amd, pSRB);
1560 if (pDCB->DCBFlag & ABORT_DEV_) {
1561 pSRB->SRBState = SRB_ABORT_SENT;
1562 EnableMsgOut1(amd, pSRB);
1564 pDCB->pActiveSRB = pSRB;
1565 pSRB->SRBState = SRB_DATA_XFER;
1568 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED)
1569 && (pSRB->MsgCnt == 5)) {
1570 pSRB->SRBState &= ~(SRB_MSGIN_MULTI + DO_SYNC_NEGO);
1571 if ((pSRB->MsgInBuf[1] != 3)
1572 || (pSRB->MsgInBuf[2] != 1)) { /* reject_msg: */
1574 pSRB->MsgInBuf[0] = MSG_MESSAGE_REJECT;
1575 amd_write8(amd, SCSICMDREG, SET_ATN_CMD);
1576 } else if (!(pSRB->MsgInBuf[3])
1577 || !(pSRB->MsgInBuf[4])) {
1578 set_async: /* set async */
1580 pDCB = pSRB->pSRBDCB;
1581 /* disable sync & sync nego */
1582 pDCB->SyncMode &= ~(SYNC_ENABLE|SYNC_NEGO_DONE);
1583 pDCB->SyncPeriod = 0;
1584 pDCB->SyncOffset = 0;
1586 pDCB->tinfo.goal.period = 0;
1587 pDCB->tinfo.goal.offset = 0;
1589 pDCB->tinfo.current.period = 0;
1590 pDCB->tinfo.current.offset = 0;
1591 pDCB->tinfo.current.width =
1592 MSG_EXT_WDTR_BUS_8_BIT;
1594 pDCB->CtrlR3 = FAST_CLK; /* non_fast */
1595 pDCB->CtrlR4 &= 0x3f;
1596 pDCB->CtrlR4 |= EATER_25NS;
1598 } else {/* set sync */
1600 pDCB = pSRB->pSRBDCB;
1601 /* enable sync & sync nego */
1602 pDCB->SyncMode |= SYNC_ENABLE|SYNC_NEGO_DONE;
1604 /* set sync offset */
1605 pDCB->SyncOffset &= 0x0f0;
1606 pDCB->SyncOffset |= pSRB->MsgInBuf[4];
1608 /* set sync period */
1609 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3];
1611 wval = (u_int16_t) pSRB->MsgInBuf[3];
1615 if ((wval1 * 25) != wval) {
1618 bval = FAST_CLK|FAST_SCSI;
1619 pDCB->CtrlR4 &= 0x3f;
1624 pDCB->CtrlR4 |= EATER_25NS;
1626 pDCB->CtrlR3 = bval;
1627 pDCB->SyncPeriod = (u_int8_t) wval1;
1629 pDCB->tinfo.goal.period =
1630 tinfo_sync_period[pDCB->SyncPeriod - 4];
1631 pDCB->tinfo.goal.offset = pDCB->SyncOffset;
1632 pDCB->tinfo.current.period =
1633 tinfo_sync_period[pDCB->SyncPeriod - 4];
1634 pDCB->tinfo.current.offset = pDCB->SyncOffset;
1637 * program SCSI control register
1640 amd_write8(amd, SYNCPERIOREG, pDCB->SyncPeriod);
1641 amd_write8(amd, SYNCOFFREG, pDCB->SyncOffset);
1642 amd_write8(amd, CNTLREG3, pDCB->CtrlR3);
1643 amd_write8(amd, CNTLREG4, pDCB->CtrlR4);
1648 amd_write8(amd, SCSICMDREG, MSG_ACCEPTED_CMD);
1654 amd_DataOutPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1656 DataIO_Comm(amd, pSRB, WRITE_DIRECTION);
1661 amd_DataInPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1663 DataIO_Comm(amd, pSRB, READ_DIRECTION);
1668 DataIO_Comm(struct amd_softc *amd, struct amd_srb *pSRB, u_int ioDir)
1670 struct amd_sg * psgl;
1673 if (pSRB->SGIndex < pSRB->SGcount) {
1674 amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD|ioDir);/* |EN_DMA_INT */
1676 if (!pSRB->SGToBeXferLen) {
1677 psgl = pSRB->pSGlist;
1678 pSRB->SGPhysAddr = psgl->SGXPtr;
1679 pSRB->SGToBeXferLen = psgl->SGXLen;
1681 lval = pSRB->SGToBeXferLen;
1682 amd_write8(amd, CTCREG_LOW, lval);
1683 amd_write8(amd, CTCREG_MID, lval >> 8);
1684 amd_write8(amd, CURTXTCNTREG, lval >> 16);
1686 amd_write32(amd, DMA_XferCnt, pSRB->SGToBeXferLen);
1688 amd_write32(amd, DMA_XferAddr, pSRB->SGPhysAddr);
1690 pSRB->SRBState = SRB_DATA_XFER;
1692 amd_write8(amd, SCSICMDREG, DMA_COMMAND|INFO_XFER_CMD);
1694 amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD|ioDir); /* |EN_DMA_INT */
1696 amd_write8(amd, DMA_Cmd, DMA_START_CMD|ioDir);/* |EN_DMA_INT */
1697 } else { /* xfer pad */
1698 if (pSRB->SGcount) {
1699 pSRB->AdaptStatus = H_OVER_UNDER_RUN;
1700 pSRB->SRBStatus |= OVER_RUN;
1702 amd_write8(amd, CTCREG_LOW, 0);
1703 amd_write8(amd, CTCREG_MID, 0);
1704 amd_write8(amd, CURTXTCNTREG, 0);
1706 pSRB->SRBState |= SRB_XFERPAD;
1707 amd_write8(amd, SCSICMDREG, DMA_COMMAND|XFER_PAD_BYTE);
1712 amd_CommandPhase1(struct amd_softc *amd, struct amd_srb *srb, u_int scsistat)
1714 amd_write8(amd, SCSICMDREG, RESET_ATN_CMD);
1715 amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
1717 amdsetupcommand(amd, srb);
1719 srb->SRBState = SRB_COMMAND;
1720 amd_write8(amd, SCSICMDREG, INFO_XFER_CMD);
1725 amd_StatusPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1727 amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
1728 pSRB->SRBState = SRB_STATUS;
1729 amd_write8(amd, SCSICMDREG, INITIATOR_CMD_CMPLTE);
1734 amd_MsgOutPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1736 amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
1738 if (amd->msgout_len == 0) {
1739 amd->msgout_buf[0] = MSG_NOOP;
1740 amd->msgout_len = 1;
1742 amd_write8_multi(amd, SCSIFIFOREG, amd->msgout_buf, amd->msgout_len);
1743 amd_write8(amd, SCSICMDREG, INFO_XFER_CMD);
1748 amd_MsgInPhase1(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1750 amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
1751 amd_write8(amd, SCSICMDREG, INFO_XFER_CMD);
1756 amd_NopPhase(struct amd_softc *amd, struct amd_srb *pSRB, u_int scsistat)
1762 amd_Disconnect(struct amd_softc * amd)
1764 struct amd_srb *srb;
1768 srb = amd->active_srb;
1769 amd->active_srb = NULL;
1770 amd->last_phase = SCSI_BUS_FREE;
1771 amd_write8(amd, SCSICMDREG, EN_SEL_RESEL);
1772 target = amd->cur_target;
1776 /* Invalid reselection */
1778 } else if (srb->SRBState & SRB_ABORT_SENT) {
1779 /* Clean up and done this srb */
1781 while (( = TAILQ_FIRST(&amd->running_srbs)) != NULL) {
1782 /* XXX What about "done'ing" these srbs??? */
1783 if (pSRB->pSRBDCB == pDCB) {
1784 TAILQ_REMOVE(&amd->running_srbs, pSRB, links);
1785 TAILQ_INSERT_HEAD(&amd->free_srbs, pSRB, links);
1791 if ((srb->SRBState & (SRB_START | SRB_MSGOUT))
1792 || !(srb->SRBState & (SRB_DISCONNECT | SRB_COMPLETED))) {
1793 srb->TargetStatus = AMD_SCSI_STAT_SEL_TIMEOUT;
1795 } else if (srb->SRBState & SRB_DISCONNECT) {
1796 if (!(srb->pccb->ccb_h.flags & CAM_TAG_ACTION_VALID))
1797 amd->untagged_srbs[target][lun] = srb;
1799 } else if (srb->SRBState & SRB_COMPLETED) {
1801 srb->SRBState = SRB_FREE;
1809 amd_Reselect(struct amd_softc *amd)
1811 struct amd_target_info *tinfo;
1812 u_int16_t disc_count;
1814 amd_clear_msg_state(amd);
1815 if (amd->active_srb != NULL) {
1816 /* Requeue the SRB for our attempted Selection */
1817 TAILQ_REMOVE(&amd->running_srbs, amd->active_srb, links);
1818 TAILQ_INSERT_HEAD(&amd->waiting_srbs, amd->active_srb, links);
1819 amd->active_srb = NULL;
1822 amd->cur_target = amd_read8(amd, SCSIFIFOREG);
1823 amd->cur_target ^= amd->HostID_Bit;
1824 amd->cur_target = ffs(amd->cur_target) - 1;
1825 amd->cur_lun = amd_read8(amd, SCSIFIFOREG) & 7;
1826 tinfo = &amd->tinfo[amd->cur_target];
1827 amd->active_srb = amd->untagged_srbs[amd->cur_target][amd->cur_lun];
1828 disc_count = amd->disc_count[amd->cur_target][amd->cur_lun];
1829 if (disc_count == 0) {
1830 kprintf("amd%d: Unexpected reselection for target %d, "
1831 "Issuing Abort\n", amd->unit, amd->cur_target);
1832 amd->msgout_buf[0] = MSG_ABORT;
1833 amd->msgout_len = 1;
1834 amd_write8(amd, SCSICMDREG, SET_ATN_CMD);
1836 if (amd->active_srb != NULL) {
1837 amd->disc_count[amd->cur_target][amd->cur_lun]--;
1838 amd->untagged_srbs[amd->cur_target][amd->cur_lun] = NULL;
1841 amd_write8(amd, SCSIDESTIDREG, amd->cur_target);
1842 amd_write8(amd, SYNCPERIOREG, tinfo->sync_period_reg);
1843 amd_write8(amd, SYNCOFFREG, tinfo->sync_offset_reg);
1844 amd_write8(amd, CNTLREG1, tinfo->CtrlR1);
1845 amd_write8(amd, CNTLREG3, tinfo->CtrlR3);
1846 amd_write8(amd, CNTLREG4, tinfo->CtrlR4);
1847 amd_write8(amd, SCSICMDREG, MSG_ACCEPTED_CMD);/* drop /ACK */
1848 amd->last_phase = SCSI_NOP0;
1852 SRBdone(struct amd_softc *amd, struct amd_srb *pSRB)
1854 u_int8_t bval, i, status;
1856 struct ccb_scsiio *pcsio;
1857 struct amd_sg *ptr2;
1861 pcsio = &pccb->csio;
1863 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE,
1864 ("SRBdone - TagNumber %d\n", pSRB->TagNumber));
1866 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1867 bus_dmasync_op_t op;
1869 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1870 op = BUS_DMASYNC_POSTREAD;
1872 op = BUS_DMASYNC_POSTWRITE;
1873 bus_dmamap_sync(amd->buffer_dmat, pSRB->dmamap, op);
1874 bus_dmamap_unload(amd->buffer_dmat, pSRB->dmamap);
1877 status = pSRB->TargetStatus;
1878 pccb->ccb_h.status = CAM_REQ_CMP;
1879 if (pSRB->SRBFlag & AUTO_REQSENSE) {
1880 pSRB->SRBFlag &= ~AUTO_REQSENSE;
1881 pSRB->AdaptStatus = 0;
1882 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND;
1884 if (status == SCSI_STATUS_CHECK_COND) {
1885 pccb->ccb_h.status = CAM_SEL_TIMEOUT;
1888 *((u_int32_t *)&(pSRB->CmdBlock[0])) = pSRB->Segment0[0];
1890 pcsio->sense_resid = pcsio->sense_len
1891 - pSRB->TotalXferredLen;
1892 pSRB->TotalXferredLen = pSRB->Segment1[1];
1893 if (pSRB->TotalXferredLen) {
1895 pcsio->resid = pcsio->dxfer_len
1896 - pSRB->TotalXferredLen;
1897 /* The resid field contains valid data */
1898 /* Flush resid bytes on complete */
1900 pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
1902 pccb->ccb_h.status = CAM_AUTOSNS_VALID|CAM_SCSI_STATUS_ERROR;
1906 if (status == SCSI_STATUS_CHECK_COND) {
1908 if ((pSRB->SGIndex < pSRB->SGcount)
1909 && (pSRB->SGcount) && (pSRB->SGToBeXferLen)) {
1910 bval = pSRB->SGcount;
1911 swlval = pSRB->SGToBeXferLen;
1912 ptr2 = pSRB->pSGlist;
1914 for (i = pSRB->SGIndex + 1; i < bval; i++) {
1915 swlval += ptr2->SGXLen;
1919 pcsio->resid = swlval;
1922 kprintf("XferredLen=%8x,NotYetXferLen=%8x,",
1923 pSRB->TotalXferredLen, swlval);
1926 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) {
1928 kprintf("RequestSense..................\n");
1930 RequestSense(amd, pSRB);
1933 pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
1934 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1936 } else if (status == SCSI_STATUS_QUEUE_FULL) {
1937 pSRB->AdaptStatus = 0;
1938 pSRB->TargetStatus = 0;
1939 pcsio->scsi_status = SCSI_STATUS_QUEUE_FULL;
1940 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1942 } else if (status == AMD_SCSI_STAT_SEL_TIMEOUT) {
1943 pSRB->AdaptStatus = H_SEL_TIMEOUT;
1944 pSRB->TargetStatus = 0;
1946 pcsio->scsi_status = AMD_SCSI_STAT_SEL_TIMEOUT;
1947 pccb->ccb_h.status = CAM_SEL_TIMEOUT;
1948 } else if (status == SCSI_STATUS_BUSY) {
1950 kprintf("DC390: target busy at %s %d\n",
1951 __FILE__, __LINE__);
1953 pcsio->scsi_status = SCSI_STATUS_BUSY;
1954 pccb->ccb_h.status = CAM_SCSI_BUSY;
1955 } else if (status == SCSI_STATUS_RESERV_CONFLICT) {
1957 kprintf("DC390: target reserved at %s %d\n",
1958 __FILE__, __LINE__);
1960 pcsio->scsi_status = SCSI_STATUS_RESERV_CONFLICT;
1961 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /* XXX */
1963 pSRB->AdaptStatus = 0;
1965 kprintf("DC390: driver stuffup at %s %d\n",
1966 __FILE__, __LINE__);
1968 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1971 status = pSRB->AdaptStatus;
1972 if (status & H_OVER_UNDER_RUN) {
1973 pSRB->TargetStatus = 0;
1975 pccb->ccb_h.status = CAM_DATA_RUN_ERR;
1976 } else if (pSRB->SRBStatus & PARITY_ERROR) {
1978 kprintf("DC390: driver stuffup %s %d\n",
1979 __FILE__, __LINE__);
1981 /* Driver failed to perform operation */
1982 pccb->ccb_h.status = CAM_UNCOR_PARITY;
1983 } else { /* No error */
1984 pSRB->AdaptStatus = 0;
1985 pSRB->TargetStatus = 0;
1987 /* there is no error, (sense is invalid) */
1992 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) {
1993 /* CAM request not yet complete =>device_Q frozen */
1994 xpt_freeze_devq(pccb->ccb_h.path, 1);
1995 pccb->ccb_h.status |= CAM_DEV_QFRZN;
1997 TAILQ_REMOVE(&amd->running_srbs, pSRB, links);
1998 TAILQ_INSERT_HEAD(&amd->free_srbs, pSRB, links);
2006 amd_ResetSCSIBus(struct amd_softc * amd)
2009 amd->ACBFlag |= RESET_DEV;
2010 amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD);
2011 amd_write8(amd, SCSICMDREG, RST_SCSI_BUS_CMD);
2017 amd_ScsiRstDetect(struct amd_softc * amd)
2022 kprintf("amd_ScsiRstDetect \n");
2026 while (--wlval) { /* delay 1 sec */
2031 amd_write8(amd, DMA_Cmd, DMA_IDLE_CMD);
2032 amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
2034 if (amd->ACBFlag & RESET_DEV) {
2035 amd->ACBFlag |= RESET_DONE;
2037 amd->ACBFlag |= RESET_DETECT;
2039 amdcompletematch(amd, CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD,
2040 AMD_TAG_WILDCARD, &amd->running_srbs,
2041 CAM_DEV_QFRZN|CAM_SCSI_BUS_RESET);
2042 amdcompletematch(amd, CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD,
2043 AMD_TAG_WILDCARD, &amd->waiting_srbs,
2044 CAM_DEV_QFRZN|CAM_SCSI_BUS_RESET);
2045 amd->active_srb = NULL;
2054 RequestSense(struct amd_softc *amd, struct amd_srb *pSRB)
2057 struct ccb_scsiio *pcsio;
2060 pcsio = &pccb->csio;
2062 pSRB->SRBFlag |= AUTO_REQSENSE;
2063 pSRB->Segment0[0] = *((u_int32_t *) & (pSRB->CmdBlock[0]));
2064 pSRB->Segment0[1] = *((u_int32_t *) & (pSRB->CmdBlock[4]));
2065 pSRB->Segment1[0] = (pSRB->ScsiCmdLen << 8) + pSRB->SGcount;
2066 pSRB->Segment1[1] = pSRB->TotalXferredLen;
2068 pSRB->AdaptStatus = 0;
2069 pSRB->TargetStatus = 0;
2071 pSRB->Segmentx.SGXPtr = (u_int32_t) vtophys(&pcsio->sense_data);
2072 pSRB->Segmentx.SGXLen = (u_int32_t) pcsio->sense_len;
2074 pSRB->pSGlist = &pSRB->Segmentx;
2078 *((u_int32_t *) & (pSRB->CmdBlock[0])) = 0x00000003;
2079 pSRB->CmdBlock[1] = pSRB->pccb->ccb_h.target_lun << 5;
2080 *((u_int16_t *) & (pSRB->CmdBlock[4])) = pcsio->sense_len;
2081 pSRB->ScsiCmdLen = 6;
2083 pSRB->TotalXferredLen = 0;
2084 pSRB->SGToBeXferLen = 0;
2085 if (amdstart(amd, pSRB) != 0) {
2086 TAILQ_REMOVE(&amd->running_srbs, pSRB, links);
2087 TAILQ_INSERT_HEAD(&amd->waiting_srbs, pSRB, links);
2092 amd_InvalidCmd(struct amd_softc * amd)
2094 struct amd_srb *srb;
2096 srb = amd->active_srb;
2097 if (srb->SRBState & (SRB_START|SRB_MSGOUT))
2098 amd_write8(amd, SCSICMDREG, CLEAR_FIFO_CMD);
2102 amd_linkSRB(struct amd_softc *amd)
2105 struct amd_srb *psrb;
2108 count = amd->SRBCount;
2110 for (i = 0; i < count; i++) {
2111 psrb = (struct amd_srb *)&amd->SRB_array[i];
2112 psrb->TagNumber = i;
2115 * Create the dmamap. This is no longer optional!
2117 error = bus_dmamap_create(amd->buffer_dmat, 0, &psrb->dmamap);
2119 device_printf(amd->dev, "Error %d creating buffer "
2120 "dmamap!\n", error);
2123 TAILQ_INSERT_TAIL(&amd->free_srbs, psrb, links);
2128 amd_EnDisableCE(struct amd_softc *amd, int mode, int *regval)
2130 if (mode == ENABLE_CE) {
2135 pci_write_config(amd->dev, *regval, 0, /*bytes*/1);
2136 if (mode == DISABLE_CE) {
2137 pci_write_config(amd->dev, *regval, 0, /*bytes*/1);
2143 amd_EEpromOutDI(struct amd_softc *amd, int *regval, int Carry)
2151 pci_write_config(amd->dev, *regval, bval, /*bytes*/1);
2155 pci_write_config(amd->dev, *regval, bval, /*bytes*/1);
2157 pci_write_config(amd->dev, *regval, 0, /*bytes*/1);
2162 amd_EEpromInDO(struct amd_softc *amd)
2164 pci_write_config(amd->dev, 0x80, 0x80, /*bytes*/1);
2166 pci_write_config(amd->dev, 0x80, 0x40, /*bytes*/1);
2168 if (pci_read_config(amd->dev, 0, /*bytes*/1) == 0x22)
2174 EEpromGetData1(struct amd_softc *amd)
2181 for (i = 0; i < 16; i++) {
2183 carryFlag = amd_EEpromInDO(amd);
2190 amd_Prepare(struct amd_softc *amd, int *regval, u_int8_t EEpromCmd)
2197 for (i = 0; i < 9; i++) {
2198 amd_EEpromOutDI(amd, regval, carryFlag);
2199 carryFlag = (EEpromCmd & j) ? 1 : 0;
2205 amd_ReadEEprom(struct amd_softc *amd)
2212 ptr = (u_int16_t *)&amd->eepromBuf[0];
2214 for (i = 0; i < 0x40; i++) {
2215 amd_EnDisableCE(amd, ENABLE_CE, ®val);
2216 amd_Prepare(amd, ®val, cmd);
2217 *ptr = EEpromGetData1(amd);
2220 amd_EnDisableCE(amd, DISABLE_CE, ®val);
2225 amd_load_defaults(struct amd_softc *amd)
2229 bzero(&amd->eepromBuf, sizeof amd->eepromBuf);
2230 for (target = 0; target < MAX_SCSI_ID; target++)
2231 amd->eepromBuf[target << 2] =
2232 (TAG_QUEUING|EN_DISCONNECT|SYNC_NEGO|PARITY_CHK);
2233 amd->eepromBuf[EE_ADAPT_SCSI_ID] = 7;
2234 amd->eepromBuf[EE_MODE2] = ACTIVE_NEGATION|LUN_CHECK|GREATER_1G;
2235 amd->eepromBuf[EE_TAG_CMD_NUM] = 4;
2239 amd_load_eeprom_or_defaults(struct amd_softc *amd)
2241 u_int16_t wval, *ptr;
2244 amd_ReadEEprom(amd);
2246 ptr = (u_int16_t *) & amd->eepromBuf[0];
2247 for (i = 0; i < EE_DATA_SIZE; i += 2, ptr++)
2250 if (wval != EE_CHECKSUM) {
2252 kprintf("amd%d: SEEPROM data unavailable. "
2253 "Using default device parameters.\n",
2255 amd_load_defaults(amd);
2260 **********************************************************************
2261 * Function : static int amd_init (struct Scsi_Host *host)
2262 * Purpose : initialize the internal structures for a given SCSI host
2263 * Inputs : host - pointer to this host adapter's structure/
2264 **********************************************************************
2267 amd_init(device_t dev)
2269 struct amd_softc *amd = device_get_softc(dev);
2270 struct resource *iores;
2274 rid = PCI_BASE_ADDR0;
2275 iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1,
2277 if (iores == NULL) {
2279 kprintf("amd_init: bus_alloc_resource failure!\n");
2282 amd->tag = rman_get_bustag(iores);
2283 amd->bsh = rman_get_bushandle(iores);
2285 /* DMA tag for mapping buffers into device visible space. */
2286 if (bus_dma_tag_create(/*parent_dmat*/NULL, /*alignment*/1,
2288 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
2289 /*highaddr*/BUS_SPACE_MAXADDR,
2290 /*filter*/NULL, /*filterarg*/NULL,
2291 /*maxsize*/MAXBSIZE, /*nsegments*/AMD_NSEG,
2292 /*maxsegsz*/AMD_MAXTRANSFER_SIZE,
2293 /*flags*/BUS_DMA_ALLOCNOW,
2294 &amd->buffer_dmat) != 0) {
2296 kprintf("amd_init: bus_dma_tag_create failure!\n");
2299 TAILQ_INIT(&amd->free_srbs);
2300 TAILQ_INIT(&amd->running_srbs);
2301 TAILQ_INIT(&amd->waiting_srbs);
2302 amd->last_phase = SCSI_BUS_FREE;
2304 amd->unit = device_get_unit(dev);
2305 amd->SRBCount = MAX_SRB_CNT;
2307 amd_load_eeprom_or_defaults(amd);
2309 if (amd->eepromBuf[EE_MODE2] & LUN_CHECK) {
2314 amd->AdaptSCSIID = amd->eepromBuf[EE_ADAPT_SCSI_ID];
2315 amd->HostID_Bit = (1 << amd->AdaptSCSIID);
2316 amd->AdaptSCSILUN = 0;
2317 /* (eepromBuf[EE_TAG_CMD_NUM]) << 2; */
2319 amd->Gmode2 = amd->eepromBuf[EE_MODE2];
2321 for (i = 0; i <= amd->max_id; i++) {
2323 if (amd->AdaptSCSIID != i) {
2324 struct amd_target_info *tinfo;
2327 tinfo = &amd->tinfo[i];
2328 prom = (PEEprom)&amd->eepromBuf[i << 2];
2329 if ((prom->EE_MODE1 & EN_DISCONNECT) != 0) {
2330 tinfo->disc_tag |= AMD_USR_DISCENB;
2331 if ((prom->EE_MODE1 & TAG_QUEUING) != 0)
2332 tinfo->disc_tag |= AMD_USR_TAGENB;
2334 if ((prom->EE_MODE1 & SYNC_NEGO) != 0) {
2335 tinfo->user.period =
2336 eeprom_period[prom->EE_SPEED];
2337 tinfo->user.offset = AMD_MAX_SYNC_OFFSET;
2339 tinfo->CtrlR1 = amd->AdaptSCSIID;
2340 if ((prom->EE_MODE1 & PARITY_CHK) != 0)
2341 tinfo->CtrlR1 |= PARITY_ERR_REPO;
2342 tinfo->CtrlR3 = FAST_CLK;
2343 tinfo->CtrlR4 = EATER_25NS;
2344 if ((amd->eepromBuf[EE_MODE2] & ACTIVE_NEGATION) != 0)
2345 tinfo->CtrlR4 |= NEGATE_REQACKDATA;
2348 amd_write8(amd, SCSITIMEOUTREG, 153); /* 250ms selection timeout */
2349 /* Conversion factor = 0 , 40MHz clock */
2350 amd_write8(amd, CLKFACTREG, CLK_FREQ_40MHZ);
2351 /* NOP cmd - clear command register */
2352 amd_write8(amd, SCSICMDREG, NOP_CMD);
2353 amd_write8(amd, CNTLREG2, EN_FEATURE|EN_SCSI2_CMD);
2354 amd_write8(amd, CNTLREG3, FAST_CLK);
2356 if (amd->eepromBuf[EE_MODE2] & ACTIVE_NEGATION) {
2357 bval |= NEGATE_REQACKDATA;
2359 amd_write8(amd, CNTLREG4, bval);
2361 /* Disable SCSI bus reset interrupt */
2362 amd_write8(amd, CNTLREG1, DIS_INT_ON_SCSI_RST);
2368 * attach and init a host adapter
2371 amd_attach(device_t dev)
2373 struct cam_devq *devq; /* Device Queue to use for this SIM */
2375 struct amd_softc *amd = device_get_softc(dev);
2376 int unit = device_get_unit(dev);
2379 struct resource *irqres;
2381 if (amd_init(dev)) {
2383 kprintf("amd_attach: amd_init failure!\n");
2387 /* Reset Pending INT */
2388 intstat = amd_read8(amd, INTSTATREG);
2390 /* After setting up the adapter, map our interrupt */
2392 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2393 RF_SHAREABLE | RF_ACTIVE);
2394 if (irqres == NULL ||
2395 bus_setup_intr(dev, irqres, 0, amd_intr, amd, &ih, NULL)
2398 kprintf("amd%d: unable to register interrupt handler!\n",
2404 * Now let the CAM generic SCSI layer find the SCSI devices on
2405 * the bus * start queue to reset to the idle loop. *
2406 * Create device queue of SIM(s) * (MAX_START_JOB - 1) :
2407 * max_sim_transactions
2409 devq = cam_simq_alloc(MAX_START_JOB);
2412 kprintf("amd_attach: cam_simq_alloc failure!\n");
2416 amd->psim = cam_sim_alloc(amd_action, amd_poll, "amd",
2417 amd, amd->unit, &sim_mplock, 1,
2418 MAX_TAGS_CMD_QUEUE, devq);
2419 cam_simq_release(devq);
2420 if (amd->psim == NULL) {
2422 kprintf("amd_attach: cam_sim_alloc failure!\n");
2426 if (xpt_bus_register(amd->psim, 0) != CAM_SUCCESS) {
2427 cam_sim_free(amd->psim);
2429 kprintf("amd_attach: xpt_bus_register failure!\n");
2433 if (xpt_create_path(&amd->ppath, /* periph */ NULL,
2434 cam_sim_path(amd->psim), CAM_TARGET_WILDCARD,
2435 CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
2436 xpt_bus_deregister(cam_sim_path(amd->psim));
2437 cam_sim_free(amd->psim);
2439 kprintf("amd_attach: xpt_create_path failure!\n");
2447 amd_probe(device_t dev)
2449 if (pci_get_devid(dev) == PCI_DEVICE_ID_AMD53C974) {
2450 device_set_desc(dev,
2451 "Tekram DC390(T)/AMD53c974 SCSI Host Adapter");
2457 static device_method_t amd_methods[] = {
2458 /* Device interface */
2459 DEVMETHOD(device_probe, amd_probe),
2460 DEVMETHOD(device_attach, amd_attach),
2464 static driver_t amd_driver = {
2465 "amd", amd_methods, sizeof(struct amd_softc)
2468 static devclass_t amd_devclass;
2469 DRIVER_MODULE(amd, pci, amd_driver, amd_devclass, NULL, NULL);