2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include <drm/i915_drm.h>
31 #include "intel_drv.h"
33 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
34 * them for both DP and FDI transports, allowing those ports to
35 * automatically adapt to HDMI connections as well
37 static const u32 hsw_ddi_translations_dp[] = {
38 0x00FFFFFF, 0x0006000E, /* DP parameters */
39 0x00D75FFF, 0x0005000A,
40 0x00C30FFF, 0x00040006,
41 0x80AAAFFF, 0x000B0000,
42 0x00FFFFFF, 0x0005000A,
43 0x00D75FFF, 0x000C0004,
44 0x80C30FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006,
46 0x80D75FFF, 0x000B0000,
47 0x00FFFFFF, 0x00040006 /* HDMI parameters */
50 static const u32 hsw_ddi_translations_fdi[] = {
51 0x00FFFFFF, 0x0007000E, /* FDI parameters */
52 0x00D75FFF, 0x000F000A,
53 0x00C30FFF, 0x00060006,
54 0x00AAAFFF, 0x001E0000,
55 0x00FFFFFF, 0x000F000A,
56 0x00D75FFF, 0x00160004,
57 0x00C30FFF, 0x001E0000,
58 0x00FFFFFF, 0x00060006,
59 0x00D75FFF, 0x001E0000,
60 0x00FFFFFF, 0x00040006 /* HDMI parameters */
63 static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
65 struct drm_encoder *encoder = &intel_encoder->base;
66 int type = intel_encoder->type;
68 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
69 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
70 struct intel_digital_port *intel_dig_port =
71 enc_to_dig_port(encoder);
72 return intel_dig_port->port;
74 } else if (type == INTEL_OUTPUT_ANALOG) {
78 DRM_ERROR("Invalid DDI encoder type %d\n", type);
83 /* On Haswell, DDI port buffers must be programmed with correct values
84 * in advance. The buffer values are different for FDI and DP modes,
85 * but the HDMI/DVI fields are shared among those. So we program the DDI
86 * in either FDI or DP modes only, as HDMI connections will work with both
89 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode)
91 struct drm_i915_private *dev_priv = dev->dev_private;
94 const u32 *ddi_translations = ((use_fdi_mode) ?
95 hsw_ddi_translations_fdi :
96 hsw_ddi_translations_dp);
98 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
100 use_fdi_mode ? "FDI" : "DP");
102 WARN((use_fdi_mode && (port != PORT_E)),
103 "Programming port %c in FDI mode, this probably will not work.\n",
106 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
107 I915_WRITE(reg, ddi_translations[i]);
112 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
113 * mode and port E for FDI.
115 void intel_prepare_ddi(struct drm_device *dev)
119 if (IS_HASWELL(dev)) {
120 for (port = PORT_A; port < PORT_E; port++)
121 intel_prepare_ddi_buffers(dev, port, false);
123 /* DDI E is the suggested one to work in FDI mode, so program is as such by
124 * default. It will have to be re-programmed in case a digital DP output
125 * will be detected on it
127 intel_prepare_ddi_buffers(dev, PORT_E, true);
131 static const long hsw_ddi_buf_ctl_values[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW,
133 DDI_BUF_EMP_400MV_3_5DB_HSW,
134 DDI_BUF_EMP_400MV_6DB_HSW,
135 DDI_BUF_EMP_400MV_9_5DB_HSW,
136 DDI_BUF_EMP_600MV_0DB_HSW,
137 DDI_BUF_EMP_600MV_3_5DB_HSW,
138 DDI_BUF_EMP_600MV_6DB_HSW,
139 DDI_BUF_EMP_800MV_0DB_HSW,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
143 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
146 uint32_t reg = DDI_BUF_CTL(port);
149 for (i = 0; i < 8; i++) {
151 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
157 /* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
166 void hsw_fdi_link_train(struct drm_crtc *crtc)
168 struct drm_device *dev = crtc->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
171 u32 temp, i, rx_ctl_val;
173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
178 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
179 FDI_RX_PWRDN_LANE0_VAL(2) |
180 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
182 /* Enable the PCH Receiver FDI PLL */
183 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
184 FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19);
185 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
186 POSTING_READ(_FDI_RXA_CTL);
189 /* Switch from Rawclk to PCDclk */
190 rx_ctl_val |= FDI_PCDCLK;
191 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
193 /* Configure Port Clock Select */
194 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
196 /* Start the training iterating through available voltages and emphasis,
197 * testing each value twice. */
198 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
199 /* Configure DP_TP_CTL with auto-training */
200 I915_WRITE(DP_TP_CTL(PORT_E),
201 DP_TP_CTL_FDI_AUTOTRAIN |
202 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
203 DP_TP_CTL_LINK_TRAIN_PAT1 |
206 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
207 * DDI E does not support port reversal, the functionality is
208 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
209 * port reversal bit */
210 I915_WRITE(DDI_BUF_CTL(PORT_E),
212 ((intel_crtc->fdi_lanes - 1) << 1) |
213 hsw_ddi_buf_ctl_values[i / 2]);
214 POSTING_READ(DDI_BUF_CTL(PORT_E));
218 /* Program PCH FDI Receiver TU */
219 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
221 /* Enable PCH FDI Receiver with auto-training */
222 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
223 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
224 POSTING_READ(_FDI_RXA_CTL);
226 /* Wait for FDI receiver lane calibration */
229 /* Unset FDI_RX_MISC pwrdn lanes */
230 temp = I915_READ(_FDI_RXA_MISC);
231 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
232 I915_WRITE(_FDI_RXA_MISC, temp);
233 POSTING_READ(_FDI_RXA_MISC);
235 /* Wait for FDI auto training time */
238 temp = I915_READ(DP_TP_STATUS(PORT_E));
239 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
240 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
242 /* Enable normal pixel sending for FDI */
243 I915_WRITE(DP_TP_CTL(PORT_E),
244 DP_TP_CTL_FDI_AUTOTRAIN |
245 DP_TP_CTL_LINK_TRAIN_NORMAL |
246 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
252 temp = I915_READ(DDI_BUF_CTL(PORT_E));
253 temp &= ~DDI_BUF_CTL_ENABLE;
254 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
255 POSTING_READ(DDI_BUF_CTL(PORT_E));
257 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
258 temp = I915_READ(DP_TP_CTL(PORT_E));
259 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
260 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
261 I915_WRITE(DP_TP_CTL(PORT_E), temp);
262 POSTING_READ(DP_TP_CTL(PORT_E));
264 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
266 rx_ctl_val &= ~FDI_RX_ENABLE;
267 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
268 POSTING_READ(_FDI_RXA_CTL);
270 /* Reset FDI_RX_MISC pwrdn lanes */
271 temp = I915_READ(_FDI_RXA_MISC);
272 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
273 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
274 I915_WRITE(_FDI_RXA_MISC, temp);
275 POSTING_READ(_FDI_RXA_MISC);
278 DRM_ERROR("FDI link training failed!\n");
281 /* WRPLL clock dividers */
282 struct wrpll_tmds_clock {
284 u16 p; /* Post divider */
285 u16 n2; /* Feedback divider */
286 u16 r2; /* Reference divider */
289 /* Table of matching values for WRPLL clocks programming for each frequency.
290 * The code assumes this table is sorted. */
291 static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
306 {27027, 18, 100, 111},
334 {40541, 22, 147, 89},
344 {44900, 20, 108, 65},
360 {54054, 16, 173, 108},
412 {81081, 6, 100, 111},
457 {108108, 8, 173, 108},
464 {111264, 8, 150, 91},
508 {135250, 6, 167, 111},
531 {148352, 4, 100, 91},
553 {162162, 4, 131, 109},
561 {169000, 4, 104, 83},
608 {202000, 4, 112, 75},
610 {203000, 4, 146, 97},
667 static void intel_ddi_mode_set(struct drm_encoder *encoder,
668 struct drm_display_mode *mode,
669 struct drm_display_mode *adjusted_mode)
671 struct drm_crtc *crtc = encoder->crtc;
672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
673 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
674 int port = intel_ddi_get_encoder_port(intel_encoder);
675 int pipe = intel_crtc->pipe;
676 int type = intel_encoder->type;
678 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
679 port_name(port), pipe_name(pipe));
681 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
682 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
683 struct intel_digital_port *intel_dig_port =
684 enc_to_dig_port(encoder);
686 intel_dp->DP = intel_dig_port->port_reversal |
687 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
688 switch (intel_dp->lane_count) {
690 intel_dp->DP |= DDI_PORT_WIDTH_X1;
693 intel_dp->DP |= DDI_PORT_WIDTH_X2;
696 intel_dp->DP |= DDI_PORT_WIDTH_X4;
699 intel_dp->DP |= DDI_PORT_WIDTH_X4;
700 WARN(1, "Unexpected DP lane count %d\n",
701 intel_dp->lane_count);
705 if (intel_dp->has_audio) {
706 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
707 pipe_name(intel_crtc->pipe));
710 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
711 intel_write_eld(encoder, adjusted_mode);
714 intel_dp_init_link_config(intel_dp);
716 } else if (type == INTEL_OUTPUT_HDMI) {
717 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
719 if (intel_hdmi->has_audio) {
720 /* Proper support for digital audio needs a new logic
721 * and a new set of registers, so we leave it for future
724 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
725 pipe_name(intel_crtc->pipe));
728 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
729 intel_write_eld(encoder, adjusted_mode);
732 intel_hdmi->set_infoframes(encoder, adjusted_mode);
736 static struct intel_encoder *
737 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
739 struct drm_device *dev = crtc->dev;
740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
741 struct intel_encoder *intel_encoder, *ret = NULL;
742 int num_encoders = 0;
744 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
749 if (num_encoders != 1)
750 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,
757 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
759 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
760 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
764 switch (intel_crtc->ddi_pll_sel) {
765 case PORT_CLK_SEL_SPLL:
766 plls->spll_refcount--;
767 if (plls->spll_refcount == 0) {
768 DRM_DEBUG_KMS("Disabling SPLL\n");
769 val = I915_READ(SPLL_CTL);
770 WARN_ON(!(val & SPLL_PLL_ENABLE));
771 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
772 POSTING_READ(SPLL_CTL);
775 case PORT_CLK_SEL_WRPLL1:
776 plls->wrpll1_refcount--;
777 if (plls->wrpll1_refcount == 0) {
778 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
779 val = I915_READ(WRPLL_CTL1);
780 WARN_ON(!(val & WRPLL_PLL_ENABLE));
781 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
782 POSTING_READ(WRPLL_CTL1);
785 case PORT_CLK_SEL_WRPLL2:
786 plls->wrpll2_refcount--;
787 if (plls->wrpll2_refcount == 0) {
788 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
789 val = I915_READ(WRPLL_CTL2);
790 WARN_ON(!(val & WRPLL_PLL_ENABLE));
791 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
792 POSTING_READ(WRPLL_CTL2);
797 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
798 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
799 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
801 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
804 static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2)
808 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
809 if (clock <= wrpll_tmds_clock_table[i].clock)
812 if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
815 *p = wrpll_tmds_clock_table[i].p;
816 *n2 = wrpll_tmds_clock_table[i].n2;
817 *r2 = wrpll_tmds_clock_table[i].r2;
819 if (wrpll_tmds_clock_table[i].clock != clock)
820 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
821 wrpll_tmds_clock_table[i].clock, clock);
823 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
824 clock, *p, *n2, *r2);
827 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
830 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
831 struct drm_encoder *encoder = &intel_encoder->base;
832 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
833 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
834 int type = intel_encoder->type;
835 enum i915_pipe pipe = intel_crtc->pipe;
838 /* TODO: reuse PLLs when possible (compare values) */
840 intel_ddi_put_crtc_pll(crtc);
842 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
843 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
845 switch (intel_dp->link_bw) {
846 case DP_LINK_BW_1_62:
847 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
850 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
853 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
856 DRM_ERROR("Link bandwidth %d unsupported\n",
861 /* We don't need to turn any PLL on because we'll use LCPLL. */
864 } else if (type == INTEL_OUTPUT_HDMI) {
867 if (plls->wrpll1_refcount == 0) {
868 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
870 plls->wrpll1_refcount++;
872 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
873 } else if (plls->wrpll2_refcount == 0) {
874 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
876 plls->wrpll2_refcount++;
878 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
880 DRM_ERROR("No WRPLLs available!\n");
884 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
885 "WRPLL already enabled\n");
887 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2);
889 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
890 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
891 WRPLL_DIVIDER_POST(p);
893 } else if (type == INTEL_OUTPUT_ANALOG) {
894 if (plls->spll_refcount == 0) {
895 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
897 plls->spll_refcount++;
899 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
902 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
903 "SPLL already enabled\n");
905 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
908 WARN(1, "Invalid DDI encoder type %d\n", type);
912 I915_WRITE(reg, val);
918 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
920 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
922 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
923 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
924 int type = intel_encoder->type;
927 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
929 temp = TRANS_MSA_SYNC_CLK;
930 switch (intel_crtc->bpp) {
932 temp |= TRANS_MSA_6_BPC;
935 temp |= TRANS_MSA_8_BPC;
938 temp |= TRANS_MSA_10_BPC;
941 temp |= TRANS_MSA_12_BPC;
944 temp |= TRANS_MSA_8_BPC;
945 WARN(1, "%d bpp unsupported by DDI function\n",
948 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
952 void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
955 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
956 struct drm_encoder *encoder = &intel_encoder->base;
957 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
958 enum i915_pipe pipe = intel_crtc->pipe;
959 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
960 enum port port = intel_ddi_get_encoder_port(intel_encoder);
961 int type = intel_encoder->type;
964 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
965 temp = TRANS_DDI_FUNC_ENABLE;
966 temp |= TRANS_DDI_SELECT_PORT(port);
968 switch (intel_crtc->bpp) {
970 temp |= TRANS_DDI_BPC_6;
973 temp |= TRANS_DDI_BPC_8;
976 temp |= TRANS_DDI_BPC_10;
979 temp |= TRANS_DDI_BPC_12;
982 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
986 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
987 temp |= TRANS_DDI_PVSYNC;
988 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
989 temp |= TRANS_DDI_PHSYNC;
991 if (cpu_transcoder == TRANSCODER_EDP) {
994 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
997 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1000 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1008 if (type == INTEL_OUTPUT_HDMI) {
1009 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1011 if (intel_hdmi->has_hdmi_sink)
1012 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1014 temp |= TRANS_DDI_MODE_SELECT_DVI;
1016 } else if (type == INTEL_OUTPUT_ANALOG) {
1017 temp |= TRANS_DDI_MODE_SELECT_FDI;
1018 temp |= (intel_crtc->fdi_lanes - 1) << 1;
1020 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1021 type == INTEL_OUTPUT_EDP) {
1022 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1024 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1026 switch (intel_dp->lane_count) {
1028 temp |= TRANS_DDI_PORT_WIDTH_X1;
1031 temp |= TRANS_DDI_PORT_WIDTH_X2;
1034 temp |= TRANS_DDI_PORT_WIDTH_X4;
1037 temp |= TRANS_DDI_PORT_WIDTH_X4;
1038 WARN(1, "Unsupported lane count %d\n",
1039 intel_dp->lane_count);
1043 WARN(1, "Invalid encoder type %d for pipe %d\n",
1044 intel_encoder->type, pipe);
1047 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1050 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1051 enum transcoder cpu_transcoder)
1053 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1054 uint32_t val = I915_READ(reg);
1056 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1057 val |= TRANS_DDI_PORT_NONE;
1058 I915_WRITE(reg, val);
1061 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1063 struct drm_device *dev = intel_connector->base.dev;
1064 struct drm_i915_private *dev_priv = dev->dev_private;
1065 struct intel_encoder *intel_encoder = intel_connector->encoder;
1066 int type = intel_connector->base.connector_type;
1067 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1068 enum i915_pipe pipe = 0;
1069 enum transcoder cpu_transcoder;
1072 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1076 cpu_transcoder = TRANSCODER_EDP;
1078 cpu_transcoder = pipe;
1080 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1082 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1083 case TRANS_DDI_MODE_SELECT_HDMI:
1084 case TRANS_DDI_MODE_SELECT_DVI:
1085 return (type == DRM_MODE_CONNECTOR_HDMIA);
1087 case TRANS_DDI_MODE_SELECT_DP_SST:
1088 if (type == DRM_MODE_CONNECTOR_eDP)
1090 case TRANS_DDI_MODE_SELECT_DP_MST:
1091 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1093 case TRANS_DDI_MODE_SELECT_FDI:
1094 return (type == DRM_MODE_CONNECTOR_VGA);
1101 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1102 enum i915_pipe *pipe)
1104 struct drm_device *dev = encoder->base.dev;
1105 struct drm_i915_private *dev_priv = dev->dev_private;
1106 enum port port = intel_ddi_get_encoder_port(encoder);
1110 tmp = I915_READ(DDI_BUF_CTL(port));
1112 if (!(tmp & DDI_BUF_CTL_ENABLE))
1115 if (port == PORT_A) {
1116 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1118 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1119 case TRANS_DDI_EDP_INPUT_A_ON:
1120 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1123 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1126 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1133 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1134 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1136 if ((tmp & TRANS_DDI_PORT_MASK)
1137 == TRANS_DDI_SELECT_PORT(port)) {
1144 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
1149 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1150 enum i915_pipe pipe)
1153 enum port port = I915_MAX_PORTS;
1154 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1158 if (cpu_transcoder == TRANSCODER_EDP) {
1161 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1162 temp &= TRANS_DDI_PORT_MASK;
1164 for (i = PORT_B; i <= PORT_E; i++)
1165 if (temp == TRANS_DDI_SELECT_PORT(i))
1169 ret = I915_READ(PORT_CLK_SEL(port));
1171 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1172 pipe_name(pipe), port_name(port), ret);
1177 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 enum i915_pipe pipe;
1181 struct intel_crtc *intel_crtc;
1183 for_each_pipe(pipe) {
1185 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1187 if (!intel_crtc->active)
1190 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1193 switch (intel_crtc->ddi_pll_sel) {
1194 case PORT_CLK_SEL_SPLL:
1195 dev_priv->ddi_plls.spll_refcount++;
1197 case PORT_CLK_SEL_WRPLL1:
1198 dev_priv->ddi_plls.wrpll1_refcount++;
1200 case PORT_CLK_SEL_WRPLL2:
1201 dev_priv->ddi_plls.wrpll2_refcount++;
1207 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1209 struct drm_crtc *crtc = &intel_crtc->base;
1210 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1211 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1212 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1213 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1215 if (cpu_transcoder != TRANSCODER_EDP)
1216 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1217 TRANS_CLK_SEL_PORT(port));
1220 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1222 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1223 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1225 if (cpu_transcoder != TRANSCODER_EDP)
1226 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1227 TRANS_CLK_SEL_DISABLED);
1230 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1232 struct drm_encoder *encoder = &intel_encoder->base;
1233 struct drm_crtc *crtc = encoder->crtc;
1234 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1236 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1237 int type = intel_encoder->type;
1239 if (type == INTEL_OUTPUT_EDP) {
1240 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1241 ironlake_edp_panel_vdd_on(intel_dp);
1242 ironlake_edp_panel_on(intel_dp);
1243 ironlake_edp_panel_vdd_off(intel_dp, true);
1246 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1247 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1249 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1250 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1252 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1253 intel_dp_start_link_train(intel_dp);
1254 intel_dp_complete_link_train(intel_dp);
1258 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1260 struct drm_encoder *encoder = &intel_encoder->base;
1261 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1262 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1263 int type = intel_encoder->type;
1267 val = I915_READ(DDI_BUF_CTL(port));
1268 if (val & DDI_BUF_CTL_ENABLE) {
1269 val &= ~DDI_BUF_CTL_ENABLE;
1270 I915_WRITE(DDI_BUF_CTL(port), val);
1274 val = I915_READ(DP_TP_CTL(port));
1275 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1276 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1277 I915_WRITE(DP_TP_CTL(port), val);
1280 intel_wait_ddi_buf_idle(dev_priv, port);
1282 if (type == INTEL_OUTPUT_EDP) {
1283 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1284 ironlake_edp_panel_vdd_on(intel_dp);
1285 ironlake_edp_panel_off(intel_dp);
1288 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1291 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1293 struct drm_encoder *encoder = &intel_encoder->base;
1294 struct drm_device *dev = encoder->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1297 int type = intel_encoder->type;
1299 if (type == INTEL_OUTPUT_HDMI) {
1300 struct intel_digital_port *intel_dig_port =
1301 enc_to_dig_port(encoder);
1303 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1304 * are ignored so nothing special needs to be done besides
1305 * enabling the port.
1307 I915_WRITE(DDI_BUF_CTL(port),
1308 intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);
1309 } else if (type == INTEL_OUTPUT_EDP) {
1310 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1312 ironlake_edp_backlight_on(intel_dp);
1316 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1318 struct drm_encoder *encoder = &intel_encoder->base;
1319 int type = intel_encoder->type;
1321 if (type == INTEL_OUTPUT_EDP) {
1322 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1324 ironlake_edp_backlight_off(intel_dp);
1328 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1330 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1332 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1335 else if (IS_ULT(dev_priv->dev))
1341 void intel_ddi_pll_init(struct drm_device *dev)
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1344 uint32_t val = I915_READ(LCPLL_CTL);
1346 /* The LCPLL register should be turned on by the BIOS. For now let's
1347 * just check its state and print errors in case something is wrong.
1348 * Don't even try to turn it on.
1351 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1352 intel_ddi_get_cdclk_freq(dev_priv));
1354 if (val & LCPLL_CD_SOURCE_FCLK)
1355 DRM_ERROR("CDCLK source is not LCPLL\n");
1357 if (val & LCPLL_PLL_DISABLE)
1358 DRM_ERROR("LCPLL is disabled\n");
1361 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1363 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1364 struct intel_dp *intel_dp = &intel_dig_port->dp;
1365 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1366 enum port port = intel_dig_port->port;
1370 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1371 val = I915_READ(DDI_BUF_CTL(port));
1372 if (val & DDI_BUF_CTL_ENABLE) {
1373 val &= ~DDI_BUF_CTL_ENABLE;
1374 I915_WRITE(DDI_BUF_CTL(port), val);
1378 val = I915_READ(DP_TP_CTL(port));
1379 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1380 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1381 I915_WRITE(DP_TP_CTL(port), val);
1382 POSTING_READ(DP_TP_CTL(port));
1385 intel_wait_ddi_buf_idle(dev_priv, port);
1388 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1389 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1390 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1391 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1392 I915_WRITE(DP_TP_CTL(port), val);
1393 POSTING_READ(DP_TP_CTL(port));
1395 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1396 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1397 POSTING_READ(DDI_BUF_CTL(port));
1402 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1404 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1405 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1408 intel_ddi_post_disable(intel_encoder);
1410 val = I915_READ(_FDI_RXA_CTL);
1411 val &= ~FDI_RX_ENABLE;
1412 I915_WRITE(_FDI_RXA_CTL, val);
1414 val = I915_READ(_FDI_RXA_MISC);
1415 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1416 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1417 I915_WRITE(_FDI_RXA_MISC, val);
1419 val = I915_READ(_FDI_RXA_CTL);
1421 I915_WRITE(_FDI_RXA_CTL, val);
1423 val = I915_READ(_FDI_RXA_CTL);
1424 val &= ~FDI_RX_PLL_ENABLE;
1425 I915_WRITE(_FDI_RXA_CTL, val);
1428 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1430 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1431 int type = intel_encoder->type;
1433 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1434 intel_dp_check_link_status(intel_dp);
1437 static void intel_ddi_destroy(struct drm_encoder *encoder)
1439 /* HDMI has nothing special to destroy, so we can go with this. */
1440 intel_dp_encoder_destroy(encoder);
1443 static bool intel_ddi_mode_fixup(struct drm_encoder *encoder,
1444 const struct drm_display_mode *mode,
1445 struct drm_display_mode *adjusted_mode)
1447 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1448 int type = intel_encoder->type;
1450 WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n");
1452 if (type == INTEL_OUTPUT_HDMI)
1453 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode);
1455 return intel_dp_mode_fixup(encoder, mode, adjusted_mode);
1458 static const struct drm_encoder_funcs intel_ddi_funcs = {
1459 .destroy = intel_ddi_destroy,
1462 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1463 .mode_fixup = intel_ddi_mode_fixup,
1464 .mode_set = intel_ddi_mode_set,
1465 .disable = intel_encoder_noop,
1468 void intel_ddi_init(struct drm_device *dev, enum port port)
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 struct intel_digital_port *intel_dig_port;
1472 struct intel_encoder *intel_encoder;
1473 struct drm_encoder *encoder;
1474 struct intel_connector *hdmi_connector = NULL;
1475 struct intel_connector *dp_connector = NULL;
1477 intel_dig_port = kmalloc(sizeof(struct intel_digital_port),
1478 M_DRM, M_WAITOK | M_ZERO);
1479 if (!intel_dig_port)
1482 dp_connector = kmalloc(sizeof(struct intel_connector),
1483 M_DRM, M_WAITOK | M_ZERO);
1484 if (!dp_connector) {
1485 kfree(intel_dig_port, M_DRM);
1489 if (port != PORT_A) {
1490 hdmi_connector = kmalloc(sizeof(struct intel_connector),
1491 M_DRM, M_WAITOK | M_ZERO);
1492 if (!hdmi_connector) {
1493 kfree(dp_connector, M_DRM);
1494 kfree(intel_dig_port, M_DRM);
1499 intel_encoder = &intel_dig_port->base;
1500 encoder = &intel_encoder->base;
1502 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1503 DRM_MODE_ENCODER_TMDS);
1504 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1506 intel_encoder->enable = intel_enable_ddi;
1507 intel_encoder->pre_enable = intel_ddi_pre_enable;
1508 intel_encoder->disable = intel_disable_ddi;
1509 intel_encoder->post_disable = intel_ddi_post_disable;
1510 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1512 intel_dig_port->port = port;
1513 intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
1514 DDI_BUF_PORT_REVERSAL;
1516 intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port);
1518 intel_dig_port->hdmi.sdvox_reg = 0;
1519 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1521 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1522 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1523 intel_encoder->cloneable = false;
1524 intel_encoder->hot_plug = intel_ddi_hot_plug;
1527 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1528 intel_dp_init_connector(intel_dig_port, dp_connector);