2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
28 * The order of pokes in the initiation sequence is based on Linux
29 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
30 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org)
31 * contributed towards power management.
34 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include <dev/sound/pcm/sound.h>
39 #include <dev/sound/pcm/ac97.h>
41 #include <bus/pci/pcireg.h>
42 #include <bus/pci/pcivar.h>
44 #include <dev/sound/pci/cs4281.h>
46 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cs4281.c 274035 2014-11-03 11:11:45Z bapt $");
48 #define CS4281_DEFAULT_BUFSZ 16384
50 /* Max fifo size for full duplex is 64 */
51 #define CS4281_FIFO_SIZE 15
53 /* DMA Engine Indices */
54 #define CS4281_DMA_PLAY 0
55 #define CS4281_DMA_REC 1
59 #define inline __inline
62 #define DEB(x) /* x */
65 /* ------------------------------------------------------------------------- */
70 /* channel registers */
72 struct sc_info *parent;
74 struct snd_dbuf *buffer;
75 struct pcm_channel *channel;
77 u_int32_t spd, fmt, bps, blksz;
79 int dma_setup, dma_active, dma_chan;
82 /* device private data */
88 bus_space_handle_t sh;
89 bus_dma_tag_t parent_dmat;
91 struct resource *reg, *irq, *mem;
92 int regtype, regid, irqid, memid;
101 /* -------------------------------------------------------------------- */
104 /* ADC/DAC control */
105 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
106 static void adcdac_prog(struct sc_chinfo *ch);
108 /* power management and interrupt control */
109 static void cs4281_intr(void *);
110 static int cs4281_power(struct sc_info *, int);
111 static int cs4281_init(struct sc_info *);
113 /* talk to the card */
114 static u_int32_t cs4281_rd(struct sc_info *, int);
115 static void cs4281_wr(struct sc_info *, int, u_int32_t);
118 static u_int8_t cs4281_rate_to_rv(u_int32_t);
119 static u_int32_t cs4281_format_to_dmr(u_int32_t);
120 static u_int32_t cs4281_format_to_bps(u_int32_t);
122 /* -------------------------------------------------------------------- */
123 /* formats (do not add formats without editing cs_fmt_tab) */
125 static u_int32_t cs4281_fmts[] = {
126 SND_FORMAT(AFMT_U8, 1, 0),
127 SND_FORMAT(AFMT_U8, 2, 0),
128 SND_FORMAT(AFMT_S8, 1, 0),
129 SND_FORMAT(AFMT_S8, 2, 0),
130 SND_FORMAT(AFMT_S16_LE, 1, 0),
131 SND_FORMAT(AFMT_S16_LE, 2, 0),
132 SND_FORMAT(AFMT_U16_LE, 1, 0),
133 SND_FORMAT(AFMT_U16_LE, 2, 0),
134 SND_FORMAT(AFMT_S16_BE, 1, 0),
135 SND_FORMAT(AFMT_S16_BE, 2, 0),
136 SND_FORMAT(AFMT_U16_BE, 1, 0),
137 SND_FORMAT(AFMT_U16_BE, 2, 0),
141 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
143 /* -------------------------------------------------------------------- */
146 static inline u_int32_t
147 cs4281_rd(struct sc_info *sc, int regno)
149 return bus_space_read_4(sc->st, sc->sh, regno);
153 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
155 bus_space_write_4(sc->st, sc->sh, regno, data);
160 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
163 r = cs4281_rd(sc, regno);
164 cs4281_wr(sc, regno, r & ~mask);
168 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
171 v = cs4281_rd(sc, regno);
172 cs4281_wr(sc, regno, v | mask);
176 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
182 v = cs4281_rd(sc, regno);
183 if ((v & mask) == mask) break;
190 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
196 v = ~ cs4281_rd(sc, regno);
203 /* ------------------------------------------------------------------------- */
204 /* Register value mapping functions */
206 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
207 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
210 cs4281_rate_to_rv(u_int32_t rate)
214 for (v = 0; v < CS4281_NUM_RATES; v++) {
215 if (rate == cs4281_rates[v]) return v;
219 if (v > 255 || v < 32) v = 5; /* default to 8k */
224 cs4281_rv_to_rate(u_int8_t rv)
228 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
233 static inline u_int32_t
234 cs4281_format_to_dmr(u_int32_t format)
237 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8;
238 if (AFMT_CHANNEL(format) < 2) dmr |= CS4281PCI_DMR_MONO;
239 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND;
240 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
244 static inline u_int32_t
245 cs4281_format_to_bps(u_int32_t format)
247 return ((AFMT_8BIT & format) ? 1 : 2) *
248 ((AFMT_CHANNEL(format) > 1) ? 2 : 1);
251 /* -------------------------------------------------------------------- */
255 cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
257 struct sc_info *sc = (struct sc_info *)devinfo;
260 codecno = regno >> 8;
263 /* Remove old state */
264 cs4281_rd(sc, CS4281PCI_ACSDA);
266 /* Fill in AC97 register value request form */
267 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
268 cs4281_wr(sc, CS4281PCI_ACCDA, 0);
269 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
270 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV |
271 CS4281PCI_ACCTL_CRW);
273 /* Wait for read to complete */
274 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
275 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
279 /* Wait for valid status */
280 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) {
281 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
285 return cs4281_rd(sc, CS4281PCI_ACSDA);
289 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
291 struct sc_info *sc = (struct sc_info *)devinfo;
294 codecno = regno >> 8;
297 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
298 cs4281_wr(sc, CS4281PCI_ACCDA, data);
299 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
300 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV);
302 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
303 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
309 static kobj_method_t cs4281_ac97_methods[] = {
310 KOBJMETHOD(ac97_read, cs4281_rdcd),
311 KOBJMETHOD(ac97_write, cs4281_wrcd),
314 AC97_DECLARE(cs4281_ac97);
316 /* ------------------------------------------------------------------------- */
317 /* shared rec/play channel interface */
320 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
322 struct sc_info *sc = devinfo;
323 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
326 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
332 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
333 ch->spd = DSP_DEFAULT_SPEED;
335 ch->blksz = sndbuf_getsize(ch->buffer);
337 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC;
347 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
349 struct sc_chinfo *ch = data;
350 struct sc_info *sc = ch->parent;
353 go = adcdac_go(ch, 0);
355 /* 2 interrupts are possible and used in buffer (half-empty,empty),
356 * hence factor of 2. */
357 ch->blksz = MIN(blocksize, sc->bufsz / 2);
358 sndbuf_resize(ch->buffer, 2, ch->blksz);
363 DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz));
369 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
371 struct sc_chinfo *ch = data;
372 struct sc_info *sc = ch->parent;
375 go = adcdac_go(ch, 0); /* pause */
376 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR;
377 v = cs4281_rate_to_rv(speed);
379 adcdac_go(ch, go); /* unpause */
381 ch->spd = cs4281_rv_to_rate(v);
386 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
388 struct sc_chinfo *ch = data;
389 struct sc_info *sc = ch->parent;
392 go = adcdac_go(ch, 0); /* pause */
394 if (ch->dma_chan == CS4281_DMA_PLAY)
395 v = CS4281PCI_DMR_TR_PLAY;
397 v = CS4281PCI_DMR_TR_REC;
398 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO;
399 v |= cs4281_format_to_dmr(format);
400 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v);
402 adcdac_go(ch, go); /* unpause */
405 ch->bps = cs4281_format_to_bps(format);
412 cs4281chan_getptr(kobj_t obj, void *data)
414 struct sc_chinfo *ch = data;
415 struct sc_info *sc = ch->parent;
416 u_int32_t dba, dca, ptr;
419 sz = sndbuf_getsize(ch->buffer);
420 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
421 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
422 ptr = (dca - dba + sz) % sz;
428 cs4281chan_trigger(kobj_t obj, void *data, int go)
430 struct sc_chinfo *ch = data;
449 static struct pcmchan_caps *
450 cs4281chan_getcaps(kobj_t obj, void *data)
455 static kobj_method_t cs4281chan_methods[] = {
456 KOBJMETHOD(channel_init, cs4281chan_init),
457 KOBJMETHOD(channel_setformat, cs4281chan_setformat),
458 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed),
459 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize),
460 KOBJMETHOD(channel_trigger, cs4281chan_trigger),
461 KOBJMETHOD(channel_getptr, cs4281chan_getptr),
462 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps),
465 CHANNEL_DECLARE(cs4281chan);
467 /* -------------------------------------------------------------------- */
468 /* ADC/DAC control */
470 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
471 * active before call */
474 adcdac_go(struct sc_chinfo *ch, u_int32_t go)
476 struct sc_info *sc = ch->parent;
479 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK);
482 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
484 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
486 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
492 adcdac_prog(struct sc_chinfo *ch)
494 struct sc_info *sc = ch->parent;
497 if (!ch->dma_setup) {
498 go = adcdac_go(ch, 0);
499 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan),
500 sndbuf_getbufaddr(ch->buffer));
501 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan),
502 sndbuf_getsize(ch->buffer) / ch->bps - 1);
508 /* -------------------------------------------------------------------- */
509 /* The interrupt handler */
514 struct sc_info *sc = (struct sc_info *)p;
517 hisr = cs4281_rd(sc, CS4281PCI_HISR);
519 if (hisr == 0) return;
521 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) {
522 chn_intr(sc->pch.channel);
523 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
526 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) {
527 chn_intr(sc->rch.channel);
528 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
531 /* Signal End-of-Interrupt */
532 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
535 /* -------------------------------------------------------------------- */
536 /* power management related */
539 cs4281_power(struct sc_info *sc, int state)
544 /* Permit r/w access to all BA0 registers */
545 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC);
547 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
550 /* Power off card and codec */
551 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
552 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
556 DEB(printf("cs4281_power %d -> %d\n", sc->power, state));
563 cs4281_init(struct sc_info *sc)
567 /* (0) Blast clock register and serial port */
568 cs4281_wr(sc, CS4281PCI_CLKCR1, 0);
569 cs4281_wr(sc, CS4281PCI_SERMC, 0);
571 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
572 cs4281_wr(sc, CS4281PCI_ACCTL, 0);
575 /* (2) Effect Reset */
576 cs4281_wr(sc, CS4281PCI_SPMC, 0);
578 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
579 /* Wait 50ms for ABITCLK to become stable */
582 /* (3) Enable Sound System Clocks */
583 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);
584 DELAY(50000); /* Wait for PLL to stabilize */
585 cs4281_wr(sc, CS4281PCI_CLKCR1,
586 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);
588 /* (4) Power Up - this combination is essential. */
589 cs4281_set4(sc, CS4281PCI_SSPM,
590 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |
591 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);
593 /* (5) Wait for clock stabilization */
594 if (cs4281_waitset(sc,
596 CS4281PCI_CLKCR1_DLLRDY,
598 device_printf(sc->dev, "Clock stabilization failed\n");
602 /* (6) Enable ASYNC generation. */
603 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);
605 /* Wait to allow AC97 to start generating clock bit */
608 /* Set AC97 timing */
609 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
611 /* (7) Wait for AC97 ready signal */
612 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {
613 device_printf(sc->dev, "codec did not avail\n");
617 /* (8) Assert valid frame signal to begin sending commands to
621 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);
623 /* (9) Wait for codec calibration */
624 for(i = 0 ; i < 1000; i++) {
626 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
627 if ((v & 0x0f) == 0x0f) {
632 device_printf(sc->dev, "codec failed to calibrate\n");
636 /* (10) Set AC97 timing */
637 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
639 /* (11) Wait for valid data to arrive */
640 if (cs4281_waitset(sc,
642 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),
644 device_printf(sc->dev, "cs4281 never got valid data\n");
648 /* (12) Start digital data transfer of audio data to codec */
651 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));
653 /* Set Master and headphone to max */
654 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0);
655 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
657 /* Power on the DAC */
658 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
659 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
661 /* Wait until DAC state ready */
662 for(i = 0; i < 320; i++) {
664 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
668 /* Power on the ADC */
669 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
670 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
672 /* Wait until ADC state ready */
673 for(i = 0; i < 320; i++) {
675 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
679 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
682 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) |
683 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) |
684 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
686 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v);
688 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN);
691 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) |
692 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) |
693 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
694 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1);
695 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH);
696 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN);
698 /* Match AC97 slots to FIFOs */
699 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) |
700 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) |
701 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) |
702 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT);
703 cs4281_wr(sc, CS4281PCI_SRCSA, v);
705 /* Set Auto-Initialize and set directions */
707 CS4281PCI_DMR(CS4281_DMA_PLAY),
710 CS4281PCI_DMR_TR_PLAY);
712 CS4281PCI_DMR(CS4281_DMA_REC),
715 CS4281PCI_DMR_TR_REC);
717 /* Enable half and empty buffer interrupts keeping DMA paused */
719 CS4281PCI_DCR(CS4281_DMA_PLAY),
720 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
722 CS4281PCI_DCR(CS4281_DMA_REC),
723 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
725 /* Enable Interrupts */
728 CS4281PCI_HIMR_DMAI |
729 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) |
730 CS4281PCI_HIMR_DMA(CS4281_DMA_REC));
732 /* Set playback volume */
733 cs4281_wr(sc, CS4281PCI_PPLVC, 7);
734 cs4281_wr(sc, CS4281PCI_PPRVC, 7);
739 /* -------------------------------------------------------------------- */
740 /* Probe and attach the card */
743 cs4281_pci_probe(device_t dev)
747 switch (pci_get_devid(dev)) {
749 s = "Crystal Semiconductor CS4281";
754 device_set_desc(dev, s);
755 return s ? BUS_PROBE_DEFAULT : ENXIO;
759 cs4281_pci_attach(device_t dev)
762 struct ac97_info *codec = NULL;
763 char status[SND_STATUSLEN];
765 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
767 sc->type = pci_get_devid(dev);
769 pci_enable_busmaster(dev);
771 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
772 /* Reset the power state. */
773 device_printf(dev, "chip is in D%d power mode "
774 "-- setting to D0\n", pci_get_powerstate(dev));
776 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
779 sc->regid = PCIR_BAR(0);
780 sc->regtype = SYS_RES_MEMORY;
781 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
782 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
784 sc->regtype = SYS_RES_IOPORT;
785 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
786 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
788 device_printf(dev, "unable to allocate register space\n");
792 sc->st = rman_get_bustag(sc->reg);
793 sc->sh = rman_get_bushandle(sc->reg);
795 sc->memid = PCIR_BAR(1);
796 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0,
797 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE);
798 if (sc->mem == NULL) {
799 device_printf(dev, "unable to allocate fifo space\n");
804 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
805 RF_ACTIVE | RF_SHAREABLE);
807 device_printf(dev, "unable to allocate interrupt\n");
811 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) {
812 device_printf(dev, "unable to setup interrupt\n");
816 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536);
818 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
820 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
821 /*highaddr*/BUS_SPACE_MAXADDR,
822 /*filter*/NULL, /*filterarg*/NULL,
823 /*maxsize*/sc->bufsz, /*nsegments*/1,
826 &sc->parent_dmat) != 0) {
827 device_printf(dev, "unable to create dma tag\n");
835 if (cs4281_init(sc) == -1) {
836 device_printf(dev, "unable to initialize the card\n");
840 /* create/init mixer */
841 codec = AC97_CREATE(dev, sc, cs4281_ac97);
845 mixer_init(dev, ac97_getmixerclass(), codec);
847 if (pcm_register(dev, sc, 1, 1))
850 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
851 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
853 ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
854 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
855 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281));
856 pcm_setstatus(dev, status);
864 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
866 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
868 bus_teardown_intr(dev, sc->irq, sc->ih);
870 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
872 bus_dma_tag_destroy(sc->parent_dmat);
879 cs4281_pci_detach(device_t dev)
884 r = pcm_unregister(dev);
888 sc = pcm_getdevinfo(dev);
893 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
894 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
895 bus_teardown_intr(dev, sc->irq, sc->ih);
896 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
897 bus_dma_tag_destroy(sc->parent_dmat);
904 cs4281_pci_suspend(device_t dev)
908 sc = pcm_getdevinfo(dev);
910 sc->rch.dma_active = adcdac_go(&sc->rch, 0);
911 sc->pch.dma_active = adcdac_go(&sc->pch, 0);
919 cs4281_pci_resume(device_t dev)
923 sc = pcm_getdevinfo(dev);
928 /* initialize chip */
929 if (cs4281_init(sc) == -1) {
930 device_printf(dev, "unable to reinitialize the card\n");
934 /* restore mixer state */
935 if (mixer_reinit(dev) == -1) {
936 device_printf(dev, "unable to reinitialize the mixer\n");
940 /* restore chip state */
941 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd);
942 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz);
943 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt);
944 adcdac_go(&sc->rch, sc->rch.dma_active);
946 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd);
947 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz);
948 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt);
949 adcdac_go(&sc->pch, sc->pch.dma_active);
954 static device_method_t cs4281_methods[] = {
955 /* Device interface */
956 DEVMETHOD(device_probe, cs4281_pci_probe),
957 DEVMETHOD(device_attach, cs4281_pci_attach),
958 DEVMETHOD(device_detach, cs4281_pci_detach),
959 DEVMETHOD(device_suspend, cs4281_pci_suspend),
960 DEVMETHOD(device_resume, cs4281_pci_resume),
964 static driver_t cs4281_driver = {
970 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0);
971 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
972 MODULE_VERSION(snd_cs4281, 1);