2 * Copyright (c) 1998, 1999 Takanori Watanabe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/pci/intpm.c,v 1.45 2009/09/19 08:56:28 avg Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <sys/globaldata.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
38 #include <sys/machintr.h>
39 #include <bus/smbus/smbconf.h>
43 #include <bus/pci/pcireg.h>
44 #include <bus/pci/pcivar.h>
45 #include <dev/powermng/intpm/intpmreg.h>
47 #include "opt_intpm.h"
51 struct resource *io_res;
52 struct resource *irq_res;
61 #define INTSMB_LOCK(sc) lockmgr(&(sc)->lock, LK_EXCLUSIVE)
62 #define INTSMB_UNLOCK(sc) lockmgr(&(sc)->lock, LK_RELEASE)
63 #define INTSMB_LOCK_ASSERT(sc) KKASSERT(lockstatus(&(sc)->lock, curthread) != 0)
65 static int intsmb_probe(device_t);
66 static int intsmb_attach(device_t);
67 static int intsmb_detach(device_t);
68 static int intsmb_intr(struct intsmb_softc *sc);
69 static int intsmb_slvintr(struct intsmb_softc *sc);
70 static void intsmb_alrintr(struct intsmb_softc *sc);
71 static int intsmb_callback(device_t dev, int index, void *data);
72 static int intsmb_quick(device_t dev, u_char slave, int how);
73 static int intsmb_sendb(device_t dev, u_char slave, char byte);
74 static int intsmb_recvb(device_t dev, u_char slave, char *byte);
75 static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte);
76 static int intsmb_writew(device_t dev, u_char slave, char cmd, short word);
77 static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte);
78 static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word);
79 static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata);
80 static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf);
81 static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf);
82 static void intsmb_start(struct intsmb_softc *sc, u_char cmd, int nointr);
83 static int intsmb_stop(struct intsmb_softc *sc);
84 static int intsmb_stop_poll(struct intsmb_softc *sc);
85 static int intsmb_free(struct intsmb_softc *sc);
86 static void intsmb_rawintr(void *arg);
89 intsmb_probe(device_t dev)
92 switch (pci_get_devid(dev)) {
93 case 0x71138086: /* Intel 82371AB */
94 case 0x719b8086: /* Intel 82443MX */
96 /* Not a good idea yet, this stops isab0 functioning */
97 case 0x02001166: /* ServerWorks OSB4 */
99 device_set_desc(dev, "Intel PIIX4 SMBUS Interface");
102 device_set_desc(dev, "AMD SB600/700/710/750 SMBus Controller");
103 /* XXX Maybe force polling right here? */
109 return (BUS_PROBE_DEFAULT);
113 intsmb_attach(device_t dev)
115 struct intsmb_softc *sc = device_get_softc(dev);
116 int error, rid, value;
122 lockinit(&sc->lock, "intsmb", 0, LK_CANRECURSE);
125 #ifndef NO_CHANGE_PCICONF
126 switch (pci_get_devid(dev)) {
127 case 0x71138086: /* Intel 82371AB */
128 case 0x719b8086: /* Intel 82443MX */
129 /* Changing configuration is allowed. */
135 rid = PCI_BASE_ADDR_SMB;
136 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
138 if (sc->io_res == NULL) {
139 device_printf(dev, "Could not allocate I/O space\n");
145 pci_write_config(dev, PCIR_INTLINE, 0x9, 1);
146 pci_write_config(dev, PCI_HST_CFG_SMB,
147 PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1);
149 value = pci_read_config(dev, PCI_HST_CFG_SMB, 1);
150 sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0;
151 intr = value & PCI_INTR_SMB_MASK;
153 case PCI_INTR_SMB_SMI:
156 case PCI_INTR_SMB_IRQ9:
159 case PCI_INTR_SMB_IRQ_PCI:
166 device_printf(dev, "intr %s %s ", str,
167 sc->poll == 0 ? "enabled" : "disabled");
168 kprintf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1));
170 if (!sc->poll && intr == PCI_INTR_SMB_SMI) {
172 "using polling mode when configured interrupt is SMI\n");
179 if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) {
180 device_printf(dev, "Unsupported interrupt mode\n");
188 bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1,
189 machintr_intr_cpuid(9));
192 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
193 RF_SHAREABLE | RF_ACTIVE);
194 if (sc->irq_res == NULL) {
195 device_printf(dev, "Could not allocate irq\n");
200 error = bus_setup_intr(dev, sc->irq_res, 0,
201 intsmb_rawintr, sc, &sc->irq_hand, NULL);
203 device_printf(dev, "Failed to map intr\n");
209 sc->smbus = device_add_child(dev, "smbus", -1);
210 if (sc->smbus == NULL) {
214 error = device_probe_and_attach(sc->smbus);
220 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
230 intsmb_detach(device_t dev)
232 struct intsmb_softc *sc = device_get_softc(dev);
235 error = bus_generic_detach(dev);
240 device_delete_child(dev, sc->smbus);
242 bus_teardown_intr(dev, sc->irq_res, sc->irq_hand);
244 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
246 bus_release_resource(dev, SYS_RES_IOPORT, PCI_BASE_ADDR_SMB,
248 lockuninit(&sc->lock);
253 intsmb_rawintr(void *arg)
255 struct intsmb_softc *sc = arg;
264 intsmb_callback(device_t dev, int index, void *data)
269 case SMB_REQUEST_BUS:
271 case SMB_RELEASE_BUS:
280 /* Counterpart of smbtx_smb_free(). */
282 intsmb_free(struct intsmb_softc *sc)
285 INTSMB_LOCK_ASSERT(sc);
286 if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
288 (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
294 /* Disable Interrupt in slave part. */
296 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
298 /* Reset INTR Flag to prepare INTR. */
299 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
300 PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
301 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL);
306 intsmb_intr(struct intsmb_softc *sc)
310 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
311 if (status & PIIX4_SMBHSTSTAT_BUSY)
314 if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
315 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) {
317 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
318 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
319 tmp & ~PIIX4_SMBHSTCNT_INTREN);
326 return (1); /* Not Completed */
330 intsmb_slvintr(struct intsmb_softc *sc)
334 status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS);
335 if (status & PIIX4_SMBSLVSTS_BUSY)
337 if (status & PIIX4_SMBSLVSTS_ALART)
339 else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2
340 | PIIX4_SMBSLVSTS_SDW1)) {
343 /* Reset Status Register */
344 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS,
345 PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 |
346 PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV);
351 intsmb_alrintr(struct intsmb_softc *sc)
359 /* Stop generating INTR from ALART. */
360 slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT);
362 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
363 slvcnt & ~PIIX4_SMBSLVCNT_ALTEN);
367 /* Ask bus who asserted it and then ask it what's the matter. */
369 error = intsmb_free(sc);
373 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB);
374 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1);
375 error = intsmb_stop_poll(sc);
377 device_printf(sc->dev, "ALART: ERROR\n");
379 addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
380 device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr);
383 /* Re-enable INTR from ALART. */
384 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
385 slvcnt | PIIX4_SMBSLVCNT_ALTEN);
391 intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr)
395 INTSMB_LOCK_ASSERT(sc);
396 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
399 tmp |= PIIX4_SMBHSTCNT_START;
401 /* While not in autoconfiguration enable interrupts. */
402 if (!sc->poll && !cold && !nointr)
403 tmp |= PIIX4_SMBHSTCNT_INTREN;
404 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
408 intsmb_error(device_t dev, int status)
412 if (status & PIIX4_SMBHSTSTAT_ERR)
413 error |= SMB_EBUSERR;
414 if (status & PIIX4_SMBHSTSTAT_BUSC)
416 if (status & PIIX4_SMBHSTSTAT_FAIL)
419 if (error != 0 && bootverbose)
420 device_printf(dev, "error = %d, status = %#x\n", error, status);
428 * Polling is not encouraged because it requires waiting for the
429 * device if it is busy.
430 * (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use
434 intsmb_stop_poll(struct intsmb_softc *sc)
436 int error, i, status, tmp;
438 INTSMB_LOCK_ASSERT(sc);
440 /* First, wait for busy to be set. */
441 for (i = 0; i < 0x7fff; i++)
442 if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) &
443 PIIX4_SMBHSTSTAT_BUSY)
446 /* Wait for busy to clear. */
447 for (i = 0; i < 0x7fff; i++) {
448 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
449 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
451 error = intsmb_error(sc->dev, status);
456 /* Timed out waiting for busy to clear. */
458 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
459 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
460 return (SMB_ETIMEOUT);
464 * Wait for completion and return result.
467 intsmb_stop(struct intsmb_softc *sc)
471 INTSMB_LOCK_ASSERT(sc);
473 if (sc->poll || cold)
474 /* So that it can use device during device probe on SMBus. */
475 return (intsmb_stop_poll(sc));
477 error = lksleep(sc, &sc->lock, PCATCH, "SMBWAI", hz / 8);
479 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
480 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
481 error = intsmb_error(sc->dev, status);
482 if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR))
483 device_printf(sc->dev, "unknown cause why?\n");
485 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
486 PIIX4_SMBSLVCNT_ALTEN);
492 /* Timeout Procedure. */
495 /* Re-enable supressed interrupt from slave part. */
496 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
497 if (error == EWOULDBLOCK)
498 return (SMB_ETIMEOUT);
504 intsmb_quick(device_t dev, u_char slave, int how)
506 struct intsmb_softc *sc = device_get_softc(dev);
512 /* Quick command is part of Address, I think. */
525 error = intsmb_free(sc);
530 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data);
531 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_QUICK, 0);
532 error = intsmb_stop(sc);
538 intsmb_sendb(device_t dev, u_char slave, char byte)
540 struct intsmb_softc *sc = device_get_softc(dev);
544 error = intsmb_free(sc);
549 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
550 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte);
551 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
552 error = intsmb_stop(sc);
558 intsmb_recvb(device_t dev, u_char slave, char *byte)
560 struct intsmb_softc *sc = device_get_softc(dev);
564 error = intsmb_free(sc);
569 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
570 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
571 error = intsmb_stop(sc);
573 #ifdef RECV_IS_IN_CMD
575 * Linux SMBus stuff also troubles
576 * Because Intel's datasheet does not make clear.
578 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD);
580 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
588 intsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
590 struct intsmb_softc *sc = device_get_softc(dev);
594 error = intsmb_free(sc);
599 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
600 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
601 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte);
602 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
603 error = intsmb_stop(sc);
609 intsmb_writew(device_t dev, u_char slave, char cmd, short word)
611 struct intsmb_softc *sc = device_get_softc(dev);
615 error = intsmb_free(sc);
620 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
621 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
622 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff);
623 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff);
624 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
625 error = intsmb_stop(sc);
631 intsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
633 struct intsmb_softc *sc = device_get_softc(dev);
637 error = intsmb_free(sc);
642 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
643 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
644 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
645 error = intsmb_stop(sc);
647 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
653 intsmb_readw(device_t dev, u_char slave, char cmd, short *word)
655 struct intsmb_softc *sc = device_get_softc(dev);
659 error = intsmb_free(sc);
664 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
665 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
666 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
667 error = intsmb_stop(sc);
669 *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
670 *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
677 * Data sheet claims that it implements all function, but also claims
678 * that it implements 7 function and not mention PCALL. So I don't know
679 * whether it will work.
682 intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
685 struct intsmb_softc *sc = device_get_softc(dev);
689 error = intsmb_free(sc);
694 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
695 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
696 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, sdata & 0xff);
697 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (sdata & 0xff) >> 8);
698 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
699 error = intsmb_stop(sc);
701 *rdata = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
702 *rdata |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
707 return (SMB_ENOTSUPP);
712 intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
714 struct intsmb_softc *sc = device_get_softc(dev);
717 if (count > SMBBLOCKTRANS_MAX || count == 0)
721 error = intsmb_free(sc);
727 /* Reset internal array index. */
728 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
730 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
731 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
732 for (i = 0; i < count; i++)
733 bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]);
734 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count);
735 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
736 error = intsmb_stop(sc);
742 intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
744 struct intsmb_softc *sc = device_get_softc(dev);
748 if (*count > SMBBLOCKTRANS_MAX || *count == 0)
752 error = intsmb_free(sc);
758 /* Reset internal array index. */
759 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
761 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
762 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
763 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, *count);
764 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
765 error = intsmb_stop(sc);
767 nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
768 if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) {
769 for (i = 0; i < nread; i++) {
770 data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT);
782 static devclass_t intsmb_devclass;
784 static device_method_t intsmb_methods[] = {
785 /* Device interface */
786 DEVMETHOD(device_probe, intsmb_probe),
787 DEVMETHOD(device_attach, intsmb_attach),
788 DEVMETHOD(device_detach, intsmb_detach),
791 DEVMETHOD(bus_print_child, bus_generic_print_child),
793 /* SMBus interface */
794 DEVMETHOD(smbus_callback, intsmb_callback),
795 DEVMETHOD(smbus_quick, intsmb_quick),
796 DEVMETHOD(smbus_sendb, intsmb_sendb),
797 DEVMETHOD(smbus_recvb, intsmb_recvb),
798 DEVMETHOD(smbus_writeb, intsmb_writeb),
799 DEVMETHOD(smbus_writew, intsmb_writew),
800 DEVMETHOD(smbus_readb, intsmb_readb),
801 DEVMETHOD(smbus_readw, intsmb_readw),
802 DEVMETHOD(smbus_pcall, intsmb_pcall),
803 DEVMETHOD(smbus_bwrite, intsmb_bwrite),
804 DEVMETHOD(smbus_bread, intsmb_bread),
809 static driver_t intsmb_driver = {
812 sizeof(struct intsmb_softc),
815 DRIVER_MODULE(intsmb, pci, intsmb_driver, intsmb_devclass, NULL, NULL);
816 DRIVER_MODULE(smbus, intsmb, smbus_driver, smbus_devclass, NULL, NULL);
817 MODULE_DEPEND(intsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
818 MODULE_VERSION(intsmb, 1);