2 * Copyright (c) 2000-2004 Taku YAMAMOTO <taku@tackymt.homeip.net>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * maestro.c,v 1.23.2.1 2003/10/03 18:21:38 taku Exp
27 * $FreeBSD: src/sys/dev/sound/pci/maestro.c,v 1.28.2.3 2006/02/04 11:58:28 netchild Exp $
33 * Part of this code (especially in many magic numbers) was heavily inspired
34 * by the Linux driver originally written by
35 * Alan Cox <alan.cox@linux.org>, modified heavily by
36 * Zach Brown <zab@zabbo.net>.
38 * busdma()-ize and buffer size reduction were suggested by
39 * Cameron Grant <cg@freebsd.org>.
40 * Also he showed me the way to use busdma() suite.
42 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
44 * Munehiro Matsuda <haro@tk.kubota.co.jp>,
45 * who brought patches based on the Linux driver with some simplification.
47 * Hardware volume controller was implemented by
48 * John Baldwin <jhb@freebsd.org>.
51 #include <dev/sound/pcm/sound.h>
52 #include <dev/sound/pcm/ac97.h>
53 #include <bus/pci/pcireg.h>
54 #include <bus/pci/pcivar.h>
56 #include <dev/sound/pci/maestro_reg.h>
58 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/maestro.c,v 1.10 2007/06/16 20:07:19 dillon Exp $");
61 #define inline __inline
64 * PCI IDs of supported chips:
66 * MAESTRO-1 0x01001285
67 * MAESTRO-2 0x1968125d
68 * MAESTRO-2E 0x1978125d
71 #define MAESTRO_1_PCI_ID 0x01001285
72 #define MAESTRO_2_PCI_ID 0x1968125d
73 #define MAESTRO_2E_PCI_ID 0x1978125d
75 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
76 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
79 # if AGG_MAXPLAYCH > 4
81 # define AGG_MAXPLAYCH 4
84 # define AGG_MAXPLAYCH 4
87 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
91 # define critical_enter() crit_enter()
92 # define critical_exit() crit_exit()
95 #define PCIR_BAR(x) (PCIR_MAPS + (x) * 4)
99 /* -----------------------------
104 struct agg_info *parent;
106 /* FreeBSD newpcm related */
107 struct pcm_channel *channel;
108 struct snd_dbuf *buffer;
111 bus_addr_t phys; /* channel buffer physical address */
112 bus_addr_t base; /* channel buffer segment base */
113 u_int32_t blklen; /* DMA block length in WORDs */
114 u_int32_t buflen; /* channel buffer length in WORDs */
118 unsigned qs16 : 1; /* quantum size is 16bit */
119 unsigned us : 1; /* in unsigned format */
124 struct agg_info *parent;
126 /* FreeBSD newpcm related */
127 struct pcm_channel *channel;
128 struct snd_dbuf *buffer;
131 bus_addr_t phys; /* channel buffer physical address */
132 bus_addr_t base; /* channel buffer segment base */
133 u_int32_t blklen; /* DMA block length in WORDs */
134 u_int32_t buflen; /* channel buffer length in WORDs */
139 int16_t *src; /* stereo peer buffer */
140 int16_t *sink; /* channel buffer pointer */
141 volatile u_int32_t hwptr; /* ready point in 16bit sample */
145 /* FreeBSD newbus related */
148 /* I wonder whether bus_space_* are in common in *BSD... */
149 struct resource *reg;
152 bus_space_handle_t sh;
154 struct resource *irq;
158 bus_dma_tag_t buf_dmat;
159 bus_dma_tag_t stat_dmat;
161 /* FreeBSD SMPng related */
165 /* FreeBSD newpcm related */
166 struct ac97_info *codec;
169 u_int8_t *stat; /* status buffer pointer */
170 bus_addr_t phys; /* status buffer physical address */
171 unsigned int bufsz; /* channel buffer size in bytes */
173 volatile u_int active;
174 struct agg_chinfo pch[AGG_MAXPLAYCH];
175 struct agg_rchinfo rch;
176 volatile u_int8_t curpwr; /* current power status: D[0-3] */
180 /* -----------------------------
183 static unsigned int powerstate_active = PCI_POWERSTATE_D1;
184 #ifdef MAESTRO_AGGRESSIVE_POWERSAVE
185 static unsigned int powerstate_idle = PCI_POWERSTATE_D2;
187 static unsigned int powerstate_idle = PCI_POWERSTATE_D1;
189 static unsigned int powerstate_init = PCI_POWERSTATE_D2;
191 SYSCTL_NODE(_debug, OID_AUTO, maestro, CTLFLAG_RD, 0, "");
192 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_active, CTLFLAG_RW,
193 &powerstate_active, 0, "The Dx power state when active (0-1)");
194 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_idle, CTLFLAG_RW,
195 &powerstate_idle, 0, "The Dx power state when idle (0-2)");
196 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_init, CTLFLAG_RW,
197 &powerstate_init, 0, "The Dx power state prior to the first use (0-2)");
200 /* -----------------------------
204 static inline void agg_lock(struct agg_info*);
205 static inline void agg_unlock(struct agg_info*);
206 static inline void agg_sleep(struct agg_info*, const char *wmesg, int msec);
208 static inline u_int32_t agg_rd(struct agg_info*, int, int size);
209 static inline void agg_wr(struct agg_info*, int, u_int32_t data, int size);
211 static inline int agg_rdcodec(struct agg_info*, int);
212 static inline int agg_wrcodec(struct agg_info*, int, u_int32_t);
214 static inline void ringbus_setdest(struct agg_info*, int, int);
216 static inline u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
217 static inline void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
218 static inline u_int16_t wp_rdapu(struct agg_info*, unsigned, u_int16_t);
219 static inline void wp_wrapu(struct agg_info*, unsigned, u_int16_t, u_int16_t);
220 static inline void wp_settimer(struct agg_info*, u_int);
221 static inline void wp_starttimer(struct agg_info*);
222 static inline void wp_stoptimer(struct agg_info*);
224 static inline u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
225 static inline void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
226 static inline u_int16_t wc_rdchctl(struct agg_info*, int);
227 static inline void wc_wrchctl(struct agg_info*, int, u_int16_t);
229 static inline void agg_stopclock(struct agg_info*, int part, int st);
231 static inline void agg_initcodec(struct agg_info*);
232 static void agg_init(struct agg_info*);
233 static void agg_power(struct agg_info*, int);
235 static void aggch_start_dac(struct agg_chinfo*);
236 static void aggch_stop_dac(struct agg_chinfo*);
237 static void aggch_start_adc(struct agg_rchinfo*);
238 static void aggch_stop_adc(struct agg_rchinfo*);
239 static void aggch_feed_adc_stereo(struct agg_rchinfo*);
240 static void aggch_feed_adc_mono(struct agg_rchinfo*);
242 static inline void suppress_jitter(struct agg_chinfo*);
243 static inline void suppress_rec_jitter(struct agg_rchinfo*);
245 static void set_timer(struct agg_info*);
247 static void agg_intr(void *);
248 static int agg_probe(device_t);
249 static int agg_attach(device_t);
250 static int agg_detach(device_t);
251 static int agg_suspend(device_t);
252 static int agg_resume(device_t);
253 static int agg_shutdown(device_t);
255 static void *dma_malloc(bus_dma_tag_t, u_int32_t, bus_addr_t*);
256 static void dma_free(bus_dma_tag_t, void *);
259 /* -----------------------------
266 agg_lock(struct agg_info *sc)
269 snd_mtxlock(sc->lock);
274 agg_unlock(struct agg_info *sc)
277 snd_mtxunlock(sc->lock);
282 agg_sleep(struct agg_info *sc, const char *wmesg, int msec)
286 timo = msec * hz / 1000;
290 snd_mtxsleep(sc, sc->lock, 0, wmesg, timo);
292 tsleep(sc, PWAIT, wmesg, timo);
299 static inline u_int32_t
300 agg_rd(struct agg_info *sc, int regno, int size)
304 return bus_space_read_1(sc->st, sc->sh, regno);
306 return bus_space_read_2(sc->st, sc->sh, regno);
308 return bus_space_read_4(sc->st, sc->sh, regno);
310 return ~(u_int32_t)0;
314 #define AGG_RD(sc, regno, size) \
315 bus_space_read_##size( \
316 ((struct agg_info*)(sc))->st, \
317 ((struct agg_info*)(sc))->sh, (regno))
320 agg_wr(struct agg_info *sc, int regno, u_int32_t data, int size)
324 bus_space_write_1(sc->st, sc->sh, regno, data);
327 bus_space_write_2(sc->st, sc->sh, regno, data);
330 bus_space_write_4(sc->st, sc->sh, regno, data);
335 #define AGG_WR(sc, regno, data, size) \
336 bus_space_write_##size( \
337 ((struct agg_info*)(sc))->st, \
338 ((struct agg_info*)(sc))->sh, (regno), (data))
340 /* -------------------------------------------------------------------- */
345 agg_codec_wait4idle(struct agg_info *ess)
349 while (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) {
352 DELAY(2); /* 20.8us / 13 */
359 agg_rdcodec(struct agg_info *ess, int regno)
363 /* We have to wait for a SAFE time to write addr/data */
364 if (agg_codec_wait4idle(ess)) {
365 /* Timed out. No read performed. */
366 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
370 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
371 /*DELAY(21); * AC97 cycle = 20.8usec */
373 /* Wait for data retrieve */
374 if (!agg_codec_wait4idle(ess)) {
375 ret = AGG_RD(ess, PORT_CODEC_REG, 2);
377 /* Timed out. No read performed. */
378 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
386 agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data)
388 /* We have to wait for a SAFE time to write addr/data */
389 if (agg_codec_wait4idle(ess)) {
390 /* Timed out. Abort writing. */
391 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
395 AGG_WR(ess, PORT_CODEC_REG, data, 2);
396 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
398 /* Wait for write completion */
399 if (agg_codec_wait4idle(ess)) {
401 device_printf(ess->dev, "agg_wrcodec() RW_DONE timed out.\n");
409 ringbus_setdest(struct agg_info *ess, int src, int dest)
413 data = AGG_RD(ess, PORT_RINGBUS_CTRL, 4);
414 data &= ~(0xfU << src);
415 data |= (0xfU & dest) << src;
416 AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
419 /* -------------------------------------------------------------------- */
423 static inline u_int16_t
424 wp_rdreg(struct agg_info *ess, u_int16_t reg)
426 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
427 return AGG_RD(ess, PORT_DSP_DATA, 2);
431 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
433 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
434 AGG_WR(ess, PORT_DSP_DATA, data, 2);
438 wp_wait_data(struct agg_info *ess, u_int16_t data)
442 while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
446 AGG_WR(ess, PORT_DSP_DATA, data, 2);
452 static inline u_int16_t
453 wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)
455 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
456 if (wp_wait_data(ess, reg | (ch << 4)) != 0)
457 device_printf(ess->dev, "wp_rdapu() indexing timed out.\n");
458 return wp_rdreg(ess, WPREG_DATA_PORT);
462 wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)
464 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
465 if (wp_wait_data(ess, reg | (ch << 4)) == 0) {
466 wp_wrreg(ess, WPREG_DATA_PORT, data);
467 if (wp_wait_data(ess, data) != 0)
468 device_printf(ess->dev, "wp_wrapu() write timed out.\n");
470 device_printf(ess->dev, "wp_wrapu() indexing timed out.\n");
475 apu_setparam(struct agg_info *ess, int apuch,
476 u_int32_t wpwa, u_int16_t size, int16_t pan, u_int dv)
478 wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK);
479 wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa);
480 wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size);
481 wp_wrapu(ess, apuch, APUREG_LOOPLEN, size);
482 wp_wrapu(ess, apuch, APUREG_ROUTING, 0);
483 wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000);
484 wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00
485 | (APU_RADIUS_MASK & (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT))
486 | (APU_PAN_MASK & ((pan + PAN_FRONT) << APU_PAN_SHIFT)));
487 wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE,
488 APU_plus6dB | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
489 wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8);
493 wp_settimer(struct agg_info *ess, u_int divide)
497 RANGE(divide, 2, 32 << 7);
499 for (; divide > 32; divide >>= 1) {
504 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
507 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
508 wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 |
509 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
510 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
514 wp_starttimer(struct agg_info *ess)
516 AGG_WR(ess, PORT_INT_STAT, 1, 2);
517 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
518 | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
519 wp_wrreg(ess, WPREG_TIMER_START, 1);
523 wp_stoptimer(struct agg_info *ess)
525 AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
526 & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
527 AGG_WR(ess, PORT_INT_STAT, 1, 2);
528 wp_wrreg(ess, WPREG_TIMER_START, 0);
531 /* -------------------------------------------------------------------- */
535 static inline u_int16_t
536 wc_rdreg(struct agg_info *ess, u_int16_t reg)
538 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
539 return AGG_RD(ess, PORT_WAVCACHE_DATA, 2);
543 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
545 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
546 AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
549 static inline u_int16_t
550 wc_rdchctl(struct agg_info *ess, int ch)
552 return wc_rdreg(ess, ch << 3);
556 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
558 wc_wrreg(ess, ch << 3, data);
561 /* -------------------------------------------------------------------- */
563 /* Power management */
565 agg_stopclock(struct agg_info *ess, int part, int st)
569 data = pci_read_config(ess->dev, CONF_ACPI_STOPCLOCK, 4);
571 if (st == PCI_POWERSTATE_D1)
572 data &= ~(1 << part);
575 if (st == PCI_POWERSTATE_D1 || st == PCI_POWERSTATE_D2)
576 data |= (0x10000 << part);
578 data &= ~(0x10000 << part);
579 pci_write_config(ess->dev, CONF_ACPI_STOPCLOCK, data, 4);
584 /* -----------------------------
589 agg_initcodec(struct agg_info* ess)
593 if (AGG_RD(ess, PORT_RINGBUS_CTRL, 4) & RINGBUS_CTRL_ACLINK_ENABLED) {
594 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
595 DELAY(104); /* 20.8us * (4 + 1) */
597 /* XXX - 2nd codec should be looked at. */
598 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
600 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
603 if (agg_rdcodec(ess, 0) < 0) {
604 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
607 /* Try cold reset. */
608 device_printf(ess->dev, "will perform cold reset.\n");
609 data = AGG_RD(ess, PORT_GPIO_DIR, 2);
610 if (pci_read_config(ess->dev, 0x58, 2) & 1)
612 data |= 0x009 & ~AGG_RD(ess, PORT_GPIO_DATA, 2);
613 AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
614 AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
615 AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
617 AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
619 AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
620 agg_sleep(ess, "agginicd", 500);
621 AGG_WR(ess, PORT_GPIO_DIR, data, 2);
622 DELAY(84); /* 20.8us * 4 */
623 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
629 agg_init(struct agg_info* ess)
633 /* Setup PCI config registers. */
635 /* Disable all legacy emulations. */
636 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
637 data |= LEGACY_DISABLED;
638 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
640 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
641 * Enable posted write.
642 * Prefer PCI timing rather than that of ISA.
644 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
646 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
647 data &= ~MAESTRO_SWAP_LR;
648 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
650 /* Turn off unused parts if necessary. */
651 /* consult CONF_MAESTRO. */
652 if (data & MAESTRO_SPDIF)
653 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D2);
655 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D1);
656 if (data & MAESTRO_HWVOL)
657 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D3);
659 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D1);
661 /* parts that never be used */
662 agg_stopclock(ess, ACPI_PART_978, PCI_POWERSTATE_D1);
663 agg_stopclock(ess, ACPI_PART_DAA, PCI_POWERSTATE_D1);
664 agg_stopclock(ess, ACPI_PART_GPIO, PCI_POWERSTATE_D1);
665 agg_stopclock(ess, ACPI_PART_SB, PCI_POWERSTATE_D1);
666 agg_stopclock(ess, ACPI_PART_FM, PCI_POWERSTATE_D1);
667 agg_stopclock(ess, ACPI_PART_MIDI, PCI_POWERSTATE_D1);
668 agg_stopclock(ess, ACPI_PART_GAME_PORT, PCI_POWERSTATE_D1);
670 /* parts that will be used only when play/recording */
671 agg_stopclock(ess, ACPI_PART_WP, PCI_POWERSTATE_D2);
673 /* parts that should always be turned on */
674 agg_stopclock(ess, ACPI_PART_CODEC_CLOCK, PCI_POWERSTATE_D3);
675 agg_stopclock(ess, ACPI_PART_GLUE, PCI_POWERSTATE_D3);
676 agg_stopclock(ess, ACPI_PART_PCI_IF, PCI_POWERSTATE_D3);
677 agg_stopclock(ess, ACPI_PART_RINGBUS, PCI_POWERSTATE_D3);
679 /* Reset direct sound. */
680 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
682 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
684 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
686 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
689 /* Enable hardware volume control interruption. */
690 if (data & MAESTRO_HWVOL) /* XXX - why not use device flags? */
691 AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
693 /* Setup Wave Processor. */
695 /* Enable WaveCache, set DMA base address. */
696 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
697 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
698 wp_wrreg(ess, WPREG_CRAM_DATA, 0);
700 AGG_WR(ess, PORT_WAVCACHE_CTRL,
701 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_2MB | WAVCACHE_SGC_32_47, 2);
703 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
704 wc_wrreg(ess, data, ess->phys >> WAVCACHE_BASEADDR_SHIFT);
706 /* Setup Codec/Ringbus. */
708 AGG_WR(ess, PORT_RINGBUS_CTRL,
709 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED, 4);
711 wp_wrreg(ess, 0x08, 0xB004);
712 wp_wrreg(ess, 0x09, 0x001B);
713 wp_wrreg(ess, 0x0A, 0x8000);
714 wp_wrreg(ess, 0x0B, 0x3F37);
715 wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
716 wp_wrreg(ess, WPREG_BASE + 1, 0x7632);
717 ringbus_setdest(ess, RINGBUS_SRC_ADC,
718 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
719 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
720 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
722 /* Enable S/PDIF if necessary. */
723 if (pci_read_config(ess->dev, CONF_MAESTRO, 4) & MAESTRO_SPDIF)
724 /* XXX - why not use device flags? */
725 AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
726 AGG_RD(ess, PORT_RINGBUS_CTRL_B, 1), 1);
728 /* Setup ASSP. Needed for Dell Inspiron 7500? */
729 AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
730 AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
731 AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
735 * There seems to be speciality with NEC systems.
737 switch (pci_get_subvendor(ess->dev)
738 | (pci_get_subdevice(ess->dev) << 16)) {
741 /* Matthew Braithwaite <matt@braithwaite.net> reported that
742 * NEC Versa LX doesn't need GPIO operation. */
743 AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
744 AGG_WR(ess, PORT_GPIO_DIR,
745 AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2);
746 AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
751 /* Deals power state transition. Must be called with softc->lock held. */
753 agg_power(struct agg_info *ess, int status)
757 lastpwr = ess->curpwr;
758 if (lastpwr == status)
762 case PCI_POWERSTATE_D0:
763 case PCI_POWERSTATE_D1:
765 case PCI_POWERSTATE_D2:
766 pci_set_powerstate(ess->dev, status);
767 /* Turn on PCM-related parts. */
768 agg_wrcodec(ess, AC97_REG_POWER, 0);
771 if ((agg_rdcodec(ess, AC97_REG_POWER) & 3) != 3)
772 device_printf(ess->dev, "warning: codec not ready.\n");
774 AGG_WR(ess, PORT_RINGBUS_CTRL,
775 (AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
776 & ~RINGBUS_CTRL_ACLINK_ENABLED)
777 | RINGBUS_CTRL_RINGBUS_ENABLED, 4);
779 AGG_WR(ess, PORT_RINGBUS_CTRL,
780 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
781 | RINGBUS_CTRL_ACLINK_ENABLED, 4);
783 case PCI_POWERSTATE_D3:
785 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
789 case PCI_POWERSTATE_D0:
790 case PCI_POWERSTATE_D1:
791 pci_set_powerstate(ess->dev, status);
795 case PCI_POWERSTATE_D2:
797 case PCI_POWERSTATE_D3:
799 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
803 case PCI_POWERSTATE_D0:
804 case PCI_POWERSTATE_D1:
805 /* Turn off PCM-related parts. */
806 AGG_WR(ess, PORT_RINGBUS_CTRL,
807 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
808 & ~RINGBUS_CTRL_RINGBUS_ENABLED, 4);
810 agg_wrcodec(ess, AC97_REG_POWER, 0x300);
814 pci_set_powerstate(ess->dev, status);
816 case PCI_POWERSTATE_D3:
817 /* Entirely power down. */
818 agg_wrcodec(ess, AC97_REG_POWER, 0xdf00);
820 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
822 if (lastpwr != PCI_POWERSTATE_D2)
824 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
825 AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);
826 pci_set_powerstate(ess->dev, status);
829 /* Invalid power state; let it ignored. */
834 ess->curpwr = status;
837 /* -------------------------------------------------------------------- */
839 /* Channel controller. */
842 aggch_start_dac(struct agg_chinfo *ch)
846 u_int16_t size, apuch, wtbar, wcreg, aputype;
851 wpwa = (ch->phys - ch->base) >> 1;
852 wtbar = 0xc & (wpwa >> WPWA_WTBAR_SHIFT(2));
853 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
855 apuch = (ch->num << 1) | 32;
856 pan = PAN_RIGHT - PAN_FRONT;
859 wcreg |= WAVCACHE_CHCTL_STEREO;
861 aputype = APUTYPE_16BITSTEREO;
866 aputype = APUTYPE_8BITSTEREO;
870 aputype = APUTYPE_16BITLINEAR;
872 aputype = APUTYPE_8BITLINEAR;
877 wcreg |= WAVCACHE_CHCTL_U8;
880 wtbar = (wtbar >> 1) + 4;
882 dv = (((speed % 48000) << 16) + 24000) / 48000
883 + ((speed / 48000) << 16);
885 agg_lock(ch->parent);
886 agg_power(ch->parent, powerstate_active);
888 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar,
889 ch->base >> WAVCACHE_BASEADDR_SHIFT);
890 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 1,
891 ch->base >> WAVCACHE_BASEADDR_SHIFT);
893 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 2,
894 ch->base >> WAVCACHE_BASEADDR_SHIFT);
895 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 3,
896 ch->base >> WAVCACHE_BASEADDR_SHIFT);
898 wc_wrchctl(ch->parent, apuch, wcreg);
899 wc_wrchctl(ch->parent, apuch + 1, wcreg);
901 apu_setparam(ch->parent, apuch, wpwa, size, pan, dv);
904 wpwa |= (WPWA_STEREO >> 1);
905 apu_setparam(ch->parent, apuch + 1, wpwa, size, -pan, dv);
908 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
909 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
910 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
911 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
914 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
915 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
918 /* to mark that this channel is ready for intr. */
919 ch->parent->active |= (1 << ch->num);
921 set_timer(ch->parent);
922 wp_starttimer(ch->parent);
923 agg_unlock(ch->parent);
927 aggch_stop_dac(struct agg_chinfo *ch)
929 agg_lock(ch->parent);
931 /* to mark that this channel no longer needs further intrs. */
932 ch->parent->active &= ~(1 << ch->num);
934 wp_wrapu(ch->parent, (ch->num << 1) | 32, APUREG_APUTYPE,
935 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
936 wp_wrapu(ch->parent, (ch->num << 1) | 33, APUREG_APUTYPE,
937 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
939 if (ch->parent->active) {
940 set_timer(ch->parent);
941 wp_starttimer(ch->parent);
943 wp_stoptimer(ch->parent);
944 agg_power(ch->parent, powerstate_idle);
946 agg_unlock(ch->parent);
950 aggch_start_adc(struct agg_rchinfo *ch)
952 bus_addr_t wpwa, wpwa2;
953 u_int16_t wcreg, wcreg2;
957 /* speed > 48000 not cared */
958 dv = ((ch->speed << 16) + 24000) / 48000;
960 /* RATECONV doesn't seem to like dv == 0x10000. */
965 wpwa = (ch->srcphys - ch->base) >> 1;
966 wpwa2 = (ch->srcphys + ch->parent->bufsz/2 - ch->base) >> 1;
967 wcreg = (ch->srcphys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
968 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
969 pan = PAN_LEFT - PAN_FRONT;
971 wpwa = (ch->phys - ch->base) >> 1;
972 wpwa2 = (ch->srcphys - ch->base) >> 1;
973 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
974 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
978 agg_lock(ch->parent);
981 agg_power(ch->parent, powerstate_active);
983 /* Invalidate WaveCache. */
984 wc_wrchctl(ch->parent, 0, wcreg | WAVCACHE_CHCTL_STEREO);
985 wc_wrchctl(ch->parent, 1, wcreg | WAVCACHE_CHCTL_STEREO);
986 wc_wrchctl(ch->parent, 2, wcreg2 | WAVCACHE_CHCTL_STEREO);
987 wc_wrchctl(ch->parent, 3, wcreg2 | WAVCACHE_CHCTL_STEREO);
989 /* Load APU registers. */
990 /* APU #0 : Sample rate converter for left/center. */
991 apu_setparam(ch->parent, 0, WPWA_USE_SYSMEM | wpwa,
992 ch->buflen >> ch->stereo, 0, dv);
993 wp_wrapu(ch->parent, 0, APUREG_AMPLITUDE, 0);
994 wp_wrapu(ch->parent, 0, APUREG_ROUTING, 2 << APU_DATASRC_A_SHIFT);
996 /* APU #1 : Sample rate converter for right. */
997 apu_setparam(ch->parent, 1, WPWA_USE_SYSMEM | wpwa2,
998 ch->buflen >> ch->stereo, 0, dv);
999 wp_wrapu(ch->parent, 1, APUREG_AMPLITUDE, 0);
1000 wp_wrapu(ch->parent, 1, APUREG_ROUTING, 3 << APU_DATASRC_A_SHIFT);
1002 /* APU #2 : Input mixer for left. */
1003 apu_setparam(ch->parent, 2, WPWA_USE_SYSMEM | 0,
1004 ch->parent->bufsz >> 2, pan, 0x10000);
1005 wp_wrapu(ch->parent, 2, APUREG_AMPLITUDE, 0);
1006 wp_wrapu(ch->parent, 2, APUREG_EFFECT_GAIN, 0xf0);
1007 wp_wrapu(ch->parent, 2, APUREG_ROUTING, 0x15 << APU_DATASRC_A_SHIFT);
1009 /* APU #3 : Input mixer for right. */
1010 apu_setparam(ch->parent, 3, WPWA_USE_SYSMEM | (ch->parent->bufsz >> 2),
1011 ch->parent->bufsz >> 2, -pan, 0x10000);
1012 wp_wrapu(ch->parent, 3, APUREG_AMPLITUDE, 0);
1013 wp_wrapu(ch->parent, 3, APUREG_EFFECT_GAIN, 0xf0);
1014 wp_wrapu(ch->parent, 3, APUREG_ROUTING, 0x14 << APU_DATASRC_A_SHIFT);
1016 /* to mark this channel ready for intr. */
1017 ch->parent->active |= (1 << ch->parent->playchns);
1021 wp_wrapu(ch->parent, 0, APUREG_APUTYPE,
1022 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1023 wp_wrapu(ch->parent, 1, APUREG_APUTYPE,
1024 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1025 wp_wrapu(ch->parent, 2, APUREG_APUTYPE,
1026 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1027 wp_wrapu(ch->parent, 3, APUREG_APUTYPE,
1028 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1031 set_timer(ch->parent);
1032 wp_starttimer(ch->parent);
1033 agg_unlock(ch->parent);
1037 aggch_stop_adc(struct agg_rchinfo *ch)
1041 agg_lock(ch->parent);
1043 /* to mark that this channel no longer needs further intrs. */
1044 ch->parent->active &= ~(1 << ch->parent->playchns);
1046 for (apuch = 0; apuch < 4; apuch++)
1047 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
1048 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1050 if (ch->parent->active) {
1051 set_timer(ch->parent);
1052 wp_starttimer(ch->parent);
1054 wp_stoptimer(ch->parent);
1055 agg_power(ch->parent, powerstate_idle);
1057 agg_unlock(ch->parent);
1061 * Feed from L/R channel of ADC to destination with stereo interleaving.
1062 * This function expects n not overwrapping the buffer boundary.
1063 * Note that n is measured in sample unit.
1065 * XXX - this function works in 16bit stereo format only.
1068 interleave(int16_t *l, int16_t *r, int16_t *p, unsigned n)
1072 for (end = l + n; l < end; ) {
1079 aggch_feed_adc_stereo(struct agg_rchinfo *ch)
1084 agg_lock(ch->parent);
1085 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1086 agg_unlock(ch->parent);
1087 cur -= 0xffff & ((ch->srcphys - ch->base) >> 1);
1089 src2 = ch->src + ch->parent->bufsz/4;
1092 interleave(ch->src + last, src2 + last,
1093 ch->sink + 2*last, ch->buflen/2 - last);
1094 interleave(ch->src, src2,
1096 } else if (cur > last)
1097 interleave(ch->src + last, src2 + last,
1098 ch->sink + 2*last, cur - last);
1103 * Feed from R channel of ADC and mixdown to destination L/center.
1104 * This function expects n not overwrapping the buffer boundary.
1105 * Note that n is measured in sample unit.
1107 * XXX - this function works in 16bit monoral format only.
1110 mixdown(int16_t *src, int16_t *dest, unsigned n)
1114 for (end = dest + n; dest < end; dest++)
1115 *dest = (int16_t)(((int)*dest - (int)*src++) / 2);
1119 aggch_feed_adc_mono(struct agg_rchinfo *ch)
1123 agg_lock(ch->parent);
1124 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1125 agg_unlock(ch->parent);
1126 cur -= 0xffff & ((ch->phys - ch->base) >> 1);
1130 mixdown(ch->src + last, ch->sink + last, ch->buflen - last);
1131 mixdown(ch->src, ch->sink, cur);
1132 } else if (cur > last)
1133 mixdown(ch->src + last, ch->sink + last, cur - last);
1138 * Stereo jitter suppressor.
1139 * Sometimes playback pointers differ in stereo-paired channels.
1140 * Calling this routine within intr fixes the problem.
1143 suppress_jitter(struct agg_chinfo *ch)
1146 int cp1, cp2, diff /*, halfsize*/ ;
1148 /*halfsize = (ch->qs16? ch->buflen >> 2 : ch->buflen >> 1);*/
1149 cp1 = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1150 cp2 = wp_rdapu(ch->parent, (ch->num << 1) | 33, APUREG_CURPTR);
1152 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1153 if (diff > 1 /* && diff < halfsize*/ )
1154 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1160 suppress_rec_jitter(struct agg_rchinfo *ch)
1162 int cp1, cp2, diff /*, halfsize*/ ;
1164 /*halfsize = (ch->stereo? ch->buflen >> 2 : ch->buflen >> 1);*/
1165 cp1 = (ch->stereo? ch->parent->bufsz >> 2 : ch->parent->bufsz >> 1)
1166 + wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1167 cp2 = wp_rdapu(ch->parent, 1, APUREG_CURPTR);
1169 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1170 if (diff > 1 /* && diff < halfsize*/ )
1171 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1176 calc_timer_div(struct agg_chinfo *ch)
1183 kprintf("snd_maestro: pch[%d].speed == 0, which shouldn't\n",
1188 return (48000 * (ch->blklen << (!ch->qs16 + !ch->stereo))
1189 + speed - 1) / speed;
1193 calc_timer_div_rch(struct agg_rchinfo *ch)
1200 kprintf("snd_maestro: rch.speed == 0, which shouldn't\n");
1204 return (48000 * (ch->blklen << (!ch->stereo))
1205 + speed - 1) / speed;
1209 set_timer(struct agg_info *ess)
1212 u_int dv = 32 << 7, newdv;
1214 for (i = 0; i < ess->playchns; i++)
1215 if ((ess->active & (1 << i)) &&
1216 (dv > (newdv = calc_timer_div(ess->pch + i))))
1218 if ((ess->active & (1 << i)) &&
1219 (dv > (newdv = calc_timer_div_rch(&ess->rch))))
1222 wp_settimer(ess, dv);
1226 /* -----------------------------
1230 /* AC97 mixer interface. */
1233 agg_ac97_init(kobj_t obj, void *sc)
1235 struct agg_info *ess = sc;
1237 return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1;
1241 agg_ac97_read(kobj_t obj, void *sc, int regno)
1243 struct agg_info *ess = sc;
1246 /* XXX sound locking violation: agg_lock(ess); */
1247 ret = agg_rdcodec(ess, regno);
1248 /* agg_unlock(ess); */
1253 agg_ac97_write(kobj_t obj, void *sc, int regno, u_int32_t data)
1255 struct agg_info *ess = sc;
1258 /* XXX sound locking violation: agg_lock(ess); */
1259 ret = agg_wrcodec(ess, regno, data);
1260 /* agg_unlock(ess); */
1265 static kobj_method_t agg_ac97_methods[] = {
1266 KOBJMETHOD(ac97_init, agg_ac97_init),
1267 KOBJMETHOD(ac97_read, agg_ac97_read),
1268 KOBJMETHOD(ac97_write, agg_ac97_write),
1271 AC97_DECLARE(agg_ac97);
1274 /* -------------------------------------------------------------------- */
1276 /* Playback channel. */
1279 aggpch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1281 struct agg_info *ess = devinfo;
1282 struct agg_chinfo *ch;
1283 bus_addr_t physaddr;
1286 KASSERT((dir == PCMDIR_PLAY),
1287 ("aggpch_init() called for RECORDING channel!"));
1288 ch = ess->pch + ess->playchns;
1293 ch->num = ess->playchns;
1295 p = dma_malloc(ess->buf_dmat, ess->bufsz, &physaddr);
1298 ch->phys = physaddr;
1299 ch->base = physaddr & ((~(bus_addr_t)0) << WAVCACHE_BASEADDR_SHIFT);
1301 sndbuf_setup(b, p, ess->bufsz);
1302 ch->blklen = sndbuf_getblksz(b) / 2;
1303 ch->buflen = sndbuf_getsize(b) / 2;
1310 adjust_pchbase(struct agg_chinfo *chans, u_int n, u_int size)
1312 struct agg_chinfo *pchs[AGG_MAXPLAYCH];
1316 /* sort pchs by phys address */
1317 for (i = 0; i < n; i++) {
1318 for (j = 0; j < i; j++)
1319 if (chans[i].phys < pchs[j]->phys) {
1320 for (k = i; k > j; k--)
1321 pchs[k] = pchs[k - 1];
1324 pchs[j] = chans + i;
1327 /* use new base register if next buffer can not be addressed
1328 via current base. */
1329 #define BASE_SHIFT (WPWA_WTBAR_SHIFT(2) + 2 + 1)
1330 base = pchs[0]->base;
1331 for (k = 1, i = 1; i < n; i++) {
1332 if (pchs[i]->phys + size - base >= 1 << BASE_SHIFT)
1333 /* not addressable: assign new base */
1334 base = (pchs[i]->base -= k++ << BASE_SHIFT);
1336 pchs[i]->base = base;
1341 kprintf("Total of %d bases are assigned.\n", k);
1342 for (i = 0; i < n; i++) {
1343 kprintf("ch.%d: phys 0x%llx, wpwa 0x%llx\n",
1344 i, (long long)chans[i].phys,
1345 (long long)(chans[i].phys -
1346 chans[i].base) >> 1);
1352 aggpch_free(kobj_t obj, void *data)
1354 struct agg_chinfo *ch = data;
1355 struct agg_info *ess = ch->parent;
1357 /* kfree up buffer - called after channel stopped */
1358 dma_free(ess->buf_dmat, sndbuf_getbuf(ch->buffer));
1360 /* return 0 if ok */
1365 aggpch_setformat(kobj_t obj, void *data, u_int32_t format)
1367 struct agg_chinfo *ch = data;
1369 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE)
1371 ch->stereo = ch->qs16 = ch->us = 0;
1372 if (format & AFMT_STEREO)
1375 if (format & AFMT_U8 || format & AFMT_S8) {
1376 if (format & AFMT_U8)
1384 aggpch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1386 return ((struct agg_chinfo*)data)->speed = speed;
1390 aggpch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1392 struct agg_chinfo *ch = data;
1395 /* try to keep at least 20msec DMA space */
1396 blkcnt = (ch->speed << (ch->stereo + ch->qs16)) / (50 * blocksize);
1397 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1399 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1400 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1401 blkcnt = sndbuf_getblkcnt(ch->buffer);
1402 blocksize = sndbuf_getblksz(ch->buffer);
1404 sndbuf_setblkcnt(ch->buffer, blkcnt);
1405 sndbuf_setblksz(ch->buffer, blocksize);
1408 ch->blklen = blocksize / 2;
1409 ch->buflen = blkcnt * blocksize / 2;
1414 aggpch_trigger(kobj_t obj, void *data, int go)
1416 struct agg_chinfo *ch = data;
1419 case PCMTRIG_EMLDMAWR:
1422 aggch_start_dac(ch);
1433 aggpch_getptr(kobj_t obj, void *data)
1435 struct agg_chinfo *ch = data;
1438 agg_lock(ch->parent);
1439 cp = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1440 agg_unlock(ch->parent);
1442 return ch->qs16 && ch->stereo
1443 ? (cp << 2) - ((0xffff << 2) & (ch->phys - ch->base))
1444 : (cp << 1) - ((0xffff << 1) & (ch->phys - ch->base));
1447 static struct pcmchan_caps *
1448 aggpch_getcaps(kobj_t obj, void *data)
1450 static u_int32_t playfmt[] = {
1452 AFMT_STEREO | AFMT_U8,
1454 AFMT_STEREO | AFMT_S8,
1456 AFMT_STEREO | AFMT_S16_LE,
1459 static struct pcmchan_caps playcaps = {8000, 48000, playfmt, 0};
1465 static kobj_method_t aggpch_methods[] = {
1466 KOBJMETHOD(channel_init, aggpch_init),
1467 KOBJMETHOD(channel_free, aggpch_free),
1468 KOBJMETHOD(channel_setformat, aggpch_setformat),
1469 KOBJMETHOD(channel_setspeed, aggpch_setspeed),
1470 KOBJMETHOD(channel_setblocksize, aggpch_setblocksize),
1471 KOBJMETHOD(channel_trigger, aggpch_trigger),
1472 KOBJMETHOD(channel_getptr, aggpch_getptr),
1473 KOBJMETHOD(channel_getcaps, aggpch_getcaps),
1476 CHANNEL_DECLARE(aggpch);
1479 /* -------------------------------------------------------------------- */
1481 /* Recording channel. */
1484 aggrch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
1486 struct agg_info *ess = devinfo;
1487 struct agg_rchinfo *ch;
1490 KASSERT((dir == PCMDIR_REC),
1491 ("aggrch_init() called for PLAYBACK channel!"));
1498 /* Uses the bottom-half of the status buffer. */
1499 p = ess->stat + ess->bufsz;
1500 ch->phys = ess->phys + ess->bufsz;
1501 ch->base = ess->phys;
1502 ch->src = (int16_t *)(p + ess->bufsz);
1503 ch->srcphys = ch->phys + ess->bufsz;
1504 ch->sink = (int16_t *)p;
1506 sndbuf_setup(b, p, ess->bufsz);
1507 ch->blklen = sndbuf_getblksz(b) / 2;
1508 ch->buflen = sndbuf_getsize(b) / 2;
1514 aggrch_setformat(kobj_t obj, void *data, u_int32_t format)
1516 struct agg_rchinfo *ch = data;
1518 if (!(format & AFMT_S16_LE))
1520 if (format & AFMT_STEREO)
1528 aggrch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1530 return ((struct agg_rchinfo*)data)->speed = speed;
1534 aggrch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1536 struct agg_rchinfo *ch = data;
1539 /* try to keep at least 20msec DMA space */
1540 blkcnt = (ch->speed << ch->stereo) / (25 * blocksize);
1541 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1543 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1544 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1545 blkcnt = sndbuf_getblkcnt(ch->buffer);
1546 blocksize = sndbuf_getblksz(ch->buffer);
1548 sndbuf_setblkcnt(ch->buffer, blkcnt);
1549 sndbuf_setblksz(ch->buffer, blocksize);
1552 ch->blklen = blocksize / 2;
1553 ch->buflen = blkcnt * blocksize / 2;
1558 aggrch_trigger(kobj_t obj, void *sc, int go)
1560 struct agg_rchinfo *ch = sc;
1563 case PCMTRIG_EMLDMARD:
1565 aggch_feed_adc_stereo(ch);
1567 aggch_feed_adc_mono(ch);
1570 aggch_start_adc(ch);
1581 aggrch_getptr(kobj_t obj, void *sc)
1583 struct agg_rchinfo *ch = sc;
1585 return ch->stereo? ch->hwptr << 2 : ch->hwptr << 1;
1588 static struct pcmchan_caps *
1589 aggrch_getcaps(kobj_t obj, void *sc)
1591 static u_int32_t recfmt[] = {
1593 AFMT_STEREO | AFMT_S16_LE,
1596 static struct pcmchan_caps reccaps = {8000, 48000, recfmt, 0};
1601 static kobj_method_t aggrch_methods[] = {
1602 KOBJMETHOD(channel_init, aggrch_init),
1603 /* channel_free: no-op */
1604 KOBJMETHOD(channel_setformat, aggrch_setformat),
1605 KOBJMETHOD(channel_setspeed, aggrch_setspeed),
1606 KOBJMETHOD(channel_setblocksize, aggrch_setblocksize),
1607 KOBJMETHOD(channel_trigger, aggrch_trigger),
1608 KOBJMETHOD(channel_getptr, aggrch_getptr),
1609 KOBJMETHOD(channel_getcaps, aggrch_getcaps),
1612 CHANNEL_DECLARE(aggrch);
1615 /* -----------------------------
1622 struct agg_info* ess = sc;
1623 register u_int8_t status;
1627 status = AGG_RD(ess, PORT_HOSTINT_STAT, 1);
1631 /* Acknowledge intr. */
1632 AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
1634 if (status & HOSTINT_STAT_DSOUND) {
1635 #ifdef AGG_JITTER_CORRECTION
1638 if (ess->curpwr <= PCI_POWERSTATE_D1) {
1639 AGG_WR(ess, PORT_INT_STAT, 1, 2);
1640 #ifdef AGG_JITTER_CORRECTION
1641 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1642 if (ess->active & m)
1643 suppress_jitter(ess->pch + i);
1645 if (ess->active & m)
1646 suppress_rec_jitter(&ess->rch);
1649 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1650 if (ess->active & m) {
1651 if (ess->curpwr <= PCI_POWERSTATE_D1)
1652 chn_intr(ess->pch[i].channel);
1659 if ((ess->active & m)
1660 && ess->curpwr <= PCI_POWERSTATE_D1)
1661 chn_intr(ess->rch.channel);
1663 #ifdef AGG_JITTER_CORRECTION
1669 if (status & HOSTINT_STAT_HWVOL) {
1670 register u_int8_t event;
1673 event = AGG_RD(ess, PORT_HWVOL_MASTER, 1);
1674 AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
1679 mixer_hwvol_step(ess->dev, 1, 1);
1682 mixer_hwvol_step(ess->dev, -1, -1);
1687 if (event & HWVOL_MUTE) {
1688 mixer_hwvol_mute(ess->dev);
1691 device_printf(ess->dev,
1692 "%s: unknown HWVOL event 0x%x\n",
1693 device_get_nameunit(ess->dev), event);
1699 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1701 bus_addr_t *phys = arg;
1703 *phys = error? 0 : segs->ds_addr;
1706 kprintf("setmap (%lx, %lx), nseg=%d, error=%d\n",
1707 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1713 dma_malloc(bus_dma_tag_t dmat, u_int32_t sz, bus_addr_t *phys)
1718 if (bus_dmamem_alloc(dmat, &buf, BUS_DMA_NOWAIT, &map))
1720 if (bus_dmamap_load(dmat, map, buf, sz, setmap, phys, 0)
1722 bus_dmamem_free(dmat, buf, map);
1729 dma_free(bus_dma_tag_t dmat, void *buf)
1731 bus_dmamem_free(dmat, buf, NULL);
1735 agg_probe(device_t dev)
1739 switch (pci_get_devid(dev)) {
1740 case MAESTRO_1_PCI_ID:
1741 s = "ESS Technology Maestro-1";
1744 case MAESTRO_2_PCI_ID:
1745 s = "ESS Technology Maestro-2";
1748 case MAESTRO_2E_PCI_ID:
1749 s = "ESS Technology Maestro-2E";
1753 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
1754 device_set_desc(dev, s);
1755 return BUS_PROBE_DEFAULT;
1761 agg_attach(device_t dev)
1763 struct agg_info *ess = NULL;
1765 int regid = PCIR_BAR(0);
1766 struct resource *reg = NULL;
1767 struct ac97_info *codec = NULL;
1769 struct resource *irq = NULL;
1771 char status[SND_STATUSLEN];
1774 ess = kmalloc(sizeof *ess, M_DEVBUF, M_WAITOK | M_ZERO);
1778 ess->lock = snd_mtxcreate(device_get_desc(dev), "hardware status lock");
1779 if (ess->lock == NULL) {
1780 device_printf(dev, "failed to create a mutex.\n");
1786 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
1787 if (bus_dma_tag_create(/*parent*/ NULL,
1788 /*align */ 4, 1 << (16+1),
1789 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1790 /*filter*/ NULL, NULL,
1791 /*size */ ess->bufsz, 1, 0x3ffff,
1793 #if __FreeBSD_version >= 501102
1794 /*lock */ busdma_lock_mutex, &Giant,
1796 &ess->buf_dmat) != 0) {
1797 device_printf(dev, "unable to create dma tag\n");
1802 if (bus_dma_tag_create(/*parent*/NULL,
1803 /*align */ 1 << WAVCACHE_BASEADDR_SHIFT,
1805 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1806 /*filter*/ NULL, NULL,
1807 /*size */ 3*ess->bufsz, 1, 0x3ffff,
1809 #if __FreeBSD_version >= 501102
1810 /*lock */ busdma_lock_mutex, &Giant,
1812 &ess->stat_dmat) != 0) {
1813 device_printf(dev, "unable to create dma tag\n");
1818 /* Allocate the room for brain-damaging status buffer. */
1819 ess->stat = dma_malloc(ess->stat_dmat, 3*ess->bufsz, &ess->phys);
1820 if (ess->stat == NULL) {
1821 device_printf(dev, "cannot allocate status buffer\n");
1826 device_printf(dev, "Maestro status/record buffer: %#llx\n",
1827 (long long)ess->phys);
1829 /* State D0-uninitialized. */
1830 ess->curpwr = PCI_POWERSTATE_D3;
1831 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1833 data = pci_read_config(dev, PCIR_COMMAND, 2);
1834 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
1835 pci_write_config(dev, PCIR_COMMAND, data, 2);
1836 data = pci_read_config(dev, PCIR_COMMAND, 2);
1838 /* Allocate resources. */
1839 if (data & PCIM_CMD_PORTEN)
1840 reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, ®id,
1845 ess->st = rman_get_bustag(reg);
1846 ess->sh = rman_get_bushandle(reg);
1848 device_printf(dev, "unable to map register space\n");
1852 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
1853 RF_ACTIVE | RF_SHAREABLE);
1858 device_printf(dev, "unable to map interrupt\n");
1863 /* Setup resources. */
1864 if (snd_setup_intr(dev, irq, INTR_MPSAFE, agg_intr, ess, &ih)) {
1865 device_printf(dev, "unable to setup interrupt\n");
1871 /* Transition from D0-uninitialized to D0. */
1873 agg_power(ess, PCI_POWERSTATE_D0);
1874 if (agg_rdcodec(ess, 0) == 0x80) {
1875 /* XXX - TODO: PT101 */
1877 device_printf(dev, "PT101 codec detected!\n");
1882 codec = AC97_CREATE(dev, ess, agg_ac97);
1883 if (codec == NULL) {
1884 device_printf(dev, "failed to create AC97 codec softc!\n");
1888 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) {
1889 device_printf(dev, "mixer initialization failed!\n");
1895 ret = pcm_register(dev, ess, AGG_MAXPLAYCH, 1);
1899 mixer_hwvol_init(dev);
1901 agg_power(ess, powerstate_init);
1903 for (data = 0; data < AGG_MAXPLAYCH; data++)
1904 pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess);
1905 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1906 adjust_pchbase(ess->pch, ess->playchns, ess->bufsz);
1908 ksnprintf(status, SND_STATUSLEN,
1909 "port 0x%lx-0x%lx irq %ld at device %d.%d on pci%d",
1910 rman_get_start(reg), rman_get_end(reg), rman_get_start(irq),
1911 pci_get_slot(dev), pci_get_function(dev), pci_get_bus(dev));
1912 pcm_setstatus(dev, status);
1918 ac97_destroy(codec);
1920 bus_teardown_intr(dev, irq, ih);
1922 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1924 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1926 if (ess->stat != NULL)
1927 dma_free(ess->stat_dmat, ess->stat);
1928 if (ess->stat_dmat != NULL)
1929 bus_dma_tag_destroy(ess->stat_dmat);
1930 if (ess->buf_dmat != NULL)
1931 bus_dma_tag_destroy(ess->buf_dmat);
1933 if (ess->lock != NULL)
1934 snd_mtxfree(ess->lock);
1936 kfree(ess, M_DEVBUF);
1943 agg_detach(device_t dev)
1945 struct agg_info *ess = pcm_getdevinfo(dev);
1949 icr = AGG_RD(ess, PORT_HOSTINT_CTRL, 2);
1950 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1954 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1960 r = pcm_unregister(dev);
1962 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1967 agg_power(ess, PCI_POWERSTATE_D3);
1970 bus_teardown_intr(dev, ess->irq, ess->ih);
1971 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1972 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1973 dma_free(ess->stat_dmat, ess->stat);
1974 bus_dma_tag_destroy(ess->stat_dmat);
1975 bus_dma_tag_destroy(ess->buf_dmat);
1977 snd_mtxfree(ess->lock);
1979 kfree(ess, M_DEVBUF);
1984 agg_suspend(device_t dev)
1986 struct agg_info *ess = pcm_getdevinfo(dev);
1992 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1994 agg_power(ess, PCI_POWERSTATE_D3);
2004 agg_resume(device_t dev)
2007 struct agg_info *ess = pcm_getdevinfo(dev);
2013 for (i = 0; i < ess->playchns; i++)
2014 if (ess->active & (1 << i))
2015 aggch_start_dac(ess->pch + i);
2016 if (ess->active & (1 << i))
2017 aggch_start_adc(&ess->rch);
2021 agg_power(ess, powerstate_init);
2027 if (mixer_reinit(dev)) {
2028 device_printf(dev, "unable to reinitialize the mixer\n");
2036 agg_shutdown(device_t dev)
2038 struct agg_info *ess = pcm_getdevinfo(dev);
2041 agg_power(ess, PCI_POWERSTATE_D3);
2048 static device_method_t agg_methods[] = {
2049 DEVMETHOD(device_probe, agg_probe),
2050 DEVMETHOD(device_attach, agg_attach),
2051 DEVMETHOD(device_detach, agg_detach),
2052 DEVMETHOD(device_suspend, agg_suspend),
2053 DEVMETHOD(device_resume, agg_resume),
2054 DEVMETHOD(device_shutdown, agg_shutdown),
2059 static driver_t agg_driver = {
2065 /*static devclass_t pcm_devclass;*/
2067 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, NULL, NULL);
2068 MODULE_DEPEND(snd_maestro, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2069 MODULE_VERSION(snd_maestro, 1);