1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
4 /******************************************************************************
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
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18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
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24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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28 * in the file called COPYING.
30 * Contact Information:
31 * Intel Linux Wireless <ilw@linux.intel.com>
32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *****************************************************************************/
66 #ifndef __IF_IWM_REG_H__
67 #define __IF_IWM_REG_H__
69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
73 * CSR (control and status registers)
75 * CSR registers are mapped directly into PCI bus space, and are accessible
76 * whenever platform supplies power to device, even when device is in
77 * low power states due to driver-invoked device resets
78 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
80 * Use iwl_write32() and iwl_read32() family to access these registers;
81 * these provide simple PCI bus access, without waking up the MAC.
82 * Do not use iwl_write_direct32() family for these registers;
83 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
84 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
87 * NOTE: Device does need to be awake in order to read this memory
88 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
90 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
91 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
92 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
93 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
94 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
95 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
96 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
97 #define IWM_CSR_GP_CNTRL (0x024)
99 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
100 #define IWM_CSR_INT_PERIODIC_REG (0x005)
103 * Hardware revision info
106 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
108 * 1-0: "Dash" (-) value, as in A-1, etc.
110 #define IWM_CSR_HW_REV (0x028)
113 * EEPROM and OTP (one-time-programmable) memory reads
115 * NOTE: Device must be awake, initialized via apm_ops.init(),
118 #define IWM_CSR_EEPROM_REG (0x02c)
119 #define IWM_CSR_EEPROM_GP (0x030)
120 #define IWM_CSR_OTP_GP_REG (0x034)
122 #define IWM_CSR_GIO_REG (0x03C)
123 #define IWM_CSR_GP_UCODE_REG (0x048)
124 #define IWM_CSR_GP_DRIVER_REG (0x050)
127 * UCODE-DRIVER GP (general purpose) mailbox registers.
128 * SET/CLR registers set/clear bit(s) if "1" is written.
130 #define IWM_CSR_UCODE_DRV_GP1 (0x054)
131 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
132 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
133 #define IWM_CSR_UCODE_DRV_GP2 (0x060)
135 #define IWM_CSR_MBOX_SET_REG (0x088)
136 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20
138 #define IWM_CSR_LED_REG (0x094)
139 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
140 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
143 /* GIO Chicken Bits (PCI Express bus link power management) */
144 #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
146 /* Analog phase-lock-loop configuration */
147 #define IWM_CSR_ANA_PLL_CFG (0x20c)
150 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
151 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
152 * See also IWM_CSR_HW_REV register.
154 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
155 * 1-0: "Dash" (-) value, as in C-1, etc.
157 #define IWM_CSR_HW_REV_WA_REG (0x22C)
159 #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
160 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
162 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */
163 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
164 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
166 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
167 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
172 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
173 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
179 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
180 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
183 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
184 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
185 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
187 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
188 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
190 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
191 * acknowledged (reset) by host writing "1" to flagged bits. */
192 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
193 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
194 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
195 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
196 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
197 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
198 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
199 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
200 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
201 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
202 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
204 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
205 IWM_CSR_INT_BIT_HW_ERR | \
206 IWM_CSR_INT_BIT_FH_TX | \
207 IWM_CSR_INT_BIT_SW_ERR | \
208 IWM_CSR_INT_BIT_RF_KILL | \
209 IWM_CSR_INT_BIT_SW_RX | \
210 IWM_CSR_INT_BIT_WAKEUP | \
211 IWM_CSR_INT_BIT_ALIVE | \
212 IWM_CSR_INT_BIT_RX_PERIODIC)
214 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
215 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
216 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
217 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
218 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
219 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
220 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
222 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
223 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
224 IWM_CSR_FH_INT_BIT_RX_CHNL0)
226 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
227 IWM_CSR_FH_INT_BIT_TX_CHNL0)
230 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
231 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
232 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
235 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
236 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
237 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
238 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
239 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
240 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
243 * GP (general purpose) CONTROL REGISTER
246 * Indicates state of (platform's) hardware RF-Kill switch
247 * 26-24: POWER_SAVE_TYPE
248 * Indicates current power-saving mode:
249 * 000 -- No power saving
250 * 001 -- MAC power-down
251 * 010 -- PHY (radio) power-down
254 * Indicates current system configuration, reflecting pins on chip
255 * as forced high/low by device circuit board.
257 * Indicates MAC is entering a power-saving sleep power-down.
258 * Not a good time to access device-internal resources.
260 * Host sets this to request and maintain MAC wakeup, to allow host
261 * access to device-internal resources. Host must wait for
262 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
265 * Host sets this to put device into fully operational D0 power mode.
266 * Host resets this after SW_RESET to put device into low power mode.
268 * Indicates MAC (ucode processor, etc.) is powered up and can run.
269 * Internal resources are accessible.
270 * NOTE: This does not indicate that the processor is actually running.
271 * NOTE: This does not indicate that device has completed
272 * init or post-power-down restore of internal SRAM memory.
273 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
274 * SRAM is restored and uCode is in normal operation mode.
275 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
276 * do not need to save/restore it.
277 * NOTE: After device reset, this bit remains "0" until host sets
280 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
281 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
283 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
285 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
287 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
288 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
289 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
293 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
294 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
300 IWM_SILICON_A_STEP = 0,
306 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
307 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
308 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
309 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
310 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
311 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
312 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
313 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
314 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
315 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
316 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
317 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
318 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
319 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
320 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
321 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
322 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)
323 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
326 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
327 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
328 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
329 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
332 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
333 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
334 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
335 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
336 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
337 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
339 /* One-time-programmable memory general purpose reg */
340 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
341 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
342 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
343 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
346 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
347 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
348 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
349 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
350 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
354 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
357 * UCODE-DRIVER GP (general purpose) mailbox register 1
358 * Host driver and uCode write and/or read this register to communicate with
362 * Host sets this to request permanent halt of uCode, same as
363 * sending CARD_STATE command with "halt" bit set.
365 * Host sets this to request exit from CT_KILL state, i.e. host thinks
366 * device temperature is low enough to continue normal operation.
368 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
369 * to release uCode to clear all Tx and command queues, enter
370 * unassociated mode, and power down.
371 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
373 * Host sets this when issuing CARD_STATE command to request
376 * uCode sets this when preparing a power-saving power-down.
377 * uCode resets this when power-up is complete and SRAM is sane.
378 * NOTE: device saves internal SRAM data to host when powering down,
379 * and must restore this data after powering back up.
380 * MAC_SLEEP is the best indication that restore is complete.
381 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
382 * do not need to save/restore it.
384 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
385 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
386 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
387 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
388 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
391 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
392 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
393 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
394 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
395 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
396 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
400 /* GIO Chicken Bits (PCI Express bus link power management) */
401 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
402 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
405 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
406 #define IWM_CSR_LED_REG_TURN_ON (0x60)
407 #define IWM_CSR_LED_REG_TURN_OFF (0x20)
410 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
413 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
416 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
417 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
418 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
420 /* SECURE boot registers */
421 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
422 enum iwm_secure_boot_config_reg {
423 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
424 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
427 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
428 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
429 enum iwm_secure_boot_status_reg {
430 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
431 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
432 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
433 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
434 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
437 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0
438 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70
439 enum iwm_secure_load_status_reg {
440 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001,
441 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003,
442 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007,
443 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
444 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
446 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
448 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38
449 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c
450 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
451 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
453 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000
454 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000
455 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
456 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
458 #define IWM_CSR_SECURE_TIME_OUT (100)
460 /* extended range in FW SRAM */
461 #define IWM_FW_MEM_EXTENDED_START 0x40000
462 #define IWM_FW_MEM_EXTENDED_END 0x57FFF
464 /* FW chicken bits */
465 #define IWM_LMPM_CHICK 0xa01ff8
466 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
468 #define IWM_FH_TCSR_0_REG0 (0x1D00)
471 * HBUS (Host-side Bus)
473 * HBUS registers are mapped directly into PCI bus space, but are used
474 * to indirectly access device's internal memory or registers that
475 * may be powered-down.
477 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
478 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
479 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
480 * internal resources.
482 * Do not use iwl_write32()/iwl_read32() family to access these registers;
483 * these provide only simple PCI bus access, without waking up the MAC.
485 #define IWM_HBUS_BASE (0x400)
488 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
489 * structures, error log, event log, verifying uCode load).
490 * First write to address register, then read from or write to data register
491 * to complete the job. Once the address register is set up, accesses to
492 * data registers auto-increment the address by one dword.
493 * Bit usage for address registers (read or write):
494 * 0-31: memory address within device
496 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
497 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
498 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
499 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
501 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
502 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
503 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
506 * Registers for accessing device's internal peripheral registers
507 * (e.g. SCD, BSM, etc.). First write to address register,
508 * then read from or write to data register to complete the job.
509 * Bit usage for address registers (read or write):
510 * 0-15: register address (offset) within device
511 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
513 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
514 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
515 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
516 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
518 /* enable the ID buf for read */
519 #define IWM_WFPM_PS_CTL_CLR 0xa0300c
520 #define IWM_WFMP_MAC_ADDR_0 0xa03080
521 #define IWM_WFMP_MAC_ADDR_1 0xa03084
522 #define IWM_LMPM_PMG_EN 0xa01cec
523 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
524 #define IWM_RFIC_REG_RD 0xad0470
525 #define IWM_WFPM_CTRL_REG 0xa03030
526 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
527 #define IWM_ENABLE_WFPM 0x80000000
529 #define IWM_AUX_MISC_REG 0xa200b0
530 #define IWM_HW_STEP_LOCATION_BITS 24
532 #define IWM_AUX_MISC_MASTER1_EN 0xa20818
533 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
534 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
535 #define IWM_RSA_ENABLE 0xa24b08
536 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
537 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
538 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
539 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
540 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088
541 #define IWM_SB_CPU_1_STATUS 0xa01e30
542 #define IWM_SB_CPU_2_STATUS 0Xa01e34
544 /* Used to enable DBGM */
545 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
548 * Per-Tx-queue write pointer (index, really!)
549 * Indicates index to next TFD that driver will fill (1 past latest filled).
551 * 0-7: queue write index
552 * 11-8: queue selector
554 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
556 /**********************************************************
558 **********************************************************/
560 * host interrupt timeout value
561 * used with setting interrupt coalescing timer
562 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
564 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
566 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
567 #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
568 #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
569 #define IWM_HOST_INT_OPER_MODE (1 << 31)
571 /*****************************************************************************
572 * 7000/3000 series SHR DTS addresses *
573 *****************************************************************************/
575 /* Diode Results Register Structure: */
576 enum iwm_dtd_diode_reg {
577 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
578 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
579 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
580 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
581 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
582 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
583 /* Those are the masks INSIDE the flags bit-field: */
584 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
585 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
586 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
587 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
591 * enum iwm_ucode_tlv_flag - ucode API flags
592 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
593 * was a separate TLV but moved here to save space.
594 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
595 * treats good CRC threshold as a boolean
596 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
597 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
598 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
599 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
600 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
601 * offload profile config command.
602 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
603 * (rather than two) IPv6 addresses
604 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
605 * from the probe request template.
606 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
607 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
608 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
609 * single bound interface).
610 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
611 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
612 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
613 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
614 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
617 enum iwm_ucode_tlv_flag {
618 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
619 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
620 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
621 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3),
622 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
623 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
624 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
625 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
626 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
627 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
628 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21),
629 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22),
630 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23),
631 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
632 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25),
633 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
634 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29),
635 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30),
636 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31),
639 #define IWM_UCODE_TLV_FLAG_BITS \
640 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \
641 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \
642 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \
643 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
646 * enum iwm_ucode_tlv_api - ucode api
647 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
648 * longer than the passive one, which is essential for fragmented scan.
649 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
650 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
651 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
652 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
654 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
655 * (command version 3) that supports per-chain limits
657 * @IWM_NUM_UCODE_TLV_API: number of bits used
659 enum iwm_ucode_tlv_api {
660 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8),
661 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9),
662 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14),
663 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18),
664 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24),
665 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27),
667 IWM_NUM_UCODE_TLV_API = 32
670 #define IWM_UCODE_TLV_API_BITS \
671 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN"
674 * enum iwm_ucode_tlv_capa - ucode capabilities
675 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
676 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
677 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
678 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
679 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
680 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
681 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
682 * tx power value into TPC Report action frame and Link Measurement Report
684 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
685 * channel in DS parameter set element in probe requests.
686 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
688 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
689 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
690 * which also implies support for the scheduler configuration command
691 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
692 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
693 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
694 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
695 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
696 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
697 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
698 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
699 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
700 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
701 * sources for the MCC. This TLV bit is a future replacement to
702 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
704 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
705 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
706 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
707 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
709 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
710 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
711 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
712 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
713 * antenna the beacon should be transmitted
714 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
715 * from AP and will send it upon d0i3 exit.
716 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
717 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
718 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
719 * thresholds reporting
720 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
721 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
723 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
724 * memory addresses from the firmware.
725 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
726 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
729 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
731 enum iwm_ucode_tlv_capa {
732 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0,
733 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1,
734 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2,
735 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3,
736 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5,
737 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6,
738 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8,
739 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9,
740 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10,
741 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11,
742 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12,
743 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13,
744 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17,
745 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18,
746 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19,
747 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20,
748 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21,
749 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22,
750 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26,
751 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28,
752 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29,
753 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30,
754 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31,
755 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34,
756 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35,
757 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64,
758 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65,
759 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67,
760 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68,
761 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71,
762 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72,
763 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73,
764 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74,
765 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75,
766 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76,
767 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77,
768 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79,
769 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80,
770 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81,
772 IWM_NUM_UCODE_TLV_CAPA = 128
775 /* The default calibrate table size if not specified by firmware file */
776 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
777 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
778 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
780 /* The default max probe length if not specified by the firmware file */
781 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200
784 * enumeration of ucode section.
785 * This enumeration is used directly for older firmware (before 16.0).
786 * For new firmware, there can be up to 4 sections (see below) but the
787 * first one packaged into the firmware file is the DATA section and
788 * some debugging code accesses that.
791 IWM_UCODE_SECTION_DATA,
792 IWM_UCODE_SECTION_INST,
795 * For 16.0 uCode and above, there is no differentiation between sections,
796 * just an offset to the HW address.
798 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
799 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
801 /* uCode version contains 4 values: Major/Minor/API/Serial */
802 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
803 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
804 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
805 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
808 * Calibration control struct.
809 * Sent as part of the phy configuration command.
810 * @flow_trigger: bitmap for which calibrations to perform according to
812 * @event_trigger: bitmap for which calibrations to perform according to
815 struct iwm_tlv_calib_ctrl {
816 uint32_t flow_trigger;
817 uint32_t event_trigger;
820 enum iwm_fw_phy_cfg {
821 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
822 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
823 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
824 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
825 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
826 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
827 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
828 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
829 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
830 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
833 #define IWM_UCODE_MAX_CS 1
836 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
837 * @cipher: a cipher suite selector
838 * @flags: cipher scheme flags (currently reserved for a future use)
839 * @hdr_len: a size of MPDU security header
840 * @pn_len: a size of PN
841 * @pn_off: an offset of pn from the beginning of the security header
842 * @key_idx_off: an offset of key index byte in the security header
843 * @key_idx_mask: a bit mask of key_idx bits
844 * @key_idx_shift: bit shift needed to get key_idx
845 * @mic_len: mic length in bytes
846 * @hw_cipher: a HW cipher index used in host commands
848 struct iwm_fw_cipher_scheme {
855 uint8_t key_idx_mask;
856 uint8_t key_idx_shift;
862 * struct iwm_fw_cscheme_list - a cipher scheme list
863 * @size: a number of entries
864 * @cs: cipher scheme entries
866 struct iwm_fw_cscheme_list {
868 struct iwm_fw_cipher_scheme cs[];
871 /* v1/v2 uCode file layout */
872 struct iwm_ucode_header {
873 uint32_t ver; /* major/minor/API/serial */
876 uint32_t inst_size; /* bytes of runtime code */
877 uint32_t data_size; /* bytes of runtime data */
878 uint32_t init_size; /* bytes of init code */
879 uint32_t init_data_size; /* bytes of init data */
880 uint32_t boot_size; /* bytes of bootstrap code */
881 uint8_t data[0]; /* in same order as sizes */
884 uint32_t build; /* build number */
885 uint32_t inst_size; /* bytes of runtime code */
886 uint32_t data_size; /* bytes of runtime data */
887 uint32_t init_size; /* bytes of init code */
888 uint32_t init_data_size; /* bytes of init data */
889 uint32_t boot_size; /* bytes of bootstrap code */
890 uint8_t data[0]; /* in same order as sizes */
896 * new TLV uCode file layout
898 * The new TLV file format contains TLVs, that each specify
899 * some piece of data.
902 enum iwm_ucode_tlv_type {
903 IWM_UCODE_TLV_INVALID = 0, /* unused */
904 IWM_UCODE_TLV_INST = 1,
905 IWM_UCODE_TLV_DATA = 2,
906 IWM_UCODE_TLV_INIT = 3,
907 IWM_UCODE_TLV_INIT_DATA = 4,
908 IWM_UCODE_TLV_BOOT = 5,
909 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
910 IWM_UCODE_TLV_PAN = 7,
911 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
912 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
913 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
914 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
915 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
916 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
917 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
918 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
919 IWM_UCODE_TLV_WOWLAN_INST = 16,
920 IWM_UCODE_TLV_WOWLAN_DATA = 17,
921 IWM_UCODE_TLV_FLAGS = 18,
922 IWM_UCODE_TLV_SEC_RT = 19,
923 IWM_UCODE_TLV_SEC_INIT = 20,
924 IWM_UCODE_TLV_SEC_WOWLAN = 21,
925 IWM_UCODE_TLV_DEF_CALIB = 22,
926 IWM_UCODE_TLV_PHY_SKU = 23,
927 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
928 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
929 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
930 IWM_UCODE_TLV_NUM_OF_CPU = 27,
931 IWM_UCODE_TLV_CSCHEME = 28,
934 * Following two are not in our base tag, but allow
935 * handling ucode version 9.
937 IWM_UCODE_TLV_API_CHANGES_SET = 29,
938 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30,
940 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31,
941 IWM_UCODE_TLV_PAGING = 32,
942 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34,
943 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35,
944 IWM_UCODE_TLV_FW_VERSION = 36,
945 IWM_UCODE_TLV_FW_DBG_DEST = 38,
946 IWM_UCODE_TLV_FW_DBG_CONF = 39,
947 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40,
948 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50,
949 IWM_UCODE_TLV_FW_MEM_SEG = 51,
952 struct iwm_ucode_tlv {
953 uint32_t type; /* see above */
954 uint32_t length; /* not including type/length fields */
958 struct iwm_ucode_api {
963 struct iwm_ucode_capa {
968 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
970 struct iwm_tlv_ucode_header {
972 * The TLV style ucode header is distinguished from
973 * the v1/v2 style header by first four bytes being
974 * zero, as such is an invalid combination of
975 * major/minor/API/serial versions.
979 uint8_t human_readable[64];
980 uint32_t ver; /* major/minor/API/serial */
984 * The data contained herein has a TLV layout,
985 * see above for the TLV header and types.
986 * Note that each TLV is padded to a length
987 * that is a multiple of 4 for alignment.
993 * Registers in this file are internal, not PCI bus memory mapped.
994 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
996 #define IWM_PRPH_BASE (0x00000)
997 #define IWM_PRPH_END (0xFFFFF)
999 /* APMG (power management) constants */
1000 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
1001 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
1002 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
1003 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
1004 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
1005 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
1006 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
1007 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
1008 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
1009 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
1010 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
1012 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
1013 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
1014 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
1016 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
1017 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
1018 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
1019 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
1020 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
1021 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
1022 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
1024 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
1026 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
1028 /* Device system time */
1029 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
1031 /* Device NMI register */
1032 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
1033 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1034 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
1035 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1036 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1039 * Device reset for family 8000
1040 * write to bit 24 in order to reset the CPU
1042 #define IWM_RELEASE_CPU_RESET 0x300c
1043 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1046 /*****************************************************************************
1047 * 7000/3000 series SHR DTS addresses *
1048 *****************************************************************************/
1050 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
1051 #define IWM_DTSC_CFG_MODE (0x00a10604)
1052 #define IWM_DTSC_VREF_AVG (0x00a10648)
1053 #define IWM_DTSC_VREF5_AVG (0x00a1064c)
1054 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
1055 #define IWM_DTSC_PTAT_AVG (0x00a10650)
1061 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
1062 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1063 * host DRAM. It steers each frame's Tx command (which contains the frame
1064 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1065 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1066 * but one DMA channel may take input from several queues.
1068 * Tx DMA FIFOs have dedicated purposes.
1070 * For 5000 series and up, they are used differently
1071 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
1073 * 0 -- EDCA BK (background) frames, lowest priority
1074 * 1 -- EDCA BE (best effort) frames, normal priority
1075 * 2 -- EDCA VI (video) frames, higher priority
1076 * 3 -- EDCA VO (voice) and management frames, highest priority
1082 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1083 * In addition, driver can map the remaining queues to Tx DMA/FIFO
1084 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1086 * The driver sets up each queue to work in one of two modes:
1088 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1089 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1090 * contains TFDs for a unique combination of Recipient Address (RA)
1091 * and Traffic Identifier (TID), that is, traffic of a given
1092 * Quality-Of-Service (QOS) priority, destined for a single station.
1094 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1095 * each frame within the BA window, including whether it's been transmitted,
1096 * and whether it's been acknowledged by the receiving station. The device
1097 * automatically processes block-acks received from the receiving STA,
1098 * and reschedules un-acked frames to be retransmitted (successful
1099 * Tx completion may end up being out-of-order).
1101 * The driver must maintain the queue's Byte Count table in host DRAM
1103 * This mode does not support fragmentation.
1105 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1106 * The device may automatically retry Tx, but will retry only one frame
1107 * at a time, until receiving ACK from receiving station, or reaching
1108 * retry limit and giving up.
1110 * The command queue (#4/#9) must use this mode!
1111 * This mode does not require use of the Byte Count table in host DRAM.
1113 * Driver controls scheduler operation via 3 means:
1114 * 1) Scheduler registers
1115 * 2) Shared scheduler data base in internal SRAM
1116 * 3) Shared data in host DRAM
1120 * When loading, driver should allocate memory for:
1121 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1122 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1123 * (1024 bytes for each queue).
1125 * After receiving "Alive" response from uCode, driver must initialize
1126 * the scheduler (especially for queue #4/#9, the command queue, otherwise
1127 * the driver can't issue commands!):
1129 #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
1132 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1133 * can keep track of at one time when creating block-ack chains of frames.
1134 * Note that "64" matches the number of ack bits in a block-ack packet.
1136 #define IWM_SCD_WIN_SIZE 64
1137 #define IWM_SCD_FRAME_LIMIT 64
1139 #define IWM_SCD_TXFIFO_POS_TID (0)
1140 #define IWM_SCD_TXFIFO_POS_RA (4)
1141 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1144 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
1145 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
1146 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
1147 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
1148 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
1150 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1151 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1152 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1153 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1154 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
1155 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
1156 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1157 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1158 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)
1159 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)
1162 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
1163 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1166 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1167 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1169 /* Translation Data */
1170 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1171 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
1173 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
1174 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
1176 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
1177 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
1179 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
1180 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
1182 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
1184 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1185 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1186 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1187 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1188 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1189 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1190 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1191 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1192 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
1193 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1194 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
1196 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
1199 return IWM_SCD_BASE + 0x18 + chnl * 4;
1200 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1203 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1206 return IWM_SCD_BASE + 0x68 + chnl * 4;
1207 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1210 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1213 return IWM_SCD_BASE + 0x10c + chnl * 4;
1214 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1217 /*********************** END TX SCHEDULER *************************************/
1219 /* Oscillator clock */
1220 #define IWM_OSC_CLK (0xa04068)
1221 #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1223 /****************************/
1224 /* Flow Handler Definitions */
1225 /****************************/
1228 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1229 * Addresses are offsets from device's PCI hardware base address.
1231 #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1232 #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1235 * Keep-Warm (KW) buffer base address.
1237 * Driver must allocate a 4KByte buffer that is for keeping the
1238 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1239 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1240 * from going into a power-savings mode that would cause higher DRAM latency,
1241 * and possible data over/under-runs, before all Tx/Rx is complete.
1243 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1244 * of the buffer, which must be 4K aligned. Once this is set up, the device
1245 * automatically invokes keep-warm accesses when normal accesses might not
1246 * be sufficient to maintain fast DRAM response.
1249 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1251 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1255 * TFD Circular Buffers Base (CBBC) addresses
1257 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1258 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1259 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1260 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1261 * aligned (address bits 0-7 must be 0).
1262 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1263 * for them are in different places.
1265 * Bit fields in each pointer register:
1266 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1268 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1269 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1270 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1271 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1272 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1273 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1275 /* Find TFD CB base pointer for given queue */
1276 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1279 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1281 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1282 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1287 * Rx SRAM Control and Status Registers (RSCSR)
1289 * These registers provide handshake between driver and device for the Rx queue
1290 * (this queue handles *all* command responses, notifications, Rx data, etc.
1291 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1292 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1293 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1294 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1295 * mapping between RBDs and RBs.
1297 * Driver must allocate host DRAM memory for the following, and set the
1298 * physical address of each into device registers:
1300 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1301 * entries (although any power of 2, up to 4096, is selectable by driver).
1302 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1303 * (typically 4K, although 8K or 16K are also selectable by driver).
1304 * Driver sets up RB size and number of RBDs in the CB via Rx config
1305 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1307 * Bit fields within one RBD:
1308 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1310 * Driver sets physical address [35:8] of base of RBD circular buffer
1311 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1313 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1314 * (RBs) have been filled, via a "write pointer", actually the index of
1315 * the RB's corresponding RBD within the circular buffer. Driver sets
1316 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1318 * Bit fields in lower dword of Rx status buffer (upper dword not used
1320 * 31-12: Not used by driver
1321 * 11- 0: Index of last filled Rx buffer descriptor
1322 * (device writes, driver reads this value)
1324 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1325 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1326 * and update the device's "write" index register,
1327 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1329 * This "write" index corresponds to the *next* RBD that the driver will make
1330 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1331 * the circular buffer. This value should initially be 0 (before preparing any
1332 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1333 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1334 * "read" index has advanced past 1! See below).
1335 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1337 * As the device fills RBs (referenced from contiguous RBDs within the circular
1338 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1339 * to tell the driver the index of the latest filled RBD. The driver must
1340 * read this "read" index from DRAM after receiving an Rx interrupt from device
1342 * The driver must also internally keep track of a third index, which is the
1343 * next RBD to process. When receiving an Rx interrupt, driver should process
1344 * all filled but unprocessed RBs up to, but not including, the RB
1345 * corresponding to the "read" index. For example, if "read" index becomes "1",
1346 * driver may process the RB pointed to by RBD 0. Depending on volume of
1347 * traffic, there may be many RBs to process.
1349 * If read index == write index, device thinks there is no room to put new data.
1350 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1351 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1352 * and "read" indexes; that is, make sure that there are no more than 254
1353 * buffers waiting to be filled.
1355 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1356 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1357 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1360 * Physical base address of 8-byte Rx Status buffer.
1362 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1364 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1367 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1369 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1371 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1374 * Rx write pointer (index, really!).
1376 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1377 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1379 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1380 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1382 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1383 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1386 * Rx Config/Status Registers (RCSR)
1387 * Rx Config Reg for channel 0 (only channel used)
1389 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1390 * normal operation (see bit fields).
1392 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1393 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1394 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1397 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1398 * '10' operate normally
1400 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1401 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1403 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1404 * '10' 12K, '11' 16K.
1406 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1407 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1408 * typical value 0x10 (about 1/2 msec)
1411 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1412 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1413 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1415 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1416 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1417 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1419 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1420 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1421 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1422 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1423 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1424 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1426 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1427 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1428 #define IWM_RX_RB_TIMEOUT (0x11)
1430 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1431 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1432 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1434 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1435 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1436 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1437 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1439 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1440 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1441 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1444 * Rx Shared Status Registers (RSSR)
1446 * After stopping Rx DMA channel (writing 0 to
1447 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1448 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1451 * 24: 1 = Channel 0 is idle
1453 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1454 * contain default values that should not be altered by the driver.
1456 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1457 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1459 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1460 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1461 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1462 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1464 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1466 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1468 /* TFDB Area - TFDs buffer table */
1469 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1470 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1471 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1472 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1473 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1476 * Transmit DMA Channel Control/Status Registers (TCSR)
1478 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1479 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1480 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1482 * To use a Tx DMA channel, driver must initialize its
1483 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1485 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1486 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1488 * All other bits should be 0.
1491 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1492 * '10' operate normally
1493 * 29- 4: Reserved, set to "0"
1494 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1495 * 2- 0: Reserved, set to "0"
1497 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1498 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1500 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1501 #define IWM_FH_TCSR_CHNL_NUM (8)
1503 /* TCSR: tx_config register values */
1504 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1505 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1506 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1507 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1508 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1509 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1511 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1512 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1514 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1515 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1517 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1518 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1519 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1521 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1522 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1523 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1525 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1526 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1527 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1529 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1530 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1531 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1533 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1534 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1537 * Tx Shared Status Registers (TSSR)
1539 * After stopping Tx DMA channel (writing 0 to
1540 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1541 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1542 * (channel's buffers empty | no pending requests).
1545 * 31-24: 1 = Channel buffers empty (channel 7:0)
1546 * 23-16: 1 = No pending requests (channel 7:0)
1548 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1549 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1551 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1554 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1555 * 31: Indicates an address error when accessed to internal memory
1556 * uCode/driver must write "1" in order to clear this flag
1557 * 30: Indicates that Host did not send the expected number of dwords to FH
1558 * uCode/driver must write "1" in order to clear this flag
1559 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1560 * command was received from the scheduler while the TRB was already full
1561 * with previous command
1562 * uCode/driver must write "1" in order to clear this flag
1563 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1564 * bit is set, it indicates that the FH has received a full indication
1565 * from the RTC TxFIFO and the current value of the TxCredit counter was
1566 * not equal to zero. This mean that the credit mechanism was not
1567 * synchronized to the TxFIFO status
1568 * uCode/driver must write "1" in order to clear this flag
1570 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1571 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1573 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1575 /* Tx service channels */
1576 #define IWM_FH_SRVC_CHNL (9)
1577 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1578 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1579 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1580 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1582 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1583 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1586 /* Instruct FH to increment the retry count of a packet when
1587 * it is brought from the memory to TX-FIFO
1589 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1591 #define IWM_RX_QUEUE_SIZE 256
1592 #define IWM_RX_QUEUE_MASK 255
1593 #define IWM_RX_QUEUE_SIZE_LOG 8
1596 * RX related structures and functions
1598 #define IWM_RX_FREE_BUFFERS 64
1599 #define IWM_RX_LOW_WATERMARK 8
1602 * struct iwm_rb_status - reseve buffer status
1603 * host memory mapped FH registers
1604 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1605 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1606 * @finished_rb_num [0:11] - Indicates the index of the current RB
1607 * in which the last frame was written to
1608 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1609 * which was transferred
1611 struct iwm_rb_status {
1612 uint16_t closed_rb_num;
1613 uint16_t closed_fr_num;
1614 uint16_t finished_rb_num;
1615 uint16_t finished_fr_nam;
1620 #define IWM_TFD_QUEUE_SIZE_MAX (256)
1621 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1622 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1623 IWM_TFD_QUEUE_SIZE_BC_DUP)
1624 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1625 #define IWM_NUM_OF_TBS 20
1627 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1629 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1632 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1634 * This structure contains dma address and length of transmission address
1636 * @lo: low [31:0] portion of the dma address of TX buffer
1637 * every even is unaligned on 16 bit boundary
1638 * @hi_n_len 0-3 [35:32] portion of dma
1639 * 4-15 length of the tx buffer
1649 * Transmit Frame Descriptor (TFD)
1651 * @ __reserved1[3] reserved
1652 * @ num_tbs 0-4 number of active tbs
1654 * 6-7 padding (not used)
1655 * @ tbs[20] transmit frame buffer descriptors
1658 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1659 * Both driver and device share these circular buffers, each of which must be
1660 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1662 * Driver must indicate the physical address of the base of each
1663 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1665 * Each TFD contains pointer/size information for up to 20 data buffers
1666 * in host DRAM. These buffers collectively contain the (one) frame described
1667 * by the TFD. Each buffer must be a single contiguous block of memory within
1668 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1669 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1670 * Tx frame, up to 8 KBytes in size.
1672 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1675 uint8_t __reserved1[3];
1677 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1681 /* Keep Warm Size */
1682 #define IWM_KW_SIZE 0x1000 /* 4k */
1684 /* Fixed (non-configurable) rx data from phy */
1687 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1688 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1689 * @tfd_offset 0-12 - tx command byte count
1690 * 12-16 - station index
1692 struct iwm_agn_scd_bc_tbl {
1693 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1696 /* Maximum number of Tx queues. */
1697 #define IWM_MVM_MAX_QUEUES 31
1699 /* Tx queue numbers */
1701 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1702 IWM_MVM_CMD_QUEUE = 9,
1703 IWM_MVM_AUX_QUEUE = 15,
1706 enum iwm_mvm_tx_fifo {
1707 IWM_MVM_TX_FIFO_BK = 0,
1711 IWM_MVM_TX_FIFO_MCAST = 5,
1712 IWM_MVM_TX_FIFO_CMD = 7,
1715 #define IWM_MVM_STATION_COUNT 16
1719 IWM_MVM_ALIVE = 0x1,
1720 IWM_REPLY_ERROR = 0x2,
1722 IWM_INIT_COMPLETE_NOTIF = 0x4,
1724 /* PHY context commands */
1725 IWM_PHY_CONTEXT_CMD = 0x8,
1728 /* UMAC scan commands */
1729 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
1730 IWM_SCAN_CFG_CMD = 0xc,
1731 IWM_SCAN_REQ_UMAC = 0xd,
1732 IWM_SCAN_ABORT_UMAC = 0xe,
1733 IWM_SCAN_COMPLETE_UMAC = 0xf,
1736 IWM_ADD_STA_KEY = 0x17,
1738 IWM_REMOVE_STA = 0x19,
1742 IWM_TXPATH_FLUSH = 0x1e,
1743 IWM_MGMT_MCAST_KEY = 0x1f,
1745 /* scheduler config */
1746 IWM_SCD_QUEUE_CFG = 0x1d,
1751 /* MAC and Binding commands */
1752 IWM_MAC_CONTEXT_CMD = 0x28,
1753 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1754 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1755 IWM_BINDING_CONTEXT_CMD = 0x2b,
1756 IWM_TIME_QUOTA_CMD = 0x2c,
1757 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1761 /* paging block to FW cpu2 */
1762 IWM_FW_PAGING_BLOCK_CMD = 0x4f,
1765 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1766 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1767 IWM_HOT_SPOT_CMD = 0x53,
1768 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d,
1769 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e,
1770 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1771 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1772 IWM_SCAN_ITERATION_COMPLETE = 0xe7,
1775 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1776 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1777 /* IWM_PHY_DB_CMD = 0x6c, */
1779 /* Power - legacy power table command */
1780 IWM_POWER_TABLE_CMD = 0x77,
1781 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1783 /* Thermal Throttling*/
1784 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1787 IWM_SCAN_ABORT_CMD = 0x81,
1788 IWM_SCAN_START_NOTIFICATION = 0x82,
1789 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
1792 IWM_NVM_ACCESS_CMD = 0x88,
1794 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1796 IWM_BEACON_NOTIFICATION = 0x90,
1797 IWM_BEACON_TEMPLATE_CMD = 0x91,
1798 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1799 IWM_BT_CONFIG = 0x9b,
1800 IWM_STATISTICS_NOTIFICATION = 0x9d,
1801 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1803 /* RF-KILL commands and notifications */
1804 IWM_CARD_STATE_CMD = 0xa0,
1805 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1807 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1809 IWM_MFUART_LOAD_NOTIFICATION = 0xb1,
1811 /* Power - new power table command */
1812 IWM_MAC_PM_POWER_TABLE = 0xa9,
1814 IWM_REPLY_RX_PHY_CMD = 0xc0,
1815 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1816 IWM_BA_NOTIF = 0xc5,
1818 /* Location Aware Regulatory */
1819 IWM_MCC_UPDATE_CMD = 0xc8,
1820 IWM_MCC_CHUB_UPDATE_CMD = 0xc9,
1823 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1824 IWM_BT_COEX_PROT_ENV = 0xcd,
1825 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1826 IWM_BT_COEX_CI = 0x5d,
1828 IWM_REPLY_SF_CFG_CMD = 0xd1,
1829 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1831 /* DTS measurements */
1832 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
1833 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd,
1835 IWM_REPLY_DEBUG_CMD = 0xf0,
1836 IWM_DEBUG_LOG_MSG = 0xf7,
1838 IWM_MCAST_FILTER_CMD = 0xd0,
1840 /* D3 commands/notifications */
1841 IWM_D3_CONFIG_CMD = 0xd3,
1842 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1843 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1844 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1846 /* for WoWLAN in particular */
1847 IWM_WOWLAN_PATTERNS = 0xe0,
1848 IWM_WOWLAN_CONFIGURATION = 0xe1,
1849 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1850 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1851 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1852 IWM_WOWLAN_GET_STATUSES = 0xe5,
1853 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1855 /* and for NetDetect */
1856 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1857 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1858 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1859 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1860 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1862 IWM_REPLY_MAX = 0xff,
1865 enum iwm_phy_ops_subcmd_ids {
1866 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0,
1867 IWM_CTDP_CONFIG_CMD = 0x03,
1868 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04,
1869 IWM_CT_KILL_NOTIFICATION = 0xFE,
1870 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF,
1873 /* command groups */
1875 IWM_LEGACY_GROUP = 0x0,
1876 IWM_LONG_GROUP = 0x1,
1877 IWM_SYSTEM_GROUP = 0x2,
1878 IWM_MAC_CONF_GROUP = 0x3,
1879 IWM_PHY_OPS_GROUP = 0x4,
1880 IWM_DATA_PATH_GROUP = 0x5,
1881 IWM_PROT_OFFLOAD_GROUP = 0xb,
1885 * struct iwm_cmd_response - generic response struct for most commands
1886 * @status: status of the command asked, changes for each one
1888 struct iwm_cmd_response {
1893 * struct iwm_tx_ant_cfg_cmd
1894 * @valid: valid antenna configuration
1896 struct iwm_tx_ant_cfg_cmd {
1901 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1902 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1903 * @flags: (reserved for future implementation)
1904 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1905 * @pwr_restriction: TX power restriction in dBms.
1907 struct iwm_reduce_tx_power_cmd {
1909 uint8_t mac_context_id;
1910 uint16_t pwr_restriction;
1911 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1914 * Calibration control struct.
1915 * Sent as part of the phy configuration command.
1916 * @flow_trigger: bitmap for which calibrations to perform according to
1918 * @event_trigger: bitmap for which calibrations to perform according to
1921 struct iwm_calib_ctrl {
1922 uint32_t flow_trigger;
1923 uint32_t event_trigger;
1926 /* This enum defines the bitmap of various calibrations to enable in both
1927 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1929 enum iwm_calib_cfg {
1930 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1931 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
1932 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
1933 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
1934 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
1935 IWM_CALIB_CFG_DC_IDX = (1 << 5),
1936 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
1937 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
1938 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
1939 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
1940 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
1941 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
1942 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
1943 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
1944 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
1945 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
1946 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
1947 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
1948 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
1952 * Phy configuration command.
1954 struct iwm_phy_cfg_cmd {
1956 struct iwm_calib_ctrl calib_control;
1959 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1960 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1961 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1962 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1963 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1964 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1965 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1966 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1967 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1968 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1971 /* Target of the IWM_NVM_ACCESS_CMD */
1973 IWM_NVM_ACCESS_TARGET_CACHE = 0,
1974 IWM_NVM_ACCESS_TARGET_OTP = 1,
1975 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
1978 /* Section types for IWM_NVM_ACCESS_CMD */
1980 IWM_NVM_SECTION_TYPE_SW = 1,
1981 IWM_NVM_SECTION_TYPE_REGULATORY = 3,
1982 IWM_NVM_SECTION_TYPE_CALIBRATION = 4,
1983 IWM_NVM_SECTION_TYPE_PRODUCTION = 5,
1984 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
1985 IWM_NVM_SECTION_TYPE_PHY_SKU = 12,
1986 IWM_NVM_MAX_NUM_SECTIONS = 13,
1990 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
1991 * @op_code: 0 - read, 1 - write
1992 * @target: IWM_NVM_ACCESS_TARGET_*
1993 * @type: IWM_NVM_SECTION_TYPE_*
1994 * @offset: offset in bytes into the section
1995 * @length: in bytes, to read/write
1996 * @data: if write operation, the data to write. On read its empty
1998 struct iwm_nvm_access_cmd {
2005 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2007 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */
2010 * struct iwm_fw_paging_cmd - paging layout
2012 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f)
2014 * Send to FW the paging layout in the driver.
2016 * @flags: various flags for the command
2017 * @block_size: the block size in powers of 2
2018 * @block_num: number of blocks specified in the command.
2019 * @device_phy_addr: virtual addresses from device side
2021 struct iwm_fw_paging_cmd {
2023 uint32_t block_size;
2025 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS];
2026 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */
2031 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload
2034 enum iwm_fw_item_id {
2035 IWM_FW_ITEM_ID_PAGING = 3,
2039 * struct iwm_fw_get_item_cmd - get an item from the fw
2041 struct iwm_fw_get_item_cmd {
2043 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */
2046 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2047 * @offset: offset in bytes into the section
2048 * @length: in bytes, either how much was written or read
2049 * @type: IWM_NVM_SECTION_TYPE_*
2050 * @status: 0 for success, fail otherwise
2051 * @data: if read operation, the data returned. Empty on write.
2053 struct iwm_nvm_access_resp {
2059 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
2061 /* IWM_MVM_ALIVE 0x1 */
2063 /* alive response is_valid values */
2064 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2065 #define IWM_ALIVE_RESP_RFKILL (1 << 1)
2067 /* alive response ver_type values */
2070 IWM_FW_TYPE_PROT = 1,
2072 IWM_FW_TYPE_WOWLAN = 3,
2073 IWM_FW_TYPE_TIMING = 4,
2074 IWM_FW_TYPE_WIPAN = 5
2077 /* alive response ver_subtype values */
2079 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
2080 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
2081 IWM_FW_SUBTYPE_REDUCED = 2,
2082 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
2083 IWM_FW_SUBTYPE_WOWLAN = 4,
2084 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
2085 IWM_FW_SUBTYPE_WIPAN = 6,
2086 IWM_FW_SUBTYPE_INITIALIZE = 9
2089 #define IWM_ALIVE_STATUS_ERR 0xDEAD
2090 #define IWM_ALIVE_STATUS_OK 0xCAFE
2092 #define IWM_ALIVE_FLG_RFKILL (1 << 0)
2094 struct iwm_mvm_alive_resp_ver1 {
2097 uint8_t ucode_minor;
2098 uint8_t ucode_major;
2102 uint8_t ver_subtype;
2108 uint32_t error_event_table_ptr; /* SRAM address for error log */
2109 uint32_t log_event_table_ptr; /* SRAM address for event log */
2110 uint32_t cpu_register_ptr;
2111 uint32_t dbgm_config_ptr;
2112 uint32_t alive_counter_ptr;
2113 uint32_t scd_base_ptr; /* SRAM address for SCD */
2114 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
2116 struct iwm_mvm_alive_resp_ver2 {
2119 uint8_t ucode_minor;
2120 uint8_t ucode_major;
2124 uint8_t ver_subtype;
2130 uint32_t error_event_table_ptr; /* SRAM address for error log */
2131 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2132 uint32_t cpu_register_ptr;
2133 uint32_t dbgm_config_ptr;
2134 uint32_t alive_counter_ptr;
2135 uint32_t scd_base_ptr; /* SRAM address for SCD */
2136 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2137 uint32_t st_fwrd_size;
2138 uint8_t umac_minor; /* UMAC version: minor */
2139 uint8_t umac_major; /* UMAC version: major */
2140 uint16_t umac_id; /* UMAC version: id */
2141 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2142 uint32_t dbg_print_buff_addr;
2143 } __packed; /* ALIVE_RES_API_S_VER_2 */
2145 struct iwm_mvm_alive_resp {
2148 uint32_t ucode_minor;
2149 uint32_t ucode_major;
2150 uint8_t ver_subtype;
2155 uint32_t error_event_table_ptr; /* SRAM address for error log */
2156 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2157 uint32_t cpu_register_ptr;
2158 uint32_t dbgm_config_ptr;
2159 uint32_t alive_counter_ptr;
2160 uint32_t scd_base_ptr; /* SRAM address for SCD */
2161 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2162 uint32_t st_fwrd_size;
2163 uint32_t umac_minor; /* UMAC version: minor */
2164 uint32_t umac_major; /* UMAC version: major */
2165 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2166 uint32_t dbg_print_buff_addr;
2167 } __packed; /* ALIVE_RES_API_S_VER_3 */
2169 /* Error response/notification */
2171 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
2172 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
2173 IWM_FW_ERR_SERVICE = 0x2,
2174 IWM_FW_ERR_ARC_MEMORY = 0x3,
2175 IWM_FW_ERR_ARC_CODE = 0x4,
2176 IWM_FW_ERR_WATCH_DOG = 0x5,
2177 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
2178 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
2179 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
2180 IWM_FW_ERR_UNEXPECTED = 0xFE,
2181 IWM_FW_ERR_FATAL = 0xFF
2185 * struct iwm_error_resp - FW error indication
2186 * ( IWM_REPLY_ERROR = 0x2 )
2187 * @error_type: one of IWM_FW_ERR_*
2188 * @cmd_id: the command ID for which the error occurred
2189 * @bad_cmd_seq_num: sequence number of the erroneous command
2190 * @error_service: which service created the error, applicable only if
2191 * error_type = 2, otherwise 0
2192 * @timestamp: TSF in usecs.
2194 struct iwm_error_resp {
2195 uint32_t error_type;
2198 uint16_t bad_cmd_seq_num;
2199 uint32_t error_service;
2204 /* Common PHY, MAC and Bindings definitions */
2206 #define IWM_MAX_MACS_IN_BINDING (3)
2207 #define IWM_MAX_BINDINGS (4)
2208 #define IWM_AUX_BINDING_INDEX (3)
2209 #define IWM_MAX_PHYS (4)
2211 /* Used to extract ID and color from the context dword */
2212 #define IWM_FW_CTXT_ID_POS (0)
2213 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2214 #define IWM_FW_CTXT_COLOR_POS (8)
2215 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2216 #define IWM_FW_CTXT_INVALID (0xffffffff)
2218 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2219 (_color << IWM_FW_CTXT_COLOR_POS))
2221 /* Possible actions on PHYs, MACs and Bindings */
2223 IWM_FW_CTXT_ACTION_STUB = 0,
2224 IWM_FW_CTXT_ACTION_ADD,
2225 IWM_FW_CTXT_ACTION_MODIFY,
2226 IWM_FW_CTXT_ACTION_REMOVE,
2227 IWM_FW_CTXT_ACTION_NUM
2228 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2232 /* Time Event types, according to MAC type */
2233 enum iwm_time_event_type {
2234 /* BSS Station Events */
2235 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
2236 IWM_TE_BSS_STA_ASSOC,
2237 IWM_TE_BSS_EAP_DHCP_PROT,
2238 IWM_TE_BSS_QUIET_PERIOD,
2240 /* P2P Device Events */
2241 IWM_TE_P2P_DEVICE_DISCOVERABLE,
2242 IWM_TE_P2P_DEVICE_LISTEN,
2243 IWM_TE_P2P_DEVICE_ACTION_SCAN,
2244 IWM_TE_P2P_DEVICE_FULL_SCAN,
2246 /* P2P Client Events */
2247 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
2248 IWM_TE_P2P_CLIENT_ASSOC,
2249 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
2252 IWM_TE_P2P_GO_ASSOC_PROT,
2253 IWM_TE_P2P_GO_REPETITIVE_NOA,
2254 IWM_TE_P2P_GO_CT_WINDOW,
2256 /* WiDi Sync Events */
2257 IWM_TE_WIDI_TX_SYNC,
2260 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2264 /* Time event - defines for command API v1 */
2267 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2268 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2269 * the first fragment is scheduled.
2270 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2271 * the first 2 fragments are scheduled.
2272 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2273 * number of fragments are valid.
2275 * Other than the constant defined above, specifying a fragmentation value 'x'
2276 * means that the event can be fragmented but only the first 'x' will be
2280 IWM_TE_V1_FRAG_NONE = 0,
2281 IWM_TE_V1_FRAG_SINGLE = 1,
2282 IWM_TE_V1_FRAG_DUAL = 2,
2283 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
2286 /* If a Time Event can be fragmented, this is the max number of fragments */
2287 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2288 /* Repeat the time event endlessly (until removed) */
2289 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2290 /* If a Time Event has bounded repetitions, this is the maximal value */
2291 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2293 /* Time Event dependencies: none, on another TE, or in a specific time */
2295 IWM_TE_V1_INDEPENDENT = 0,
2296 IWM_TE_V1_DEP_OTHER = (1 << 0),
2297 IWM_TE_V1_DEP_TSF = (1 << 1),
2298 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
2299 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2302 * @IWM_TE_V1_NOTIF_NONE: no notifications
2303 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2304 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2305 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2306 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2307 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2308 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2309 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2310 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2312 * Supported Time event notifications configuration.
2313 * A notification (both event and fragment) includes a status indicating weather
2314 * the FW was able to schedule the event or not. For fragment start/end
2315 * notification the status is always success. There is no start/end fragment
2316 * notification for monolithic events.
2319 IWM_TE_V1_NOTIF_NONE = 0,
2320 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2321 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2322 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2323 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2324 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2325 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2326 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2327 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2328 IWM_T2_V2_START_IMMEDIATELY = (1 << 11),
2329 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2331 /* Time event - defines for command API */
2334 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2335 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2336 * the first fragment is scheduled.
2337 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2338 * the first 2 fragments are scheduled.
2339 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2340 * number of fragments are valid.
2342 * Other than the constant defined above, specifying a fragmentation value 'x'
2343 * means that the event can be fragmented but only the first 'x' will be
2347 IWM_TE_V2_FRAG_NONE = 0,
2348 IWM_TE_V2_FRAG_SINGLE = 1,
2349 IWM_TE_V2_FRAG_DUAL = 2,
2350 IWM_TE_V2_FRAG_MAX = 0xfe,
2351 IWM_TE_V2_FRAG_ENDLESS = 0xff
2354 /* Repeat the time event endlessly (until removed) */
2355 #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2356 /* If a Time Event has bounded repetitions, this is the maximal value */
2357 #define IWM_TE_V2_REPEAT_MAX 0xfe
2359 #define IWM_TE_V2_PLACEMENT_POS 12
2360 #define IWM_TE_V2_ABSENCE_POS 15
2362 /* Time event policy values
2363 * A notification (both event and fragment) includes a status indicating weather
2364 * the FW was able to schedule the event or not. For fragment start/end
2365 * notification the status is always success. There is no start/end fragment
2366 * notification for monolithic events.
2368 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2369 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2370 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2371 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2372 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2373 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2374 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2375 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2376 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2377 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2378 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2379 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2380 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2383 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2385 /* notifications (event start/stop, fragment start/stop) */
2386 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2387 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2388 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2389 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2391 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2392 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2393 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2394 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2396 IWM_TE_V2_NOTIF_MSK = 0xff,
2398 /* placement characteristics */
2399 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2400 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2401 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2403 /* are we present or absent during the Time Event. */
2404 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2408 * struct iwm_time_event_cmd_api - configuring Time Events
2409 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2410 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2411 * ( IWM_TIME_EVENT_CMD = 0x29 )
2412 * @id_and_color: ID and color of the relevant MAC
2413 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2414 * @id: this field has two meanings, depending on the action:
2415 * If the action is ADD, then it means the type of event to add.
2416 * For all other actions it is the unique event ID assigned when the
2417 * event was added by the FW.
2418 * @apply_time: When to start the Time Event (in GP2)
2419 * @max_delay: maximum delay to event's start (apply time), in TU
2420 * @depends_on: the unique ID of the event we depend on (if any)
2421 * @interval: interval between repetitions, in TU
2422 * @duration: duration of event in TU
2423 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2424 * @max_frags: maximal number of fragments the Time Event can be divided to
2425 * @policy: defines whether uCode shall notify the host or other uCode modules
2426 * on event and/or fragment start and/or end
2427 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2428 * IWM_TE_EVENT_SOCIOPATHIC
2429 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2431 struct iwm_time_event_cmd {
2432 /* COMMON_INDEX_HDR_API_S_VER_1 */
2433 uint32_t id_and_color;
2436 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2437 uint32_t apply_time;
2439 uint32_t depends_on;
2445 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2448 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2449 * @status: bit 0 indicates success, all others specify errors
2450 * @id: the Time Event type
2451 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2452 * @id_and_color: ID and color of the relevant MAC
2454 struct iwm_time_event_resp {
2458 uint32_t id_and_color;
2459 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2462 * struct iwm_time_event_notif - notifications of time event start/stop
2463 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2464 * @timestamp: action timestamp in GP2
2465 * @session_id: session's unique id
2466 * @unique_id: unique id of the Time Event itself
2467 * @id_and_color: ID and color of the relevant MAC
2468 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2469 * @status: true if scheduled, false otherwise (not executed)
2471 struct iwm_time_event_notif {
2473 uint32_t session_id;
2475 uint32_t id_and_color;
2478 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2481 /* Bindings and Time Quota */
2484 * struct iwm_binding_cmd - configuring bindings
2485 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2486 * @id_and_color: ID and color of the relevant Binding
2487 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2488 * @macs: array of MAC id and colors which belong to the binding
2489 * @phy: PHY id and color which belongs to the binding
2491 struct iwm_binding_cmd {
2492 /* COMMON_INDEX_HDR_API_S_VER_1 */
2493 uint32_t id_and_color;
2495 /* IWM_BINDING_DATA_API_S_VER_1 */
2496 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2498 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2500 /* The maximal number of fragments in the FW's schedule session */
2501 #define IWM_MVM_MAX_QUOTA 128
2504 * struct iwm_time_quota_data - configuration of time quota per binding
2505 * @id_and_color: ID and color of the relevant Binding
2506 * @quota: absolute time quota in TU. The scheduler will try to divide the
2507 * remainig quota (after Time Events) according to this quota.
2508 * @max_duration: max uninterrupted context duration in TU
2510 struct iwm_time_quota_data {
2511 uint32_t id_and_color;
2513 uint32_t max_duration;
2514 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2517 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2518 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2519 * @quotas: allocations per binding
2521 struct iwm_time_quota_cmd {
2522 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2523 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2528 /* Supported bands */
2529 #define IWM_PHY_BAND_5 (0)
2530 #define IWM_PHY_BAND_24 (1)
2532 /* Supported channel width, vary if there is VHT support */
2533 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2534 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2535 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2536 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2539 * Control channel position:
2540 * For legacy set bit means upper channel, otherwise lower.
2541 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2542 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2545 * 40Mhz |_______|_______|
2546 * 80Mhz |_______|_______|_______|_______|
2547 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2548 * code 011 010 001 000 | 100 101 110 111
2550 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2551 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2552 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2553 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2554 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2555 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2556 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2557 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2560 * @band: IWM_PHY_BAND_*
2561 * @channel: channel number
2562 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2563 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2565 struct iwm_fw_channel_info {
2572 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2573 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2574 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2575 #define IWM_PHY_RX_CHAIN_VALID_POS (1)
2576 #define IWM_PHY_RX_CHAIN_VALID_MSK \
2577 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2578 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2579 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2580 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2581 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2582 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2583 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2584 #define IWM_PHY_RX_CHAIN_CNT_POS (10)
2585 #define IWM_PHY_RX_CHAIN_CNT_MSK \
2586 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2587 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2588 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2589 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2590 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2591 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2592 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2594 /* TODO: fix the value, make it depend on firmware at runtime? */
2595 #define IWM_NUM_PHY_CTX 3
2597 /* TODO: complete missing documentation */
2599 * struct iwm_phy_context_cmd - config of the PHY context
2600 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2601 * @id_and_color: ID and color of the relevant Binding
2602 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2603 * @apply_time: 0 means immediate apply and context switch.
2604 * other value means apply new params after X usecs
2605 * @tx_param_color: ???
2607 * @txchain_info: ???
2608 * @rxchain_info: ???
2609 * @acquisition_data: ???
2610 * @dsp_cfg_flags: set to 0
2612 struct iwm_phy_context_cmd {
2613 /* COMMON_INDEX_HDR_API_S_VER_1 */
2614 uint32_t id_and_color;
2616 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2617 uint32_t apply_time;
2618 uint32_t tx_param_color;
2619 struct iwm_fw_channel_info ci;
2620 uint32_t txchain_info;
2621 uint32_t rxchain_info;
2622 uint32_t acquisition_data;
2623 uint32_t dsp_cfg_flags;
2624 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2626 #define IWM_RX_INFO_PHY_CNT 8
2627 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2628 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2629 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2630 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2631 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2632 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2633 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2635 #define IWM_RX_INFO_AGC_IDX 1
2636 #define IWM_RX_INFO_RSSI_AB_IDX 2
2637 #define IWM_OFDM_AGC_A_MSK 0x0000007f
2638 #define IWM_OFDM_AGC_A_POS 0
2639 #define IWM_OFDM_AGC_B_MSK 0x00003f80
2640 #define IWM_OFDM_AGC_B_POS 7
2641 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2642 #define IWM_OFDM_AGC_CODE_POS 20
2643 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2644 #define IWM_OFDM_RSSI_A_POS 0
2645 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2646 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2647 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2648 #define IWM_OFDM_RSSI_B_POS 16
2649 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2650 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2653 * struct iwm_rx_phy_info - phy info
2654 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2655 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2656 * @cfg_phy_cnt: configurable DSP phy data byte count
2657 * @stat_id: configurable DSP phy data set ID
2659 * @system_timestamp: GP2 at on air rise
2660 * @timestamp: TSF at on air rise
2661 * @beacon_time_stamp: beacon at on-air rise
2662 * @phy_flags: general phy flags: band, modulation, ...
2663 * @channel: channel number
2664 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2665 * @rate_n_flags: IWM_RATE_MCS_*
2666 * @byte_count: frame's byte-count
2667 * @frame_time: frame's time on the air, based on byte count and frame rate
2669 * @mac_active_msk: what MACs were active when the frame was received
2671 * Before each Rx, the device sends this data. It contains PHY information
2672 * about the reception of the packet.
2674 struct iwm_rx_phy_info {
2675 uint8_t non_cfg_phy_cnt;
2676 uint8_t cfg_phy_cnt;
2679 uint32_t system_timestamp;
2681 uint32_t beacon_time_stamp;
2683 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2685 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2689 uint32_t byte_count;
2690 uint16_t mac_active_msk;
2691 uint16_t frame_time;
2694 struct iwm_rx_mpdu_res_start {
2695 uint16_t byte_count;
2700 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2701 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2702 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2703 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2704 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2705 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2706 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2707 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2708 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2709 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2711 enum iwm_rx_phy_flags {
2712 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2713 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2714 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2715 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2716 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2717 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2718 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2719 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2720 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2721 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2725 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2726 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2727 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2728 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2729 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2730 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2731 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2732 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2734 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2735 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2736 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2737 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2738 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2739 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2740 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2741 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2742 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2743 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2744 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2745 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2746 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2747 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2748 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2749 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2750 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2751 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2752 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2753 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2754 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2756 enum iwm_mvm_rx_status {
2757 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2758 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2759 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2760 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2761 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2762 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2763 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2764 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2765 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2766 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2767 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2768 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2769 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2770 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2771 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2772 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2773 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2774 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2775 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2776 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2777 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2778 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2779 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2780 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2781 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2782 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2783 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2787 * struct iwm_radio_version_notif - information on the radio version
2788 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2793 struct iwm_radio_version_notif {
2794 uint32_t radio_flavor;
2795 uint32_t radio_step;
2796 uint32_t radio_dash;
2797 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2799 enum iwm_card_state_flags {
2800 IWM_CARD_ENABLED = 0x00,
2801 IWM_HW_CARD_DISABLED = 0x01,
2802 IWM_SW_CARD_DISABLED = 0x02,
2803 IWM_CT_KILL_CARD_DISABLED = 0x04,
2804 IWM_HALT_CARD_DISABLED = 0x08,
2805 IWM_CARD_DISABLED_MSK = 0x0f,
2806 IWM_CARD_IS_RX_ON = 0x10,
2810 * struct iwm_radio_version_notif - information on the radio version
2811 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2812 * @flags: %iwm_card_state_flags
2814 struct iwm_card_state_notif {
2816 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2819 * struct iwm_missed_beacons_notif - information on missed beacons
2820 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2821 * @mac_id: interface ID
2822 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2823 * beacons since last RX.
2824 * @consec_missed_beacons: number of consecutive missed beacons
2825 * @num_expected_beacons:
2826 * @num_recvd_beacons:
2828 struct iwm_missed_beacons_notif {
2830 uint32_t consec_missed_beacons_since_last_rx;
2831 uint32_t consec_missed_beacons;
2832 uint32_t num_expected_beacons;
2833 uint32_t num_recvd_beacons;
2834 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2837 * struct iwm_mfuart_load_notif - mfuart image version & status
2838 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 )
2839 * @installed_ver: installed image version
2840 * @external_ver: external image version
2841 * @status: MFUART loading status
2842 * @duration: MFUART loading time
2844 struct iwm_mfuart_load_notif {
2845 uint32_t installed_ver;
2846 uint32_t external_ver;
2849 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
2852 * struct iwm_set_calib_default_cmd - set default value for calibration.
2853 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2854 * @calib_index: the calibration to set value for
2856 * @data: the value to set for the calibration result
2858 struct iwm_set_calib_default_cmd {
2859 uint16_t calib_index;
2862 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2864 #define IWM_MAX_PORT_ID_NUM 2
2865 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2868 * struct iwm_mcast_filter_cmd - configure multicast filter.
2869 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2870 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2871 * to identify network interface adopted in host-device IF.
2872 * It is used by FW as index in array of addresses. This array has
2873 * IWM_MAX_PORT_ID_NUM members.
2874 * @count: Number of MAC addresses in the array
2875 * @pass_all: Set 1 to pass all multicast packets.
2876 * @bssid: current association BSSID.
2877 * @addr_list: Place holder for array of MAC addresses.
2878 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2880 struct iwm_mcast_filter_cmd {
2886 uint8_t reserved[2];
2887 uint8_t addr_list[0];
2888 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2890 struct iwm_mvm_statistics_dbg {
2891 uint32_t burst_check;
2892 uint32_t burst_count;
2893 uint32_t wait_for_silence_timeout_cnt;
2894 uint32_t reserved[3];
2895 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2897 struct iwm_mvm_statistics_div {
2901 uint32_t probe_time;
2904 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2906 struct iwm_mvm_statistics_general_common {
2907 uint32_t temperature; /* radio temperature */
2908 uint32_t temperature_m; /* radio voltage */
2909 struct iwm_mvm_statistics_dbg dbg;
2910 uint32_t sleep_time;
2912 uint32_t slots_idle;
2913 uint32_t ttl_timestamp;
2914 struct iwm_mvm_statistics_div div;
2915 uint32_t rx_enable_counter;
2917 * num_of_sos_states:
2918 * count the number of times we have to re-tune
2919 * in order to get out of bad PHY status
2921 uint32_t num_of_sos_states;
2922 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2924 struct iwm_mvm_statistics_rx_non_phy {
2925 uint32_t bogus_cts; /* CTS received when not expecting CTS */
2926 uint32_t bogus_ack; /* ACK received when not expecting ACK */
2927 uint32_t non_bssid_frames; /* number of frames with BSSID that
2928 * doesn't belong to the STA BSSID */
2929 uint32_t filtered_frames; /* count frames that were dumped in the
2930 * filtering process */
2931 uint32_t non_channel_beacons; /* beacons with our bss id but not on
2932 * our serving channel */
2933 uint32_t channel_beacons; /* beacons with our bss id and in our
2934 * serving channel */
2935 uint32_t num_missed_bcon; /* number of missed beacons */
2936 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
2937 * ADC was in saturation */
2938 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
2940 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
2941 uint32_t interference_data_flag; /* flag for interference data
2942 * availability. 1 when data is
2944 uint32_t channel_load; /* counts RX Enable time in uSec */
2945 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
2946 * and CCK) counter */
2947 uint32_t beacon_rssi_a;
2948 uint32_t beacon_rssi_b;
2949 uint32_t beacon_rssi_c;
2950 uint32_t beacon_energy_a;
2951 uint32_t beacon_energy_b;
2952 uint32_t beacon_energy_c;
2953 uint32_t num_bt_kills;
2955 uint32_t directed_data_mpdu;
2956 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
2958 struct iwm_mvm_statistics_rx_phy {
2963 uint32_t overrun_err;
2964 uint32_t early_overrun_err;
2965 uint32_t crc32_good;
2966 uint32_t false_alarm_cnt;
2967 uint32_t fina_sync_err_cnt;
2968 uint32_t sfd_timeout;
2969 uint32_t fina_timeout;
2970 uint32_t unresponded_rts;
2971 uint32_t rxe_frame_limit_overrun;
2972 uint32_t sent_ack_cnt;
2973 uint32_t sent_cts_cnt;
2974 uint32_t sent_ba_rsp_cnt;
2975 uint32_t dsp_self_kill;
2976 uint32_t mh_format_err;
2977 uint32_t re_acq_main_rssi_sum;
2979 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
2981 struct iwm_mvm_statistics_rx_ht_phy {
2983 uint32_t overrun_err;
2984 uint32_t early_overrun_err;
2985 uint32_t crc32_good;
2987 uint32_t mh_format_err;
2988 uint32_t agg_crc32_good;
2989 uint32_t agg_mpdu_cnt;
2991 uint32_t unsupport_mcs;
2992 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
2994 #define IWM_MAX_CHAINS 3
2996 struct iwm_mvm_statistics_tx_non_phy_agg {
2997 uint32_t ba_timeout;
2998 uint32_t ba_reschedule_frames;
2999 uint32_t scd_query_agg_frame_cnt;
3000 uint32_t scd_query_no_agg;
3001 uint32_t scd_query_agg;
3002 uint32_t scd_query_mismatch;
3003 uint32_t frame_not_ready;
3005 uint32_t bt_prio_kill;
3006 uint32_t rx_ba_rsp_cnt;
3007 int8_t txpower[IWM_MAX_CHAINS];
3010 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
3012 struct iwm_mvm_statistics_tx_channel_width {
3013 uint32_t ext_cca_narrow_ch20[1];
3014 uint32_t ext_cca_narrow_ch40[2];
3015 uint32_t ext_cca_narrow_ch80[3];
3016 uint32_t ext_cca_narrow_ch160[4];
3017 uint32_t last_tx_ch_width_indx;
3018 uint32_t rx_detected_per_ch_width[4];
3019 uint32_t success_per_ch_width[4];
3020 uint32_t fail_per_ch_width[4];
3021 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3023 struct iwm_mvm_statistics_tx {
3024 uint32_t preamble_cnt;
3025 uint32_t rx_detected_cnt;
3026 uint32_t bt_prio_defer_cnt;
3027 uint32_t bt_prio_kill_cnt;
3028 uint32_t few_bytes_cnt;
3029 uint32_t cts_timeout;
3030 uint32_t ack_timeout;
3031 uint32_t expected_ack_cnt;
3032 uint32_t actual_ack_cnt;
3033 uint32_t dump_msdu_cnt;
3034 uint32_t burst_abort_next_frame_mismatch_cnt;
3035 uint32_t burst_abort_missing_next_frame_cnt;
3036 uint32_t cts_timeout_collision;
3037 uint32_t ack_or_ba_timeout_collision;
3038 struct iwm_mvm_statistics_tx_non_phy_agg agg;
3039 struct iwm_mvm_statistics_tx_channel_width channel_width;
3040 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3043 struct iwm_mvm_statistics_bt_activity {
3044 uint32_t hi_priority_tx_req_cnt;
3045 uint32_t hi_priority_tx_denied_cnt;
3046 uint32_t lo_priority_tx_req_cnt;
3047 uint32_t lo_priority_tx_denied_cnt;
3048 uint32_t hi_priority_rx_req_cnt;
3049 uint32_t hi_priority_rx_denied_cnt;
3050 uint32_t lo_priority_rx_req_cnt;
3051 uint32_t lo_priority_rx_denied_cnt;
3052 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3054 struct iwm_mvm_statistics_general {
3055 struct iwm_mvm_statistics_general_common common;
3056 uint32_t beacon_filtered;
3057 uint32_t missed_beacons;
3058 int8_t beacon_filter_average_energy;
3059 int8_t beacon_filter_reason;
3060 int8_t beacon_filter_current_energy;
3061 int8_t beacon_filter_reserved;
3062 uint32_t beacon_filter_delta_time;
3063 struct iwm_mvm_statistics_bt_activity bt_activity;
3064 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
3066 struct iwm_mvm_statistics_rx {
3067 struct iwm_mvm_statistics_rx_phy ofdm;
3068 struct iwm_mvm_statistics_rx_phy cck;
3069 struct iwm_mvm_statistics_rx_non_phy general;
3070 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
3071 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3074 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3076 * By default, uCode issues this notification after receiving a beacon
3077 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3078 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
3080 * Statistics counters continue to increment beacon after beacon, but are
3081 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
3082 * 0x9c with CLEAR_STATS bit set (see above).
3084 * uCode also issues this notification during scans. uCode clears statistics
3085 * appropriately so that each notification contains statistics for only the
3086 * one channel that has just been scanned.
3089 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
3091 struct iwm_mvm_statistics_rx rx;
3092 struct iwm_mvm_statistics_tx tx;
3093 struct iwm_mvm_statistics_general general;
3096 /***********************************
3098 ***********************************/
3099 /* Smart Fifo state */
3101 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3105 IWM_SF_HW_NUM_STATES
3108 /* Smart Fifo possible scenario */
3109 enum iwm_sf_scenario {
3110 IWM_SF_SCENARIO_SINGLE_UNICAST,
3111 IWM_SF_SCENARIO_AGG_UNICAST,
3112 IWM_SF_SCENARIO_MULTICAST,
3113 IWM_SF_SCENARIO_BA_RESP,
3114 IWM_SF_SCENARIO_TX_RESP,
3118 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
3119 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
3121 /* smart FIFO default values */
3122 #define IWM_SF_W_MARK_SISO 4096
3123 #define IWM_SF_W_MARK_MIMO2 8192
3124 #define IWM_SF_W_MARK_MIMO3 6144
3125 #define IWM_SF_W_MARK_LEGACY 4096
3126 #define IWM_SF_W_MARK_SCAN 4096
3128 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3129 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3130 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3131 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3132 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3133 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3134 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3135 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3136 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3137 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3138 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3140 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3141 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3142 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3143 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3144 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3145 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
3146 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
3147 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
3148 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
3149 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
3150 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3152 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3154 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3157 * Smart Fifo configuration command.
3158 * @state: smart fifo state, types listed in enum %iwm_sf_state.
3159 * @watermark: Minimum allowed available free space in RXF for transient state.
3160 * @long_delay_timeouts: aging and idle timer values for each scenario
3161 * in long delay state.
3162 * @full_on_timeouts: timer values for each scenario in full on state.
3164 struct iwm_sf_cfg_cmd {
3166 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3167 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3168 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3169 } __packed; /* IWM_SF_CFG_API_S_VER_2 */
3172 * The first MAC indices (starting from 0)
3173 * are available to the driver, AUX follows
3175 #define IWM_MAC_INDEX_AUX 4
3176 #define IWM_MAC_INDEX_MIN_DRIVER 0
3177 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3188 * enum iwm_mac_protection_flags - MAC context flags
3189 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3190 * this will require CCK RTS/CTS2self.
3191 * RTS/CTS will protect full burst time.
3192 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3193 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3194 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3196 enum iwm_mac_protection_flags {
3197 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
3198 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
3199 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
3200 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
3203 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3204 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3207 * enum iwm_mac_types - Supported MAC types
3208 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3209 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3210 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3211 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3212 * @IWM_FW_MAC_TYPE_IBSS: IBSS
3213 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3214 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3215 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3216 * @IWM_FW_MAC_TYPE_GO: P2P GO
3217 * @IWM_FW_MAC_TYPE_TEST: ?
3218 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3220 enum iwm_mac_types {
3221 IWM_FW_MAC_TYPE_FIRST = 1,
3222 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
3223 IWM_FW_MAC_TYPE_LISTENER,
3224 IWM_FW_MAC_TYPE_PIBSS,
3225 IWM_FW_MAC_TYPE_IBSS,
3226 IWM_FW_MAC_TYPE_BSS_STA,
3227 IWM_FW_MAC_TYPE_P2P_DEVICE,
3228 IWM_FW_MAC_TYPE_P2P_STA,
3230 IWM_FW_MAC_TYPE_TEST,
3231 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
3232 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3235 * enum iwm_tsf_id - TSF hw timer ID
3236 * @IWM_TSF_ID_A: use TSF A
3237 * @IWM_TSF_ID_B: use TSF B
3238 * @IWM_TSF_ID_C: use TSF C
3239 * @IWM_TSF_ID_D: use TSF D
3240 * @IWM_NUM_TSF_IDS: number of TSF timers available
3247 IWM_NUM_TSF_IDS = 4,
3248 }; /* IWM_TSF_ID_API_E_VER_1 */
3251 * struct iwm_mac_data_ap - configuration data for AP MAC context
3252 * @beacon_time: beacon transmit time in system time
3253 * @beacon_tsf: beacon transmit time in TSF
3254 * @bi: beacon interval in TU
3255 * @bi_reciprocal: 2^32 / bi
3256 * @dtim_interval: dtim transmit time in TU
3257 * @dtim_reciprocal: 2^32 / dtim_interval
3258 * @mcast_qid: queue ID for multicast traffic
3259 * @beacon_template: beacon template ID
3261 struct iwm_mac_data_ap {
3262 uint32_t beacon_time;
3263 uint64_t beacon_tsf;
3265 uint32_t bi_reciprocal;
3266 uint32_t dtim_interval;
3267 uint32_t dtim_reciprocal;
3269 uint32_t beacon_template;
3270 } __packed; /* AP_MAC_DATA_API_S_VER_1 */
3273 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3274 * @beacon_time: beacon transmit time in system time
3275 * @beacon_tsf: beacon transmit time in TSF
3276 * @bi: beacon interval in TU
3277 * @bi_reciprocal: 2^32 / bi
3278 * @beacon_template: beacon template ID
3280 struct iwm_mac_data_ibss {
3281 uint32_t beacon_time;
3282 uint64_t beacon_tsf;
3284 uint32_t bi_reciprocal;
3285 uint32_t beacon_template;
3286 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
3289 * struct iwm_mac_data_sta - configuration data for station MAC context
3290 * @is_assoc: 1 for associated state, 0 otherwise
3291 * @dtim_time: DTIM arrival time in system time
3292 * @dtim_tsf: DTIM arrival time in TSF
3293 * @bi: beacon interval in TU, applicable only when associated
3294 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3295 * @dtim_interval: DTIM interval in TU, applicable only when associated
3296 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3297 * @listen_interval: in beacon intervals, applicable only when associated
3298 * @assoc_id: unique ID assigned by the AP during association
3300 struct iwm_mac_data_sta {
3305 uint32_t bi_reciprocal;
3306 uint32_t dtim_interval;
3307 uint32_t dtim_reciprocal;
3308 uint32_t listen_interval;
3310 uint32_t assoc_beacon_arrive_time;
3311 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3314 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3315 * @ap: iwm_mac_data_ap struct with most config data
3316 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3317 * 0 indicates that there is no CT window.
3318 * @opp_ps_enabled: indicate that opportunistic PS allowed
3320 struct iwm_mac_data_go {
3321 struct iwm_mac_data_ap ap;
3323 uint32_t opp_ps_enabled;
3324 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
3327 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3328 * @sta: iwm_mac_data_sta struct with most config data
3329 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3330 * 0 indicates that there is no CT window.
3332 struct iwm_mac_data_p2p_sta {
3333 struct iwm_mac_data_sta sta;
3335 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3338 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3339 * @stats_interval: interval in TU between statistics notifications to host.
3341 struct iwm_mac_data_pibss {
3342 uint32_t stats_interval;
3343 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3346 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3348 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3349 * other channels as well. This should be to true only in case that the
3350 * device is discoverable and there is an active GO. Note that setting this
3351 * field when not needed, will increase the number of interrupts and have
3352 * effect on the platform power, as this setting opens the Rx filters on
3355 struct iwm_mac_data_p2p_dev {
3356 uint32_t is_disc_extended;
3357 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3360 * enum iwm_mac_filter_flags - MAC context filter flags
3361 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3362 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3363 * control frames to the host
3364 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3365 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3366 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3367 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3368 * (in station mode when associated)
3369 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3370 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3371 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3373 enum iwm_mac_filter_flags {
3374 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3375 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3376 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3377 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3378 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3379 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3380 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3381 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3382 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3386 * enum iwm_mac_qos_flags - QoS flags
3387 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3388 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3389 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3392 enum iwm_mac_qos_flags {
3393 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3394 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3395 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3399 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3400 * @cw_min: Contention window, start value in numbers of slots.
3401 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3402 * @cw_max: Contention window, max value in numbers of slots.
3403 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3404 * @aifsn: Number of slots in Arbitration Interframe Space (before
3405 * performing random backoff timing prior to Tx). Device default 1.
3406 * @fifos_mask: FIFOs used by this MAC for this AC
3407 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3409 * One instance of this config struct for each of 4 EDCA access categories
3410 * in struct iwm_qosparam_cmd.
3412 * Device will automatically increase contention window by (2*CW) + 1 for each
3413 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3414 * value, to cap the CW value.
3422 } __packed; /* IWM_AC_QOS_API_S_VER_2 */
3425 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3426 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3427 * @id_and_color: ID and color of the MAC
3428 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3429 * @mac_type: one of IWM_FW_MAC_TYPE_*
3430 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3431 * @node_addr: MAC address
3432 * @bssid_addr: BSSID
3433 * @cck_rates: basic rates available for CCK
3434 * @ofdm_rates: basic rates available for OFDM
3435 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3436 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3437 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3438 * @filter_flags: combination of IWM_MAC_FILTER_*
3439 * @qos_flags: from IWM_MAC_QOS_FLG_*
3440 * @ac: one iwm_mac_qos configuration for each AC
3441 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3443 struct iwm_mac_ctx_cmd {
3444 /* COMMON_INDEX_HDR_API_S_VER_1 */
3445 uint32_t id_and_color;
3447 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3450 uint8_t node_addr[6];
3451 uint16_t reserved_for_node_addr;
3452 uint8_t bssid_addr[6];
3453 uint16_t reserved_for_bssid_addr;
3455 uint32_t ofdm_rates;
3456 uint32_t protection_flags;
3457 uint32_t cck_short_preamble;
3458 uint32_t short_slot;
3459 uint32_t filter_flags;
3460 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3462 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3463 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3465 struct iwm_mac_data_ap ap;
3466 struct iwm_mac_data_go go;
3467 struct iwm_mac_data_sta sta;
3468 struct iwm_mac_data_p2p_sta p2p_sta;
3469 struct iwm_mac_data_p2p_dev p2p_dev;
3470 struct iwm_mac_data_pibss pibss;
3471 struct iwm_mac_data_ibss ibss;
3473 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3475 static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3479 return 0xFFFFFFFF / v;
3482 #define IWM_NONQOS_SEQ_GET 0x1
3483 #define IWM_NONQOS_SEQ_SET 0x2
3484 struct iwm_nonqos_seq_query_cmd {
3485 uint32_t get_set_flag;
3486 uint32_t mac_id_n_color;
3489 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3491 /* Power Management Commands, Responses, Notifications */
3493 /* Radio LP RX Energy Threshold measured in dBm */
3494 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3495 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3496 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3499 * enum iwm_scan_flags - masks for power table command flags
3500 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3501 * receiver and transmitter. '0' - does not allow.
3502 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3503 * '1' Driver enables PM (use rest of parameters)
3504 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3505 * '1' PM could sleep over DTIM till listen Interval.
3506 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3507 * access categories are both delivery and trigger enabled.
3508 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3509 * PBW Snoozing enabled
3510 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3511 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3512 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3513 * detection enablement
3515 enum iwm_power_flags {
3516 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3517 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3518 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3519 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3520 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3521 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3522 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3523 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3526 #define IWM_POWER_VEC_SIZE 5
3529 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3530 * is used also with a new power API for device wide power settings.
3531 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3533 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3534 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3535 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3536 * set regardless of power scheme or current power state.
3537 * FW use this value also when PM is disabled.
3538 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3539 * PSM transition - legacy PM
3540 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3541 * PSM transition - legacy PM
3542 * @sleep_interval: not in use
3543 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3544 * is set. For example, if it is required to skip over
3545 * one DTIM, this value need to be set to 2 (DTIM periods).
3546 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3549 struct iwm_powertable_cmd {
3550 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3552 uint8_t keep_alive_seconds;
3553 uint8_t debug_flags;
3554 uint32_t rx_data_timeout;
3555 uint32_t tx_data_timeout;
3556 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3557 uint32_t skip_dtim_periods;
3558 uint32_t lprx_rssi_threshold;
3562 * enum iwm_device_power_flags - masks for device power command flags
3563 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3564 * receiver and transmitter. '0' - does not allow.
3566 enum iwm_device_power_flags {
3567 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3571 * struct iwm_device_power_cmd - device wide power command.
3572 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3574 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3576 struct iwm_device_power_cmd {
3577 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3583 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3584 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3585 * @id_and_color: MAC contex identifier
3586 * @flags: Power table command flags from POWER_FLAGS_*
3587 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3588 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3589 * set regardless of power scheme or current power state.
3590 * FW use this value also when PM is disabled.
3591 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3592 * PSM transition - legacy PM
3593 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3594 * PSM transition - legacy PM
3595 * @sleep_interval: not in use
3596 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3597 * is set. For example, if it is required to skip over
3598 * one DTIM, this value need to be set to 2 (DTIM periods).
3599 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3600 * PSM transition - uAPSD
3601 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3602 * PSM transition - uAPSD
3603 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3605 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3606 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3607 * from the AP [msec]
3608 * @snooze_window: A window of time in which PBW snoozing insures that all
3609 * packets received. It is also the minimum time from last
3610 * received unicast RX packet, before client stops snoozing
3613 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3614 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3615 * each corresponding AC.
3616 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3617 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3619 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3620 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3621 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3622 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3623 * @limited_ps_threshold:
3625 struct iwm_mac_power_cmd {
3626 /* CONTEXT_DESC_API_T_VER_1 */
3627 uint32_t id_and_color;
3629 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3631 uint16_t keep_alive_seconds;
3632 uint32_t rx_data_timeout;
3633 uint32_t tx_data_timeout;
3634 uint32_t rx_data_timeout_uapsd;
3635 uint32_t tx_data_timeout_uapsd;
3636 uint8_t lprx_rssi_threshold;
3637 uint8_t skip_dtim_periods;
3638 uint16_t snooze_interval;
3639 uint16_t snooze_window;
3640 uint8_t snooze_step;
3642 uint8_t uapsd_ac_flags;
3643 uint8_t uapsd_max_sp;
3644 uint8_t heavy_tx_thld_packets;
3645 uint8_t heavy_rx_thld_packets;
3646 uint8_t heavy_tx_thld_percentage;
3647 uint8_t heavy_rx_thld_percentage;
3648 uint8_t limited_ps_threshold;
3653 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3654 * associated AP is identified as improperly implementing uAPSD protocol.
3655 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3656 * @sta_id: index of station in uCode's station table - associated AP ID in
3659 struct iwm_uapsd_misbehaving_ap_notif {
3662 uint8_t reserved[3];
3666 * struct iwm_beacon_filter_cmd
3667 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3668 * @id_and_color: MAC contex identifier
3669 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3670 * to driver if delta in Energy values calculated for this and last
3671 * passed beacon is greater than this threshold. Zero value means that
3672 * the Energy change is ignored for beacon filtering, and beacon will
3673 * not be forced to be sent to driver regardless of this delta. Typical
3675 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3676 * Send beacon to driver if delta in Energy values calculated for this
3677 * and last passed beacon is greater than this threshold. Zero value
3678 * means that the Energy change is ignored for beacon filtering while in
3679 * Roaming state, typical energy delta 1dB.
3680 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3681 * calculated for current beacon is less than the threshold, use
3682 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3683 * Threshold. Typical energy threshold is -72dBm.
3684 * @bf_temp_threshold: This threshold determines the type of temperature
3685 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3686 * If the current temperature is above this threshold - Fast filter
3687 * will be used, If the current temperature is below this threshold -
3688 * Slow filter will be used.
3689 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3690 * calculated for this and the last passed beacon is greater than this
3691 * threshold. Zero value means that the temperature change is ignored for
3692 * beacon filtering; beacons will not be forced to be sent to driver
3693 * regardless of whether its temperature has been changed.
3694 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3695 * calculated for this and the last passed beacon is greater than this
3696 * threshold. Zero value means that the temperature change is ignored for
3697 * beacon filtering; beacons will not be forced to be sent to driver
3698 * regardless of whether its temperature has been changed.
3699 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3700 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3701 * for a specific period of time. Units: Beacons.
3702 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3703 * for a longer period of time then this escape-timeout. Units: Beacons.
3704 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3706 struct iwm_beacon_filter_cmd {
3707 uint32_t bf_energy_delta;
3708 uint32_t bf_roaming_energy_delta;
3709 uint32_t bf_roaming_state;
3710 uint32_t bf_temp_threshold;
3711 uint32_t bf_temp_fast_filter;
3712 uint32_t bf_temp_slow_filter;
3713 uint32_t bf_enable_beacon_filter;
3714 uint32_t bf_debug_flag;
3715 uint32_t bf_escape_timer;
3716 uint32_t ba_escape_timer;
3717 uint32_t ba_enable_beacon_abort;
3720 /* Beacon filtering and beacon abort */
3721 #define IWM_BF_ENERGY_DELTA_DEFAULT 5
3722 #define IWM_BF_ENERGY_DELTA_MAX 255
3723 #define IWM_BF_ENERGY_DELTA_MIN 0
3725 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3726 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3727 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3729 #define IWM_BF_ROAMING_STATE_DEFAULT 72
3730 #define IWM_BF_ROAMING_STATE_MAX 255
3731 #define IWM_BF_ROAMING_STATE_MIN 0
3733 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3734 #define IWM_BF_TEMP_THRESHOLD_MAX 255
3735 #define IWM_BF_TEMP_THRESHOLD_MIN 0
3737 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3738 #define IWM_BF_TEMP_FAST_FILTER_MAX 255
3739 #define IWM_BF_TEMP_FAST_FILTER_MIN 0
3741 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3742 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3743 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3745 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3747 #define IWM_BF_DEBUG_FLAG_DEFAULT 0
3749 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3750 #define IWM_BF_ESCAPE_TIMER_MAX 1024
3751 #define IWM_BF_ESCAPE_TIMER_MIN 0
3753 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3754 #define IWM_BA_ESCAPE_TIMER_D3 9
3755 #define IWM_BA_ESCAPE_TIMER_MAX 1024
3756 #define IWM_BA_ESCAPE_TIMER_MIN 0
3758 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3760 #define IWM_BF_CMD_CONFIG_DEFAULTS \
3761 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3762 .bf_roaming_energy_delta = \
3763 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3764 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3765 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3766 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3767 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3768 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3769 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3770 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3773 * These serve as indexes into
3774 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3775 * TODO: avoid overlap between legacy and HT rates
3778 IWM_RATE_1M_INDEX = 0,
3779 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3783 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3785 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3786 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3787 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3788 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3791 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3793 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3795 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3797 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3799 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3801 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3802 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3804 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3805 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3806 IWM_RATE_MCS_8_INDEX,
3807 IWM_RATE_MCS_9_INDEX,
3808 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3809 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3810 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3813 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3815 /* fw API values for legacy bit rates, both OFDM and CCK */
3817 IWM_RATE_6M_PLCP = 13,
3818 IWM_RATE_9M_PLCP = 15,
3819 IWM_RATE_12M_PLCP = 5,
3820 IWM_RATE_18M_PLCP = 7,
3821 IWM_RATE_24M_PLCP = 9,
3822 IWM_RATE_36M_PLCP = 11,
3823 IWM_RATE_48M_PLCP = 1,
3824 IWM_RATE_54M_PLCP = 3,
3825 IWM_RATE_1M_PLCP = 10,
3826 IWM_RATE_2M_PLCP = 20,
3827 IWM_RATE_5M_PLCP = 55,
3828 IWM_RATE_11M_PLCP = 110,
3829 IWM_RATE_INVM_PLCP = -1,
3833 * rate_n_flags bit fields
3835 * The 32-bit value has different layouts in the low 8 bites depending on the
3836 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3837 * for CCK and OFDM).
3839 * High-throughput (HT) rate format
3840 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3841 * Very High-throughput (VHT) rate format
3842 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3843 * Legacy OFDM rate format for bits 7:0
3844 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3845 * Legacy CCK rate format for bits 7:0:
3846 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3849 /* Bit 8: (1) HT format, (0) legacy or VHT format */
3850 #define IWM_RATE_MCS_HT_POS 8
3851 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3853 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3854 #define IWM_RATE_MCS_CCK_POS 9
3855 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3857 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3858 #define IWM_RATE_MCS_VHT_POS 26
3859 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3863 * High-throughput (HT) rate format for bits 7:0
3865 * 2-0: MCS rate base
3874 * 4-3: 0) Single stream (SISO)
3875 * 1) Dual stream (MIMO)
3876 * 2) Triple stream (MIMO)
3877 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3878 * (bits 7-6 are zero)
3880 * Together the low 5 bits work out to the MCS index because we don't
3881 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3882 * streams and 16-23 have three streams. We could also support MCS 32
3883 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3885 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3886 #define IWM_RATE_HT_MCS_NSS_POS 3
3887 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3889 /* Bit 10: (1) Use Green Field preamble */
3890 #define IWM_RATE_HT_MCS_GF_POS 10
3891 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3893 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3896 * Very High-throughput (VHT) rate format for bits 7:0
3898 * 3-0: VHT MCS (0-9)
3899 * 5-4: number of streams - 1:
3900 * 0) Single stream (SISO)
3901 * 1) Dual stream (MIMO)
3902 * 2) Triple stream (MIMO)
3905 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3906 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3907 #define IWM_RATE_VHT_MCS_NSS_POS 4
3908 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3911 * Legacy OFDM rate format for bits 7:0
3923 * Legacy CCK rate format for bits 7:0:
3924 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
3932 #define IWM_RATE_LEGACY_RATE_MSK 0xff
3936 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
3937 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
3939 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11
3940 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3941 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3942 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3943 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3944 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3946 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
3947 #define IWM_RATE_MCS_SGI_POS 13
3948 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
3950 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
3951 #define IWM_RATE_MCS_ANT_POS 14
3952 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
3953 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
3954 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
3955 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
3956 IWM_RATE_MCS_ANT_B_MSK)
3957 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
3958 IWM_RATE_MCS_ANT_C_MSK)
3959 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
3960 #define IWM_RATE_MCS_ANT_NUM 3
3962 /* Bit 17-18: (0) SS, (1) SS*2 */
3963 #define IWM_RATE_MCS_STBC_POS 17
3964 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
3966 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
3967 #define IWM_RATE_MCS_BF_POS 19
3968 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
3970 /* Bit 20: (0) ZLF is off, (1) ZLF is on */
3971 #define IWM_RATE_MCS_ZLF_POS 20
3972 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
3974 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
3975 #define IWM_RATE_MCS_DUP_POS 24
3976 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
3978 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
3979 #define IWM_RATE_MCS_LDPC_POS 27
3980 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
3983 /* Link Quality definitions */
3985 /* # entries in rate scale table to support Tx retries */
3986 #define IWM_LQ_MAX_RETRY_NUM 16
3988 /* Link quality command flags bit fields */
3990 /* Bit 0: (0) Don't use RTS (1) Use RTS */
3991 #define IWM_LQ_FLAG_USE_RTS_POS 0
3992 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
3994 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
3995 #define IWM_LQ_FLAG_COLOR_POS 1
3996 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
3998 /* Bit 4-5: Tx RTS BW Signalling
3999 * (0) No RTS BW signalling
4000 * (1) Static BW signalling
4001 * (2) Dynamic BW signalling
4003 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
4004 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4005 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4006 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4008 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4009 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
4011 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
4012 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
4015 * struct iwm_lq_cmd - link quality command
4016 * @sta_id: station to update
4017 * @control: not used
4018 * @flags: combination of IWM_LQ_FLAG_*
4019 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
4021 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
4022 * Should be ANT_[ABC]
4023 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
4024 * @initial_rate_index: first index from rs_table per AC category
4025 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
4026 * value of 100 is one usec. Range is 100 to 8000
4027 * @agg_disable_start_th: try-count threshold for starting aggregation.
4028 * If a frame has higher try-count, it should not be selected for
4029 * starting an aggregation sequence.
4030 * @agg_frame_cnt_limit: max frame count in an aggregation.
4032 * 1: no aggregation (one frame per aggregation)
4033 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4034 * @rs_table: array of rates for each TX try, each is rate_n_flags,
4035 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
4036 * @bf_params: beam forming params, currently not used
4042 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
4045 uint8_t single_stream_ant_msk;
4046 uint8_t dual_stream_ant_msk;
4047 uint8_t initial_rate_index[IWM_AC_NUM];
4048 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
4049 uint16_t agg_time_limit;
4050 uint8_t agg_disable_start_th;
4051 uint8_t agg_frame_cnt_limit;
4053 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
4055 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
4058 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
4059 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4060 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
4061 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
4062 * Otherwise, use rate_n_flags from the TX command
4063 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
4064 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
4065 * Must set IWM_TX_CMD_FLG_ACK with this flag.
4066 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
4067 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
4068 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
4069 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
4070 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
4071 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
4072 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
4073 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
4074 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
4075 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
4076 * Should be set for beacons and probe responses
4077 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
4078 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
4079 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
4080 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
4081 * Should be set for 26/30 length MAC headers
4082 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
4083 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
4084 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
4085 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4086 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
4087 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
4088 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4089 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
4092 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
4093 IWM_TX_CMD_FLG_ACK = (1 << 3),
4094 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
4095 IWM_TX_CMD_FLG_BA = (1 << 5),
4096 IWM_TX_CMD_FLG_BAR = (1 << 6),
4097 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
4098 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
4099 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
4100 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
4101 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
4102 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
4103 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
4104 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
4105 IWM_TX_CMD_FLG_TSF = (1 << 16),
4106 IWM_TX_CMD_FLG_CALIB = (1 << 17),
4107 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
4108 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
4109 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
4110 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
4111 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22),
4112 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
4113 IWM_TX_CMD_FLG_DUR = (1 << 25),
4114 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
4115 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
4116 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
4117 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
4118 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
4121 * enum iwm_tx_pm_timeouts - pm timeout values in TX command
4122 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode
4123 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU
4124 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec
4126 enum iwm_tx_pm_timeouts {
4127 IWM_PM_FRAME_NONE = 0,
4128 IWM_PM_FRAME_MGMT = 2,
4129 IWM_PM_FRAME_ASSOC = 3,
4133 * TX command security control
4135 #define IWM_TX_CMD_SEC_WEP 0x01
4136 #define IWM_TX_CMD_SEC_CCM 0x02
4137 #define IWM_TX_CMD_SEC_TKIP 0x03
4138 #define IWM_TX_CMD_SEC_EXT 0x04
4139 #define IWM_TX_CMD_SEC_MSK 0x07
4140 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
4141 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4142 #define IWM_TX_CMD_SEC_KEY128 0x08
4144 /* TODO: how does these values are OK with only 16 bit variable??? */
4146 * TX command next frame info
4148 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
4149 * bit 3 - immediate ACK required
4150 * bit 4 - rate is taken from STA table
4151 * bit 5 - frame belongs to BA stream
4152 * bit 6 - immediate BA response expected
4154 * bits 8:15 - Station ID
4157 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
4158 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
4159 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
4160 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
4161 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
4162 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
4163 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
4164 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
4165 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
4168 * TX command Frame life time in us - to be written in pm_frame_timeout
4170 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4171 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
4172 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
4173 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4176 * TID for non QoS frames - to be written in tid_tspec
4178 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
4181 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4183 #define IWM_DEFAULT_TX_RETRY 15
4184 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3
4185 #define IWM_RTS_DFAULT_RETRY_LIMIT 60
4186 #define IWM_BAR_DFAULT_RETRY_LIMIT 60
4187 #define IWM_LOW_RETRY_LIMIT 7
4189 /* TODO: complete documentation for try_cnt and btkill_cnt */
4191 * struct iwm_tx_cmd - TX command struct to FW
4192 * ( IWM_TX_CMD = 0x1c )
4193 * @len: in bytes of the payload, see below for details
4194 * @next_frame_len: same as len, but for next frame (0 if not applicable)
4195 * Used for fragmentation and bursting, but not in 11n aggregation.
4196 * @tx_flags: combination of IWM_TX_CMD_FLG_*
4197 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
4198 * cleared. Combination of IWM_RATE_MCS_*
4199 * @sta_id: index of destination station in FW station table
4200 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
4201 * @initial_rate_index: index into the rate table for initial TX attempt.
4202 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4203 * @key: security key
4204 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_*
4205 * @life_time: frame life time (usecs??)
4206 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
4207 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4208 * @dram_msb_ptr: upper bits of the scratch physical address
4209 * @rts_retry_limit: max attempts for RTS
4210 * @data_retry_limit: max attempts to send the data packet
4211 * @tid_spec: TID/tspec
4212 * @pm_frame_timeout: PM TX frame timeout
4213 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
4214 * specified by HCCA protocol
4216 * The byte count (both len and next_frame_len) includes MAC header
4217 * (24/26/30/32 bytes)
4218 * + 2 bytes pad if 26/30 header size
4219 * + 8 byte IV for CCM or TKIP (not used for WEP)
4221 * + 8-byte MIC (not used for CCM/WEP)
4222 * It does not include post-MAC padding, i.e.,
4223 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.
4224 * Range of len: 14-2342 bytes.
4226 * After the struct fields the MAC header is placed, plus any padding,
4227 * and then the actial payload.
4231 uint16_t next_frame_len;
4237 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */
4238 uint32_t rate_n_flags;
4241 uint8_t initial_rate_index;
4244 uint16_t next_frame_flags;
4247 uint32_t dram_lsb_ptr;
4248 uint8_t dram_msb_ptr;
4249 uint8_t rts_retry_limit;
4250 uint8_t data_retry_limit;
4252 uint16_t pm_frame_timeout;
4253 uint16_t driver_txop;
4255 struct ieee80211_frame hdr[0];
4256 } __packed; /* IWM_TX_CMD_API_S_VER_3 */
4259 * TX response related data
4263 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx
4264 * @IWM_TX_STATUS_SUCCESS:
4265 * @IWM_TX_STATUS_DIRECT_DONE:
4266 * @IWM_TX_STATUS_POSTPONE_DELAY:
4267 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES:
4268 * @IWM_TX_STATUS_POSTPONE_BT_PRIO:
4269 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD:
4270 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK:
4271 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
4272 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT:
4273 * @IWM_TX_STATUS_FAIL_LONG_LIMIT:
4274 * @IWM_TX_STATUS_FAIL_UNDERRUN:
4275 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW:
4276 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH:
4277 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE:
4278 * @IWM_TX_STATUS_FAIL_DEST_PS:
4279 * @IWM_TX_STATUS_FAIL_HOST_ABORTED:
4280 * @IWM_TX_STATUS_FAIL_BT_RETRY:
4281 * @IWM_TX_STATUS_FAIL_STA_INVALID:
4282 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED:
4283 * @IWM_TX_STATUS_FAIL_TID_DISABLE:
4284 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED:
4285 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL:
4286 * @IWM_TX_STATUS_FAIL_FW_DROP:
4287 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
4289 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT:
4291 * @IWM_TX_MODE_NO_BURST:
4292 * @IWM_TX_MODE_IN_BURST_SEQ:
4293 * @IWM_TX_MODE_FIRST_IN_BURST:
4294 * @IWM_TX_QUEUE_NUM_MSK:
4296 * Valid only if frame_count =1
4297 * TODO: complete documentation
4299 enum iwm_tx_status {
4300 IWM_TX_STATUS_MSK = 0x000000ff,
4301 IWM_TX_STATUS_SUCCESS = 0x01,
4302 IWM_TX_STATUS_DIRECT_DONE = 0x02,
4304 IWM_TX_STATUS_POSTPONE_DELAY = 0x40,
4305 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
4306 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42,
4307 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
4308 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
4310 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
4311 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
4312 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83,
4313 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84,
4314 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
4315 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
4316 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
4317 IWM_TX_STATUS_FAIL_DEST_PS = 0x88,
4318 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89,
4319 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a,
4320 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b,
4321 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
4322 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d,
4323 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
4324 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f,
4325 IWM_TX_STATUS_FAIL_FW_DROP = 0x90,
4326 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91,
4327 IWM_TX_STATUS_INTERNAL_ABORT = 0x92,
4328 IWM_TX_MODE_MSK = 0x00000f00,
4329 IWM_TX_MODE_NO_BURST = 0x00000000,
4330 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100,
4331 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200,
4332 IWM_TX_QUEUE_NUM_MSK = 0x0001f000,
4333 IWM_TX_NARROW_BW_MSK = 0x00060000,
4334 IWM_TX_NARROW_BW_1DIV2 = 0x00020000,
4335 IWM_TX_NARROW_BW_1DIV4 = 0x00040000,
4336 IWM_TX_NARROW_BW_1DIV8 = 0x00060000,
4340 * enum iwm_tx_agg_status - TX aggregation status
4341 * @IWM_AGG_TX_STATE_STATUS_MSK:
4342 * @IWM_AGG_TX_STATE_TRANSMITTED:
4343 * @IWM_AGG_TX_STATE_UNDERRUN:
4344 * @IWM_AGG_TX_STATE_BT_PRIO:
4345 * @IWM_AGG_TX_STATE_FEW_BYTES:
4346 * @IWM_AGG_TX_STATE_ABORT:
4347 * @IWM_AGG_TX_STATE_LAST_SENT_TTL:
4348 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT:
4349 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL:
4350 * @IWM_AGG_TX_STATE_SCD_QUERY:
4351 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32:
4352 * @IWM_AGG_TX_STATE_RESPONSE:
4353 * @IWM_AGG_TX_STATE_DUMP_TX:
4354 * @IWM_AGG_TX_STATE_DELAY_TX:
4355 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4356 * occur if tx failed for this frame when it was a member of a previous
4357 * aggregation block). If rate scaling is used, retry count indicates the
4358 * rate table entry used for all frames in the new agg.
4359 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4362 * TODO: complete documentation
4364 enum iwm_tx_agg_status {
4365 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff,
4366 IWM_AGG_TX_STATE_TRANSMITTED = 0x000,
4367 IWM_AGG_TX_STATE_UNDERRUN = 0x001,
4368 IWM_AGG_TX_STATE_BT_PRIO = 0x002,
4369 IWM_AGG_TX_STATE_FEW_BYTES = 0x004,
4370 IWM_AGG_TX_STATE_ABORT = 0x008,
4371 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010,
4372 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020,
4373 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040,
4374 IWM_AGG_TX_STATE_SCD_QUERY = 0x080,
4375 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100,
4376 IWM_AGG_TX_STATE_RESPONSE = 0x1ff,
4377 IWM_AGG_TX_STATE_DUMP_TX = 0x200,
4378 IWM_AGG_TX_STATE_DELAY_TX = 0x400,
4379 IWM_AGG_TX_STATE_TRY_CNT_POS = 12,
4380 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS,
4383 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4384 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4385 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4388 * The mask below describes a status where we are absolutely sure that the MPDU
4389 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
4390 * written the bytes to the TXE, but we know nothing about what the DSP did.
4392 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \
4393 IWM_AGG_TX_STATE_ABORT | \
4394 IWM_AGG_TX_STATE_SCD_QUERY)
4397 * IWM_REPLY_TX = 0x1c (response)
4399 * This response may be in one of two slightly different formats, indicated
4400 * by the frame_count field:
4402 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
4403 * frame. Multiple attempts, at various bit rates, may have been made for
4406 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
4407 * frames that used block-acknowledge. All frames were transmitted at
4408 * same rate. Rate scaling may have been used if first frame in this new
4409 * agg block failed in previous agg block(s).
4411 * Note that, for aggregation, ACK (block-ack) status is not delivered
4412 * here; block-ack has not been received by the time the device records
4414 * This status relates to reasons the tx might have been blocked or aborted
4415 * within the device, rather than whether it was received successfully by
4416 * the destination station.
4420 * struct iwm_agg_tx_status - per packet TX aggregation status
4421 * @status: enum iwm_tx_agg_status
4422 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
4424 struct iwm_agg_tx_status {
4430 * definitions for initial rate index field
4431 * bits [3:0] initial rate index
4432 * bits [6:4] rate table color, used for the initial rate
4433 * bit-7 invalid rate indication
4435 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
4436 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
4437 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
4439 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
4440 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
4443 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet
4444 * ( IWM_REPLY_TX = 0x1c )
4445 * @frame_count: 1 no aggregation, >1 aggregation
4446 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
4447 * @failure_rts: num of failures due to unsuccessful RTS
4448 * @failure_frame: num failures due to no ACK (unused for agg)
4449 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
4450 * Tx of all the batch. IWM_RATE_MCS_*
4451 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
4452 * for agg: RTS + CTS + aggregation tx time + block-ack time.
4454 * @pa_status: tx power info
4455 * @pa_integ_res_a: tx power info
4456 * @pa_integ_res_b: tx power info
4457 * @pa_integ_res_c: tx power info
4458 * @measurement_req_id: tx power info
4459 * @tfd_info: TFD information set by the FH
4460 * @seq_ctl: sequence control from the Tx cmd
4461 * @byte_cnt: byte count from the Tx cmd
4462 * @tlc_info: TLC rate info
4463 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4464 * @frame_ctrl: frame control
4465 * @status: for non-agg: frame status IWM_TX_STATUS_*
4466 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4467 * follow this one, up to frame_count.
4469 * After the array of statuses comes the SSN of the SCD. Look at
4470 * %iwm_mvm_get_scd_ssn for more details.
4472 struct iwm_mvm_tx_resp {
4473 uint8_t frame_count;
4474 uint8_t bt_kill_count;
4475 uint8_t failure_rts;
4476 uint8_t failure_frame;
4477 uint32_t initial_rate;
4478 uint16_t wireless_media_time;
4481 uint8_t pa_integ_res_a[3];
4482 uint8_t pa_integ_res_b[3];
4483 uint8_t pa_integ_res_c[3];
4484 uint16_t measurement_req_id;
4492 uint16_t frame_ctrl;
4494 struct iwm_agg_tx_status status;
4495 } __packed; /* IWM_TX_RSP_API_S_VER_3 */
4498 * struct iwm_mvm_ba_notif - notifies about reception of BA
4499 * ( IWM_BA_NOTIF = 0xc5 )
4500 * @sta_addr_lo32: lower 32 bits of the MAC address
4501 * @sta_addr_hi16: upper 16 bits of the MAC address
4502 * @sta_id: Index of recipient (BA-sending) station in fw's station table
4503 * @tid: tid of the session
4505 * @bitmap: the bitmap of the BA notification as seen in the air
4506 * @scd_flow: the tx queue this BA relates to
4507 * @scd_ssn: the index of the last contiguously sent packet
4508 * @txed: number of Txed frames in this batch
4509 * @txed_2_done: number of Acked frames in this batch
4511 struct iwm_mvm_ba_notif {
4512 uint32_t sta_addr_lo32;
4513 uint16_t sta_addr_hi16;
4523 uint8_t txed_2_done;
4528 * struct iwm_mac_beacon_cmd - beacon template command
4529 * @tx: the tx commands associated with the beacon frame
4530 * @template_id: currently equal to the mac context id of the coresponding
4532 * @tim_idx: the offset of the tim IE in the beacon
4533 * @tim_size: the length of the tim IE
4534 * @frame: the template of the beacon frame
4536 struct iwm_mac_beacon_cmd {
4537 struct iwm_tx_cmd tx;
4538 uint32_t template_id;
4541 struct ieee80211_frame frame[0];
4544 struct iwm_beacon_notif {
4545 struct iwm_mvm_tx_resp beacon_notify_hdr;
4547 uint32_t ibss_mgr_status;
4551 * enum iwm_dump_control - dump (flush) control flags
4552 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
4553 * and the TFD queues are empty.
4555 enum iwm_dump_control {
4556 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4560 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4561 * @queues_ctl: bitmap of queues to flush
4562 * @flush_ctl: control flags
4563 * @reserved: reserved
4565 struct iwm_tx_path_flush_cmd {
4566 uint32_t queues_ctl;
4569 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4572 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD
4573 * @tx_resp: the Tx response from the fw (agg or non-agg)
4575 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4576 * it can't know that everything will go well until the end of the AMPDU, it
4577 * can't know in advance the number of MPDUs that will be sent in the current
4578 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4579 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4580 * of the batch. This is why the SSN of the SCD is written at the end of the
4581 * whole struct at a variable offset. This function knows how to cope with the
4582 * variable offset and returns the SSN of the SCD.
4584 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp)
4586 return le32_to_cpup((uint32_t *)&tx_resp->status +
4587 tx_resp->frame_count) & 0xfff;
4591 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command
4593 * @sta_id: station id
4595 * @scd_queue: scheduler queue to confiug
4596 * @enable: 1 queue enable, 0 queue disable
4597 * @aggregate: 1 aggregated queue, 0 otherwise
4598 * @tx_fifo: %enum iwm_mvm_tx_fifo
4599 * @window: BA window size
4600 * @ssn: SSN for the BA agreement
4602 struct iwm_scd_txq_cfg_cmd {
4613 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */
4616 * struct iwm_scd_txq_cfg_rsp
4617 * @token: taken from the command
4618 * @sta_id: station id from the command
4619 * @tid: tid from the command
4620 * @scd_queue: scd_queue from the command
4622 struct iwm_scd_txq_cfg_rsp {
4627 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
4630 /* Scan Commands, Responses, Notifications */
4632 /* Max number of IEs for direct SSID scans in a command */
4633 #define IWM_PROBE_OPTION_MAX 20
4636 * struct iwm_ssid_ie - directed scan network information element
4638 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4639 * selected by "type" bit field in struct iwm_scan_channel;
4640 * each channel may select different ssids from among the 20 entries.
4641 * SSID IEs get transmitted in reverse order of entry.
4643 struct iwm_ssid_ie {
4646 uint8_t ssid[IEEE80211_NWID_LEN];
4647 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4650 #define IWM_SCAN_MAX_BLACKLIST_LEN 64
4651 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4652 #define IWM_SCAN_MAX_PROFILES 11
4653 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4655 /* Default watchdog (in MS) for scheduled scan iteration */
4656 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4658 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4659 #define IWM_CAN_ABORT_STATUS 1
4661 #define IWM_FULL_SCAN_MULTIPLIER 5
4662 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4663 #define IWM_MAX_SCHED_SCAN_PLANS 2
4666 * iwm_scan_schedule_lmac - schedule of scan offload
4667 * @delay: delay between iterations, in seconds.
4668 * @iterations: num of scan iterations
4669 * @full_scan_mul: number of partial scans before each full scan
4671 struct iwm_scan_schedule_lmac {
4674 uint8_t full_scan_mul;
4675 } __packed; /* SCAN_SCHEDULE_API_S */
4678 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
4679 * @tx_flags: combination of TX_CMD_FLG_*
4680 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
4681 * cleared. Combination of RATE_MCS_*
4682 * @sta_id: index of destination station in FW station table
4683 * @reserved: for alignment and future use
4685 struct iwm_scan_req_tx_cmd {
4687 uint32_t rate_n_flags;
4689 uint8_t reserved[3];
4692 enum iwm_scan_channel_flags_lmac {
4693 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27),
4694 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28),
4698 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
4699 * @flags: bits 1-20: directed scan to i'th ssid
4700 * other bits &enum iwm_scan_channel_flags_lmac
4701 * @channel_number: channel number 1-13 etc
4702 * @iter_count: scan iteration on this channel
4703 * @iter_interval: interval in seconds between iterations on one channel
4705 struct iwm_scan_channel_cfg_lmac {
4707 uint16_t channel_num;
4708 uint16_t iter_count;
4709 uint32_t iter_interval;
4713 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
4714 * @offset: offset in the data block
4715 * @len: length of the segment
4717 struct iwm_scan_probe_segment {
4722 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
4723 * @mac_header: first (and common) part of the probe
4724 * @band_data: band specific data
4725 * @common_data: last (and common) part of the probe
4726 * @buf: raw data block
4728 struct iwm_scan_probe_req {
4729 struct iwm_scan_probe_segment mac_header;
4730 struct iwm_scan_probe_segment band_data[2];
4731 struct iwm_scan_probe_segment common_data;
4732 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
4735 enum iwm_scan_channel_flags {
4736 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0),
4737 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1),
4738 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2),
4741 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
4742 * @flags: enum iwm_scan_channel_flags
4743 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
4745 * 1 - EBS is disabled.
4746 * 2 - every second scan will be full scan(and so on).
4748 struct iwm_scan_channel_opt {
4750 uint16_t non_ebs_ratio;
4754 * iwm_mvm_lmac_scan_flags
4755 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses
4756 * without filtering.
4757 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
4758 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan
4759 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification
4760 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching
4761 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented
4762 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
4763 * and DS parameter set IEs into probe requests.
4764 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
4766 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches
4768 enum iwm_mvm_lmac_scan_flags {
4769 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0),
4770 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1),
4771 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2),
4772 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3),
4773 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4),
4774 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5),
4775 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6),
4776 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7),
4777 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9),
4780 enum iwm_scan_priority {
4781 IWM_SCAN_PRIORITY_LOW,
4782 IWM_SCAN_PRIORITY_MEDIUM,
4783 IWM_SCAN_PRIORITY_HIGH,
4787 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
4788 * @reserved1: for alignment and future use
4789 * @channel_num: num of channels to scan
4790 * @active-dwell: dwell time for active channels
4791 * @passive-dwell: dwell time for passive channels
4792 * @fragmented-dwell: dwell time for fragmented passive scan
4793 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases)
4794 * @reserved2: for alignment and future use
4795 * @rx_chain_selct: PHY_RX_CHAIN_* flags
4796 * @scan_flags: &enum iwm_mvm_lmac_scan_flags
4797 * @max_out_time: max time (in TU) to be out of associated channel
4798 * @suspend_time: pause scan this long (TUs) when returning to service channel
4799 * @flags: RXON flags
4800 * @filter_flags: RXON filter
4801 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz
4802 * @direct_scan: list of SSIDs for directed active scan
4803 * @scan_prio: enum iwm_scan_priority
4804 * @iter_num: number of scan iterations
4805 * @delay: delay in seconds before first iteration
4806 * @schedule: two scheduling plans. The first one is finite, the second one can
4808 * @channel_opt: channel optimization options, for full and partial scan
4809 * @data: channel configuration and probe request packet.
4811 struct iwm_scan_req_lmac {
4812 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */
4815 uint8_t active_dwell;
4816 uint8_t passive_dwell;
4817 uint8_t fragmented_dwell;
4818 uint8_t extended_dwell;
4820 uint16_t rx_chain_select;
4821 uint32_t scan_flags;
4822 uint32_t max_out_time;
4823 uint32_t suspend_time;
4824 /* RX_ON_FLAGS_API_S_VER_1 */
4826 uint32_t filter_flags;
4827 struct iwm_scan_req_tx_cmd tx_cmd[2];
4828 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4830 /* SCAN_REQ_PERIODIC_PARAMS_API_S */
4833 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS];
4834 struct iwm_scan_channel_opt channel_opt[2];
4839 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
4840 * @last_schedule_line: last schedule line executed (fast or regular)
4841 * @last_schedule_iteration: last scan iteration executed before scan abort
4842 * @status: enum iwm_scan_offload_complete_status
4843 * @ebs_status: EBS success status &enum iwm_scan_ebs_status
4844 * @time_after_last_iter; time in seconds elapsed after last iteration
4846 struct iwm_periodic_scan_complete {
4847 uint8_t last_schedule_line;
4848 uint8_t last_schedule_iteration;
4851 uint32_t time_after_last_iter;
4855 /* How many statistics are gathered for each channel */
4856 #define IWM_SCAN_RESULTS_STATISTICS 1
4859 * enum iwm_scan_complete_status - status codes for scan complete notifications
4860 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully
4861 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user
4862 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed
4863 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready
4864 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed
4865 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed
4866 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command
4867 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort
4868 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax
4869 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful
4871 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver
4873 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events
4875 enum iwm_scan_complete_status {
4876 IWM_SCAN_COMP_STATUS_OK = 0x1,
4877 IWM_SCAN_COMP_STATUS_ABORT = 0x2,
4878 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3,
4879 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4,
4880 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5,
4881 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6,
4882 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7,
4883 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8,
4884 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9,
4885 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA,
4886 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B,
4887 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C,
4891 * struct iwm_scan_results_notif - scan results for one channel
4892 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 )
4893 * @channel: which channel the results are from
4894 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4895 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
4896 * @num_probe_not_sent: # of request that weren't sent due to not enough time
4897 * @duration: duration spent in channel, in usecs
4898 * @statistics: statistics gathered for this channel
4900 struct iwm_scan_results_notif {
4903 uint8_t probe_status;
4904 uint8_t num_probe_not_sent;
4906 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
4907 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
4909 enum iwm_scan_framework_client {
4910 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
4911 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
4912 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
4916 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
4917 * @ssid: MAC address to filter out
4918 * @reported_rssi: AP rssi reported to the host
4919 * @client_bitmap: clients ignore this entry - enum scan_framework_client
4921 struct iwm_scan_offload_blacklist {
4922 uint8_t ssid[IEEE80211_ADDR_LEN];
4923 uint8_t reported_rssi;
4924 uint8_t client_bitmap;
4927 enum iwm_scan_offload_network_type {
4928 IWM_NETWORK_TYPE_BSS = 1,
4929 IWM_NETWORK_TYPE_IBSS = 2,
4930 IWM_NETWORK_TYPE_ANY = 3,
4933 enum iwm_scan_offload_band_selection {
4934 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
4935 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
4936 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
4940 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
4941 * @ssid_index: index to ssid list in fixed part
4942 * @unicast_cipher: encryption olgorithm to match - bitmap
4943 * @aut_alg: authentication olgorithm to match - bitmap
4944 * @network_type: enum iwm_scan_offload_network_type
4945 * @band_selection: enum iwm_scan_offload_band_selection
4946 * @client_bitmap: clients waiting for match - enum scan_framework_client
4948 struct iwm_scan_offload_profile {
4950 uint8_t unicast_cipher;
4952 uint8_t network_type;
4953 uint8_t band_selection;
4954 uint8_t client_bitmap;
4955 uint8_t reserved[2];
4959 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
4960 * @blaclist: AP list to filter off from scan results
4961 * @profiles: profiles to search for match
4962 * @blacklist_len: length of blacklist
4963 * @num_profiles: num of profiles in the list
4964 * @match_notify: clients waiting for match found notification
4965 * @pass_match: clients waiting for the results
4966 * @active_clients: active clients bitmap - enum scan_framework_client
4967 * @any_beacon_notify: clients waiting for match notification without match
4969 struct iwm_scan_offload_profile_cfg {
4970 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
4971 uint8_t blacklist_len;
4972 uint8_t num_profiles;
4973 uint8_t match_notify;
4975 uint8_t active_clients;
4976 uint8_t any_beacon_notify;
4977 uint8_t reserved[2];
4980 enum iwm_scan_offload_complete_status {
4981 IWM_SCAN_OFFLOAD_COMPLETED = 1,
4982 IWM_SCAN_OFFLOAD_ABORTED = 2,
4985 enum iwm_scan_ebs_status {
4986 IWM_SCAN_EBS_SUCCESS,
4987 IWM_SCAN_EBS_FAILED,
4988 IWM_SCAN_EBS_CHAN_NOT_FOUND,
4989 IWM_SCAN_EBS_INACTIVE,
4993 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels)
4994 * SCAN_COMPLETE_NTF_API_S_VER_3
4995 * @scanned_channels: number of channels scanned (and number of valid results)
4996 * @status: one of SCAN_COMP_STATUS_*
4997 * @bt_status: BT on/off status
4998 * @last_channel: last channel that was scanned
4999 * @tsf_low: TSF timer (lower half) in usecs
5000 * @tsf_high: TSF timer (higher half) in usecs
5001 * @results: an array of scan results, only "scanned_channels" of them are valid
5003 struct iwm_lmac_scan_complete_notif {
5004 uint8_t scanned_channels;
5007 uint8_t last_channel;
5010 struct iwm_scan_results_notif results[];
5016 /* The maximum of either of these cannot exceed 8, because we use an
5017 * 8-bit mask (see IWM_MVM_SCAN_MASK).
5019 #define IWM_MVM_MAX_UMAC_SCANS 8
5020 #define IWM_MVM_MAX_LMAC_SCANS 1
5022 enum iwm_scan_config_flags {
5023 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0),
5024 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1),
5025 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2),
5026 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3),
5027 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8),
5028 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9),
5029 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10),
5030 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11),
5031 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12),
5032 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13),
5033 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14),
5034 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15),
5035 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16),
5036 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17),
5037 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18),
5038 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19),
5039 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20),
5040 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21),
5042 /* Bits 26-31 are for num of channels in channel_array */
5043 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
5046 enum iwm_scan_config_rates {
5047 /* OFDM basic rates */
5048 IWM_SCAN_CONFIG_RATE_6M = (1 << 0),
5049 IWM_SCAN_CONFIG_RATE_9M = (1 << 1),
5050 IWM_SCAN_CONFIG_RATE_12M = (1 << 2),
5051 IWM_SCAN_CONFIG_RATE_18M = (1 << 3),
5052 IWM_SCAN_CONFIG_RATE_24M = (1 << 4),
5053 IWM_SCAN_CONFIG_RATE_36M = (1 << 5),
5054 IWM_SCAN_CONFIG_RATE_48M = (1 << 6),
5055 IWM_SCAN_CONFIG_RATE_54M = (1 << 7),
5056 /* CCK basic rates */
5057 IWM_SCAN_CONFIG_RATE_1M = (1 << 8),
5058 IWM_SCAN_CONFIG_RATE_2M = (1 << 9),
5059 IWM_SCAN_CONFIG_RATE_5M = (1 << 10),
5060 IWM_SCAN_CONFIG_RATE_11M = (1 << 11),
5062 /* Bits 16-27 are for supported rates */
5063 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
5066 enum iwm_channel_flags {
5067 IWM_CHANNEL_FLAG_EBS = (1 << 0),
5068 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1),
5069 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2),
5070 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3),
5074 * struct iwm_scan_config
5075 * @flags: enum scan_config_flags
5076 * @tx_chains: valid_tx antenna - ANT_* definitions
5077 * @rx_chains: valid_rx antenna - ANT_* definitions
5078 * @legacy_rates: default legacy rates - enum scan_config_rates
5079 * @out_of_channel_time: default max out of serving channel time
5080 * @suspend_time: default max suspend time
5081 * @dwell_active: default dwell time for active scan
5082 * @dwell_passive: default dwell time for passive scan
5083 * @dwell_fragmented: default dwell time for fragmented scan
5084 * @dwell_extended: default dwell time for channels 1, 6 and 11
5085 * @mac_addr: default mac address to be used in probes
5086 * @bcast_sta_id: the index of the station in the fw
5087 * @channel_flags: default channel flags - enum iwm_channel_flags
5088 * scan_config_channel_flag
5089 * @channel_array: default supported channels
5091 struct iwm_scan_config {
5095 uint32_t legacy_rates;
5096 uint32_t out_of_channel_time;
5097 uint32_t suspend_time;
5098 uint8_t dwell_active;
5099 uint8_t dwell_passive;
5100 uint8_t dwell_fragmented;
5101 uint8_t dwell_extended;
5102 uint8_t mac_addr[IEEE80211_ADDR_LEN];
5103 uint8_t bcast_sta_id;
5104 uint8_t channel_flags;
5105 uint8_t channel_array[];
5106 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */
5109 * iwm_umac_scan_flags
5110 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
5111 * can be preempted by other scan requests with higher priority.
5112 * The low priority scan will be resumed when the higher proirity scan is
5114 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
5117 enum iwm_umac_scan_flags {
5118 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0),
5119 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1),
5122 enum iwm_umac_scan_uid_offsets {
5123 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0,
5124 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8,
5127 enum iwm_umac_scan_general_flags {
5128 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0),
5129 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1),
5130 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2),
5131 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3),
5132 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4),
5133 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5),
5134 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6),
5135 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7),
5136 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8),
5137 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9),
5138 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10),
5142 * struct iwm_scan_channel_cfg_umac
5143 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5144 * @channel_num: channel number 1-13 etc.
5145 * @iter_count: repetition count for the channel.
5146 * @iter_interval: interval between two scan iterations on one channel.
5148 struct iwm_scan_channel_cfg_umac {
5150 uint8_t channel_num;
5152 uint16_t iter_interval;
5153 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */
5156 * struct iwm_scan_umac_schedule
5157 * @interval: interval in seconds between scan iterations
5158 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5159 * @reserved: for alignment and future use
5161 struct iwm_scan_umac_schedule {
5165 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */
5168 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5169 * parameters following channels configuration array.
5170 * @schedule: two scheduling plans.
5171 * @delay: delay in TUs before starting the first scan iteration
5172 * @reserved: for future use and alignment
5173 * @preq: probe request with IEs blocks
5174 * @direct_scan: list of SSIDs for directed active scan
5176 struct iwm_scan_req_umac_tail {
5177 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5178 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5181 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
5182 struct iwm_scan_probe_req preq;
5183 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5187 * struct iwm_scan_req_umac
5188 * @flags: &enum iwm_umac_scan_flags
5189 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5190 * @ooc_priority: out of channel priority - &enum iwm_scan_priority
5191 * @general_flags: &enum iwm_umac_scan_general_flags
5192 * @extended_dwell: dwell time for channels 1, 6 and 11
5193 * @active_dwell: dwell time for active scan
5194 * @passive_dwell: dwell time for passive scan
5195 * @fragmented_dwell: dwell time for fragmented passive scan
5196 * @max_out_time: max out of serving channel time
5197 * @suspend_time: max suspend time
5198 * @scan_priority: scan internal prioritization &enum iwm_scan_priority
5199 * @channel_flags: &enum iwm_scan_channel_flags
5200 * @n_channels: num of channels in scan request
5201 * @reserved: for future use and alignment
5202 * @data: &struct iwm_scan_channel_cfg_umac and
5203 * &struct iwm_scan_req_umac_tail
5205 struct iwm_scan_req_umac {
5208 uint32_t ooc_priority;
5209 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */
5210 uint32_t general_flags;
5211 uint8_t extended_dwell;
5212 uint8_t active_dwell;
5213 uint8_t passive_dwell;
5214 uint8_t fragmented_dwell;
5215 uint32_t max_out_time;
5216 uint32_t suspend_time;
5217 uint32_t scan_priority;
5218 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */
5219 uint8_t channel_flags;
5223 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */
5226 * struct iwm_umac_scan_abort
5227 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5230 struct iwm_umac_scan_abort {
5233 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */
5236 * struct iwm_umac_scan_complete
5237 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5238 * @last_schedule: last scheduling line
5239 * @last_iter: last scan iteration number
5240 * @scan status: &enum iwm_scan_offload_complete_status
5241 * @ebs_status: &enum iwm_scan_ebs_status
5242 * @time_from_last_iter: time elapsed from last iteration
5243 * @reserved: for future use
5245 struct iwm_umac_scan_complete {
5247 uint8_t last_schedule;
5251 uint32_t time_from_last_iter;
5253 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */
5255 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5
5257 * struct iwm_scan_offload_profile_match - match information
5258 * @bssid: matched bssid
5259 * @channel: channel where the match occurred
5261 * @matching_feature:
5262 * @matching_channels: bitmap of channels that matched, referencing
5263 * the channels passed in tue scan offload request
5265 struct iwm_scan_offload_profile_match {
5266 uint8_t bssid[IEEE80211_ADDR_LEN];
5270 uint8_t matching_feature;
5271 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
5272 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
5275 * struct iwm_scan_offload_profiles_query - match results query response
5276 * @matched_profiles: bitmap of matched profiles, referencing the
5277 * matches passed in the scan offload request
5278 * @last_scan_age: age of the last offloaded scan
5279 * @n_scans_done: number of offloaded scans done
5280 * @gp2_d0u: GP2 when D0U occurred
5281 * @gp2_invoked: GP2 when scan offload was invoked
5282 * @resume_while_scanning: not used
5283 * @self_recovery: obsolete
5284 * @reserved: reserved
5285 * @matches: array of match information, one for each match
5287 struct iwm_scan_offload_profiles_query {
5288 uint32_t matched_profiles;
5289 uint32_t last_scan_age;
5290 uint32_t n_scans_done;
5292 uint32_t gp2_invoked;
5293 uint8_t resume_while_scanning;
5294 uint8_t self_recovery;
5296 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES];
5297 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */
5300 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration
5301 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5302 * @scanned_channels: number of channels scanned and number of valid elements in
5304 * @status: one of SCAN_COMP_STATUS_*
5305 * @bt_status: BT on/off status
5306 * @last_channel: last channel that was scanned
5307 * @tsf_low: TSF timer (lower half) in usecs
5308 * @tsf_high: TSF timer (higher half) in usecs
5309 * @results: array of scan results, only "scanned_channels" of them are valid
5311 struct iwm_umac_scan_iter_complete_notif {
5313 uint8_t scanned_channels;
5316 uint8_t last_channel;
5319 struct iwm_scan_results_notif results[];
5320 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
5322 /* Please keep this enum *SORTED* by hex value.
5323 * Needed for binary search, otherwise a warning will be triggered.
5325 enum iwm_scan_subcmd_ids {
5326 IWM_GSCAN_START_CMD = 0x0,
5327 IWM_GSCAN_STOP_CMD = 0x1,
5328 IWM_GSCAN_SET_HOTLIST_CMD = 0x2,
5329 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3,
5330 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4,
5331 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5,
5332 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD,
5333 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE,
5334 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF,
5340 * enum iwm_sta_flags - flags for the ADD_STA host command
5341 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
5342 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
5343 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled
5344 * @IWM_STA_FLG_PS: set if STA is in Power Save
5345 * @IWM_STA_FLG_INVALID: set if STA is invalid
5346 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
5347 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
5348 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
5349 * @IWM_STA_FLG_PAN: STA is for PAN interface
5350 * @IWM_STA_FLG_CLASS_AUTH:
5351 * @IWM_STA_FLG_CLASS_ASSOC:
5352 * @IWM_STA_FLG_CLASS_MIMO_PROT:
5353 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
5354 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
5355 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
5356 * initialised by driver and can be updated by fw upon reception of
5357 * action frames that can change the channel width. When cleared the fw
5358 * will send all the frames in 20MHz even when FAT channel is requested.
5359 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
5360 * driver and can be updated by fw upon reception of action frames.
5361 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
5363 enum iwm_sta_flags {
5364 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
5365 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
5367 IWM_STA_FLG_DISABLE_TX = (1 << 4),
5369 IWM_STA_FLG_PS = (1 << 8),
5370 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
5371 IWM_STA_FLG_PAN = (1 << 13),
5372 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
5373 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
5374 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
5376 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
5377 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5378 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5379 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5380 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5381 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5382 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5383 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5384 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5385 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5387 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
5388 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5389 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5390 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5391 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5392 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5394 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
5395 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
5396 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
5397 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
5398 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
5400 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
5401 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
5402 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
5403 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
5407 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
5408 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
5409 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
5410 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
5411 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
5412 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
5413 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
5414 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
5415 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
5416 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
5417 * station info array (1 - n 1X mode)
5418 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
5419 * @IWM_STA_KEY_NOT_VALID: key is invalid
5420 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
5421 * @IWM_STA_KEY_MULTICAST: set for multical key
5422 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
5424 enum iwm_sta_key_flag {
5425 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
5426 IWM_STA_KEY_FLG_WEP = (1 << 0),
5427 IWM_STA_KEY_FLG_CCM = (2 << 0),
5428 IWM_STA_KEY_FLG_TKIP = (3 << 0),
5429 IWM_STA_KEY_FLG_EXT = (4 << 0),
5430 IWM_STA_KEY_FLG_CMAC = (6 << 0),
5431 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
5432 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
5434 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
5435 IWM_STA_KEY_FLG_KEYID_POS = 8,
5436 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
5437 IWM_STA_KEY_NOT_VALID = (1 << 11),
5438 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
5439 IWM_STA_KEY_MULTICAST = (1 << 14),
5440 IWM_STA_KEY_MFP = (1 << 15),
5444 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
5445 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
5446 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
5447 * @IWM_STA_MODIFY_TX_RATE: unused
5448 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
5449 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
5450 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
5451 * @IWM_STA_MODIFY_PROT_TH:
5452 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
5454 enum iwm_sta_modify_flag {
5455 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0),
5456 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
5457 IWM_STA_MODIFY_TX_RATE = (1 << 2),
5458 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
5459 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
5460 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
5461 IWM_STA_MODIFY_PROT_TH = (1 << 6),
5462 IWM_STA_MODIFY_QUEUES = (1 << 7),
5465 #define IWM_STA_MODE_MODIFY 1
5468 * enum iwm_sta_sleep_flag - type of sleep of the station
5469 * @IWM_STA_SLEEP_STATE_AWAKE:
5470 * @IWM_STA_SLEEP_STATE_PS_POLL:
5471 * @IWM_STA_SLEEP_STATE_UAPSD:
5472 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
5473 * (last) released frame
5475 enum iwm_sta_sleep_flag {
5476 IWM_STA_SLEEP_STATE_AWAKE = 0,
5477 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
5478 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
5479 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2),
5482 /* STA ID and color bits definitions */
5483 #define IWM_STA_ID_SEED (0x0f)
5484 #define IWM_STA_ID_POS (0)
5485 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
5487 #define IWM_STA_COLOR_SEED (0x7)
5488 #define IWM_STA_COLOR_POS (4)
5489 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5491 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5492 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5493 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5494 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5496 #define IWM_STA_KEY_MAX_NUM (16)
5497 #define IWM_STA_KEY_IDX_INVALID (0xff)
5498 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5499 #define IWM_MAX_GLOBAL_KEYS (4)
5500 #define IWM_STA_KEY_LEN_WEP40 (5)
5501 #define IWM_STA_KEY_LEN_WEP104 (13)
5504 * struct iwm_mvm_keyinfo - key information
5505 * @key_flags: type %iwm_sta_key_flag
5506 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5507 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5508 * @key_offset: key offset in the fw's key table
5509 * @key: 16-byte unicast decryption key
5510 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5511 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5512 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5514 struct iwm_mvm_keyinfo {
5516 uint8_t tkip_rx_tsc_byte2;
5518 uint16_t tkip_rx_ttak[5];
5522 uint64_t tx_secur_seq_cnt;
5523 uint64_t hw_tkip_mic_rx_key;
5524 uint64_t hw_tkip_mic_tx_key;
5527 #define IWM_ADD_STA_STATUS_MASK 0xFF
5528 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000
5529 #define IWM_ADD_STA_BAID_MASK 0x7F00
5530 #define IWM_ADD_STA_BAID_SHIFT 8
5533 * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table.
5534 * ( REPLY_ADD_STA = 0x18 )
5535 * @add_modify: 1: modify existing, 0: add new station
5537 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5538 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
5539 * @mac_id_n_color: the Mac context this station belongs to
5540 * @addr[IEEE80211_ADDR_LEN]: station's MAC address
5541 * @sta_id: index of station in uCode's station table
5542 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5543 * alone. 1 - modify, 0 - don't change.
5544 * @station_flags: look at %iwm_sta_flags
5545 * @station_flags_msk: what of %station_flags have changed
5546 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5547 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5548 * add_immediate_ba_ssn.
5549 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5550 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5551 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5552 * add_immediate_ba_tid.
5553 * @sleep_tx_count: number of packets to transmit to station even though it is
5554 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5555 * keeps track of STA sleep state.
5556 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5557 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5559 * @beamform_flags: beam forming controls
5560 * @tfd_queue_msk: tfd queues used by this station
5562 * The device contains an internal table of per-station information, with info
5563 * on security keys, aggregation parameters, and Tx rates for initial Tx
5564 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5566 * ADD_STA sets up the table entry for one station, either creating a new
5567 * entry, or modifying a pre-existing one.
5569 struct iwm_mvm_add_sta_cmd {
5572 uint16_t tid_disable_tx;
5573 uint32_t mac_id_n_color;
5574 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5577 uint8_t modify_mask;
5579 uint32_t station_flags;
5580 uint32_t station_flags_msk;
5581 uint8_t add_immediate_ba_tid;
5582 uint8_t remove_immediate_ba_tid;
5583 uint16_t add_immediate_ba_ssn;
5584 uint16_t sleep_tx_count;
5585 uint16_t sleep_state_flags;
5587 uint16_t beamform_flags;
5588 uint32_t tfd_queue_msk;
5589 } __packed; /* ADD_STA_CMD_API_S_VER_7 */
5592 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key
5593 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5594 * @sta_id: index of station in uCode's station table
5595 * @key_offset: key offset in key storage
5596 * @key_flags: type %iwm_sta_key_flag
5597 * @key: key material data
5598 * @key2: key material data
5599 * @rx_secur_seq_cnt: RX security sequence counter for the key
5600 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5601 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5603 struct iwm_mvm_add_sta_key_cmd {
5609 uint8_t rx_secur_seq_cnt[16];
5610 uint8_t tkip_rx_tsc_byte2;
5612 uint16_t tkip_rx_ttak[5];
5613 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5616 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command
5617 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5618 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5619 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5620 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5621 * that doesn't exist.
5623 enum iwm_mvm_add_sta_rsp_status {
5624 IWM_ADD_STA_SUCCESS = 0x1,
5625 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
5626 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
5627 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
5631 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table
5632 * ( IWM_REMOVE_STA = 0x19 )
5633 * @sta_id: the station id of the station to be removed
5635 struct iwm_mvm_rm_sta_cmd {
5637 uint8_t reserved[3];
5638 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5641 * struct iwm_mvm_mgmt_mcast_key_cmd
5642 * ( IWM_MGMT_MCAST_KEY = 0x1f )
5643 * @ctrl_flags: %iwm_sta_key_flag
5645 * @K1: IGTK master key
5647 * @sta_id: station ID that support IGTK
5649 * @receive_seq_cnt: initial RSC/PN needed for replay check
5651 struct iwm_mvm_mgmt_mcast_key_cmd {
5652 uint32_t ctrl_flags;
5658 uint64_t receive_seq_cnt;
5659 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5661 struct iwm_mvm_wep_key {
5666 uint8_t reserved2[3];
5670 struct iwm_mvm_wep_key_cmd {
5671 uint32_t mac_id_n_color;
5673 uint8_t decryption_type;
5676 struct iwm_mvm_wep_key wep_key[0];
5677 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5683 enum iwm_bt_coex_mode {
5684 IWM_BT_COEX_DISABLE = 0x0,
5685 IWM_BT_COEX_NW = 0x1,
5686 IWM_BT_COEX_BT = 0x2,
5687 IWM_BT_COEX_WIFI = 0x3,
5688 }; /* BT_COEX_MODES_E */
5690 enum iwm_bt_coex_enabled_modules {
5691 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0),
5692 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1),
5693 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2),
5694 IWM_BT_COEX_CORUN_ENABLED = (1 << 3),
5695 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4),
5696 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */
5699 * struct iwm_bt_coex_cmd - bt coex configuration command
5700 * @mode: enum %iwm_bt_coex_mode
5701 * @enabled_modules: enum %iwm_bt_coex_enabled_modules
5703 * The structure is used for the BT_COEX command.
5705 struct iwm_bt_coex_cmd {
5707 uint32_t enabled_modules;
5708 } __packed; /* BT_COEX_CMD_API_S_VER_6 */
5712 * Location Aware Regulatory (LAR) API - MCC updates
5716 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic
5717 * regulatory profile according to the given MCC (Mobile Country Code).
5718 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5719 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5720 * MCC in the cmd response will be the relevant MCC in the NVM.
5721 * @mcc: given mobile country code
5722 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5723 * @reserved: reserved for alignment
5725 struct iwm_mcc_update_cmd_v1 {
5729 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */
5732 * struct iwm_mcc_update_cmd - Request the device to update geographic
5733 * regulatory profile according to the given MCC (Mobile Country Code).
5734 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5735 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5736 * MCC in the cmd response will be the relevant MCC in the NVM.
5737 * @mcc: given mobile country code
5738 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5739 * @reserved: reserved for alignment
5740 * @key: integrity key for MCC API OEM testing
5741 * @reserved2: reserved
5743 struct iwm_mcc_update_cmd {
5748 uint32_t reserved2[5];
5749 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */
5752 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD.
5753 * Contains the new channel control profile map, if changed, and the new MCC
5754 * (mobile country code).
5755 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5756 * @status: see &enum iwm_mcc_update_status
5757 * @mcc: the new applied MCC
5758 * @cap: capabilities for all channels which matches the MCC
5759 * @source_id: the MCC source, see iwm_mcc_source
5760 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5761 * channels, depending on platform)
5762 * @channels: channel control data map, DWORD for each channel. Only the first
5765 struct iwm_mcc_update_resp_v1 {
5770 uint32_t n_channels;
5771 uint32_t channels[0];
5772 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */
5775 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD.
5776 * Contains the new channel control profile map, if changed, and the new MCC
5777 * (mobile country code).
5778 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5779 * @status: see &enum iwm_mcc_update_status
5780 * @mcc: the new applied MCC
5781 * @cap: capabilities for all channels which matches the MCC
5782 * @source_id: the MCC source, see iwm_mcc_source
5783 * @time: time elapsed from the MCC test start (in 30 seconds TU)
5784 * @reserved: reserved.
5785 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5786 * channels, depending on platform)
5787 * @channels: channel control data map, DWORD for each channel. Only the first
5790 struct iwm_mcc_update_resp {
5797 uint32_t n_channels;
5798 uint32_t channels[0];
5799 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */
5802 * struct iwm_mcc_chub_notif - chub notifies of mcc change
5803 * (MCC_CHUB_UPDATE_CMD = 0xc9)
5804 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
5805 * the cellular and connectivity cores that gets updates of the mcc, and
5806 * notifies the ucode directly of any mcc change.
5807 * The ucode requests the driver to request the device to update geographic
5808 * regulatory profile according to the given MCC (Mobile Country Code).
5809 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5810 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5811 * MCC in the cmd response will be the relevant MCC in the NVM.
5812 * @mcc: given mobile country code
5813 * @source_id: identity of the change originator, see iwm_mcc_source
5814 * @reserved1: reserved for alignment
5816 struct iwm_mcc_chub_notif {
5820 } __packed; /* LAR_MCC_NOTIFY_S */
5822 enum iwm_mcc_update_status {
5823 IWM_MCC_RESP_NEW_CHAN_PROFILE,
5824 IWM_MCC_RESP_SAME_CHAN_PROFILE,
5825 IWM_MCC_RESP_INVALID,
5826 IWM_MCC_RESP_NVM_DISABLED,
5827 IWM_MCC_RESP_ILLEGAL,
5828 IWM_MCC_RESP_LOW_PRIORITY,
5829 IWM_MCC_RESP_TEST_MODE_ACTIVE,
5830 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE,
5831 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE,
5834 enum iwm_mcc_source {
5835 IWM_MCC_SOURCE_OLD_FW = 0,
5836 IWM_MCC_SOURCE_ME = 1,
5837 IWM_MCC_SOURCE_BIOS = 2,
5838 IWM_MCC_SOURCE_3G_LTE_HOST = 3,
5839 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4,
5840 IWM_MCC_SOURCE_WIFI = 5,
5841 IWM_MCC_SOURCE_RESERVED = 6,
5842 IWM_MCC_SOURCE_DEFAULT = 7,
5843 IWM_MCC_SOURCE_UNINITIALIZED = 8,
5844 IWM_MCC_SOURCE_MCC_API = 9,
5845 IWM_MCC_SOURCE_GET_CURRENT = 0x10,
5846 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11,
5850 * struct iwm_dts_measurement_notif_v1 - measurements notification
5852 * @temp: the measured temperature
5853 * @voltage: the measured voltage
5855 struct iwm_dts_measurement_notif_v1 {
5858 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/
5861 * struct iwm_dts_measurement_notif_v2 - measurements notification
5863 * @temp: the measured temperature
5864 * @voltage: the measured voltage
5865 * @threshold_idx: the trip index that was crossed
5867 struct iwm_dts_measurement_notif_v2 {
5870 int32_t threshold_idx;
5871 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */
5874 * Some cherry-picked definitions
5877 #define IWM_FRAME_LIMIT 64
5880 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811:
5881 * As the firmware is slowly running out of command IDs and grouping of
5882 * commands is desirable anyway, the firmware is extending the command
5883 * header from 4 bytes to 8 bytes to introduce a group (in place of the
5884 * former flags field, since that's always 0 on commands and thus can
5885 * be easily used to distinguish between the two).
5887 * These functions retrieve specific information from the id field in
5888 * the iwm_host_cmd struct which contains the command id, the group id,
5889 * and the version of the command.
5891 static inline uint8_t
5892 iwm_cmd_opcode(uint32_t cmdid)
5894 return cmdid & 0xff;
5897 static inline uint8_t
5898 iwm_cmd_groupid(uint32_t cmdid)
5900 return ((cmdid & 0Xff00) >> 8);
5903 static inline uint8_t
5904 iwm_cmd_version(uint32_t cmdid)
5906 return ((cmdid & 0xff0000) >> 16);
5909 static inline uint32_t
5910 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version)
5912 return opcode + (groupid << 8) + (version << 16);
5915 /* make uint16_t wide id out of uint8_t group and opcode */
5916 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
5918 /* due to the conversion, this group is special */
5919 #define IWM_ALWAYS_LONG_GROUP 1
5921 struct iwm_cmd_header {
5928 struct iwm_cmd_header_wide {
5939 * enum iwm_power_scheme
5940 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode
5941 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default)
5942 * @IWM_POWER_LEVEL_LP - Low Power
5944 enum iwm_power_scheme {
5945 IWM_POWER_SCHEME_CAM = 1,
5946 IWM_POWER_SCHEME_BPS,
5950 #define IWM_DEF_CMD_PAYLOAD_SIZE 320
5951 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
5952 #define IWM_CMD_FAILED_MSK 0x40
5955 * struct iwm_device_cmd
5957 * For allocation of the command and tx queues, this establishes the overall
5958 * size of the largest command we send to uCode, except for commands that
5959 * aren't fully copied and use other TFD space.
5961 struct iwm_device_cmd {
5964 struct iwm_cmd_header hdr;
5965 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
5968 struct iwm_cmd_header_wide hdr_wide;
5969 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE -
5970 sizeof(struct iwm_cmd_header_wide) +
5971 sizeof(struct iwm_cmd_header)];
5976 struct iwm_rx_packet {
5978 * The first 4 bytes of the RX frame header contain both the RX frame
5979 * size and some flags.
5981 * 31: flag flush RB request
5982 * 30: flag ignore TC (terminal counter) request
5983 * 29: flag fast IRQ request
5985 * 13-00: RX frame size
5987 uint32_t len_n_flags;
5988 struct iwm_cmd_header hdr;
5992 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
5994 static inline uint32_t
5995 iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
5998 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
6001 static inline uint32_t
6002 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
6005 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
6009 #define IWM_MIN_DBM -100
6010 #define IWM_MAX_DBM -33 /* realistic guess */
6012 #define IWM_READ(sc, reg) \
6013 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
6015 #define IWM_WRITE(sc, reg, val) \
6016 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6018 #define IWM_WRITE_1(sc, reg, val) \
6019 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6021 #define IWM_SETBITS(sc, reg, mask) \
6022 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
6024 #define IWM_CLRBITS(sc, reg, mask) \
6025 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
6027 #define IWM_BARRIER_WRITE(sc) \
6028 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6029 BUS_SPACE_BARRIER_WRITE)
6031 #define IWM_BARRIER_READ_WRITE(sc) \
6032 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6033 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
6035 #endif /* __IF_IWM_REG_H__ */