4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
21 * This code is derived from software contributed to The DragonFly Project
22 * by Matthew Dillon <dillon@backplane.com>
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
34 * 3. Neither the name of The DragonFly Project nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific, prior written permission.
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
56 static int ahci_vt8251_attach(device_t);
57 static int ahci_ati_sb600_attach(device_t);
58 static int ahci_nvidia_mcp_attach(device_t);
59 static int ahci_pci_attach(device_t);
60 static int ahci_pci_detach(device_t);
62 static const struct ahci_device ahci_devices[] = {
63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA,
66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
73 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
74 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP79-SATA" },
76 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
85 static const struct ahci_pciid ahci_msi_blacklist[] = {
86 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, -1 },
87 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_AHCI, -1 },
89 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, -1 },
90 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, -1 },
92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa1 },
93 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa1 },
94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa1 },
95 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa1 },
96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa1 },
97 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa1 },
98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa1 },
99 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa1 },
101 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa2 },
102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa2 },
103 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa2 },
104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa2 },
105 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa2 },
106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa2 },
107 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa2 },
108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa2 }
111 static int ahci_msi_enable = 1;
112 TUNABLE_INT("hw.ahci.msi.enable", &ahci_msi_enable);
115 * Match during probe and attach. The device does not yet have a softc.
117 const struct ahci_device *
118 ahci_lookup_device(device_t dev)
120 const struct ahci_device *ad;
121 u_int16_t vendor = pci_get_vendor(dev);
122 u_int16_t product = pci_get_device(dev);
123 u_int8_t class = pci_get_class(dev);
124 u_int8_t subclass = pci_get_subclass(dev);
125 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
129 * Generally speaking if the pci device does not identify as
132 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
133 progif == PCIP_STORAGE_SATA_AHCI_1_0) {
139 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
140 if (ad->ad_vendor == vendor && ad->ad_product == product)
145 * Last ad is the default match if the PCI device matches SATA.
153 * Attach functions. They all eventually fall through to ahci_pci_attach().
156 ahci_vt8251_attach(device_t dev)
158 struct ahci_softc *sc = device_get_softc(dev);
160 sc->sc_flags |= AHCI_F_NO_NCQ;
161 return (ahci_pci_attach(dev));
165 ahci_ati_sb600_attach(device_t dev)
167 struct ahci_softc *sc = device_get_softc(dev);
169 u_int8_t subclass = pci_get_subclass(dev);
172 if (subclass == PCIS_STORAGE_IDE) {
173 revid = pci_read_config(dev, PCIR_REVID, 1);
174 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
175 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
176 magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
177 pci_write_config(dev, PCIR_REVID,
178 (PCIC_STORAGE << 24) |
179 (PCIS_STORAGE_SATA << 16) |
180 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
182 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
185 sc->sc_flags |= AHCI_F_IGN_FR;
186 return (ahci_pci_attach(dev));
190 ahci_nvidia_mcp_attach(device_t dev)
192 struct ahci_softc *sc = device_get_softc(dev);
194 sc->sc_flags |= AHCI_F_IGN_FR;
195 return (ahci_pci_attach(dev));
199 ahci_pci_attach(device_t dev)
201 struct ahci_softc *sc = device_get_softc(dev);
202 struct ahci_port *ap;
209 int i, error, msi_enable, rev, fbs;
210 const char *revision;
212 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
213 device_printf(dev, "BIOS disabled PCI interrupt, "
215 pci_write_config(dev, PCIR_COMMAND,
216 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
222 * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
225 msi_enable = ahci_msi_enable;
227 vid = pci_get_vendor(dev);
228 did = pci_get_device(dev);
229 rev = pci_get_revid(dev);
230 for (i = 0; i < NELEM(ahci_msi_blacklist); ++i) {
231 const struct ahci_pciid *id = &ahci_msi_blacklist[i];
233 if (vid == id->ahci_vid && did == id->ahci_did) {
234 if (id->ahci_rev < 0 || id->ahci_rev == rev) {
241 sc->sc_irq_type = pci_alloc_1intr(dev, msi_enable,
242 &sc->sc_rid_irq, &irq_flags);
244 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
246 if (sc->sc_irq == NULL) {
247 device_printf(dev, "unable to map interrupt\n");
248 ahci_pci_detach(dev);
253 * When mapping the register window store the tag and handle
254 * separately so we can use the tag with per-port bus handle
257 sc->sc_rid_regs = PCIR_BAR(5);
258 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
259 &sc->sc_rid_regs, RF_ACTIVE);
260 if (sc->sc_regs == NULL) {
261 device_printf(dev, "unable to map registers\n");
262 ahci_pci_detach(dev);
265 sc->sc_iot = rman_get_bustag(sc->sc_regs);
266 sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
269 * Initialize the chipset and then set the interrupt vector up
271 error = ahci_init(sc);
273 ahci_pci_detach(dev);
278 * Get the AHCI capabilities and max number of concurrent
279 * command tags and set up the DMA tags. Adjust the saved
280 * sc_cap according to override flags.
282 cap = sc->sc_cap = ahci_read(sc, AHCI_REG_CAP);
283 if (sc->sc_flags & AHCI_F_NO_NCQ)
284 sc->sc_cap &= ~AHCI_REG_CAP_SNCQ;
285 if (sc->sc_flags & AHCI_F_FORCE_FBSS)
286 sc->sc_cap |= AHCI_REG_CAP_FBSS;
289 * We assume at least 4 commands.
291 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
292 if (sc->sc_ncmds < 4) {
293 device_printf(dev, "NCS must probe a value >= 4\n");
294 ahci_pci_detach(dev);
298 addr = (cap & AHCI_REG_CAP_S64A) ?
299 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
302 * DMA tags for allocation of DMA memory buffers, lists, and so
303 * forth. These are typically per-port.
305 * When FIS-based switching is supported we need a rfis for
306 * each target (4K total). The spec also requires 4K alignment
309 fbs = (cap & AHCI_REG_CAP_FBSS) ? 16 : 1;
312 error += bus_dma_tag_create(
313 NULL, /* parent tag */
314 256 * fbs, /* alignment */
315 PAGE_SIZE, /* boundary */
317 BUS_SPACE_MAXADDR, /* hiaddr */
319 NULL, /* filterarg */
320 sizeof(struct ahci_rfis) * fbs, /* [max]size */
322 sizeof(struct ahci_rfis) * fbs, /* maxsegsz */
324 &sc->sc_tag_rfis); /* return tag */
326 error += bus_dma_tag_create(
327 NULL, /* parent tag */
329 4096 * 1024, /* boundary */
331 BUS_SPACE_MAXADDR, /* hiaddr */
333 NULL, /* filterarg */
334 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
336 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
338 &sc->sc_tag_cmdh); /* return tag */
341 * NOTE: ahci_cmd_table is sized to a power of 2
343 error += bus_dma_tag_create(
344 NULL, /* parent tag */
345 sizeof(struct ahci_cmd_table), /* alignment */
346 4096 * 1024, /* boundary */
348 BUS_SPACE_MAXADDR, /* hiaddr */
350 NULL, /* filterarg */
351 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
353 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
355 &sc->sc_tag_cmdt); /* return tag */
358 * The data tag is used for later dmamaps and not immediately
361 error += bus_dma_tag_create(
362 NULL, /* parent tag */
366 BUS_SPACE_MAXADDR, /* hiaddr */
368 NULL, /* filterarg */
369 4096 * 1024, /* maxiosize */
370 AHCI_MAX_PRDT, /* maxsegs */
371 65536, /* maxsegsz */
373 &sc->sc_tag_data); /* return tag */
376 device_printf(dev, "unable to create dma tags\n");
377 ahci_pci_detach(dev);
381 switch (cap & AHCI_REG_CAP_ISS) {
382 case AHCI_REG_CAP_ISS_G1:
385 case AHCI_REG_CAP_ISS_G2:
388 case AHCI_REG_CAP_ISS_G3:
396 /* check the revision */
397 reg = ahci_read(sc, AHCI_REG_VS);
400 case AHCI_REG_VS_0_95:
401 revision = "AHCI 0.95";
403 case AHCI_REG_VS_1_0:
404 revision = "AHCI 1.0";
406 case AHCI_REG_VS_1_1:
407 revision = "AHCI 1.1";
409 case AHCI_REG_VS_1_2:
410 revision = "AHCI 1.2";
412 case AHCI_REG_VS_1_3:
413 revision = "AHCI 1.3";
415 case AHCI_REG_VS_1_4:
416 revision = "AHCI 1.4";
418 case AHCI_REG_VS_1_5:
419 revision = "AHCI 1.5"; /* future will catch up to us */
422 device_printf(sc->sc_dev,
423 "Warning: Unknown AHCI revision 0x%08x\n", reg);
424 revision = "AHCI <unknown>";
429 if (reg >= AHCI_REG_VS_1_3) {
430 cap2 = ahci_read(sc, AHCI_REG_CAP2);
432 "%s cap 0x%b cap2 0x%b, %d ports, "
433 "%d tags/port, gen %s\n",
437 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
441 "%s cap 0x%b, %d ports, "
442 "%d tags/port, gen %s\n",
445 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
449 pi = ahci_read(sc, AHCI_REG_PI);
450 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
454 /* Naive coalescing support - enable for all ports. */
455 if (cap & AHCI_REG_CAP_CCCS) {
456 u_int16_t ccc_timeout = 20;
457 u_int8_t ccc_numcomplete = 12;
460 /* disable coalescing during reconfiguration. */
461 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
462 ccc_ctl &= ~0x00000001;
463 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
465 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
466 if (pi & sc->sc_ccc_mask) {
467 /* A conflict with the implemented port list? */
468 printf("%s: coalescing interrupt/implemented port list "
469 "conflict, PI: %08x, ccc_mask: %08x\n",
470 DEVNAME(sc), pi, sc->sc_ccc_mask);
475 /* ahci_port_start will enable each port when it starts. */
476 sc->sc_ccc_ports = pi;
477 sc->sc_ccc_ports_cur = 0;
479 /* program thresholds and enable overall coalescing. */
480 ccc_ctl &= ~0xffffff00;
481 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
482 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
483 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
484 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
489 * Allocate per-port resources
491 * Ignore attach errors, leave the port intact for
492 * rescan and continue the loop.
494 * All ports are attached in parallel but the CAM scan-bus
495 * is held up until all ports are attached so we get a deterministic
498 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
499 if ((pi & (1 << i)) == 0) {
500 /* dont allocate stuff if the port isnt implemented */
503 error = ahci_port_alloc(sc, i);
507 * Setup the interrupt vector and enable interrupts. Note that
508 * since the irq may be shared we do not set it up until we are
512 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
514 &sc->sc_irq_handle, NULL);
518 device_printf(dev, "unable to install interrupt\n");
519 ahci_pci_detach(dev);
524 * Before marking the sc as good, which allows the interrupt
525 * subsystem to operate on the ports, wait for all the port threads
526 * to get past their initial pre-probe init. Otherwise an interrupt
527 * may try to process the port before it has been initialized.
529 for (i = 0; i < AHCI_MAX_PORTS; i++) {
530 if ((ap = sc->sc_ports[i]) != NULL) {
531 while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
532 tsleep(&ap->ap_signal, 0, "ahprb1", hz);
537 * Master interrupt enable, and call ahci_intr() in case we race
538 * our AHCI_F_INT_GOOD flag.
541 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
542 sc->sc_flags |= AHCI_F_INT_GOOD;
547 * All ports are probing in parallel. Wait for them to finish
548 * and then issue the cam attachment and bus scan serially so
549 * the 'da' assignments are deterministic.
551 for (i = 0; i < AHCI_MAX_PORTS; i++) {
552 if ((ap = sc->sc_ports[i]) != NULL) {
553 while (ap->ap_signal & AP_SIGF_INIT)
554 tsleep(&ap->ap_signal, 0, "ahprb2", hz);
555 ahci_os_lock_port(ap);
556 if (ahci_cam_attach(ap) == 0) {
557 ahci_cam_changed(ap, NULL, -1);
558 ahci_os_unlock_port(ap);
559 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
560 tsleep(&ap->ap_flags, 0, "ahprb2", hz);
563 ahci_os_unlock_port(ap);
572 * Device unload / detachment
575 ahci_pci_detach(device_t dev)
577 struct ahci_softc *sc = device_get_softc(dev);
578 struct ahci_port *ap;
582 * Disable the controller and de-register the interrupt, if any.
584 * XXX interlock last interrupt?
586 sc->sc_flags &= ~AHCI_F_INT_GOOD;
588 ahci_write(sc, AHCI_REG_GHC, 0);
590 if (sc->sc_irq_handle) {
591 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
592 sc->sc_irq_handle = NULL;
596 * Free port structures and DMA memory
598 for (i = 0; i < AHCI_MAX_PORTS; i++) {
599 ap = sc->sc_ports[i];
602 ahci_port_free(sc, i);
607 * Clean up the bus space
610 bus_release_resource(dev, SYS_RES_IRQ,
611 sc->sc_rid_irq, sc->sc_irq);
615 if (sc->sc_irq_type == PCI_INTR_TYPE_MSI)
616 pci_release_msi(dev);
619 bus_release_resource(dev, SYS_RES_MEMORY,
620 sc->sc_rid_regs, sc->sc_regs);
624 if (sc->sc_tag_rfis) {
625 bus_dma_tag_destroy(sc->sc_tag_rfis);
626 sc->sc_tag_rfis = NULL;
628 if (sc->sc_tag_cmdh) {
629 bus_dma_tag_destroy(sc->sc_tag_cmdh);
630 sc->sc_tag_cmdh = NULL;
632 if (sc->sc_tag_cmdt) {
633 bus_dma_tag_destroy(sc->sc_tag_cmdt);
634 sc->sc_tag_cmdt = NULL;
636 if (sc->sc_tag_data) {
637 bus_dma_tag_destroy(sc->sc_tag_data);
638 sc->sc_tag_data = NULL;