2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <sys/resourcevar.h>
56 #include <sys/sfbuf.h>
59 #include <drm/i915_drm.h>
61 #include "intel_drv.h"
62 #include "intel_ringbuffer.h"
63 #include <linux/completion.h>
64 #include <linux/jiffies.h>
65 #include <linux/time.h>
67 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
70 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
71 unsigned alignment, bool map_and_fenceable);
72 static int i915_gem_phys_pwrite(struct drm_device *dev,
73 struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
74 uint64_t size, struct drm_file *file_priv);
76 static void i915_gem_write_fence(struct drm_device *dev, int reg,
77 struct drm_i915_gem_object *obj);
78 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
79 struct drm_i915_fence_reg *fence,
82 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
84 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
85 uint32_t size, int tiling_mode);
86 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
88 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
89 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
91 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
94 i915_gem_release_mmap(obj);
96 /* As we do not have an associated fence register, we will force
97 * a tiling change if we ever need to acquire one.
99 obj->fence_dirty = false;
100 obj->fence_reg = I915_FENCE_REG_NONE;
103 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
104 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
105 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
106 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
107 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
108 uint32_t flush_domains);
109 static void i915_gem_reset_fences(struct drm_device *dev);
110 static void i915_gem_lowmem(void *arg);
112 static int i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
113 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file);
115 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
116 long i915_gem_wired_pages_cnt;
118 /* some bookkeeping */
119 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
123 dev_priv->mm.object_count++;
124 dev_priv->mm.object_memory += size;
127 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
131 dev_priv->mm.object_count--;
132 dev_priv->mm.object_memory -= size;
136 i915_gem_wait_for_error(struct drm_device *dev)
138 struct drm_i915_private *dev_priv = dev->dev_private;
139 struct completion *x = &dev_priv->error_completion;
142 if (!atomic_read(&dev_priv->mm.wedged))
146 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
147 * userspace. If it takes that long something really bad is going on and
148 * we should simply try to bail out and fail as gracefully as possible.
150 ret = wait_for_completion_interruptible_timeout(x, 10*hz);
152 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
154 } else if (ret < 0) {
158 if (atomic_read(&dev_priv->mm.wedged)) {
159 /* GPU is hung, bump the completion count to account for
160 * the token we just consumed so that we never hit zero and
161 * end up waiting upon a subsequent completion event that
164 spin_lock(&x->wait.lock);
166 spin_unlock(&x->wait.lock);
171 int i915_mutex_lock_interruptible(struct drm_device *dev)
175 ret = i915_gem_wait_for_error(dev);
179 ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
183 WARN_ON(i915_verify_lists(dev));
188 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
194 i915_gem_init_ioctl(struct drm_device *dev, void *data,
195 struct drm_file *file)
197 struct drm_i915_gem_init *args = data;
199 if (drm_core_check_feature(dev, DRIVER_MODESET))
202 if (args->gtt_start >= args->gtt_end ||
203 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
206 /* GEM with user mode setting was never supported on ilk and later. */
207 if (INTEL_INFO(dev)->gen >= 5)
211 * XXXKIB. The second-time initialization should be guarded
214 lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
215 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
216 lockmgr(&dev->dev_lock, LK_RELEASE);
222 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
223 struct drm_file *file)
225 struct drm_i915_private *dev_priv = dev->dev_private;
226 struct drm_i915_gem_get_aperture *args = data;
227 struct drm_i915_gem_object *obj;
232 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
234 pinned += obj->gtt_space->size;
237 args->aper_size = dev_priv->mm.gtt_total;
238 args->aper_available_size = args->aper_size - pinned;
244 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
247 struct drm_i915_gem_object *obj;
251 size = roundup(size, PAGE_SIZE);
255 obj = i915_gem_alloc_object(dev, size);
260 ret = drm_gem_handle_create(file, &obj->base, &handle);
262 drm_gem_object_release(&obj->base);
263 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
264 drm_free(obj, DRM_I915_GEM);
268 /* drop reference from allocate - handle holds it now */
269 drm_gem_object_unreference(&obj->base);
275 i915_gem_dumb_create(struct drm_file *file,
276 struct drm_device *dev,
277 struct drm_mode_create_dumb *args)
280 /* have to work out size/pitch and return them */
281 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
282 args->size = args->pitch * args->height;
283 return (i915_gem_create(file, dev, args->size, &args->handle));
286 int i915_gem_dumb_destroy(struct drm_file *file,
287 struct drm_device *dev,
291 return (drm_gem_handle_delete(file, handle));
295 * Creates a new mm object and returns a handle to it.
298 i915_gem_create_ioctl(struct drm_device *dev, void *data,
299 struct drm_file *file)
301 struct drm_i915_gem_create *args = data;
303 return (i915_gem_create(file, dev, args->size, &args->handle));
306 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
308 drm_i915_private_t *dev_priv;
310 dev_priv = obj->base.dev->dev_private;
311 return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
312 obj->tiling_mode != I915_TILING_NONE);
316 * Reads data from the object referenced by handle.
318 * On error, the contents of *data are undefined.
321 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
322 struct drm_file *file)
324 struct drm_i915_gem_pread *args;
327 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
328 args->offset, UIO_READ, file));
332 * Writes data to the object referenced by handle.
334 * On error, the contents of the buffer that were to be modified are undefined.
337 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
338 struct drm_file *file)
340 struct drm_i915_gem_pwrite *args;
343 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
344 args->offset, UIO_WRITE, file));
348 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
351 if (atomic_read(&dev_priv->mm.wedged)) {
352 struct completion *x = &dev_priv->error_completion;
353 bool recovery_complete;
355 /* Give the error handler a chance to run. */
356 spin_lock(&x->wait.lock);
357 recovery_complete = x->done > 0;
358 spin_unlock(&x->wait.lock);
360 /* Non-interruptible callers can't handle -EAGAIN, hence return
361 * -EIO unconditionally for these. */
365 /* Recovery complete, but still wedged means reset failure. */
366 if (recovery_complete)
376 * Compare seqno against outstanding lazy request. Emit a request if they are
380 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
384 DRM_LOCK_ASSERT(ring->dev);
387 if (seqno == ring->outstanding_lazy_request)
388 ret = i915_add_request(ring, NULL, NULL);
394 * __wait_seqno - wait until execution of seqno has finished
395 * @ring: the ring expected to report seqno
397 * @interruptible: do an interruptible wait (normally yes)
398 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
400 * Returns 0 if the seqno was found within the alloted time. Else returns the
401 * errno with remaining time filled in timeout argument.
403 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
404 bool interruptible, struct timespec *timeout)
406 drm_i915_private_t *dev_priv = ring->dev->dev_private;
407 struct timespec before, now, wait_time={1,0};
408 unsigned long timeout_jiffies;
410 bool wait_forever = true;
413 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
416 if (timeout != NULL) {
417 wait_time = *timeout;
418 wait_forever = false;
421 timeout_jiffies = timespec_to_jiffies(&wait_time);
423 if (WARN_ON(!ring->irq_get(ring)))
426 /* Record current time in case interrupted by signal, or wedged * */
427 getrawmonotonic(&before);
430 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
431 atomic_read(&dev_priv->mm.wedged))
434 end = wait_event_interruptible_timeout(ring->irq_queue,
438 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
441 ret = i915_gem_check_wedge(dev_priv, interruptible);
444 } while (end == 0 && wait_forever);
446 getrawmonotonic(&now);
452 struct timespec sleep_time = timespec_sub(now, before);
453 *timeout = timespec_sub(*timeout, sleep_time);
458 case -EAGAIN: /* Wedged */
459 case -ERESTARTSYS: /* Signal */
461 case 0: /* Timeout */
463 set_normalized_timespec(timeout, 0, 0);
464 return -ETIMEDOUT; /* -ETIME on Linux */
465 default: /* Completed */
466 WARN_ON(end < 0); /* We're not aware of other errors */
472 * Waits for a sequence number to be signaled, and cleans up the
473 * request and object lists appropriately for that event.
476 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
478 drm_i915_private_t *dev_priv = ring->dev->dev_private;
483 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
487 ret = i915_gem_check_olr(ring, seqno);
491 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
497 * Ensures that all rendering to the object has completed and the object is
498 * safe to unbind from the GTT or access from the CPU.
500 static __must_check int
501 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
508 seqno = obj->last_write_seqno;
510 seqno = obj->last_read_seqno;
514 ret = i915_wait_seqno(obj->ring, seqno);
518 /* Manually manage the write flush as we may have not yet retired
521 if (obj->last_write_seqno &&
522 i915_seqno_passed(seqno, obj->last_write_seqno)) {
523 obj->last_write_seqno = 0;
524 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
527 i915_gem_retire_requests_ring(obj->ring);
532 * Ensures that an object will eventually get non-busy by flushing any required
533 * write domains, emitting any outstanding lazy request and retiring and
534 * completed requests.
537 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
542 ret = i915_gem_object_flush_gpu_write_domain(obj);
546 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
550 i915_gem_retire_requests_ring(obj->ring);
557 * Called when user space prepares to use an object with the CPU, either
558 * through the mmap ioctl's mapping or a GTT mapping.
561 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
562 struct drm_file *file)
564 struct drm_i915_gem_set_domain *args = data;
565 struct drm_i915_gem_object *obj;
566 uint32_t read_domains = args->read_domains;
567 uint32_t write_domain = args->write_domain;
570 /* Only handle setting domains to types used by the CPU. */
571 if (write_domain & I915_GEM_GPU_DOMAINS)
574 if (read_domains & I915_GEM_GPU_DOMAINS)
577 /* Having something in the write domain implies it's in the read
578 * domain, and only that read domain. Enforce that in the request.
580 if (write_domain != 0 && read_domains != write_domain)
583 ret = i915_mutex_lock_interruptible(dev);
587 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
588 if (&obj->base == NULL) {
593 if (read_domains & I915_GEM_DOMAIN_GTT) {
594 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
596 /* Silently promote "you're not bound, there was nothing to do"
597 * to success, since the client was just asking us to
598 * make sure everything was done.
603 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
606 drm_gem_object_unreference(&obj->base);
613 * Called when user space has done writes to this buffer
616 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
617 struct drm_file *file)
619 struct drm_i915_gem_sw_finish *args = data;
620 struct drm_i915_gem_object *obj;
623 ret = i915_mutex_lock_interruptible(dev);
626 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
627 if (&obj->base == NULL) {
632 /* Pinned buffers may be scanout, so flush the cache */
633 if (obj->pin_count != 0)
634 i915_gem_object_flush_cpu_write_domain(obj);
636 drm_gem_object_unreference(&obj->base);
643 * Maps the contents of an object, returning the address it is mapped
646 * While the mapping holds a reference on the contents of the object, it doesn't
647 * imply a ref on the object itself.
650 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
651 struct drm_file *file)
653 struct drm_i915_gem_mmap *args = data;
654 struct drm_gem_object *obj;
655 struct proc *p = curproc;
656 vm_map_t map = &p->p_vmspace->vm_map;
661 obj = drm_gem_object_lookup(dev, file, args->handle);
668 size = round_page(args->size);
670 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
678 vm_object_hold(obj->vm_obj);
679 vm_object_reference_locked(obj->vm_obj);
680 vm_object_drop(obj->vm_obj);
681 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
682 PAGE_SIZE, /* align */
684 VM_MAPTYPE_NORMAL, /* maptype */
685 VM_PROT_READ | VM_PROT_WRITE, /* prot */
686 VM_PROT_READ | VM_PROT_WRITE, /* max */
687 MAP_SHARED /* cow */);
688 if (rv != KERN_SUCCESS) {
689 vm_object_deallocate(obj->vm_obj);
690 error = -vm_mmap_to_errno(rv);
692 args->addr_ptr = (uint64_t)addr;
695 drm_gem_object_unreference(obj);
700 * i915_gem_release_mmap - remove physical page mappings
701 * @obj: obj in question
703 * Preserve the reservation of the mmapping with the DRM core code, but
704 * relinquish ownership of the pages back to the system.
706 * It is vital that we remove the page mapping if we have mapped a tiled
707 * object through the GTT and then lose the fence register due to
708 * resource pressure. Similarly if the object has been moved out of the
709 * aperture, than pages mapped into userspace must be revoked. Removing the
710 * mapping will then trigger a page fault on the next user access, allowing
711 * fixup by i915_gem_fault().
714 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
720 if (!obj->fault_mappable)
723 devobj = cdev_pager_lookup(obj);
724 if (devobj != NULL) {
725 page_count = OFF_TO_IDX(obj->base.size);
727 VM_OBJECT_LOCK(devobj);
728 for (i = 0; i < page_count; i++) {
729 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
732 cdev_pager_free_page(devobj, m);
734 VM_OBJECT_UNLOCK(devobj);
735 vm_object_deallocate(devobj);
738 obj->fault_mappable = false;
742 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
746 if (INTEL_INFO(dev)->gen >= 4 ||
747 tiling_mode == I915_TILING_NONE)
750 /* Previous chips need a power-of-two fence region when tiling */
751 if (INTEL_INFO(dev)->gen == 3)
752 gtt_size = 1024*1024;
756 while (gtt_size < size)
763 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
764 * @obj: object to check
766 * Return the required GTT alignment for an object, taking into account
767 * potential fence register mapping.
770 i915_gem_get_gtt_alignment(struct drm_device *dev,
776 * Minimum alignment is 4k (GTT page size), but might be greater
777 * if a fence register is needed for the object.
779 if (INTEL_INFO(dev)->gen >= 4 ||
780 tiling_mode == I915_TILING_NONE)
784 * Previous chips need to be aligned to the size of the smallest
785 * fence register that can contain the object.
787 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
791 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
794 * @size: size of the object
795 * @tiling_mode: tiling mode of the object
797 * Return the required GTT alignment for an object, only taking into account
798 * unfenced tiled surface requirements.
801 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
806 if (tiling_mode == I915_TILING_NONE)
810 * Minimum alignment is 4k (GTT page size) for sane hw.
812 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
816 * Previous hardware however needs to be aligned to a power-of-two
817 * tile height. The simplest method for determining this is to reuse
818 * the power-of-tile object size.
820 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
824 i915_gem_mmap_gtt(struct drm_file *file,
825 struct drm_device *dev,
829 struct drm_i915_private *dev_priv;
830 struct drm_i915_gem_object *obj;
833 dev_priv = dev->dev_private;
835 ret = i915_mutex_lock_interruptible(dev);
839 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
840 if (&obj->base == NULL) {
845 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
850 if (obj->madv != I915_MADV_WILLNEED) {
851 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
856 ret = drm_gem_create_mmap_offset(&obj->base);
860 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
863 drm_gem_object_unreference(&obj->base);
870 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
872 * @data: GTT mapping ioctl data
873 * @file: GEM object info
875 * Simply returns the fake offset to userspace so it can mmap it.
876 * The mmap call will end up in drm_gem_mmap(), which will set things
877 * up so we can get faults in the handler above.
879 * The fault handler will take care of binding the object into the GTT
880 * (since it may have been evicted to make room for something), allocating
881 * a fence register, and mapping the appropriate aperture address into
885 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
886 struct drm_file *file)
888 struct drm_i915_private *dev_priv;
889 struct drm_i915_gem_mmap_gtt *args = data;
891 dev_priv = dev->dev_private;
893 return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
896 /* Immediately discard the backing storage */
898 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
902 vm_obj = obj->base.vm_obj;
903 VM_OBJECT_LOCK(vm_obj);
904 vm_object_page_remove(vm_obj, 0, 0, false);
905 VM_OBJECT_UNLOCK(vm_obj);
906 obj->madv = __I915_MADV_PURGED;
910 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
912 return obj->madv == I915_MADV_DONTNEED;
915 static inline void vm_page_reference(vm_page_t m)
917 vm_page_flag_set(m, PG_REFERENCED);
921 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
926 BUG_ON(obj->madv == __I915_MADV_PURGED);
928 if (obj->tiling_mode != I915_TILING_NONE)
929 i915_gem_object_save_bit_17_swizzle(obj);
930 if (obj->madv == I915_MADV_DONTNEED)
932 page_count = obj->base.size / PAGE_SIZE;
933 VM_OBJECT_LOCK(obj->base.vm_obj);
934 #if GEM_PARANOID_CHECK_GTT
935 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
937 for (i = 0; i < page_count; i++) {
941 if (obj->madv == I915_MADV_WILLNEED)
942 vm_page_reference(m);
943 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
944 vm_page_unwire(obj->pages[i], 1);
945 vm_page_wakeup(obj->pages[i]);
946 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
948 VM_OBJECT_UNLOCK(obj->base.vm_obj);
950 drm_free(obj->pages, DRM_I915_GEM);
955 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
958 struct drm_device *dev;
961 int page_count, i, j;
964 KASSERT(obj->pages == NULL, ("Obj already has pages"));
965 page_count = obj->base.size / PAGE_SIZE;
966 obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
968 vm_obj = obj->base.vm_obj;
969 VM_OBJECT_LOCK(vm_obj);
970 for (i = 0; i < page_count; i++) {
971 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
974 VM_OBJECT_UNLOCK(vm_obj);
975 if (i915_gem_object_needs_bit17_swizzle(obj))
976 i915_gem_object_do_bit_17_swizzle(obj);
980 for (j = 0; j < i; j++) {
982 vm_page_busy_wait(m, FALSE, "i915gem");
983 vm_page_unwire(m, 0);
985 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
987 VM_OBJECT_UNLOCK(vm_obj);
988 drm_free(obj->pages, DRM_I915_GEM);
994 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
995 struct intel_ring_buffer *ring)
997 struct drm_device *dev = obj->base.dev;
998 struct drm_i915_private *dev_priv = dev->dev_private;
999 u32 seqno = intel_ring_get_seqno(ring);
1001 BUG_ON(ring == NULL);
1004 /* Add a reference if we're newly entering the active list. */
1006 drm_gem_object_reference(&obj->base);
1010 /* Move from whatever list we were on to the tail of execution. */
1011 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1012 list_move_tail(&obj->ring_list, &ring->active_list);
1014 obj->last_read_seqno = seqno;
1016 if (obj->fenced_gpu_access) {
1017 obj->last_fenced_seqno = seqno;
1019 /* Bump MRU to take account of the delayed flush */
1020 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1021 struct drm_i915_fence_reg *reg;
1023 reg = &dev_priv->fence_regs[obj->fence_reg];
1024 list_move_tail(®->lru_list,
1025 &dev_priv->mm.fence_list);
1031 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1033 struct drm_device *dev = obj->base.dev;
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1036 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1037 BUG_ON(!obj->active);
1039 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1041 list_del_init(&obj->ring_list);
1044 obj->last_read_seqno = 0;
1045 obj->last_write_seqno = 0;
1046 obj->base.write_domain = 0;
1048 obj->last_fenced_seqno = 0;
1049 obj->fenced_gpu_access = false;
1052 drm_gem_object_unreference(&obj->base);
1054 WARN_ON(i915_verify_lists(dev));
1058 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1060 struct drm_i915_private *dev_priv = dev->dev_private;
1061 struct intel_ring_buffer *ring;
1064 /* The hardware uses various monotonic 32-bit counters, if we
1065 * detect that they will wraparound we need to idle the GPU
1066 * and reset those counters.
1069 for_each_ring(ring, dev_priv, i) {
1070 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1071 ret |= ring->sync_seqno[j] != 0;
1076 ret = i915_gpu_idle(dev);
1080 i915_gem_retire_requests(dev);
1081 for_each_ring(ring, dev_priv, i) {
1082 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1083 ring->sync_seqno[j] = 0;
1090 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1094 /* reserve 0 for non-seqno */
1095 if (dev_priv->next_seqno == 0) {
1096 int ret = i915_gem_handle_seqno_wrap(dev);
1100 dev_priv->next_seqno = 1;
1103 *seqno = dev_priv->next_seqno++;
1108 i915_add_request(struct intel_ring_buffer *ring,
1109 struct drm_file *file,
1112 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1113 struct drm_i915_gem_request *request;
1114 u32 request_ring_position;
1119 * Emit any outstanding flushes - execbuf can fail to emit the flush
1120 * after having emitted the batchbuffer command. Hence we need to fix
1121 * things up similar to emitting the lazy request. The difference here
1122 * is that the flush _must_ happen before the next request, no matter
1125 if (ring->gpu_caches_dirty) {
1126 ret = i915_gem_flush_ring(ring, 0, I915_GEM_GPU_DOMAINS);
1130 ring->gpu_caches_dirty = false;
1133 request = kmalloc(sizeof(*request), DRM_I915_GEM, M_WAITOK | M_ZERO);
1134 if (request == NULL)
1137 /* Record the position of the start of the request so that
1138 * should we detect the updated seqno part-way through the
1139 * GPU processing the request, we never over-estimate the
1140 * position of the head.
1142 request_ring_position = intel_ring_get_tail(ring);
1144 ret = ring->add_request(ring);
1146 kfree(request, DRM_I915_GEM);
1150 request->seqno = intel_ring_get_seqno(ring);
1151 request->ring = ring;
1152 request->tail = request_ring_position;
1153 request->emitted_jiffies = jiffies;
1154 was_empty = list_empty(&ring->request_list);
1155 list_add_tail(&request->list, &ring->request_list);
1156 request->file_priv = NULL;
1159 struct drm_i915_file_private *file_priv = file->driver_priv;
1161 spin_lock(&file_priv->mm.lock);
1162 request->file_priv = file_priv;
1163 list_add_tail(&request->client_list,
1164 &file_priv->mm.request_list);
1165 spin_unlock(&file_priv->mm.lock);
1168 ring->outstanding_lazy_request = 0;
1170 if (!dev_priv->mm.suspended) {
1171 if (i915_enable_hangcheck) {
1172 mod_timer(&dev_priv->hangcheck_timer,
1173 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1176 queue_delayed_work(dev_priv->wq,
1177 &dev_priv->mm.retire_work,
1178 round_jiffies_up_relative(hz));
1179 intel_mark_busy(dev_priv->dev);
1184 *out_seqno = request->seqno;
1189 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1191 struct drm_i915_file_private *file_priv = request->file_priv;
1196 DRM_LOCK_ASSERT(request->ring->dev);
1198 spin_lock(&file_priv->mm.lock);
1199 if (request->file_priv != NULL) {
1200 list_del(&request->client_list);
1201 request->file_priv = NULL;
1203 spin_unlock(&file_priv->mm.lock);
1207 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1208 struct intel_ring_buffer *ring)
1211 if (ring->dev != NULL)
1212 DRM_LOCK_ASSERT(ring->dev);
1214 while (!list_empty(&ring->request_list)) {
1215 struct drm_i915_gem_request *request;
1217 request = list_first_entry(&ring->request_list,
1218 struct drm_i915_gem_request, list);
1220 list_del(&request->list);
1221 i915_gem_request_remove_from_client(request);
1222 drm_free(request, DRM_I915_GEM);
1225 while (!list_empty(&ring->active_list)) {
1226 struct drm_i915_gem_object *obj;
1228 obj = list_first_entry(&ring->active_list,
1229 struct drm_i915_gem_object, ring_list);
1231 list_del_init(&obj->gpu_write_list);
1232 i915_gem_object_move_to_inactive(obj);
1236 static void i915_gem_reset_fences(struct drm_device *dev)
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1241 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1242 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1244 i915_gem_write_fence(dev, i, NULL);
1247 i915_gem_object_fence_lost(reg->obj);
1251 INIT_LIST_HEAD(®->lru_list);
1254 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1257 void i915_gem_reset(struct drm_device *dev)
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 struct drm_i915_gem_object *obj;
1261 struct intel_ring_buffer *ring;
1264 for_each_ring(ring, dev_priv, i)
1265 i915_gem_reset_ring_lists(dev_priv, ring);
1267 /* Move everything out of the GPU domains to ensure we do any
1268 * necessary invalidation upon reuse.
1270 list_for_each_entry(obj,
1271 &dev_priv->mm.inactive_list,
1274 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1277 /* The fence registers are invalidated so clear them out */
1278 i915_gem_reset_fences(dev);
1282 * This function clears the request list as sequence numbers are passed.
1285 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1289 if (list_empty(&ring->request_list))
1292 WARN_ON(i915_verify_lists(ring->dev));
1294 seqno = ring->get_seqno(ring, true);
1296 while (!list_empty(&ring->request_list)) {
1297 struct drm_i915_gem_request *request;
1299 request = list_first_entry(&ring->request_list,
1300 struct drm_i915_gem_request,
1303 if (!i915_seqno_passed(seqno, request->seqno))
1306 /* We know the GPU must have read the request to have
1307 * sent us the seqno + interrupt, so use the position
1308 * of tail of the request to update the last known position
1311 ring->last_retired_head = request->tail;
1313 list_del(&request->list);
1314 i915_gem_request_remove_from_client(request);
1315 kfree(request, DRM_I915_GEM);
1318 /* Move any buffers on the active list that are no longer referenced
1319 * by the ringbuffer to the flushing/inactive lists as appropriate.
1321 while (!list_empty(&ring->active_list)) {
1322 struct drm_i915_gem_object *obj;
1324 obj = list_first_entry(&ring->active_list,
1325 struct drm_i915_gem_object,
1328 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1331 i915_gem_object_move_to_inactive(obj);
1334 if (unlikely(ring->trace_irq_seqno &&
1335 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1336 ring->irq_put(ring);
1337 ring->trace_irq_seqno = 0;
1343 i915_gem_retire_requests(struct drm_device *dev)
1345 drm_i915_private_t *dev_priv = dev->dev_private;
1346 struct intel_ring_buffer *ring;
1349 for_each_ring(ring, dev_priv, i)
1350 i915_gem_retire_requests_ring(ring);
1354 i915_gem_retire_work_handler(struct work_struct *work)
1356 drm_i915_private_t *dev_priv;
1357 struct drm_device *dev;
1358 struct intel_ring_buffer *ring;
1362 dev_priv = container_of(work, drm_i915_private_t,
1363 mm.retire_work.work);
1364 dev = dev_priv->dev;
1366 /* Come back later if the device is busy... */
1367 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
1368 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1369 round_jiffies_up_relative(hz));
1373 i915_gem_retire_requests(dev);
1375 /* Send a periodic flush down the ring so we don't hold onto GEM
1376 * objects indefinitely.
1379 for_each_ring(ring, dev_priv, i) {
1380 if (ring->gpu_caches_dirty)
1381 i915_add_request(ring, NULL, NULL);
1383 idle &= list_empty(&ring->request_list);
1386 if (!dev_priv->mm.suspended && !idle)
1387 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1388 round_jiffies_up_relative(hz));
1390 intel_mark_idle(dev);
1396 * i915_gem_object_sync - sync an object to a ring.
1398 * @obj: object which may be in use on another ring.
1399 * @to: ring we wish to use the object on. May be NULL.
1401 * This code is meant to abstract object synchronization with the GPU.
1402 * Calling with NULL implies synchronizing the object with the CPU
1403 * rather than a particular GPU ring.
1405 * Returns 0 if successful, else propagates up the lower layer error.
1408 i915_gem_object_sync(struct drm_i915_gem_object *obj,
1409 struct intel_ring_buffer *to)
1411 struct intel_ring_buffer *from = obj->ring;
1415 if (from == NULL || to == from)
1418 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
1419 return i915_gem_object_wait_rendering(obj, false);
1421 idx = intel_ring_sync_index(from, to);
1423 seqno = obj->last_read_seqno;
1424 if (seqno <= from->sync_seqno[idx])
1427 ret = i915_gem_check_olr(obj->ring, seqno);
1431 ret = to->sync_to(to, from, seqno);
1433 from->sync_seqno[idx] = seqno;
1438 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
1440 u32 old_write_domain, old_read_domains;
1442 /* Act a barrier for all accesses through the GTT */
1445 /* Force a pagefault for domain tracking on next user access */
1446 i915_gem_release_mmap(obj);
1448 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
1451 old_read_domains = obj->base.read_domains;
1452 old_write_domain = obj->base.write_domain;
1454 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
1455 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
1460 * Unbinds an object from the GTT aperture.
1463 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
1465 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1468 if (obj->gtt_space == NULL)
1471 if (obj->pin_count != 0) {
1472 DRM_ERROR("Attempting to unbind pinned buffer\n");
1476 ret = i915_gem_object_finish_gpu(obj);
1479 /* Continue on if we fail due to EIO, the GPU is hung so we
1480 * should be safe and we need to cleanup or else we might
1481 * cause memory corruption through use-after-free.
1484 i915_gem_object_finish_gtt(obj);
1486 /* Move the object to the CPU domain to ensure that
1487 * any possible CPU writes while it's not in the GTT
1488 * are flushed when we go to remap it.
1491 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1492 if (ret == -ERESTART || ret == -EINTR)
1495 /* In the event of a disaster, abandon all caches and
1496 * hope for the best.
1498 i915_gem_clflush_object(obj);
1499 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1502 /* release the fence reg _after_ flushing */
1503 ret = i915_gem_object_put_fence(obj);
1507 if (obj->has_global_gtt_mapping)
1508 i915_gem_gtt_unbind_object(obj);
1509 if (obj->has_aliasing_ppgtt_mapping) {
1510 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
1511 obj->has_aliasing_ppgtt_mapping = 0;
1513 i915_gem_gtt_finish_object(obj);
1515 i915_gem_object_put_pages_gtt(obj);
1517 list_del_init(&obj->gtt_list);
1518 list_del_init(&obj->mm_list);
1519 /* Avoid an unnecessary call to unbind on rebind. */
1520 obj->map_and_fenceable = true;
1522 drm_mm_put_block(obj->gtt_space);
1523 obj->gtt_space = NULL;
1524 obj->gtt_offset = 0;
1526 if (i915_gem_object_is_purgeable(obj))
1527 i915_gem_object_truncate(obj);
1532 int i915_gpu_idle(struct drm_device *dev)
1534 drm_i915_private_t *dev_priv = dev->dev_private;
1535 struct intel_ring_buffer *ring;
1538 /* Flush everything onto the inactive list. */
1539 for_each_ring(ring, dev_priv, i) {
1540 ret = intel_ring_idle(ring);
1548 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
1549 struct drm_i915_gem_object *obj)
1551 drm_i915_private_t *dev_priv = dev->dev_private;
1555 u32 size = obj->gtt_space->size;
1557 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1559 val |= obj->gtt_offset & 0xfffff000;
1560 val |= (uint64_t)((obj->stride / 128) - 1) <<
1561 SANDYBRIDGE_FENCE_PITCH_SHIFT;
1563 if (obj->tiling_mode == I915_TILING_Y)
1564 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1565 val |= I965_FENCE_REG_VALID;
1569 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
1570 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
1573 static void i965_write_fence_reg(struct drm_device *dev, int reg,
1574 struct drm_i915_gem_object *obj)
1576 drm_i915_private_t *dev_priv = dev->dev_private;
1580 u32 size = obj->gtt_space->size;
1582 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1584 val |= obj->gtt_offset & 0xfffff000;
1585 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1586 if (obj->tiling_mode == I915_TILING_Y)
1587 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1588 val |= I965_FENCE_REG_VALID;
1592 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
1593 POSTING_READ(FENCE_REG_965_0 + reg * 8);
1596 static void i915_write_fence_reg(struct drm_device *dev, int reg,
1597 struct drm_i915_gem_object *obj)
1599 drm_i915_private_t *dev_priv = dev->dev_private;
1603 u32 size = obj->gtt_space->size;
1607 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
1608 (size & -size) != size ||
1609 (obj->gtt_offset & (size - 1)),
1610 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
1611 obj->gtt_offset, obj->map_and_fenceable, size);
1613 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1618 /* Note: pitch better be a power of two tile widths */
1619 pitch_val = obj->stride / tile_width;
1620 pitch_val = ffs(pitch_val) - 1;
1622 val = obj->gtt_offset;
1623 if (obj->tiling_mode == I915_TILING_Y)
1624 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1625 val |= I915_FENCE_SIZE_BITS(size);
1626 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1627 val |= I830_FENCE_REG_VALID;
1632 reg = FENCE_REG_830_0 + reg * 4;
1634 reg = FENCE_REG_945_8 + (reg - 8) * 4;
1636 I915_WRITE(reg, val);
1640 static void i830_write_fence_reg(struct drm_device *dev, int reg,
1641 struct drm_i915_gem_object *obj)
1643 drm_i915_private_t *dev_priv = dev->dev_private;
1647 u32 size = obj->gtt_space->size;
1650 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
1651 (size & -size) != size ||
1652 (obj->gtt_offset & (size - 1)),
1653 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
1654 obj->gtt_offset, size);
1656 pitch_val = obj->stride / 128;
1657 pitch_val = ffs(pitch_val) - 1;
1659 val = obj->gtt_offset;
1660 if (obj->tiling_mode == I915_TILING_Y)
1661 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1662 val |= I830_FENCE_SIZE_BITS(size);
1663 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1664 val |= I830_FENCE_REG_VALID;
1668 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
1669 POSTING_READ(FENCE_REG_830_0 + reg * 4);
1672 static void i915_gem_write_fence(struct drm_device *dev, int reg,
1673 struct drm_i915_gem_object *obj)
1675 switch (INTEL_INFO(dev)->gen) {
1677 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
1679 case 4: i965_write_fence_reg(dev, reg, obj); break;
1680 case 3: i915_write_fence_reg(dev, reg, obj); break;
1681 case 2: i830_write_fence_reg(dev, reg, obj); break;
1686 static inline int fence_number(struct drm_i915_private *dev_priv,
1687 struct drm_i915_fence_reg *fence)
1689 return fence - dev_priv->fence_regs;
1692 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
1693 struct drm_i915_fence_reg *fence,
1696 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1697 int reg = fence_number(dev_priv, fence);
1699 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
1702 obj->fence_reg = reg;
1704 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
1706 obj->fence_reg = I915_FENCE_REG_NONE;
1708 list_del_init(&fence->lru_list);
1713 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
1717 if (obj->fenced_gpu_access) {
1718 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1719 ret = i915_gem_flush_ring(obj->ring,
1720 0, obj->base.write_domain);
1725 obj->fenced_gpu_access = false;
1728 if (obj->last_fenced_seqno) {
1729 ret = i915_wait_seqno(obj->ring,
1730 obj->last_fenced_seqno);
1734 obj->last_fenced_seqno = 0;
1737 /* Ensure that all CPU reads are completed before installing a fence
1738 * and all writes before removing the fence.
1740 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
1747 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
1749 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1752 ret = i915_gem_object_flush_fence(obj);
1756 if (obj->fence_reg == I915_FENCE_REG_NONE)
1759 i915_gem_object_update_fence(obj,
1760 &dev_priv->fence_regs[obj->fence_reg],
1762 i915_gem_object_fence_lost(obj);
1767 static struct drm_i915_fence_reg *
1768 i915_find_fence_reg(struct drm_device *dev)
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 struct drm_i915_fence_reg *reg, *avail;
1774 /* First try to find a free reg */
1776 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1777 reg = &dev_priv->fence_regs[i];
1781 if (!reg->pin_count)
1788 /* None available, try to steal one or wait for a user to finish */
1789 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
1800 * i915_gem_object_get_fence - set up fencing for an object
1801 * @obj: object to map through a fence reg
1803 * When mapping objects through the GTT, userspace wants to be able to write
1804 * to them without having to worry about swizzling if the object is tiled.
1805 * This function walks the fence regs looking for a free one for @obj,
1806 * stealing one if it can't find any.
1808 * It then sets up the reg based on the object's properties: address, pitch
1809 * and tiling format.
1811 * For an untiled surface, this removes any existing fence.
1814 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
1816 struct drm_device *dev = obj->base.dev;
1817 struct drm_i915_private *dev_priv = dev->dev_private;
1818 bool enable = obj->tiling_mode != I915_TILING_NONE;
1819 struct drm_i915_fence_reg *reg;
1822 /* Have we updated the tiling parameters upon the object and so
1823 * will need to serialise the write to the associated fence register?
1825 if (obj->fence_dirty) {
1826 ret = i915_gem_object_flush_fence(obj);
1831 /* Just update our place in the LRU if our fence is getting reused. */
1832 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1833 reg = &dev_priv->fence_regs[obj->fence_reg];
1834 if (!obj->fence_dirty) {
1835 list_move_tail(®->lru_list,
1836 &dev_priv->mm.fence_list);
1839 } else if (enable) {
1840 reg = i915_find_fence_reg(dev);
1845 struct drm_i915_gem_object *old = reg->obj;
1847 ret = i915_gem_object_flush_fence(old);
1851 i915_gem_object_fence_lost(old);
1856 i915_gem_object_update_fence(obj, reg, enable);
1857 obj->fence_dirty = false;
1863 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1864 unsigned alignment, bool map_and_fenceable)
1866 struct drm_device *dev;
1867 struct drm_i915_private *dev_priv;
1868 struct drm_mm_node *free_space;
1869 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
1870 bool mappable, fenceable;
1872 bool nonblocking = false;
1874 dev = obj->base.dev;
1875 dev_priv = dev->dev_private;
1877 if (obj->madv != I915_MADV_WILLNEED) {
1878 DRM_ERROR("Attempting to bind a purgeable object\n");
1882 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
1884 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
1886 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
1887 obj->base.size, obj->tiling_mode);
1889 alignment = map_and_fenceable ? fence_alignment :
1891 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
1892 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1896 size = map_and_fenceable ? fence_size : obj->base.size;
1898 /* If the object is bigger than the entire aperture, reject it early
1899 * before evicting everything in a vain attempt to find space.
1901 if (obj->base.size > (map_and_fenceable ?
1902 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
1904 "Attempting to bind an object larger than the aperture\n");
1909 if (map_and_fenceable)
1910 free_space = drm_mm_search_free_in_range(
1911 &dev_priv->mm.gtt_space, size, alignment, 0,
1912 dev_priv->mm.gtt_mappable_end, 0);
1914 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1915 size, alignment, 0);
1916 if (free_space != NULL) {
1918 if (map_and_fenceable)
1919 obj->gtt_space = drm_mm_get_block_range_generic(
1920 free_space, size, alignment, color, 0,
1921 dev_priv->mm.gtt_mappable_end, 1);
1923 obj->gtt_space = drm_mm_get_block_generic(free_space,
1924 size, alignment, color, 1);
1926 if (obj->gtt_space == NULL) {
1927 ret = i915_gem_evict_something(dev, size, alignment,
1937 * NOTE: i915_gem_object_get_pages_gtt() cannot
1938 * return ENOMEM, since we used VM_ALLOC_RETRY.
1940 ret = i915_gem_object_get_pages_gtt(obj, 0);
1942 drm_mm_put_block(obj->gtt_space);
1943 obj->gtt_space = NULL;
1947 i915_gem_gtt_bind_object(obj, obj->cache_level);
1949 i915_gem_object_put_pages_gtt(obj);
1950 drm_mm_put_block(obj->gtt_space);
1951 obj->gtt_space = NULL;
1952 if (i915_gem_evict_everything(dev))
1957 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
1958 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1960 obj->gtt_offset = obj->gtt_space->start;
1963 obj->gtt_space->size == fence_size &&
1964 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
1967 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
1968 obj->map_and_fenceable = mappable && fenceable;
1974 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1977 /* If we don't have a page list set up, then we're not pinned
1978 * to GPU, and we can ignore the cache flush because it'll happen
1979 * again at bind time.
1981 if (obj->pages == NULL)
1984 /* If the GPU is snooping the contents of the CPU cache,
1985 * we do not need to manually clear the CPU cache lines. However,
1986 * the caches are only snooped when the render cache is
1987 * flushed/invalidated. As we always have to emit invalidations
1988 * and flushes when moving into and out of the RENDER domain, correct
1989 * snooping behaviour occurs naturally as the result of our domain
1992 if (obj->cache_level != I915_CACHE_NONE)
1995 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1998 /** Flushes the GTT write domain for the object if it's dirty. */
2000 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2002 uint32_t old_write_domain;
2004 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2007 /* No actual flushing is required for the GTT write domain. Writes
2008 * to it immediately go to main memory as far as we know, so there's
2009 * no chipset flush. It also doesn't land in render cache.
2011 * However, we do have to enforce the order so that all writes through
2012 * the GTT land before any writes to the device, such as updates to
2017 old_write_domain = obj->base.write_domain;
2018 obj->base.write_domain = 0;
2021 /** Flushes the CPU write domain for the object if it's dirty. */
2023 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2025 uint32_t old_write_domain;
2027 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2030 i915_gem_clflush_object(obj);
2031 intel_gtt_chipset_flush();
2032 old_write_domain = obj->base.write_domain;
2033 obj->base.write_domain = 0;
2037 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2040 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2042 return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
2046 * Moves a single object to the GTT read, and possibly write domain.
2048 * This function returns when the move is complete, including waiting on
2052 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2054 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2055 uint32_t old_write_domain, old_read_domains;
2058 /* Not valid to be called on unbound objects. */
2059 if (obj->gtt_space == NULL)
2062 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2065 ret = i915_gem_object_flush_gpu_write_domain(obj);
2069 ret = i915_gem_object_wait_rendering(obj, !write);
2073 i915_gem_object_flush_cpu_write_domain(obj);
2075 old_write_domain = obj->base.write_domain;
2076 old_read_domains = obj->base.read_domains;
2078 /* It should now be out of any other write domains, and we can update
2079 * the domain values for our changes.
2081 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2082 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2084 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2085 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2089 /* And bump the LRU for this access */
2090 if (i915_gem_object_is_inactive(obj))
2091 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2096 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2097 enum i915_cache_level cache_level)
2099 struct drm_device *dev = obj->base.dev;
2100 drm_i915_private_t *dev_priv = dev->dev_private;
2103 if (obj->cache_level == cache_level)
2106 if (obj->pin_count) {
2107 DRM_DEBUG("can not change the cache level of pinned objects\n");
2111 if (obj->gtt_space) {
2112 ret = i915_gem_object_finish_gpu(obj);
2116 i915_gem_object_finish_gtt(obj);
2118 /* Before SandyBridge, you could not use tiling or fence
2119 * registers with snooped memory, so relinquish any fences
2120 * currently pointing to our region in the aperture.
2122 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2123 ret = i915_gem_object_put_fence(obj);
2128 if (obj->has_global_gtt_mapping)
2129 i915_gem_gtt_bind_object(obj, cache_level);
2130 if (obj->has_aliasing_ppgtt_mapping)
2131 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2135 if (cache_level == I915_CACHE_NONE) {
2136 u32 old_read_domains, old_write_domain;
2138 /* If we're coming from LLC cached, then we haven't
2139 * actually been tracking whether the data is in the
2140 * CPU cache or not, since we only allow one bit set
2141 * in obj->write_domain and have been skipping the clflushes.
2142 * Just set it to the CPU cache for now.
2144 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2145 ("obj %p in CPU write domain", obj));
2146 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
2147 ("obj %p in CPU read domain", obj));
2149 old_read_domains = obj->base.read_domains;
2150 old_write_domain = obj->base.write_domain;
2152 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2153 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2157 obj->cache_level = cache_level;
2161 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *file)
2164 struct drm_i915_gem_caching *args = data;
2165 struct drm_i915_gem_object *obj;
2168 ret = i915_mutex_lock_interruptible(dev);
2172 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2173 if (&obj->base == NULL) {
2178 args->caching = obj->cache_level != I915_CACHE_NONE;
2180 drm_gem_object_unreference(&obj->base);
2186 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2187 struct drm_file *file)
2189 struct drm_i915_gem_caching *args = data;
2190 struct drm_i915_gem_object *obj;
2191 enum i915_cache_level level;
2194 switch (args->caching) {
2195 case I915_CACHING_NONE:
2196 level = I915_CACHE_NONE;
2198 case I915_CACHING_CACHED:
2199 level = I915_CACHE_LLC;
2205 ret = i915_mutex_lock_interruptible(dev);
2209 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2210 if (&obj->base == NULL) {
2215 ret = i915_gem_object_set_cache_level(obj, level);
2217 drm_gem_object_unreference(&obj->base);
2224 * Prepare buffer for display plane (scanout, cursors, etc).
2225 * Can be called from an uninterruptible phase (modesetting) and allows
2226 * any flushes to be pipelined (for pageflips).
2229 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2231 struct intel_ring_buffer *pipelined)
2233 u32 old_read_domains, old_write_domain;
2236 ret = i915_gem_object_flush_gpu_write_domain(obj);
2240 if (pipelined != obj->ring) {
2241 ret = i915_gem_object_sync(obj, pipelined);
2246 /* The display engine is not coherent with the LLC cache on gen6. As
2247 * a result, we make sure that the pinning that is about to occur is
2248 * done with uncached PTEs. This is lowest common denominator for all
2251 * However for gen6+, we could do better by using the GFDT bit instead
2252 * of uncaching, which would allow us to flush all the LLC-cached data
2253 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2255 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2259 /* As the user may map the buffer once pinned in the display plane
2260 * (e.g. libkms for the bootup splash), we have to ensure that we
2261 * always use map_and_fenceable for all scanout buffers.
2263 ret = i915_gem_object_pin(obj, alignment, true);
2267 i915_gem_object_flush_cpu_write_domain(obj);
2269 old_write_domain = obj->base.write_domain;
2270 old_read_domains = obj->base.read_domains;
2272 /* It should now be out of any other write domains, and we can update
2273 * the domain values for our changes.
2275 obj->base.write_domain = 0;
2276 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2282 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2286 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2289 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2290 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2295 ret = i915_gem_object_wait_rendering(obj, false);
2299 /* Ensure that we invalidate the GPU's caches and TLBs. */
2300 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2305 * Moves a single object to the CPU read, and possibly write domain.
2307 * This function returns when the move is complete, including waiting on
2311 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2313 uint32_t old_write_domain, old_read_domains;
2316 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2319 ret = i915_gem_object_flush_gpu_write_domain(obj);
2323 ret = i915_gem_object_wait_rendering(obj, !write);
2327 i915_gem_object_flush_gtt_write_domain(obj);
2329 old_write_domain = obj->base.write_domain;
2330 old_read_domains = obj->base.read_domains;
2332 /* Flush the CPU cache if it's still invalid. */
2333 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2334 i915_gem_clflush_object(obj);
2336 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2339 /* It should now be out of any other write domains, and we can update
2340 * the domain values for our changes.
2342 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2344 /* If we're writing through the CPU, then the GPU read domains will
2345 * need to be invalidated at next use.
2348 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2349 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2355 /* Throttle our rendering by waiting until the ring has completed our requests
2356 * emitted over 20 msec ago.
2358 * Note that if we were to use the current jiffies each time around the loop,
2359 * we wouldn't escape the function with any frames outstanding if the time to
2360 * render a frame was over 20ms.
2362 * This should get us reasonable parallelism between CPU and GPU but also
2363 * relatively low latency when blocking on a particular request to finish.
2366 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369 struct drm_i915_file_private *file_priv = file->driver_priv;
2370 unsigned long recent_enough = ticks - (20 * hz / 1000);
2371 struct drm_i915_gem_request *request;
2372 struct intel_ring_buffer *ring = NULL;
2376 if (atomic_read(&dev_priv->mm.wedged))
2379 spin_lock(&file_priv->mm.lock);
2380 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
2381 if (time_after_eq(request->emitted_jiffies, recent_enough))
2384 ring = request->ring;
2385 seqno = request->seqno;
2387 spin_unlock(&file_priv->mm.lock);
2392 ret = __wait_seqno(ring, seqno, true, NULL);
2395 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
2401 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2403 bool map_and_fenceable)
2407 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
2410 if (obj->gtt_space != NULL) {
2411 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
2412 (map_and_fenceable && !obj->map_and_fenceable)) {
2413 WARN(obj->pin_count,
2414 "bo is already pinned with incorrect alignment:"
2415 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
2416 " obj->map_and_fenceable=%d\n",
2417 obj->gtt_offset, alignment,
2419 obj->map_and_fenceable);
2420 ret = i915_gem_object_unbind(obj);
2426 if (obj->gtt_space == NULL) {
2427 ret = i915_gem_object_bind_to_gtt(obj, alignment,
2433 if (!obj->has_global_gtt_mapping && map_and_fenceable)
2434 i915_gem_gtt_bind_object(obj, obj->cache_level);
2437 obj->pin_mappable |= map_and_fenceable;
2443 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
2445 BUG_ON(obj->pin_count == 0);
2446 BUG_ON(obj->gtt_space == NULL);
2448 if (--obj->pin_count == 0)
2449 obj->pin_mappable = false;
2453 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2454 struct drm_file *file)
2456 struct drm_i915_gem_pin *args;
2457 struct drm_i915_gem_object *obj;
2458 struct drm_gem_object *gobj;
2463 ret = i915_mutex_lock_interruptible(dev);
2467 gobj = drm_gem_object_lookup(dev, file, args->handle);
2472 obj = to_intel_bo(gobj);
2474 if (obj->madv != I915_MADV_WILLNEED) {
2475 DRM_ERROR("Attempting to pin a purgeable buffer\n");
2480 if (obj->pin_filp != NULL && obj->pin_filp != file) {
2481 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2487 obj->user_pin_count++;
2488 obj->pin_filp = file;
2489 if (obj->user_pin_count == 1) {
2490 ret = i915_gem_object_pin(obj, args->alignment, true);
2495 /* XXX - flush the CPU caches for pinned objects
2496 * as the X server doesn't manage domains yet
2498 i915_gem_object_flush_cpu_write_domain(obj);
2499 args->offset = obj->gtt_offset;
2501 drm_gem_object_unreference(&obj->base);
2508 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2509 struct drm_file *file)
2511 struct drm_i915_gem_pin *args;
2512 struct drm_i915_gem_object *obj;
2516 ret = i915_mutex_lock_interruptible(dev);
2520 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2521 if (&obj->base == NULL) {
2526 if (obj->pin_filp != file) {
2527 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2532 obj->user_pin_count--;
2533 if (obj->user_pin_count == 0) {
2534 obj->pin_filp = NULL;
2535 i915_gem_object_unpin(obj);
2539 drm_gem_object_unreference(&obj->base);
2546 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2547 struct drm_file *file)
2549 struct drm_i915_gem_busy *args = data;
2550 struct drm_i915_gem_object *obj;
2553 ret = i915_mutex_lock_interruptible(dev);
2557 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2558 if (&obj->base == NULL) {
2563 /* Count all active objects as busy, even if they are currently not used
2564 * by the gpu. Users of this interface expect objects to eventually
2565 * become non-busy without any further actions, therefore emit any
2566 * necessary flushes here.
2568 ret = i915_gem_object_flush_active(obj);
2570 args->busy = obj->active;
2572 args->busy |= intel_ring_flag(obj->ring) << 17;
2575 drm_gem_object_unreference(&obj->base);
2582 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2583 struct drm_file *file_priv)
2586 return (i915_gem_ring_throttle(dev, file_priv));
2590 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2591 struct drm_file *file_priv)
2593 struct drm_i915_gem_madvise *args = data;
2594 struct drm_i915_gem_object *obj;
2597 switch (args->madv) {
2598 case I915_MADV_DONTNEED:
2599 case I915_MADV_WILLNEED:
2605 ret = i915_mutex_lock_interruptible(dev);
2609 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
2610 if (&obj->base == NULL) {
2615 if (obj->pin_count) {
2620 if (obj->madv != __I915_MADV_PURGED)
2621 obj->madv = args->madv;
2623 /* if the object is no longer attached, discard its backing storage */
2624 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
2625 i915_gem_object_truncate(obj);
2627 args->retained = obj->madv != __I915_MADV_PURGED;
2630 drm_gem_object_unreference(&obj->base);
2636 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2639 struct drm_i915_private *dev_priv;
2640 struct drm_i915_gem_object *obj;
2642 dev_priv = dev->dev_private;
2644 obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
2646 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
2647 drm_free(obj, DRM_I915_GEM);
2651 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2652 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2655 obj->cache_level = I915_CACHE_LLC;
2657 obj->cache_level = I915_CACHE_NONE;
2658 obj->base.driver_private = NULL;
2659 obj->fence_reg = I915_FENCE_REG_NONE;
2660 INIT_LIST_HEAD(&obj->mm_list);
2661 INIT_LIST_HEAD(&obj->gtt_list);
2662 INIT_LIST_HEAD(&obj->ring_list);
2663 INIT_LIST_HEAD(&obj->exec_list);
2664 INIT_LIST_HEAD(&obj->gpu_write_list);
2665 obj->madv = I915_MADV_WILLNEED;
2666 /* Avoid an unnecessary call to unbind on the first bind. */
2667 obj->map_and_fenceable = true;
2669 i915_gem_info_add_obj(dev_priv, size);
2674 int i915_gem_init_object(struct drm_gem_object *obj)
2681 void i915_gem_free_object(struct drm_gem_object *gem_obj)
2683 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
2684 struct drm_device *dev = obj->base.dev;
2685 drm_i915_private_t *dev_priv = dev->dev_private;
2688 i915_gem_detach_phys_object(dev, obj);
2691 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
2692 bool was_interruptible;
2694 was_interruptible = dev_priv->mm.interruptible;
2695 dev_priv->mm.interruptible = false;
2697 WARN_ON(i915_gem_object_unbind(obj));
2699 dev_priv->mm.interruptible = was_interruptible;
2702 drm_gem_free_mmap_offset(&obj->base);
2704 drm_gem_object_release(&obj->base);
2705 i915_gem_info_remove_obj(dev_priv, obj->base.size);
2707 drm_free(obj->bit_17, DRM_I915_GEM);
2708 drm_free(obj, DRM_I915_GEM);
2712 i915_gem_do_init(struct drm_device *dev, unsigned long start,
2713 unsigned long mappable_end, unsigned long end)
2715 drm_i915_private_t *dev_priv;
2716 unsigned long mappable;
2719 dev_priv = dev->dev_private;
2720 mappable = min(end, mappable_end) - start;
2722 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
2724 dev_priv->mm.gtt_start = start;
2725 dev_priv->mm.gtt_mappable_end = mappable_end;
2726 dev_priv->mm.gtt_end = end;
2727 dev_priv->mm.gtt_total = end - start;
2728 dev_priv->mm.mappable_gtt_total = mappable;
2730 /* Take over this portion of the GTT */
2731 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
2732 device_printf(dev->dev,
2733 "taking over the fictitious range 0x%lx-0x%lx\n",
2734 dev->agp->base + start, dev->agp->base + start + mappable);
2735 error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
2736 dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
2741 i915_gem_idle(struct drm_device *dev)
2743 drm_i915_private_t *dev_priv = dev->dev_private;
2748 if (dev_priv->mm.suspended) {
2753 ret = i915_gpu_idle(dev);
2758 i915_gem_retire_requests(dev);
2760 /* Under UMS, be paranoid and evict. */
2761 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2762 i915_gem_evict_everything(dev);
2764 i915_gem_reset_fences(dev);
2766 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2767 * We need to replace this with a semaphore, or something.
2768 * And not confound mm.suspended!
2770 dev_priv->mm.suspended = 1;
2771 del_timer_sync(&dev_priv->hangcheck_timer);
2773 i915_kernel_lost_context(dev);
2774 i915_gem_cleanup_ringbuffer(dev);
2778 /* Cancel the retire work handler, which should be idle now. */
2779 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2784 void i915_gem_l3_remap(struct drm_device *dev)
2786 drm_i915_private_t *dev_priv = dev->dev_private;
2790 if (!HAS_L3_GPU_CACHE(dev))
2793 if (!dev_priv->l3_parity.remap_info)
2796 misccpctl = I915_READ(GEN7_MISCCPCTL);
2797 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
2798 POSTING_READ(GEN7_MISCCPCTL);
2800 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
2801 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
2802 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
2803 DRM_DEBUG("0x%x was already programmed to %x\n",
2804 GEN7_L3LOG_BASE + i, remap);
2805 if (remap && !dev_priv->l3_parity.remap_info[i/4])
2806 DRM_DEBUG_DRIVER("Clearing remapped register\n");
2807 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
2810 /* Make sure all the writes land before disabling dop clock gating */
2811 POSTING_READ(GEN7_L3LOG_BASE);
2813 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
2817 i915_gem_init_swizzling(struct drm_device *dev)
2819 drm_i915_private_t *dev_priv;
2821 dev_priv = dev->dev_private;
2823 if (INTEL_INFO(dev)->gen < 5 ||
2824 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
2827 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
2828 DISP_TILE_SURFACE_SWIZZLING);
2833 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
2835 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
2837 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
2841 intel_enable_blt(struct drm_device *dev)
2848 /* The blitter was dysfunctional on early prototypes */
2849 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
2850 if (IS_GEN6(dev) && revision < 8) {
2851 DRM_INFO("BLT not supported on this pre-production hardware;"
2852 " graphics performance will be degraded.\n");
2860 i915_gem_init_hw(struct drm_device *dev)
2862 drm_i915_private_t *dev_priv = dev->dev_private;
2865 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
2866 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
2868 i915_gem_l3_remap(dev);
2870 i915_gem_init_swizzling(dev);
2872 ret = intel_init_render_ring_buffer(dev);
2877 ret = intel_init_bsd_ring_buffer(dev);
2879 goto cleanup_render_ring;
2882 if (intel_enable_blt(dev)) {
2883 ret = intel_init_blt_ring_buffer(dev);
2885 goto cleanup_bsd_ring;
2888 dev_priv->next_seqno = 1;
2891 * XXX: There was some w/a described somewhere suggesting loading
2892 * contexts before PPGTT.
2894 #if 0 /* XXX: HW context support */
2895 i915_gem_context_init(dev);
2897 i915_gem_init_ppgtt(dev);
2902 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
2903 cleanup_render_ring:
2904 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
2909 intel_enable_ppgtt(struct drm_device *dev)
2911 if (i915_enable_ppgtt >= 0)
2912 return i915_enable_ppgtt;
2914 /* Disable ppgtt on SNB if VT-d is on. */
2915 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
2921 int i915_gem_init(struct drm_device *dev)
2923 struct drm_i915_private *dev_priv = dev->dev_private;
2924 unsigned long prealloc_size, gtt_size, mappable_size;
2927 prealloc_size = dev_priv->mm.gtt->stolen_size;
2928 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
2929 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
2931 /* Basic memrange allocator for stolen space */
2932 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
2935 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
2936 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
2937 * aperture accordingly when using aliasing ppgtt. */
2938 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
2939 /* For paranoia keep the guard page in between. */
2940 gtt_size -= PAGE_SIZE;
2942 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
2944 ret = i915_gem_init_aliasing_ppgtt(dev);
2950 /* Let GEM Manage all of the aperture.
2952 * However, leave one page at the end still bound to the scratch
2953 * page. There are a number of places where the hardware
2954 * apparently prefetches past the end of the object, and we've
2955 * seen multiple hangs with the GPU head pointer stuck in a
2956 * batchbuffer bound at the last page of the aperture. One page
2957 * should be enough to keep any prefetching inside of the
2960 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
2963 ret = i915_gem_init_hw(dev);
2966 i915_gem_cleanup_aliasing_ppgtt(dev);
2971 /* Try to set up FBC with a reasonable compressed buffer size */
2972 if (I915_HAS_FBC(dev) && i915_powersave) {
2975 /* Leave 1M for line length buffer & misc. */
2977 /* Try to get a 32M buffer... */
2978 if (prealloc_size > (36*1024*1024))
2979 cfb_size = 32*1024*1024;
2980 else /* fall back to 7/8 of the stolen space */
2981 cfb_size = prealloc_size * 7 / 8;
2982 i915_setup_compression(dev, cfb_size);
2986 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
2987 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2988 dev_priv->dri1.allow_batchbuffer = 1;
2993 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2995 drm_i915_private_t *dev_priv;
2998 dev_priv = dev->dev_private;
2999 for (i = 0; i < I915_NUM_RINGS; i++)
3000 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3004 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3005 struct drm_file *file_priv)
3007 drm_i915_private_t *dev_priv = dev->dev_private;
3010 if (drm_core_check_feature(dev, DRIVER_MODESET))
3013 if (atomic_read(&dev_priv->mm.wedged)) {
3014 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3015 atomic_set(&dev_priv->mm.wedged, 0);
3019 dev_priv->mm.suspended = 0;
3021 ret = i915_gem_init_hw(dev);
3027 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
3030 ret = drm_irq_install(dev);
3032 goto cleanup_ringbuffer;
3038 i915_gem_cleanup_ringbuffer(dev);
3039 dev_priv->mm.suspended = 1;
3046 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3047 struct drm_file *file_priv)
3050 if (drm_core_check_feature(dev, DRIVER_MODESET))
3053 drm_irq_uninstall(dev);
3054 return (i915_gem_idle(dev));
3058 i915_gem_lastclose(struct drm_device *dev)
3062 if (drm_core_check_feature(dev, DRIVER_MODESET))
3065 ret = i915_gem_idle(dev);
3067 DRM_ERROR("failed to idle hardware: %d\n", ret);
3071 init_ring_lists(struct intel_ring_buffer *ring)
3074 INIT_LIST_HEAD(&ring->active_list);
3075 INIT_LIST_HEAD(&ring->request_list);
3076 INIT_LIST_HEAD(&ring->gpu_write_list);
3080 i915_gem_load(struct drm_device *dev)
3083 drm_i915_private_t *dev_priv = dev->dev_private;
3085 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3086 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3087 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3088 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3089 for (i = 0; i < I915_NUM_RINGS; i++)
3090 init_ring_lists(&dev_priv->ring[i]);
3091 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3092 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3093 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3094 i915_gem_retire_work_handler);
3095 init_completion(&dev_priv->error_completion);
3097 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3099 I915_WRITE(MI_ARB_STATE,
3100 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3103 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3105 /* Old X drivers will take 0-2 for front, back, depth buffers */
3106 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3107 dev_priv->fence_reg_start = 3;
3109 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3110 dev_priv->num_fence_regs = 16;
3112 dev_priv->num_fence_regs = 8;
3114 /* Initialize fence registers to zero */
3115 i915_gem_reset_fences(dev);
3117 i915_gem_detect_bit_6_swizzle(dev);
3118 init_waitqueue_head(&dev_priv->pending_flip_queue);
3120 dev_priv->mm.interruptible = true;
3123 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3124 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3125 register_shrinker(&dev_priv->mm.inactive_shrinker);
3127 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
3128 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
3133 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3135 drm_i915_private_t *dev_priv;
3136 struct drm_i915_gem_phys_object *phys_obj;
3139 dev_priv = dev->dev_private;
3140 if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3143 phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3148 phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3149 if (phys_obj->handle == NULL) {
3153 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3154 size / PAGE_SIZE, PAT_WRITE_COMBINING);
3156 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3161 drm_free(phys_obj, DRM_I915_GEM);
3166 i915_gem_free_phys_object(struct drm_device *dev, int id)
3168 drm_i915_private_t *dev_priv;
3169 struct drm_i915_gem_phys_object *phys_obj;
3171 dev_priv = dev->dev_private;
3172 if (dev_priv->mm.phys_objs[id - 1] == NULL)
3175 phys_obj = dev_priv->mm.phys_objs[id - 1];
3176 if (phys_obj->cur_obj != NULL)
3177 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3179 drm_pci_free(dev, phys_obj->handle);
3180 drm_free(phys_obj, DRM_I915_GEM);
3181 dev_priv->mm.phys_objs[id - 1] = NULL;
3185 i915_gem_free_all_phys_object(struct drm_device *dev)
3189 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3190 i915_gem_free_phys_object(dev, i);
3194 i915_gem_detach_phys_object(struct drm_device *dev,
3195 struct drm_i915_gem_object *obj)
3202 if (obj->phys_obj == NULL)
3204 vaddr = obj->phys_obj->handle->vaddr;
3206 page_count = obj->base.size / PAGE_SIZE;
3207 VM_OBJECT_LOCK(obj->base.vm_obj);
3208 for (i = 0; i < page_count; i++) {
3209 m = i915_gem_wire_page(obj->base.vm_obj, i);
3213 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3214 sf = sf_buf_alloc(m);
3216 dst = (char *)sf_buf_kva(sf);
3217 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3220 drm_clflush_pages(&m, 1);
3222 VM_OBJECT_LOCK(obj->base.vm_obj);
3223 vm_page_reference(m);
3225 vm_page_busy_wait(m, FALSE, "i915gem");
3226 vm_page_unwire(m, 0);
3228 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3230 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3231 intel_gtt_chipset_flush();
3233 obj->phys_obj->cur_obj = NULL;
3234 obj->phys_obj = NULL;
3238 i915_gem_attach_phys_object(struct drm_device *dev,
3239 struct drm_i915_gem_object *obj,
3243 drm_i915_private_t *dev_priv;
3247 int i, page_count, ret;
3249 if (id > I915_MAX_PHYS_OBJECT)
3252 if (obj->phys_obj != NULL) {
3253 if (obj->phys_obj->id == id)
3255 i915_gem_detach_phys_object(dev, obj);
3258 dev_priv = dev->dev_private;
3259 if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3260 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3262 DRM_ERROR("failed to init phys object %d size: %zu\n",
3263 id, obj->base.size);
3268 /* bind to the object */
3269 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3270 obj->phys_obj->cur_obj = obj;
3272 page_count = obj->base.size / PAGE_SIZE;
3274 VM_OBJECT_LOCK(obj->base.vm_obj);
3276 for (i = 0; i < page_count; i++) {
3277 m = i915_gem_wire_page(obj->base.vm_obj, i);
3282 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3283 sf = sf_buf_alloc(m);
3284 src = (char *)sf_buf_kva(sf);
3285 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3286 memcpy(dst, src, PAGE_SIZE);
3289 VM_OBJECT_LOCK(obj->base.vm_obj);
3291 vm_page_reference(m);
3292 vm_page_busy_wait(m, FALSE, "i915gem");
3293 vm_page_unwire(m, 0);
3295 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3297 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3303 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3304 uint64_t data_ptr, uint64_t offset, uint64_t size,
3305 struct drm_file *file_priv)
3307 char *user_data, *vaddr;
3310 vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3311 user_data = (char *)(uintptr_t)data_ptr;
3313 if (copyin_nofault(user_data, vaddr, size) != 0) {
3314 /* The physical object once assigned is fixed for the lifetime
3315 * of the obj, so we can safely drop the lock and continue
3319 ret = -copyin(user_data, vaddr, size);
3325 intel_gtt_chipset_flush();
3330 i915_gem_release(struct drm_device *dev, struct drm_file *file)
3332 struct drm_i915_file_private *file_priv;
3333 struct drm_i915_gem_request *request;
3335 file_priv = file->driver_priv;
3337 /* Clean up our request list when the client is going away, so that
3338 * later retire_requests won't dereference our soon-to-be-gone
3341 spin_lock(&file_priv->mm.lock);
3342 while (!list_empty(&file_priv->mm.request_list)) {
3343 request = list_first_entry(&file_priv->mm.request_list,
3344 struct drm_i915_gem_request,
3346 list_del(&request->client_list);
3347 request->file_priv = NULL;
3349 spin_unlock(&file_priv->mm.lock);
3353 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
3354 uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
3355 struct drm_file *file)
3362 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
3364 if (obj->gtt_offset != 0 && rw == UIO_READ)
3365 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
3367 do_bit17_swizzling = 0;
3370 vm_obj = obj->base.vm_obj;
3373 VM_OBJECT_LOCK(vm_obj);
3374 vm_object_pip_add(vm_obj, 1);
3376 obj_pi = OFF_TO_IDX(offset);
3377 obj_po = offset & PAGE_MASK;
3379 m = i915_gem_wire_page(vm_obj, obj_pi);
3380 VM_OBJECT_UNLOCK(vm_obj);
3382 sf = sf_buf_alloc(m);
3383 mkva = sf_buf_kva(sf);
3384 length = min(size, PAGE_SIZE - obj_po);
3385 while (length > 0) {
3386 if (do_bit17_swizzling &&
3387 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
3388 cnt = roundup2(obj_po + 1, 64);
3389 cnt = min(cnt - obj_po, length);
3390 swizzled_po = obj_po ^ 64;
3393 swizzled_po = obj_po;
3396 ret = -copyout_nofault(
3397 (char *)mkva + swizzled_po,
3398 (void *)(uintptr_t)data_ptr, cnt);
3400 ret = -copyin_nofault(
3401 (void *)(uintptr_t)data_ptr,
3402 (char *)mkva + swizzled_po, cnt);
3412 VM_OBJECT_LOCK(vm_obj);
3413 if (rw == UIO_WRITE)
3415 vm_page_reference(m);
3416 vm_page_busy_wait(m, FALSE, "i915gem");
3417 vm_page_unwire(m, 1);
3419 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3424 vm_object_pip_wakeup(vm_obj);
3425 VM_OBJECT_UNLOCK(vm_obj);
3431 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
3432 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
3438 * Pass the unaligned physical address and size to pmap_mapdev_attr()
3439 * so it can properly calculate whether an extra page needs to be
3440 * mapped or not to cover the requested range. The function will
3441 * add the page offset into the returned mkva for us.
3443 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
3444 offset, size, PAT_WRITE_COMBINING);
3445 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
3446 pmap_unmapdev(mkva, size);
3451 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
3452 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
3454 struct drm_i915_gem_object *obj;
3456 vm_offset_t start, end;
3461 start = trunc_page(data_ptr);
3462 end = round_page(data_ptr + size);
3463 npages = howmany(end - start, PAGE_SIZE);
3464 ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
3466 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
3467 (vm_offset_t)data_ptr, size,
3468 (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
3474 ret = i915_mutex_lock_interruptible(dev);
3478 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
3479 if (&obj->base == NULL) {
3483 if (offset > obj->base.size || size > obj->base.size - offset) {
3488 if (rw == UIO_READ) {
3489 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3492 if (obj->phys_obj) {
3493 ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
3495 } else if (obj->gtt_space &&
3496 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
3497 ret = i915_gem_object_pin(obj, 0, true);
3500 ret = i915_gem_object_set_to_gtt_domain(obj, true);
3503 ret = i915_gem_object_put_fence(obj);
3506 ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
3509 i915_gem_object_unpin(obj);
3511 ret = i915_gem_object_set_to_cpu_domain(obj, true);
3514 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3519 drm_gem_object_unreference(&obj->base);
3523 vm_page_unhold_pages(ma, npages);
3525 drm_free(ma, DRM_I915_GEM);
3530 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
3531 vm_ooffset_t foff, struct ucred *cred, u_short *color)
3534 *color = 0; /* XXXKIB */
3541 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
3544 struct drm_gem_object *gem_obj;
3545 struct drm_i915_gem_object *obj;
3546 struct drm_device *dev;
3547 drm_i915_private_t *dev_priv;
3552 gem_obj = vm_obj->handle;
3553 obj = to_intel_bo(gem_obj);
3554 dev = obj->base.dev;
3555 dev_priv = dev->dev_private;
3557 write = (prot & VM_PROT_WRITE) != 0;
3561 vm_object_pip_add(vm_obj, 1);
3564 * Remove the placeholder page inserted by vm_fault() from the
3565 * object before dropping the object lock. If
3566 * i915_gem_release_mmap() is active in parallel on this gem
3567 * object, then it owns the drm device sx and might find the
3568 * placeholder already. Then, since the page is busy,
3569 * i915_gem_release_mmap() sleeps waiting for the busy state
3570 * of the page cleared. We will be not able to acquire drm
3571 * device lock until i915_gem_release_mmap() is able to make a
3574 if (*mres != NULL) {
3576 vm_page_remove(oldm);
3581 VM_OBJECT_UNLOCK(vm_obj);
3587 ret = i915_mutex_lock_interruptible(dev);
3596 * Since the object lock was dropped, other thread might have
3597 * faulted on the same GTT address and instantiated the
3598 * mapping for the page. Recheck.
3600 VM_OBJECT_LOCK(vm_obj);
3601 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
3603 if ((m->flags & PG_BUSY) != 0) {
3606 vm_page_sleep(m, "915pee");
3612 VM_OBJECT_UNLOCK(vm_obj);
3614 /* Now bind it into the GTT if needed */
3615 if (!obj->map_and_fenceable) {
3616 ret = i915_gem_object_unbind(obj);
3622 if (!obj->gtt_space) {
3623 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
3629 ret = i915_gem_object_set_to_gtt_domain(obj, write);
3636 if (obj->tiling_mode == I915_TILING_NONE)
3637 ret = i915_gem_object_put_fence(obj);
3639 ret = i915_gem_object_get_fence(obj);
3645 if (i915_gem_object_is_inactive(obj))
3646 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3648 obj->fault_mappable = true;
3649 VM_OBJECT_LOCK(vm_obj);
3650 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
3657 KASSERT((m->flags & PG_FICTITIOUS) != 0,
3658 ("not fictitious %p", m));
3659 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
3661 if ((m->flags & PG_BUSY) != 0) {
3664 vm_page_sleep(m, "915pbs");
3668 m->valid = VM_PAGE_BITS_ALL;
3669 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
3672 vm_page_busy_try(m, false);
3678 vm_object_pip_wakeup(vm_obj);
3679 return (VM_PAGER_OK);
3684 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
3685 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
3686 goto unlocked_vmobj;
3688 VM_OBJECT_LOCK(vm_obj);
3689 vm_object_pip_wakeup(vm_obj);
3690 return (VM_PAGER_ERROR);
3694 i915_gem_pager_dtor(void *handle)
3696 struct drm_gem_object *obj;
3697 struct drm_device *dev;
3703 drm_gem_free_mmap_offset(obj);
3704 i915_gem_release_mmap(to_intel_bo(obj));
3705 drm_gem_object_unreference(obj);
3709 struct cdev_pager_ops i915_gem_pager_ops = {
3710 .cdev_pg_fault = i915_gem_pager_fault,
3711 .cdev_pg_ctor = i915_gem_pager_ctor,
3712 .cdev_pg_dtor = i915_gem_pager_dtor
3715 #define GEM_PARANOID_CHECK_GTT 0
3716 #if GEM_PARANOID_CHECK_GTT
3718 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
3721 struct drm_i915_private *dev_priv;
3723 unsigned long start, end;
3727 dev_priv = dev->dev_private;
3728 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
3729 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
3730 for (i = start; i < end; i++) {
3731 pa = intel_gtt_read_pte_paddr(i);
3732 for (j = 0; j < page_count; j++) {
3733 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
3734 panic("Page %p in GTT pte index %d pte %x",
3735 ma[i], i, intel_gtt_read_pte(i));
3743 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
3744 uint32_t flush_domains)
3746 struct drm_i915_gem_object *obj, *next;
3747 uint32_t old_write_domain;
3749 list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
3751 if (obj->base.write_domain & flush_domains) {
3752 old_write_domain = obj->base.write_domain;
3753 obj->base.write_domain = 0;
3754 list_del_init(&obj->gpu_write_list);
3755 i915_gem_object_move_to_active(obj, ring);
3760 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
3763 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
3768 VM_OBJECT_LOCK_ASSERT_OWNED(object);
3769 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
3770 if (m->valid != VM_PAGE_BITS_ALL) {
3771 if (vm_pager_has_page(object, pindex)) {
3772 rv = vm_pager_get_page(object, &m, 1);
3773 m = vm_page_lookup(object, pindex);
3776 if (rv != VM_PAGER_OK) {
3781 pmap_zero_page(VM_PAGE_TO_PHYS(m));
3782 m->valid = VM_PAGE_BITS_ALL;
3788 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
3793 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
3794 uint32_t flush_domains)
3798 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
3801 ret = ring->flush(ring, invalidate_domains, flush_domains);
3805 if (flush_domains & I915_GEM_GPU_DOMAINS)
3806 i915_gem_process_flushing_list(ring, flush_domains);
3811 i915_gpu_is_active(struct drm_device *dev)
3813 drm_i915_private_t *dev_priv = dev->dev_private;
3815 return !list_empty(&dev_priv->mm.active_list);
3819 i915_gem_lowmem(void *arg)
3821 struct drm_device *dev;
3822 struct drm_i915_private *dev_priv;
3823 struct drm_i915_gem_object *obj, *next;
3824 int cnt, cnt_fail, cnt_total;
3827 dev_priv = dev->dev_private;
3829 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3833 /* first scan for clean buffers */
3834 i915_gem_retire_requests(dev);
3836 cnt_total = cnt_fail = cnt = 0;
3838 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3840 if (i915_gem_object_is_purgeable(obj)) {
3841 if (i915_gem_object_unbind(obj) != 0)
3847 /* second pass, evict/count anything still on the inactive list */
3848 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3850 if (i915_gem_object_unbind(obj) == 0)
3856 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3858 * We are desperate for pages, so as a last resort, wait
3859 * for the GPU to finish and discard whatever we can.
3860 * This has a dramatic impact to reduce the number of
3861 * OOM-killer events whilst running the GPU aggressively.
3863 if (i915_gpu_idle(dev) == 0)
3870 i915_gem_unload(struct drm_device *dev)
3872 struct drm_i915_private *dev_priv;
3874 dev_priv = dev->dev_private;
3875 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);