2 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
37 #include <sys/thread2.h>
41 #include <machine/clock.h>
42 #include <machine/vmparam.h>
44 #include <bus/isa/isareg.h>
45 #include <bus/isa/isavar.h>
47 #include <bus/ppbus/ppbconf.h>
48 #include <bus/ppbus/ppb_msq.h>
54 #define LOG_PPC(function, ppc, string) \
55 if (bootverbose) kprintf("%s: %s\n", function, string)
58 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
60 devclass_t ppc_devclass;
62 static int ppc_probe(device_t dev);
63 static int ppc_attach(device_t dev);
64 static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val);
66 static void ppc_reset_epp(device_t);
67 static void ppc_ecp_sync(device_t);
68 static void ppcintr(void *arg);
70 static int ppc_exec_microseq(device_t, struct ppb_microseq **);
71 static int ppc_setmode(device_t, int);
73 static int ppc_read(device_t, char *, int, int);
74 static int ppc_write(device_t, char *, int, int);
76 static u_char ppc_io(device_t, int, u_char *, int, u_char);
78 static int ppc_setup_intr(device_t, device_t, struct resource *, int,
79 void (*)(void *), void *, void **, lwkt_serialize_t);
80 static int ppc_teardown_intr(device_t, device_t, struct resource *, void *);
82 static device_method_t ppc_methods[] = {
83 /* device interface */
84 DEVMETHOD(device_probe, ppc_probe),
85 DEVMETHOD(device_attach, ppc_attach),
88 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
89 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
90 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
91 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
94 DEVMETHOD(ppbus_io, ppc_io),
95 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
96 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
97 DEVMETHOD(ppbus_setmode, ppc_setmode),
98 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
99 DEVMETHOD(ppbus_read, ppc_read),
100 DEVMETHOD(ppbus_write, ppc_write),
105 static driver_t ppc_driver = {
108 sizeof(struct ppc_data),
111 static char *ppc_models[] = {
112 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
113 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
114 "SMC FDC37C935", "PC87303", 0
117 /* list of available modes */
118 static char *ppc_avms[] = {
119 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
120 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
121 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
122 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
125 /* list of current executing modes
126 * Note that few modes do not actually exist.
128 static char *ppc_modes[] = {
129 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
130 "EPP", "EPP", "EPP", "ECP",
131 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
132 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
135 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
139 * BIOS printer list - used by BIOS probe.
141 #define BIOS_PPC_PORTS 0x408
142 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
143 #define BIOS_MAX_PPC 4
150 ppc_ecp_sync(device_t dev)
153 struct ppc_data *ppc = DEVTOSOFTC(dev);
155 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
159 if ((r & 0xe0) != PPC_ECR_EPP)
162 for (i = 0; i < 100; i++) {
169 kprintf("ppc%d: ECP sync failed as data still " \
170 "present in FIFO.\n", ppc->ppc_unit);
178 * Detect parallel port FIFO
181 ppc_detect_fifo(struct ppc_data *ppc)
184 char ctr_sav, ctr, cc;
188 ecr_sav = r_ecr(ppc);
189 ctr_sav = r_ctr(ppc);
191 /* enter ECP configuration mode, no interrupt, no DMA */
194 /* read PWord size - transfers in FIFO mode must be PWord aligned */
195 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
197 /* XXX 16 and 32 bits implementations not supported */
198 if (ppc->ppc_pword != PPC_PWORD_8) {
199 LOG_PPC(__func__, ppc, "PWord not supported");
203 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
205 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
207 /* enter ECP test mode, no interrupt, no DMA */
211 for (i=0; i<1024; i++) {
212 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
218 LOG_PPC(__func__, ppc, "can't flush FIFO");
222 /* enable interrupts, no DMA */
225 /* determine readIntrThreshold
226 * fill the FIFO until serviceIntr is set
228 for (i=0; i<1024; i++) {
229 w_fifo(ppc, (char)i);
230 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
231 /* readThreshold reached */
234 if (r_ecr(ppc) & PPC_FIFO_FULL) {
241 LOG_PPC(__func__, ppc, "can't fill FIFO");
245 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
246 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
247 w_ecr(ppc, 0xd0); /* enable interrupts */
249 /* determine writeIntrThreshold
250 * empty the FIFO until serviceIntr is set
252 for (i=ppc->ppc_fifo; i>0; i--) {
253 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
254 LOG_PPC(__func__, ppc, "invalid data in FIFO");
257 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
258 /* writeIntrThreshold reached */
259 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
261 /* if FIFO empty before the last byte, error */
262 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
263 LOG_PPC(__func__, ppc, "data lost in FIFO");
268 /* FIFO must be empty after the last byte */
269 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
270 LOG_PPC(__func__, ppc, "can't empty the FIFO");
287 ppc_detect_port(struct ppc_data *ppc)
290 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
292 if (r_dtr(ppc) != 0xaa)
299 * EPP timeout, according to the PC87332 manual
300 * Semantics of clearing EPP timeout bit.
301 * PC87332 - reading SPP_STR does it...
302 * SMC - write 1 to EPP timeout bit XXX
303 * Others - (?) write 0 to EPP timeout bit
306 ppc_reset_epp_timeout(struct ppc_data *ppc)
312 w_str(ppc, r & 0xfe);
318 ppc_check_epp_timeout(struct ppc_data *ppc)
320 ppc_reset_epp_timeout(ppc);
322 return (!(r_str(ppc) & TIMEOUT));
326 * Configure current operating mode
329 ppc_generic_setmode(struct ppc_data *ppc, int mode)
333 /* check if mode is available */
334 if (mode && !(ppc->ppc_avm & mode))
337 /* if ECP mode, configure ecr register */
338 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
339 /* return to byte mode (keeping direction bit),
340 * no interrupt, no DMA to be able to change to
343 w_ecr(ppc, PPC_ECR_RESET);
344 ecr = PPC_DISABLE_INTR;
348 else if (mode & PPB_ECP)
349 /* select ECP mode */
351 else if (mode & PPB_PS2)
352 /* select PS2 mode with ECP */
355 /* select COMPATIBLE/NIBBLE mode */
361 ppc->ppc_mode = mode;
367 * The ppc driver is free to choose options like FIFO or DMA
368 * if ECP mode is available.
370 * The 'RAW' option allows the upper drivers to force the ppc mode
371 * even with FIFO, DMA available.
374 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
378 /* check if mode is available */
379 if (mode && !(ppc->ppc_avm & mode))
382 /* if ECP mode, configure ecr register */
383 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
384 /* return to byte mode (keeping direction bit),
385 * no interrupt, no DMA to be able to change to
388 w_ecr(ppc, PPC_ECR_RESET);
389 ecr = PPC_DISABLE_INTR;
392 /* select EPP mode */
394 else if (mode & PPB_ECP)
395 /* select ECP mode */
397 else if (mode & PPB_PS2)
398 /* select PS2 mode with ECP */
401 /* select COMPATIBLE/NIBBLE mode */
407 ppc->ppc_mode = mode;
412 #ifdef PPC_PROBE_CHIPSET
416 * Probe for a Natsemi PC873xx-family part.
418 * References in this function are to the National Semiconductor
419 * PC87332 datasheet TL/C/11930, May 1995 revision.
421 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
422 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
423 static int pc873xx_irqtab[] = {5, 7, 5, 0};
425 static int pc873xx_regstab[] = {
426 PC873_FER, PC873_FAR, PC873_PTR,
427 PC873_FCR, PC873_PCR, PC873_PMC,
428 PC873_TUP, PC873_SID, PC873_PNP0,
429 PC873_PNP1, PC873_LPTBA, -1
432 static char *pc873xx_rnametab[] = {
433 "FER", "FAR", "PTR", "FCR", "PCR",
434 "PMC", "TUP", "SID", "PNP0", "PNP1",
439 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
441 static int index = 0;
443 int ptr, pcr, val, i;
445 while ((idport = pc873xx_basetab[index++])) {
447 /* XXX should check first to see if this location is already claimed */
450 * Pull the 873xx through the power-on ID cycle (2.2,1.).
451 * We can't use this to locate the chip as it may already have
452 * been used by the BIOS.
454 (void)inb(idport); (void)inb(idport);
455 (void)inb(idport); (void)inb(idport);
458 * Read the SID byte. Possible values are :
465 outb(idport, PC873_SID);
466 val = inb(idport + 1);
467 if ((val & 0xf0) == 0x10) {
468 ppc->ppc_model = NS_PC87332;
469 } else if ((val & 0xf8) == 0x70) {
470 ppc->ppc_model = NS_PC87306;
471 } else if ((val & 0xf8) == 0x50) {
472 ppc->ppc_model = NS_PC87334;
473 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
474 documentation, but probing
476 ppc->ppc_model = NS_PC87303;
478 if (bootverbose && (val != 0xff))
479 kprintf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
480 continue ; /* not recognised */
483 /* print registers */
486 for (i=0; pc873xx_regstab[i] != -1; i++) {
487 outb(idport, pc873xx_regstab[i]);
488 kprintf(" %s=0x%x", pc873xx_rnametab[i],
489 inb(idport + 1) & 0xff);
495 * We think we have one. Is it enabled and where we want it to be?
497 outb(idport, PC873_FER);
498 val = inb(idport + 1);
499 if (!(val & PC873_PPENABLE)) {
501 kprintf("PC873xx parallel port disabled\n");
504 outb(idport, PC873_FAR);
505 val = inb(idport + 1);
506 /* XXX we should create a driver instance for every port found */
507 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
509 /* First try to change the port address to that requested... */
511 switch(ppc->ppc_base) {
529 outb(idport, PC873_FAR);
530 outb(idport + 1, val);
531 outb(idport + 1, val);
533 /* Check for success by reading back the value we supposedly
534 wrote and comparing...*/
536 outb(idport, PC873_FAR);
537 val = inb(idport + 1) & 0x3;
539 /* If we fail, report the failure... */
541 if (pc873xx_porttab[val] != ppc->ppc_base) {
543 kprintf("PC873xx at 0x%x not for driver at port 0x%x\n",
544 pc873xx_porttab[val], ppc->ppc_base);
549 outb(idport, PC873_PTR);
550 ptr = inb(idport + 1);
552 /* get irq settings */
553 if (ppc->ppc_base == 0x378)
554 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
556 irq = pc873xx_irqtab[val];
559 kprintf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
562 * Check if irq settings are correct
564 if (irq != ppc->ppc_irq) {
566 * If the chipset is not locked and base address is 0x378,
567 * we have another chance
569 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
570 if (ppc->ppc_irq == 7) {
571 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
572 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
574 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
575 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
578 kprintf("PC873xx irq set to %d\n", ppc->ppc_irq);
581 kprintf("PC873xx sorry, can't change irq setting\n");
585 kprintf("PC873xx irq settings are correct\n");
588 outb(idport, PC873_PCR);
589 pcr = inb(idport + 1);
591 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
593 kprintf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
595 ppc->ppc_avm |= PPB_NIBBLE;
599 if (pcr & PC873_EPPEN) {
600 ppc->ppc_avm |= PPB_EPP;
605 if (pcr & PC873_EPP19)
606 ppc->ppc_epp = EPP_1_9;
608 ppc->ppc_epp = EPP_1_7;
610 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
611 outb(idport, PC873_PTR);
612 ptr = inb(idport + 1);
613 if (ptr & PC873_EPPRDIR)
614 kprintf(", Regular mode");
616 kprintf(", Automatic mode");
618 } else if (pcr & PC873_ECPEN) {
619 ppc->ppc_avm |= PPB_ECP;
623 if (pcr & PC873_ECPCLK) { /* XXX */
624 ppc->ppc_avm |= PPB_PS2;
629 outb(idport, PC873_PTR);
630 ptr = inb(idport + 1);
631 if (ptr & PC873_EXTENDED) {
632 ppc->ppc_avm |= PPB_SPP;
639 kprintf("PC873xx unlocked");
641 if (chipset_mode & PPB_ECP) {
642 if ((chipset_mode & PPB_EPP) && bootverbose)
643 kprintf(", ECP+EPP not supported");
646 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
647 outb(idport + 1, pcr);
648 outb(idport + 1, pcr);
653 } else if (chipset_mode & PPB_EPP) {
654 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
655 pcr |= (PC873_EPPEN | PC873_EPP19);
656 outb(idport + 1, pcr);
657 outb(idport + 1, pcr);
659 ppc->ppc_epp = EPP_1_9; /* XXX */
664 /* enable automatic direction turnover */
665 if (ppc->ppc_model == NS_PC87332) {
666 outb(idport, PC873_PTR);
667 ptr = inb(idport + 1);
668 ptr &= ~PC873_EPPRDIR;
669 outb(idport + 1, ptr);
670 outb(idport + 1, ptr);
673 kprintf(", Automatic mode");
676 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
677 outb(idport + 1, pcr);
678 outb(idport + 1, pcr);
680 /* configure extended bit in PTR */
681 outb(idport, PC873_PTR);
682 ptr = inb(idport + 1);
684 if (chipset_mode & PPB_PS2) {
685 ptr |= PC873_EXTENDED;
691 /* default to NIBBLE mode */
692 ptr &= ~PC873_EXTENDED;
697 outb(idport + 1, ptr);
698 outb(idport + 1, ptr);
701 ppc->ppc_avm = chipset_mode;
707 ppc->ppc_type = PPC_TYPE_GENERIC;
708 ppc_generic_setmode(ppc, chipset_mode);
710 return(chipset_mode);
716 * ppc_smc37c66xgt_detect
718 * SMC FDC37C66xGT configuration.
721 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
726 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
728 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
731 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
734 * Detection: enter configuration mode and read CRD register.
738 outb(csr, SMC665_iCODE);
739 outb(csr, SMC665_iCODE);
743 if (inb(cio) == 0x65) {
748 for (i = 0; i < 2; i++) {
750 outb(csr, SMC666_iCODE);
751 outb(csr, SMC666_iCODE);
755 if (inb(cio) == 0x66) {
760 /* Another chance, CSR may be hard-configured to be at 0x370 */
766 * If chipset not found, do not continue.
774 /* read the port's address: bits 0 and 1 of CR1 */
775 r = inb(cio) & SMC_CR1_ADDR;
776 if (port_address[(int)r] != ppc->ppc_base)
779 ppc->ppc_model = type;
782 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
783 * If SPP mode is detected, try to set ECP+EPP mode
788 kprintf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
792 kprintf(" CR4=0x%x", inb(cio) & 0xff);
799 /* autodetect mode */
801 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
802 if (type == SMC_37C666GT) {
803 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
805 kprintf(" configuration hardwired, supposing " \
809 if ((inb(cio) & SMC_CR1_MODE) == 0) {
810 /* already in extended parallel port mode, read CR4 */
812 r = (inb(cio) & SMC_CR4_EMODE);
816 ppc->ppc_avm |= PPB_SPP;
822 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
828 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
834 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
836 kprintf(" ECP+EPP SPP");
840 /* not an extended port mode */
841 ppc->ppc_avm |= PPB_SPP;
848 ppc->ppc_avm = chipset_mode;
850 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
851 if (type == SMC_37C666GT)
855 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
856 /* do not use ECP when the mode is not forced to */
857 outb(cio, r | SMC_CR1_MODE);
861 /* an extended mode is selected */
862 outb(cio, r & ~SMC_CR1_MODE);
864 /* read CR4 register and reset mode field */
866 r = inb(cio) & ~SMC_CR4_EMODE;
868 if (chipset_mode & PPB_ECP) {
869 if (chipset_mode & PPB_EPP) {
870 outb(cio, r | SMC_ECPEPP);
874 outb(cio, r | SMC_ECP);
880 outb(cio, r | SMC_EPPSPP);
885 ppc->ppc_avm = chipset_mode;
888 /* set FIFO threshold to 16 */
889 if (ppc->ppc_avm & PPB_ECP) {
900 if (ppc->ppc_avm & PPB_EPP) {
906 * Set the EPP protocol...
907 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
909 if (ppc->ppc_epp == EPP_1_9)
910 outb(cio, (r & ~SMC_CR4_EPPTYPE));
912 outb(cio, (r | SMC_CR4_EPPTYPE));
915 /* end config mode */
918 ppc->ppc_type = PPC_TYPE_SMCLIKE;
919 ppc_smclike_setmode(ppc, chipset_mode);
921 return (chipset_mode);
925 * SMC FDC37C935 configuration
926 * Found on many Alpha machines
929 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
934 outb(SMC935_CFG, 0x55); /* enter config mode */
935 outb(SMC935_CFG, 0x55);
938 outb(SMC935_IND, SMC935_ID); /* check device id */
939 if (inb(SMC935_DAT) == 0x2)
943 outb(SMC935_CFG, 0xaa); /* exit config mode */
947 ppc->ppc_model = type;
949 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
950 outb(SMC935_DAT, 3); /* which is logical device 3 */
952 /* set io port base */
953 outb(SMC935_IND, SMC935_PORTHI);
954 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
955 outb(SMC935_IND, SMC935_PORTLO);
956 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
959 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
961 ppc->ppc_avm = chipset_mode;
962 outb(SMC935_IND, SMC935_PPMODE);
963 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
965 /* SPP + EPP or just plain SPP */
966 if (chipset_mode & (PPB_SPP)) {
967 if (chipset_mode & PPB_EPP) {
968 if (ppc->ppc_epp == EPP_1_9) {
969 outb(SMC935_IND, SMC935_PPMODE);
970 outb(SMC935_DAT, SMC935_EPP19SPP);
972 if (ppc->ppc_epp == EPP_1_7) {
973 outb(SMC935_IND, SMC935_PPMODE);
974 outb(SMC935_DAT, SMC935_EPP17SPP);
977 outb(SMC935_IND, SMC935_PPMODE);
978 outb(SMC935_DAT, SMC935_SPP);
982 /* ECP + EPP or just plain ECP */
983 if (chipset_mode & PPB_ECP) {
984 if (chipset_mode & PPB_EPP) {
985 if (ppc->ppc_epp == EPP_1_9) {
986 outb(SMC935_IND, SMC935_PPMODE);
987 outb(SMC935_DAT, SMC935_ECPEPP19);
989 if (ppc->ppc_epp == EPP_1_7) {
990 outb(SMC935_IND, SMC935_PPMODE);
991 outb(SMC935_DAT, SMC935_ECPEPP17);
994 outb(SMC935_IND, SMC935_PPMODE);
995 outb(SMC935_DAT, SMC935_ECP);
1000 outb(SMC935_CFG, 0xaa); /* exit config mode */
1002 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1003 ppc_smclike_setmode(ppc, chipset_mode);
1005 return (chipset_mode);
1009 * Winbond W83877F stuff
1011 * EFER: extended function enable register
1012 * EFIR: extended function index register
1013 * EFDR: extended function data register
1015 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1016 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1018 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1019 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1020 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1021 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1024 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1027 unsigned char r, hefere, hefras;
1029 for (i = 0; i < 4; i ++) {
1030 /* first try to enable configuration registers */
1031 efer = w83877f_efers[i];
1033 /* write the key to the EFER */
1034 for (j = 0; j < w83877f_keyiter[i]; j ++)
1035 outb (efer, w83877f_keys[i]);
1037 /* then check HEFERE and HEFRAS bits */
1039 hefere = inb(efdr) & WINB_HEFERE;
1042 hefras = inb(efdr) & WINB_HEFRAS;
1046 * 0 1 write 89h to 250h (power-on default)
1047 * 1 0 write 86h twice to 3f0h
1048 * 1 1 write 87h twice to 3f0h
1049 * 0 0 write 88h to 250h
1051 if ((hefere | hefras) == w83877f_hefs[i])
1055 return (-1); /* failed */
1058 /* check base port address - read from CR23 */
1060 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1063 /* read CHIP ID from CR9/bits0-3 */
1066 switch (inb(efdr) & WINB_CHIPID) {
1067 case WINB_W83877F_ID:
1068 ppc->ppc_model = WINB_W83877F;
1071 case WINB_W83877AF_ID:
1072 ppc->ppc_model = WINB_W83877AF;
1076 ppc->ppc_model = WINB_UNKNOWN;
1080 /* dump of registers */
1081 kprintf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1082 for (i = 0; i <= 0xd; i ++) {
1084 kprintf("0x%x ", inb(efdr));
1086 for (i = 0x10; i <= 0x17; i ++) {
1088 kprintf("0x%x ", inb(efdr));
1091 kprintf("0x%x ", inb(efdr));
1092 for (i = 0x20; i <= 0x29; i ++) {
1094 kprintf("0x%x ", inb(efdr));
1097 kprintf("ppc%d:", ppc->ppc_unit);
1100 ppc->ppc_type = PPC_TYPE_GENERIC;
1102 if (!chipset_mode) {
1103 /* autodetect mode */
1107 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1111 r |= (inb(efdr) & WINB_PRTMODS2);
1116 kprintf("ppc%d: W83757 compatible mode\n",
1118 return (-1); /* generic or SMC-like */
1125 kprintf(" not in parallel port mode\n");
1128 case (WINB_PARALLEL | WINB_EPP_SPP):
1129 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1131 kprintf(" EPP SPP");
1134 case (WINB_PARALLEL | WINB_ECP):
1135 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1137 kprintf(" ECP SPP");
1140 case (WINB_PARALLEL | WINB_ECP_EPP):
1141 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1142 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1145 kprintf(" ECP+EPP SPP");
1148 kprintf("%s: unknown case (0x%x)!\n", __func__, r);
1154 /* select CR9 and set PRTMODS2 bit */
1156 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1158 /* select CR0 and reset PRTMODSx bits */
1160 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1162 if (chipset_mode & PPB_ECP) {
1163 if (chipset_mode & PPB_EPP) {
1164 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1166 kprintf(" ECP+EPP");
1168 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1171 outb(efdr, inb(efdr) | WINB_ECP);
1176 /* select EPP_SPP otherwise */
1177 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1179 kprintf(" EPP SPP");
1181 ppc->ppc_avm = chipset_mode;
1187 /* exit configuration mode */
1190 switch (ppc->ppc_type) {
1191 case PPC_TYPE_SMCLIKE:
1192 ppc_smclike_setmode(ppc, chipset_mode);
1195 ppc_generic_setmode(ppc, chipset_mode);
1199 return (chipset_mode);
1204 * ppc_generic_detect
1207 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1209 /* default to generic */
1210 ppc->ppc_type = PPC_TYPE_GENERIC;
1213 kprintf("ppc%d:", ppc->ppc_unit);
1215 /* first, check for ECP */
1216 w_ecr(ppc, PPC_ECR_PS2);
1217 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1218 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1220 kprintf(" ECP SPP");
1222 /* search for SMC style ECP+EPP mode */
1223 w_ecr(ppc, PPC_ECR_EPP);
1226 /* try to reset EPP timeout bit */
1227 if (ppc_check_epp_timeout(ppc)) {
1228 ppc->ppc_dtm |= PPB_EPP;
1230 if (ppc->ppc_dtm & PPB_ECP) {
1231 /* SMC like chipset found */
1232 ppc->ppc_model = SMC_LIKE;
1233 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1236 kprintf(" ECP+EPP");
1242 /* restore to standard mode */
1243 w_ecr(ppc, PPC_ECR_STD);
1246 /* XXX try to detect NIBBLE and PS2 modes */
1247 ppc->ppc_dtm |= PPB_NIBBLE;
1253 ppc->ppc_avm = chipset_mode;
1255 ppc->ppc_avm = ppc->ppc_dtm;
1260 switch (ppc->ppc_type) {
1261 case PPC_TYPE_SMCLIKE:
1262 ppc_smclike_setmode(ppc, chipset_mode);
1265 ppc_generic_setmode(ppc, chipset_mode);
1269 return (chipset_mode);
1275 * mode is the mode suggested at boot
1278 ppc_detect(struct ppc_data *ppc, int chipset_mode)
1280 #ifdef PPC_PROBE_CHIPSET
1283 /* list of supported chipsets */
1284 int (*chipset_detect[])(struct ppc_data *, int) = {
1286 ppc_smc37c66xgt_detect,
1288 ppc_smc37c935_detect,
1294 /* if can't find the port and mode not forced return error */
1295 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1296 return (EIO); /* failed, port not present */
1298 /* assume centronics compatible mode is supported */
1299 ppc->ppc_avm = PPB_COMPATIBLE;
1301 #ifdef PPC_PROBE_CHIPSET
1302 /* we have to differenciate available chipset modes,
1303 * chipset running modes and IEEE-1284 operating modes
1305 * after detection, the port must support running in compatible mode
1307 if (ppc->ppc_flags & 0x40) {
1309 kprintf("ppc: chipset forced to generic\n");
1312 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1314 #ifdef PPC_PROBE_CHIPSET
1316 for (i=0; chipset_detect[i] != NULL; i++) {
1317 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1318 ppc->ppc_mode = mode;
1325 /* configure/detect ECP FIFO */
1326 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1327 ppc_detect_fifo(ppc);
1333 * ppc_exec_microseq()
1335 * Execute a microsequence.
1336 * Microsequence mechanism is supposed to handle fast I/O operations.
1339 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1341 struct ppc_data *ppc = DEVTOSOFTC(dev);
1342 struct ppb_microseq *mi;
1352 struct ppb_microseq *stack = NULL;
1354 /* microsequence registers are equivalent to PC-like port registers */
1356 #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register))
1357 #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte))
1359 #define INCR_PC (mi ++) /* increment program counter */
1363 switch (mi->opcode) {
1365 cc = r_reg(mi->arg[0].i, ppc);
1366 cc &= (char)mi->arg[2].i; /* clear mask */
1367 cc |= (char)mi->arg[1].i; /* assert mask */
1368 w_reg(mi->arg[0].i, ppc, cc);
1372 case MS_OP_RASSERT_P:
1376 if ((len = mi->arg[0].i) == MS_ACCUM) {
1377 accum = ppc->ppc_accum;
1378 for (; accum; accum--)
1379 w_reg(reg, ppc, *ptr++);
1380 ppc->ppc_accum = accum;
1382 for (i=0; i<len; i++)
1383 w_reg(reg, ppc, *ptr++);
1389 case MS_OP_RFETCH_P:
1391 mask = (char)mi->arg[2].i;
1394 if ((len = mi->arg[0].i) == MS_ACCUM) {
1395 accum = ppc->ppc_accum;
1396 for (; accum; accum--)
1397 *ptr++ = r_reg(reg, ppc) & mask;
1398 ppc->ppc_accum = accum;
1400 for (i=0; i<len; i++)
1401 *ptr++ = r_reg(reg, ppc) & mask;
1408 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1416 /* let's suppose the next instr. is the same */
1418 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1419 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1421 if (mi->opcode == MS_OP_DELAY) {
1422 DELAY(mi->arg[0].i);
1430 tsleep(ppc_exec_microseq, 0, "ppbdelay",
1431 mi->arg[0].i * (hz/1000));
1437 iter = mi->arg[1].i;
1438 p = (char *)mi->arg[2].p;
1440 /* XXX delay limited to 255 us */
1441 for (i=0; i<iter; i++) {
1442 w_reg(reg, ppc, *p++);
1443 DELAY((unsigned char)*p++);
1449 ppc->ppc_accum = mi->arg[0].i;
1454 if (--ppc->ppc_accum > 0)
1461 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1468 if ((cc & (char)mi->arg[0].i) == 0)
1475 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1483 * If the C call returns !0 then end the microseq.
1484 * The current state of ptr is passed to the C function
1486 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1493 ppc->ppc_ptr = (char *)mi->arg[0].p;
1499 panic("%s: too much calls", __func__);
1502 /* store the state of the actual
1507 /* jump to the new microsequence */
1508 mi = (struct ppb_microseq *)mi->arg[0].p;
1515 /* retrieve microseq and pc state before the call */
1518 /* reset the stack */
1521 /* XXX return code */
1529 /* can't return to ppb level during the execution
1530 * of a submicrosequence */
1532 panic("%s: can't return to ppb level",
1535 /* update pc for ppb level of execution */
1538 /* return to ppb level of execution */
1542 panic("%s: unknown microsequence opcode 0x%x",
1543 __func__, mi->opcode);
1553 device_t dev = (device_t)arg;
1554 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1555 u_char ctr, ecr, str;
1562 kprintf("![%x/%x/%x]", ctr, ecr, str);
1565 /* don't use ecp mode with IRQENABLE set */
1566 if (ctr & IRQENABLE) {
1570 /* interrupts are generated by nFault signal
1571 * only in ECP mode */
1572 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1573 /* check if ppc driver has programmed the
1574 * nFault interrupt */
1575 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1577 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1578 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1580 /* shall be handled by underlying layers XXX */
1585 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1586 /* disable interrupts (should be done by hardware though) */
1587 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1588 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1591 /* check if DMA completed */
1592 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1597 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1600 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1610 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1612 /* wakeup the waiting process */
1613 wakeup((caddr_t)ppc);
1616 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1618 /* classic interrupt I/O */
1619 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1626 ppc_read(device_t dev, char *buf, int len, int mode)
1632 * Call this function if you want to send data in any advanced mode
1633 * of your parallel port: FIFO, DMA
1635 * If what you want is not possible (no ECP, no DMA...),
1636 * EINVAL is returned
1639 ppc_write(device_t dev, char *buf, int len, int how)
1641 struct ppc_data *ppc = DEVTOSOFTC(dev);
1642 char ecr, ecr_sav, ctr, ctr_sav;
1650 ecr_sav = r_ecr(ppc);
1651 ctr_sav = r_ctr(ppc);
1654 * Send buffer with DMA, FIFO and interrupts
1656 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1658 if (ppc->ppc_dmachan > 0) {
1660 /* byte mode, no intr, no DMA, dir=0, flush fifo
1662 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1665 /* disable nAck interrupts */
1670 ppc->ppc_dmaflags = ISADMA_WRITE;
1671 ppc->ppc_dmaddr = (caddr_t)buf;
1672 ppc->ppc_dmacnt = (u_int)len;
1674 switch (ppc->ppc_mode) {
1675 case PPB_COMPATIBLE:
1676 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1677 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1680 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1690 /* enter splhigh() not to be preempted
1691 * by the dma interrupt, we may miss
1692 * the wakeup otherwise
1696 ppc->ppc_dmastat = PPC_DMA_INIT;
1698 /* enable interrupts */
1699 ecr &= ~PPC_SERVICE_INTR;
1700 ppc->ppc_irqstat = PPC_IRQ_DMA;
1709 kprintf("s%d", ppc->ppc_dmacnt);
1711 ppc->ppc_dmastat = PPC_DMA_STARTED;
1713 /* Wait for the DMA completed interrupt. We hope we won't
1714 * miss it, otherwise a signal will be necessary to unlock the
1719 error = tsleep((caddr_t)ppc, PCATCH, "ppcdma", 0);
1721 } while (error == EWOULDBLOCK);
1732 ppc->ppc_dmaddr, ppc->ppc_dmacnt,
1735 /* no dma, no interrupt, flush the fifo */
1736 w_ecr(ppc, PPC_ECR_RESET);
1738 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1742 /* wait for an empty fifo */
1743 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1745 for (spin=100; spin; spin--)
1746 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1751 error = tsleep((caddr_t)ppc, PCATCH, "ppcfifo", hz/100);
1752 if (error != EWOULDBLOCK) {
1756 /* no dma, no interrupt, flush the fifo */
1757 w_ecr(ppc, PPC_ECR_RESET);
1759 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1766 /* no dma, no interrupt, flush the fifo */
1767 w_ecr(ppc, PPC_ECR_RESET);
1770 error = EINVAL; /* XXX we should FIFO and
1777 /* PDRQ must be kept unasserted until nPDACK is
1778 * deasserted for a minimum of 350ns (SMC datasheet)
1780 * Consequence may be a FIFO that never empty
1784 w_ecr(ppc, ecr_sav);
1785 w_ctr(ppc, ctr_sav);
1791 ppc_reset_epp(device_t dev)
1793 struct ppc_data *ppc = DEVTOSOFTC(dev);
1795 ppc_reset_epp_timeout(ppc);
1801 ppc_setmode(device_t dev, int mode)
1803 struct ppc_data *ppc = DEVTOSOFTC(dev);
1805 switch (ppc->ppc_type) {
1806 case PPC_TYPE_SMCLIKE:
1807 return (ppc_smclike_setmode(ppc, mode));
1810 case PPC_TYPE_GENERIC:
1812 return (ppc_generic_setmode(ppc, mode));
1820 static struct isa_pnp_id lpc_ids[] = {
1821 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */
1822 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */
1827 ppc_probe(device_t dev)
1830 static short next_bios_ppc = 0;
1832 struct ppc_data *ppc;
1837 parent = device_get_parent(dev);
1839 error = ISA_PNP_PROBE(parent, dev, lpc_ids);
1842 else if (error != 0) /* XXX shall be set after detection */
1843 device_set_desc(dev, "Parallel port");
1846 * Allocate the ppc_data structure.
1848 ppc = DEVTOSOFTC(dev);
1849 bzero(ppc, sizeof(struct ppc_data));
1851 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1852 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1854 /* retrieve ISA parameters */
1855 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL);
1859 * If port not specified, use bios list.
1862 if((next_bios_ppc < BIOS_MAX_PPC) &&
1863 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1864 port = *(BIOS_PORTS+next_bios_ppc++);
1866 device_printf(dev, "parallel port found at 0x%x\n",
1869 device_printf(dev, "parallel port not found.\n");
1872 bus_set_resource(dev, SYS_RES_IOPORT, 0, port,
1873 IO_LPTSIZE_EXTENDED, -1);
1877 /* IO port is mandatory */
1879 /* Try "extended" IO port range...*/
1880 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1881 &ppc->rid_ioport, 0, ~0,
1882 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1884 if (ppc->res_ioport != 0) {
1886 device_printf(dev, "using extended I/O port range\n");
1888 /* Failed? If so, then try the "normal" IO port range... */
1889 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1890 &ppc->rid_ioport, 0, ~0,
1893 if (ppc->res_ioport != 0) {
1895 device_printf(dev, "using normal I/O port range\n");
1897 device_printf(dev, "cannot reserve I/O port range\n");
1902 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1904 ppc->bsh = rman_get_bushandle(ppc->res_ioport);
1905 ppc->bst = rman_get_bustag(ppc->res_ioport);
1907 ppc->ppc_flags = device_get_flags(dev);
1909 if (!(ppc->ppc_flags & 0x20)) {
1910 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq,
1911 0ul, ~0ul, 1, RF_SHAREABLE);
1912 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq,
1913 0ul, ~0ul, 1, RF_ACTIVE);
1917 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1919 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1921 ppc->ppc_unit = device_get_unit(dev);
1922 ppc->ppc_model = GENERIC;
1924 ppc->ppc_mode = PPB_COMPATIBLE;
1925 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1927 ppc->ppc_type = PPC_TYPE_GENERIC;
1930 * Try to detect the chipset and its mode.
1932 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1938 if (ppc->res_irq != 0) {
1939 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1942 if (ppc->res_ioport != 0) {
1943 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1945 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1948 if (ppc->res_drq != 0) {
1949 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1951 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1958 ppc_attach(device_t dev)
1960 struct ppc_data *ppc = DEVTOSOFTC(dev);
1963 device_t parent = device_get_parent(dev);
1965 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1966 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1967 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1968 ppc_epp_protocol[ppc->ppc_epp] : "");
1971 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1972 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1974 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1975 /* acquire the DMA channel forever */ /* XXX */
1976 isa_dma_acquire(ppc->ppc_dmachan);
1977 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1980 /* add ppbus as a child of this isa to parallel bridge */
1981 ppbus = device_add_child(dev, "ppbus", -1);
1984 * Probe the ppbus and attach devices found.
1986 device_probe_and_attach(ppbus);
1988 /* register the ppc interrupt handler as default */
1990 /* default to the tty mask for registration */ /* XXX */
1991 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, 0,
1993 &ppc->intr_cookie, NULL, NULL) == 0) {
1994 /* remember the ppcintr is registered */
1995 ppc->ppc_registered = 1;
2003 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
2005 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
2008 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2011 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2014 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2017 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2020 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2023 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2026 return (r_dtr(ppc));
2029 return (r_str(ppc));
2032 return (r_ctr(ppc));
2035 return (r_epp_A(ppc));
2038 return (r_epp_D(ppc));
2041 return (r_ecr(ppc));
2044 return (r_fifo(ppc));
2068 panic("%s: unknown I/O operation", __func__);
2072 return (0); /* not significative */
2076 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
2078 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
2081 case PPC_IVAR_EPP_PROTO:
2082 *val = (u_long)ppc->ppc_epp;
2085 *val = (u_long)ppc->ppc_irq;
2095 * Resource is useless here since ppbus devices' interrupt handlers are
2096 * multiplexed to the same resource initially allocated by ppc
2099 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2100 void (*ihand)(void *), void *arg,
2101 void **cookiep, lwkt_serialize_t serializer)
2104 struct ppc_data *ppc = DEVTOSOFTC(bus);
2106 if (ppc->ppc_registered) {
2107 /* XXX refuse registration if DMA is in progress */
2109 /* first, unregister the default interrupt handler */
2110 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2111 bus, ppc->res_irq, ppc->intr_cookie)))
2114 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2115 /* ppc->res_irq); */
2117 /* DMA/FIFO operation won't be possible anymore */
2118 ppc->ppc_registered = 0;
2121 /* pass registration to the upper layer, ignore the incoming resource */
2122 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2123 r, flags, ihand, arg, cookiep,
2128 * When no underlying device has a registered interrupt, register the ppc
2132 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2135 struct ppc_data *ppc = DEVTOSOFTC(bus);
2136 device_t parent = device_get_parent(bus);
2138 /* pass unregistration to the upper layer */
2139 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2142 /* default to the tty mask for registration */ /* XXX */
2144 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2146 &ppc->intr_cookie, NULL, NULL))
2148 /* remember the ppcintr is registered */
2149 ppc->ppc_registered = 1;
2155 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, NULL, NULL);
2156 DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, NULL, NULL);