sys/dev/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  *
  27  * $FreeBSD: head/sys/dev/drm2/radeon/atombios_dp.c 254885 2013-08-25 19:37:15Z dumbbell $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <uapi_drm/radeon_drm.h>
  32 #include "radeon.h"
  33
  34 #include "atom.h"
  35 #include "atom-bits.h"
  36 #include <drm/drm_dp_helper.h>
  37
  38 /* move these to drm_dp_helper.c/h */
  39 #define DP_LINK_CONFIGURATION_SIZE 9
  40 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  41
  42 static char *voltage_names[] = {
  43         "0.4V", "0.6V", "0.8V", "1.2V"
  44 };
  45 static char *pre_emph_names[] = {
  46         "0dB", "3.5dB", "6dB", "9.5dB"
  47 };
  48
  49 /***** radeon AUX functions *****/
  50 union aux_channel_transaction {
  51         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  52         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  53 };
  54
  55 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  56                                  u8 *send, int send_bytes,
  57                                  u8 *recv, int recv_size,
  58                                  u8 delay, u8 *ack)
  59 {
  60         struct drm_device *dev = chan->dev;
  61         struct radeon_device *rdev = dev->dev_private;
  62         union aux_channel_transaction args;
  63         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  64         unsigned char *base;
  65         int recv_bytes;
  66
  67         memset(&args, 0, sizeof(args));
  68
  69         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
  70
  71         memcpy(base, send, send_bytes);
  72
  73         args.v1.lpAuxRequest = 0 + 4;
  74         args.v1.lpDataOut = 16 + 4;
  75         args.v1.ucDataOutLen = 0;
  76         args.v1.ucChannelID = chan->rec.i2c_id;
  77         args.v1.ucDelay = delay / 10;
  78         if (ASIC_IS_DCE4(rdev))
  79                 args.v2.ucHPD_ID = chan->rec.hpd;
  80
  81         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  82
  83         *ack = args.v1.ucReplyStatus;
  84
  85         /* timeout */
  86         if (args.v1.ucReplyStatus == 1) {
  87                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
  88                 return -ETIMEDOUT;
  89         }
  90
  91         /* flags not zero */
  92         if (args.v1.ucReplyStatus == 2) {
  93                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
  94                 return -EBUSY;
  95         }
  96
  97         /* error */
  98         if (args.v1.ucReplyStatus == 3) {
  99                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 100                 return -EIO;
 101         }
 102
 103         recv_bytes = args.v1.ucDataOutLen;
 104         if (recv_bytes > recv_size)
 105                 recv_bytes = recv_size;
 106
 107         if (recv && recv_size)
 108                 memcpy(recv, base + 16, recv_bytes);
 109
 110         return recv_bytes;
 111 }
 112
 113 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
 114                                       u16 address, u8 *send, u8 send_bytes, u8 delay)
 115 {
 116         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 117         int ret;
 118         u8 msg[20];
 119         int msg_bytes = send_bytes + 4;
 120         u8 ack;
 121         unsigned retry;
 122
 123         if (send_bytes > 16)
 124                 return -1;
 125
 126         msg[0] = address;
 127         msg[1] = address >> 8;
 128         msg[2] = DP_AUX_NATIVE_WRITE << 4;
 129         msg[3] = (msg_bytes << 4) | (send_bytes - 1);
 130         memcpy(&msg[4], send, send_bytes);
 131
 132         for (retry = 0; retry < 4; retry++) {
 133                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 134                                             msg, msg_bytes, NULL, 0, delay, &ack);
 135                 if (ret == -EBUSY)
 136                         continue;
 137                 else if (ret < 0)
 138                         return ret;
 139                 ack >>= 4;
 140                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 141                         return send_bytes;
 142                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 143                         DRM_UDELAY(400);
 144                 else
 145                         return -EIO;
 146         }
 147
 148         return -EIO;
 149 }
 150
 151 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
 152                                      u16 address, u8 *recv, int recv_bytes, u8 delay)
 153 {
 154         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 155         u8 msg[4];
 156         int msg_bytes = 4;
 157         u8 ack;
 158         int ret;
 159         unsigned retry;
 160
 161         msg[0] = address;
 162         msg[1] = address >> 8;
 163         msg[2] = DP_AUX_NATIVE_READ << 4;
 164         msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
 165
 166         for (retry = 0; retry < 4; retry++) {
 167                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 168                                             msg, msg_bytes, recv, recv_bytes, delay, &ack);
 169                 if (ret == -EBUSY)
 170                         continue;
 171                 else if (ret < 0)
 172                         return ret;
 173                 ack >>= 4;
 174                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 175                         return ret;
 176                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 177                         DRM_UDELAY(400);
 178                 else if (ret == 0)
 179                         return -EPROTO;
 180                 else
 181                         return -EIO;
 182         }
 183
 184         return -EIO;
 185 }
 186
 187 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
 188                                  u16 reg, u8 val)
 189 {
 190         radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
 191 }
 192
 193 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
 194                                u16 reg)
 195 {
 196         u8 val = 0;
 197
 198         radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
 199
 200         return val;
 201 }
 202
 203 int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte)
 204 {
 205         struct i2c_algo_dp_aux_data *algo_data = device_get_softc(dev);
 206         struct radeon_i2c_chan *auxch = algo_data->priv;
 207         u16 address = algo_data->address;
 208         u8 msg[5];
 209         u8 reply[2];
 210         unsigned retry;
 211         int msg_bytes;
 212         int reply_bytes = 1;
 213         int ret;
 214         u8 ack;
 215
 216         /* Set up the command byte */
 217         if (mode & MODE_I2C_READ)
 218                 msg[2] = DP_AUX_I2C_READ << 4;
 219         else
 220                 msg[2] = DP_AUX_I2C_WRITE << 4;
 221
 222         if (!(mode & MODE_I2C_STOP))
 223                 msg[2] |= DP_AUX_I2C_MOT << 4;
 224
 225         msg[0] = address;
 226         msg[1] = address >> 8;
 227
 228         switch (mode) {
 229         case MODE_I2C_WRITE:
 230                 msg_bytes = 5;
 231                 msg[3] = msg_bytes << 4;
 232                 msg[4] = write_byte;
 233                 break;
 234         case MODE_I2C_READ:
 235                 msg_bytes = 4;
 236                 msg[3] = msg_bytes << 4;
 237                 break;
 238         default:
 239                 msg_bytes = 4;
 240                 msg[3] = 3 << 4;
 241                 break;
 242         }
 243
 244         for (retry = 0; retry < 4; retry++) {
 245                 ret = radeon_process_aux_ch(auxch,
 246                                             msg, msg_bytes, reply, reply_bytes, 0, &ack);
 247                 if (ret == -EBUSY)
 248                         continue;
 249                 else if (ret < 0) {
 250                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 251                         return ret;
 252                 }
 253
 254                 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
 255                 case DP_AUX_NATIVE_REPLY_ACK:
 256                         /* I2C-over-AUX Reply field is only valid
 257                          * when paired with AUX ACK.
 258                          */
 259                         break;
 260                 case DP_AUX_NATIVE_REPLY_NACK:
 261                         DRM_DEBUG_KMS("aux_ch native nack\n");
 262                         return -EREMOTEIO;
 263                 case DP_AUX_NATIVE_REPLY_DEFER:
 264                         DRM_DEBUG_KMS("aux_ch native defer\n");
 265                         DRM_UDELAY(400);
 266                         continue;
 267                 default:
 268                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
 269                         return -EREMOTEIO;
 270                 }
 271
 272                 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
 273                 case DP_AUX_I2C_REPLY_ACK:
 274                         if (mode == MODE_I2C_READ)
 275                                 *read_byte = reply[0];
 276                         return ret;
 277                 case DP_AUX_I2C_REPLY_NACK:
 278                         DRM_DEBUG_KMS("aux_i2c nack\n");
 279                         return -EREMOTEIO;
 280                 case DP_AUX_I2C_REPLY_DEFER:
 281                         DRM_DEBUG_KMS("aux_i2c defer\n");
 282                         DRM_UDELAY(400);
 283                         break;
 284                 default:
 285                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
 286                         return -EREMOTEIO;
 287                 }
 288         }
 289
 290         DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
 291         return -EREMOTEIO;
 292 }
 293
 294 /***** general DP utility functions *****/
 295
 296 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
 297 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
 298
 299 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 300                                 int lane_count,
 301                                 u8 train_set[4])
 302 {
 303         u8 v = 0;
 304         u8 p = 0;
 305         int lane;
 306
 307         for (lane = 0; lane < lane_count; lane++) {
 308                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 309                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 310
 311                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 312                           lane,
 313                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 314                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 315
 316                 if (this_v > v)
 317                         v = this_v;
 318                 if (this_p > p)
 319                         p = this_p;
 320         }
 321
 322         if (v >= DP_VOLTAGE_MAX)
 323                 v |= DP_TRAIN_MAX_SWING_REACHED;
 324
 325         if (p >= DP_PRE_EMPHASIS_MAX)
 326                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 327
 328         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 329                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 330                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 331
 332         for (lane = 0; lane < 4; lane++)
 333                 train_set[lane] = v | p;
 334 }
 335
 336 /* convert bits per color to bits per pixel */
 337 /* get bpc from the EDID */
 338 static int convert_bpc_to_bpp(int bpc)
 339 {
 340         if (bpc == 0)
 341                 return 24;
 342         else
 343                 return bpc * 3;
 344 }
 345
 346 /* get the max pix clock supported by the link rate and lane num */
 347 static int dp_get_max_dp_pix_clock(int link_rate,
 348                                    int lane_num,
 349                                    int bpp)
 350 {
 351         return (link_rate * lane_num * 8) / bpp;
 352 }
 353
 354 /***** radeon specific DP functions *****/
 355
 356 /* First get the min lane# when low rate is used according to pixel clock
 357  * (prefer low rate), second check max lane# supported by DP panel,
 358  * if the max lane# < low rate lane# then use max lane# instead.
 359  */
 360 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 361                                         u8 dpcd[DP_DPCD_SIZE],
 362                                         int pix_clock)
 363 {
 364         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 365         int max_link_rate = drm_dp_max_link_rate(dpcd);
 366         int max_lane_num = drm_dp_max_lane_count(dpcd);
 367         int lane_num;
 368         int max_dp_pix_clock;
 369
 370         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 371                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 372                 if (pix_clock <= max_dp_pix_clock)
 373                         break;
 374         }
 375
 376         return lane_num;
 377 }
 378
 379 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 380                                        u8 dpcd[DP_DPCD_SIZE],
 381                                        int pix_clock)
 382 {
 383         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 384         int lane_num, max_pix_clock;
 385
 386         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 387             ENCODER_OBJECT_ID_NUTMEG)
 388                 return 270000;
 389
 390         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 391         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 392         if (pix_clock <= max_pix_clock)
 393                 return 162000;
 394         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 395         if (pix_clock <= max_pix_clock)
 396                 return 270000;
 397         if (radeon_connector_is_dp12_capable(connector)) {
 398                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 399                 if (pix_clock <= max_pix_clock)
 400                         return 540000;
 401         }
 402
 403         return drm_dp_max_link_rate(dpcd);
 404 }
 405
 406 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 407                                     int action, int dp_clock,
 408                                     u8 ucconfig, u8 lane_num)
 409 {
 410         DP_ENCODER_SERVICE_PARAMETERS args;
 411         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 412
 413         memset(&args, 0, sizeof(args));
 414         args.ucLinkClock = dp_clock / 10;
 415         args.ucConfig = ucconfig;
 416         args.ucAction = action;
 417         args.ucLaneNum = lane_num;
 418         args.ucStatus = 0;
 419
 420         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 421         return args.ucStatus;
 422 }
 423
 424 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 425 {
 426         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 427         struct drm_device *dev = radeon_connector->base.dev;
 428         struct radeon_device *rdev = dev->dev_private;
 429
 430         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 431                                          dig_connector->dp_i2c_bus->rec.i2c_id, 0);
 432 }
 433
 434 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 435 {
 436         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 437         u8 buf[3];
 438
 439         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 440                 return;
 441
 442         if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
 443                 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n",
 444                               buf[0], buf[1], buf[2]);
 445
 446         if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
 447                 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n",
 448                               buf[0], buf[1], buf[2]);
 449 }
 450
 451 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 452 {
 453         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 454         u8 msg[DP_DPCD_SIZE];
 455         int ret, i;
 456
 457         ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
 458                                         DP_DPCD_SIZE, 0);
 459         if (ret > 0) {
 460                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 461                 DRM_DEBUG_KMS("DPCD: ");
 462                 for (i = 0; i < DP_DPCD_SIZE; i++)
 463                         DRM_DEBUG_KMS("%02x ", msg[i]);
 464                 DRM_DEBUG_KMS("\n");
 465
 466                 radeon_dp_probe_oui(radeon_connector);
 467
 468                 return true;
 469         }
 470         dig_connector->dpcd[0] = 0;
 471         return false;
 472 }
 473
 474 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 475                              struct drm_connector *connector)
 476 {
 477         struct drm_device *dev = encoder->dev;
 478         struct radeon_device *rdev = dev->dev_private;
 479         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 480         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 481         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 482         u8 tmp;
 483
 484         if (!ASIC_IS_DCE4(rdev))
 485                 return panel_mode;
 486
 487         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 488                 /* DP bridge chips */
 489                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
 490                 if (tmp & 1)
 491                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 492                 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 493                          (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 494                         panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 495                 else
 496                         panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 497         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 498                 /* eDP */
 499                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
 500                 if (tmp & 1)
 501                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 502         }
 503
 504         return panel_mode;
 505 }
 506
 507 void radeon_dp_set_link_config(struct drm_connector *connector,
 508                                const struct drm_display_mode *mode)
 509 {
 510         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 511         struct radeon_connector_atom_dig *dig_connector;
 512
 513         if (!radeon_connector->con_priv)
 514                 return;
 515         dig_connector = radeon_connector->con_priv;
 516
 517         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 518             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 519                 dig_connector->dp_clock =
 520                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 521                 dig_connector->dp_lane_count =
 522                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 523         }
 524 }
 525
 526 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 527                                 struct drm_display_mode *mode)
 528 {
 529         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 530         struct radeon_connector_atom_dig *dig_connector;
 531         int dp_clock;
 532
 533         if (!radeon_connector->con_priv)
 534                 return MODE_CLOCK_HIGH;
 535         dig_connector = radeon_connector->con_priv;
 536
 537         dp_clock =
 538                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 539
 540         if ((dp_clock == 540000) &&
 541             (!radeon_connector_is_dp12_capable(connector)))
 542                 return MODE_CLOCK_HIGH;
 543
 544         return MODE_OK;
 545 }
 546
 547 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
 548                                       u8 link_status[DP_LINK_STATUS_SIZE])
 549 {
 550         int ret;
 551         ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
 552                                         link_status, DP_LINK_STATUS_SIZE, 100);
 553         if (ret <= 0) {
 554                 return false;
 555         }
 556
 557         DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
 558         return true;
 559 }
 560
 561 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 562 {
 563         u8 link_status[DP_LINK_STATUS_SIZE];
 564         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 565
 566         if (!radeon_dp_get_link_status(radeon_connector, link_status))
 567                 return false;
 568         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 569                 return false;
 570         return true;
 571 }
 572
 573 struct radeon_dp_link_train_info {
 574         struct radeon_device *rdev;
 575         struct drm_encoder *encoder;
 576         struct drm_connector *connector;
 577         struct radeon_connector *radeon_connector;
 578         int enc_id;
 579         int dp_clock;
 580         int dp_lane_count;
 581         bool tp3_supported;
 582         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 583         u8 train_set[4];
 584         u8 link_status[DP_LINK_STATUS_SIZE];
 585         u8 tries;
 586         bool use_dpencoder;
 587 };
 588
 589 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 590 {
 591         /* set the initial vs/emph on the source */
 592         atombios_dig_transmitter_setup(dp_info->encoder,
 593                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 594                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 595
 596         /* set the vs/emph on the sink */
 597         radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
 598                                    dp_info->train_set, dp_info->dp_lane_count, 0);
 599 }
 600
 601 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 602 {
 603         int rtp = 0;
 604
 605         /* set training pattern on the source */
 606         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 607                 switch (tp) {
 608                 case DP_TRAINING_PATTERN_1:
 609                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 610                         break;
 611                 case DP_TRAINING_PATTERN_2:
 612                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 613                         break;
 614                 case DP_TRAINING_PATTERN_3:
 615                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 616                         break;
 617                 }
 618                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 619         } else {
 620                 switch (tp) {
 621                 case DP_TRAINING_PATTERN_1:
 622                         rtp = 0;
 623                         break;
 624                 case DP_TRAINING_PATTERN_2:
 625                         rtp = 1;
 626                         break;
 627                 }
 628                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 629                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 630         }
 631
 632         /* enable training pattern on the sink */
 633         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
 634 }
 635
 636 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 637 {
 638         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 639         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 640         u8 tmp;
 641
 642         /* power up the sink */
 643         if (dp_info->dpcd[0] >= 0x11)
 644                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 645                                       DP_SET_POWER, DP_SET_POWER_D0);
 646
 647         /* possibly enable downspread on the sink */
 648         if (dp_info->dpcd[3] & 0x1)
 649                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 650                                       DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 651         else
 652                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 653                                       DP_DOWNSPREAD_CTRL, 0);
 654
 655         if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
 656             (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
 657                 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
 658         }
 659
 660         /* set the lane count on the sink */
 661         tmp = dp_info->dp_lane_count;
 662         if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
 663             dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
 664                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 665         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
 666
 667         /* set the link rate on the sink */
 668         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 669         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
 670
 671         /* start training on the source */
 672         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 673                 atombios_dig_encoder_setup(dp_info->encoder,
 674                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 675         else
 676                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 677                                           dp_info->dp_clock, dp_info->enc_id, 0);
 678
 679         /* disable the training pattern on the sink */
 680         radeon_write_dpcd_reg(dp_info->radeon_connector,
 681                               DP_TRAINING_PATTERN_SET,
 682                               DP_TRAINING_PATTERN_DISABLE);
 683
 684         return 0;
 685 }
 686
 687 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 688 {
 689         DRM_UDELAY(400);
 690
 691         /* disable the training pattern on the sink */
 692         radeon_write_dpcd_reg(dp_info->radeon_connector,
 693                               DP_TRAINING_PATTERN_SET,
 694                               DP_TRAINING_PATTERN_DISABLE);
 695
 696         /* disable the training pattern on the source */
 697         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 698                 atombios_dig_encoder_setup(dp_info->encoder,
 699                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 700         else
 701                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 702                                           dp_info->dp_clock, dp_info->enc_id, 0);
 703
 704         return 0;
 705 }
 706
 707 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 708 {
 709         bool clock_recovery;
 710         u8 voltage;
 711         int i;
 712
 713         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 714         memset(dp_info->train_set, 0, 4);
 715         radeon_dp_update_vs_emph(dp_info);
 716
 717         DRM_UDELAY(400);
 718
 719         /* clock recovery loop */
 720         clock_recovery = false;
 721         dp_info->tries = 0;
 722         voltage = 0xff;
 723         while (1) {
 724                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 725
 726                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
 727                         DRM_ERROR("displayport link status failed\n");
 728                         break;
 729                 }
 730
 731                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 732                         clock_recovery = true;
 733                         break;
 734                 }
 735
 736                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 737                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 738                                 break;
 739                 }
 740                 if (i == dp_info->dp_lane_count) {
 741                         DRM_ERROR("clock recovery reached max voltage\n");
 742                         break;
 743                 }
 744
 745                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 746                         ++dp_info->tries;
 747                         if (dp_info->tries == 5) {
 748                                 DRM_ERROR("clock recovery tried 5 times\n");
 749                                 break;
 750                         }
 751                 } else
 752                         dp_info->tries = 0;
 753
 754                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 755
 756                 /* Compute new train_set as requested by sink */
 757                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 758
 759                 radeon_dp_update_vs_emph(dp_info);
 760         }
 761         if (!clock_recovery) {
 762                 DRM_ERROR("clock recovery failed\n");
 763                 return -1;
 764         } else {
 765                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 766                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 767                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 768                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 769                 return 0;
 770         }
 771 }
 772
 773 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 774 {
 775         bool channel_eq;
 776
 777         if (dp_info->tp3_supported)
 778                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 779         else
 780                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 781
 782         /* channel equalization loop */
 783         dp_info->tries = 0;
 784         channel_eq = false;
 785         while (1) {
 786                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 787
 788                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
 789                         DRM_ERROR("displayport link status failed\n");
 790                         break;
 791                 }
 792
 793                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 794                         channel_eq = true;
 795                         break;
 796                 }
 797
 798                 /* Try 5 times */
 799                 if (dp_info->tries > 5) {
 800                         DRM_ERROR("channel eq failed: 5 tries\n");
 801                         break;
 802                 }
 803
 804                 /* Compute new train_set as requested by sink */
 805                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 806
 807                 radeon_dp_update_vs_emph(dp_info);
 808                 dp_info->tries++;
 809         }
 810
 811         if (!channel_eq) {
 812                 DRM_ERROR("channel eq failed\n");
 813                 return -1;
 814         } else {
 815                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 816                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 817                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 818                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 819                 return 0;
 820         }
 821 }
 822
 823 void radeon_dp_link_train(struct drm_encoder *encoder,
 824                           struct drm_connector *connector)
 825 {
 826         struct drm_device *dev = encoder->dev;
 827         struct radeon_device *rdev = dev->dev_private;
 828         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 829         struct radeon_encoder_atom_dig *dig;
 830         struct radeon_connector *radeon_connector;
 831         struct radeon_connector_atom_dig *dig_connector;
 832         struct radeon_dp_link_train_info dp_info;
 833         int index;
 834         u8 tmp, frev, crev;
 835
 836         if (!radeon_encoder->enc_priv)
 837                 return;
 838         dig = radeon_encoder->enc_priv;
 839
 840         radeon_connector = to_radeon_connector(connector);
 841         if (!radeon_connector->con_priv)
 842                 return;
 843         dig_connector = radeon_connector->con_priv;
 844
 845         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 846             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 847                 return;
 848
 849         /* DPEncoderService newer than 1.1 can't program properly the
 850          * training pattern. When facing such version use the
 851          * DIGXEncoderControl (X== 1 | 2)
 852          */
 853         dp_info.use_dpencoder = true;
 854         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 855         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 856                 if (crev > 1) {
 857                         dp_info.use_dpencoder = false;
 858                 }
 859         }
 860
 861         dp_info.enc_id = 0;
 862         if (dig->dig_encoder)
 863                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 864         else
 865                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 866         if (dig->linkb)
 867                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 868         else
 869                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 870
 871         tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
 872         if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 873                 dp_info.tp3_supported = true;
 874         else
 875                 dp_info.tp3_supported = false;
 876
 877         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 878         dp_info.rdev = rdev;
 879         dp_info.encoder = encoder;
 880         dp_info.connector = connector;
 881         dp_info.radeon_connector = radeon_connector;
 882         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 883         dp_info.dp_clock = dig_connector->dp_clock;
 884
 885         if (radeon_dp_link_train_init(&dp_info))
 886                 goto done;
 887         if (radeon_dp_link_train_cr(&dp_info))
 888                 goto done;
 889         if (radeon_dp_link_train_ce(&dp_info))
 890                 goto done;
 891 done:
 892         if (radeon_dp_link_train_finish(&dp_info))
 893                 return;
 894 }