2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
31 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_fence.c 254885 2013-08-25 19:37:15Z dumbbell $
35 #include "radeon_reg.h"
38 #include "radeon_trace.h"
39 #endif /* DUMBBELL_WIP */
43 * Fences mark an event in the GPUs pipeline and are used
44 * for GPU/CPU synchronization. When the fence is written,
45 * it is expected that all buffers associated with that fence
46 * are no longer in use by the associated ring on the GPU and
47 * that the the relevant GPU caches have been flushed. Whether
48 * we use a scratch register or memory location depends on the asic
49 * and whether writeback is enabled.
53 * radeon_fence_write - write a fence value
55 * @rdev: radeon_device pointer
56 * @seq: sequence number to write
57 * @ring: ring index the fence is associated with
59 * Writes a fence value to memory or a scratch register (all asics).
61 static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
63 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
64 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
66 *drv->cpu_addr = cpu_to_le32(seq);
69 WREG32(drv->scratch_reg, seq);
74 * radeon_fence_read - read a fence value
76 * @rdev: radeon_device pointer
77 * @ring: ring index the fence is associated with
79 * Reads a fence value from memory or a scratch register (all asics).
80 * Returns the value of the fence read from memory or register.
82 static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
84 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
87 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
89 seq = le32_to_cpu(*drv->cpu_addr);
91 seq = lower_32_bits(atomic64_read(&drv->last_seq));
94 seq = RREG32(drv->scratch_reg);
100 * radeon_fence_emit - emit a fence on the requested ring
102 * @rdev: radeon_device pointer
103 * @fence: radeon fence object
104 * @ring: ring index the fence is associated with
106 * Emits a fence command on the requested ring (all asics).
107 * Returns 0 on success, -ENOMEM on failure.
109 int radeon_fence_emit(struct radeon_device *rdev,
110 struct radeon_fence **fence,
113 /* we are protected by the ring emission mutex */
114 *fence = kmalloc(sizeof(struct radeon_fence), M_DRM,
116 if ((*fence) == NULL) {
119 refcount_init(&((*fence)->kref), 1);
120 (*fence)->rdev = rdev;
121 (*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring];
122 (*fence)->ring = ring;
123 radeon_fence_ring_emit(rdev, ring, *fence);
128 * radeon_fence_process - process a fence
130 * @rdev: radeon_device pointer
131 * @ring: ring index the fence is associated with
133 * Checks the current fence value and wakes the fence queue
134 * if the sequence number has increased (all asics).
136 void radeon_fence_process(struct radeon_device *rdev, int ring)
138 uint64_t seq, last_seq, last_emitted;
139 unsigned count_loop = 0;
142 /* Note there is a scenario here for an infinite loop but it's
143 * very unlikely to happen. For it to happen, the current polling
144 * process need to be interrupted by another process and another
145 * process needs to update the last_seq btw the atomic read and
146 * xchg of the current process.
148 * More over for this to go in infinite loop there need to be
149 * continuously new fence signaled ie radeon_fence_read needs
150 * to return a different value each time for both the currently
151 * polling process and the other process that xchg the last_seq
152 * btw atomic read and xchg of the current process. And the
153 * value the other process set as last seq must be higher than
154 * the seq value we just read. Which means that current process
155 * need to be interrupted after radeon_fence_read and before
158 * To be even more safe we count the number of time we loop and
159 * we bail after 10 loop just accepting the fact that we might
160 * have temporarly set the last_seq not to the true real last
161 * seq but to an older one.
163 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
165 last_emitted = rdev->fence_drv[ring].sync_seq[ring];
166 seq = radeon_fence_read(rdev, ring);
167 seq |= last_seq & 0xffffffff00000000LL;
168 if (seq < last_seq) {
170 seq |= last_emitted & 0xffffffff00000000LL;
173 if (seq <= last_seq || seq > last_emitted) {
176 /* If we loop over we don't want to return without
177 * checking if a fence is signaled as it means that the
178 * seq we just read is different from the previous on.
182 if ((count_loop++) > 10) {
183 /* We looped over too many time leave with the
184 * fact that we might have set an older fence
185 * seq then the current real last seq as signaled
190 } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
193 rdev->fence_drv[ring].last_activity = jiffies;
194 wake_up_all(&rdev->fence_queue);
199 * radeon_fence_destroy - destroy a fence
203 * Frees the fence object (all asics).
205 static void radeon_fence_destroy(struct radeon_fence *fence)
208 drm_free(fence, M_DRM);
212 * radeon_fence_seq_signaled - check if a fence sequeuce number has signaled
214 * @rdev: radeon device pointer
215 * @seq: sequence number
216 * @ring: ring index the fence is associated with
218 * Check if the last singled fence sequnce number is >= the requested
219 * sequence number (all asics).
220 * Returns true if the fence has signaled (current fence value
221 * is >= requested value) or false if it has not (current fence
222 * value is < the requested value. Helper function for
223 * radeon_fence_signaled().
225 static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
226 u64 seq, unsigned ring)
228 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
231 /* poll new last sequence at least once */
232 radeon_fence_process(rdev, ring);
233 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
240 * radeon_fence_signaled - check if a fence has signaled
242 * @fence: radeon fence object
244 * Check if the requested fence has signaled (all asics).
245 * Returns true if the fence has signaled or false if it has not.
247 bool radeon_fence_signaled(struct radeon_fence *fence)
252 if (fence->seq == RADEON_FENCE_SIGNALED_SEQ) {
255 if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
256 fence->seq = RADEON_FENCE_SIGNALED_SEQ;
263 * radeon_fence_wait_seq - wait for a specific sequence number
265 * @rdev: radeon device pointer
266 * @target_seq: sequence number we want to wait for
267 * @ring: ring index the fence is associated with
268 * @intr: use interruptable sleep
269 * @lock_ring: whether the ring should be locked or not
271 * Wait for the requested sequence number to be written (all asics).
272 * @intr selects whether to use interruptable (true) or non-interruptable
273 * (false) sleep when waiting for the sequence number. Helper function
274 * for radeon_fence_wait(), et al.
275 * Returns 0 if the sequence number has passed, error for all other cases.
276 * -EDEADLK is returned when a GPU lockup has been detected and the ring is
277 * marked as not ready so no further jobs get scheduled until a successful
280 static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 target_seq,
281 unsigned ring, bool intr, bool lock_ring)
283 unsigned long timeout, last_activity;
289 while (target_seq > atomic64_read(&rdev->fence_drv[ring].last_seq)) {
290 if (!rdev->ring[ring].ready) {
294 timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
295 if (time_after(rdev->fence_drv[ring].last_activity, timeout)) {
296 /* the normal case, timeout is somewhere before last_activity */
297 timeout = rdev->fence_drv[ring].last_activity - timeout;
299 /* either jiffies wrapped around, or no fence was signaled in the last 500ms
300 * anyway we will just wait for the minimum amount and then check for a lockup
304 seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
305 /* Save current last activity valuee, used to check for GPU lockups */
306 last_activity = rdev->fence_drv[ring].last_activity;
308 radeon_irq_kms_sw_irq_get(rdev, ring);
310 r = wait_event_interruptible_timeout(rdev->fence_queue,
311 (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
314 r = wait_event_timeout(rdev->fence_queue,
315 (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
318 radeon_irq_kms_sw_irq_put(rdev, ring);
319 if (unlikely(r < 0)) {
323 if (unlikely(!signaled)) {
324 /* we were interrupted for some reason and fence
325 * isn't signaled yet, resume waiting */
330 /* check if sequence value has changed since last_activity */
331 if (seq != atomic64_read(&rdev->fence_drv[ring].last_seq)) {
336 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
339 /* test if somebody else has already decided that this is a lockup */
340 if (last_activity != rdev->fence_drv[ring].last_activity) {
342 lockmgr(&rdev->ring_lock, LK_RELEASE);
347 if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
348 /* good news we believe it's a lockup */
349 dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016jx last fence id 0x%016jx)\n",
352 /* change last activity so nobody else think there is a lockup */
353 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
354 rdev->fence_drv[i].last_activity = jiffies;
357 /* mark the ring as not ready any more */
358 rdev->ring[ring].ready = false;
360 lockmgr(&rdev->ring_lock, LK_RELEASE);
366 lockmgr(&rdev->ring_lock, LK_RELEASE);
374 * radeon_fence_wait - wait for a fence to signal
376 * @fence: radeon fence object
377 * @intr: use interruptable sleep
379 * Wait for the requested fence to signal (all asics).
380 * @intr selects whether to use interruptable (true) or non-interruptable
381 * (false) sleep when waiting for the fence.
382 * Returns 0 if the fence has passed, error for all other cases.
384 int radeon_fence_wait(struct radeon_fence *fence, bool intr)
389 DRM_ERROR("Querying an invalid fence : %p !\n", fence);
393 r = radeon_fence_wait_seq(fence->rdev, fence->seq,
394 fence->ring, intr, true);
398 fence->seq = RADEON_FENCE_SIGNALED_SEQ;
402 static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
406 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
407 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i)) {
415 * radeon_fence_wait_any_seq - wait for a sequence number on any ring
417 * @rdev: radeon device pointer
418 * @target_seq: sequence number(s) we want to wait for
419 * @intr: use interruptable sleep
421 * Wait for the requested sequence number(s) to be written by any ring
422 * (all asics). Sequnce number array is indexed by ring id.
423 * @intr selects whether to use interruptable (true) or non-interruptable
424 * (false) sleep when waiting for the sequence number. Helper function
425 * for radeon_fence_wait_any(), et al.
426 * Returns 0 if the sequence number has passed, error for all other cases.
428 static int radeon_fence_wait_any_seq(struct radeon_device *rdev,
429 u64 *target_seq, bool intr)
431 unsigned long timeout, last_activity, tmp;
432 unsigned i, ring = RADEON_NUM_RINGS;
436 for (i = 0, last_activity = 0; i < RADEON_NUM_RINGS; ++i) {
437 if (!target_seq[i]) {
441 /* use the most recent one as indicator */
442 if (time_after(rdev->fence_drv[i].last_activity, last_activity)) {
443 last_activity = rdev->fence_drv[i].last_activity;
446 /* For lockup detection just pick the lowest ring we are
447 * actively waiting for
454 /* nothing to wait for ? */
455 if (ring == RADEON_NUM_RINGS) {
459 while (!radeon_fence_any_seq_signaled(rdev, target_seq)) {
460 timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
461 if (time_after(last_activity, timeout)) {
462 /* the normal case, timeout is somewhere before last_activity */
463 timeout = last_activity - timeout;
465 /* either jiffies wrapped around, or no fence was signaled in the last 500ms
466 * anyway we will just wait for the minimum amount and then check for a lockup
471 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
473 radeon_irq_kms_sw_irq_get(rdev, i);
477 r = wait_event_interruptible_timeout(rdev->fence_queue,
478 (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
481 r = wait_event_timeout(rdev->fence_queue,
482 (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
485 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
487 radeon_irq_kms_sw_irq_put(rdev, i);
490 if (unlikely(r < 0)) {
494 if (unlikely(!signaled)) {
495 /* we were interrupted for some reason and fence
496 * isn't signaled yet, resume waiting */
501 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
502 for (i = 0, tmp = 0; i < RADEON_NUM_RINGS; ++i) {
503 if (time_after(rdev->fence_drv[i].last_activity, tmp)) {
504 tmp = rdev->fence_drv[i].last_activity;
507 /* test if somebody else has already decided that this is a lockup */
508 if (last_activity != tmp) {
510 lockmgr(&rdev->ring_lock, LK_RELEASE);
514 if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
515 /* good news we believe it's a lockup */
516 dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016jx)\n",
519 /* change last activity so nobody else think there is a lockup */
520 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
521 rdev->fence_drv[i].last_activity = jiffies;
524 /* mark the ring as not ready any more */
525 rdev->ring[ring].ready = false;
526 lockmgr(&rdev->ring_lock, LK_RELEASE);
529 lockmgr(&rdev->ring_lock, LK_RELEASE);
536 * radeon_fence_wait_any - wait for a fence to signal on any ring
538 * @rdev: radeon device pointer
539 * @fences: radeon fence object(s)
540 * @intr: use interruptable sleep
542 * Wait for any requested fence to signal (all asics). Fence
543 * array is indexed by ring id. @intr selects whether to use
544 * interruptable (true) or non-interruptable (false) sleep when
545 * waiting for the fences. Used by the suballocator.
546 * Returns 0 if any fence has passed, error for all other cases.
548 int radeon_fence_wait_any(struct radeon_device *rdev,
549 struct radeon_fence **fences,
552 uint64_t seq[RADEON_NUM_RINGS];
556 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
563 if (fences[i]->seq == RADEON_FENCE_SIGNALED_SEQ) {
564 /* something was allready signaled */
568 seq[i] = fences[i]->seq;
571 r = radeon_fence_wait_any_seq(rdev, seq, intr);
579 * radeon_fence_wait_next_locked - wait for the next fence to signal
581 * @rdev: radeon device pointer
582 * @ring: ring index the fence is associated with
584 * Wait for the next fence on the requested ring to signal (all asics).
585 * Returns 0 if the next fence has passed, error for all other cases.
586 * Caller must hold ring lock.
588 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring)
592 seq = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
593 if (seq >= rdev->fence_drv[ring].sync_seq[ring]) {
594 /* nothing to wait for, last_seq is
595 already the last emited fence */
598 return radeon_fence_wait_seq(rdev, seq, ring, false, false);
602 * radeon_fence_wait_empty_locked - wait for all fences to signal
604 * @rdev: radeon device pointer
605 * @ring: ring index the fence is associated with
607 * Wait for all fences on the requested ring to signal (all asics).
608 * Returns 0 if the fences have passed, error for all other cases.
609 * Caller must hold ring lock.
611 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
613 uint64_t seq = rdev->fence_drv[ring].sync_seq[ring];
616 r = radeon_fence_wait_seq(rdev, seq, ring, false, false);
621 dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%d)\n",
628 * radeon_fence_ref - take a ref on a fence
630 * @fence: radeon fence object
632 * Take a reference on a fence (all asics).
635 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
637 refcount_acquire(&fence->kref);
642 * radeon_fence_unref - remove a ref on a fence
644 * @fence: radeon fence object
646 * Remove a reference on a fence (all asics).
648 void radeon_fence_unref(struct radeon_fence **fence)
650 struct radeon_fence *tmp = *fence;
654 if (refcount_release(&tmp->kref)) {
655 radeon_fence_destroy(tmp);
661 * radeon_fence_count_emitted - get the count of emitted fences
663 * @rdev: radeon device pointer
664 * @ring: ring index the fence is associated with
666 * Get the number of fences emitted on the requested ring (all asics).
667 * Returns the number of emitted fences on the ring. Used by the
668 * dynpm code to ring track activity.
670 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
674 /* We are not protected by ring lock when reading the last sequence
675 * but it's ok to report slightly wrong fence count here.
677 radeon_fence_process(rdev, ring);
678 emitted = rdev->fence_drv[ring].sync_seq[ring]
679 - atomic64_read(&rdev->fence_drv[ring].last_seq);
680 /* to avoid 32bits warp around */
681 if (emitted > 0x10000000) {
682 emitted = 0x10000000;
684 return (unsigned)emitted;
688 * radeon_fence_need_sync - do we need a semaphore
690 * @fence: radeon fence object
691 * @dst_ring: which ring to check against
693 * Check if the fence needs to be synced against another ring
694 * (all asics). If so, we need to emit a semaphore.
695 * Returns true if we need to sync with another ring, false if
698 bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
700 struct radeon_fence_driver *fdrv;
706 if (fence->ring == dst_ring) {
710 /* we are protected by the ring mutex */
711 fdrv = &fence->rdev->fence_drv[dst_ring];
712 if (fence->seq <= fdrv->sync_seq[fence->ring]) {
720 * radeon_fence_note_sync - record the sync point
722 * @fence: radeon fence object
723 * @dst_ring: which ring to check against
725 * Note the sequence number at which point the fence will
726 * be synced with the requested ring (all asics).
728 void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
730 struct radeon_fence_driver *dst, *src;
737 if (fence->ring == dst_ring) {
741 /* we are protected by the ring mutex */
742 src = &fence->rdev->fence_drv[fence->ring];
743 dst = &fence->rdev->fence_drv[dst_ring];
744 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
748 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
753 * radeon_fence_driver_start_ring - make the fence driver
754 * ready for use on the requested ring.
756 * @rdev: radeon device pointer
757 * @ring: ring index to start the fence driver on
759 * Make the fence driver ready for processing (all asics).
760 * Not all asics have all rings, so each asic will only
761 * start the fence driver on the rings it has.
762 * Returns 0 for success, errors for failure.
764 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
769 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
770 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
771 rdev->fence_drv[ring].scratch_reg = 0;
772 if (ring != R600_RING_TYPE_UVD_INDEX) {
773 index = R600_WB_EVENT_OFFSET + ring * 4;
774 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
775 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
779 /* put fence directly behind firmware */
780 index = ALIGN(rdev->uvd_fw->datasize, 8);
781 rdev->fence_drv[ring].cpu_addr = (void*)((uint8_t*)rdev->uvd.cpu_addr + index);
782 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
786 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
788 dev_err(rdev->dev, "fence failed to get scratch register\n");
791 index = RADEON_WB_SCRATCH_OFFSET +
792 rdev->fence_drv[ring].scratch_reg -
793 rdev->scratch.reg_base;
794 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
795 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
797 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
798 rdev->fence_drv[ring].initialized = true;
799 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016jx and cpu addr 0x%p\n",
800 ring, (uintmax_t)rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
805 * radeon_fence_driver_init_ring - init the fence driver
806 * for the requested ring.
808 * @rdev: radeon device pointer
809 * @ring: ring index to start the fence driver on
811 * Init the fence driver for the requested ring (all asics).
812 * Helper function for radeon_fence_driver_init().
814 static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
818 rdev->fence_drv[ring].scratch_reg = -1;
819 rdev->fence_drv[ring].cpu_addr = NULL;
820 rdev->fence_drv[ring].gpu_addr = 0;
821 for (i = 0; i < RADEON_NUM_RINGS; ++i)
822 rdev->fence_drv[ring].sync_seq[i] = 0;
823 atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
824 rdev->fence_drv[ring].last_activity = jiffies;
825 rdev->fence_drv[ring].initialized = false;
829 * radeon_fence_driver_init - init the fence driver
830 * for all possible rings.
832 * @rdev: radeon device pointer
834 * Init the fence driver for all possible rings (all asics).
835 * Not all asics have all rings, so each asic will only
836 * start the fence driver on the rings it has using
837 * radeon_fence_driver_start_ring().
838 * Returns 0 for success.
840 int radeon_fence_driver_init(struct radeon_device *rdev)
844 init_waitqueue_head(&rdev->fence_queue);
845 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
846 radeon_fence_driver_init_ring(rdev, ring);
848 if (radeon_debugfs_fence_init(rdev)) {
849 dev_err(rdev->dev, "fence debugfs file creation failed\n");
855 * radeon_fence_driver_fini - tear down the fence driver
856 * for all possible rings.
858 * @rdev: radeon device pointer
860 * Tear down the fence driver for all possible rings (all asics).
862 void radeon_fence_driver_fini(struct radeon_device *rdev)
866 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
867 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
868 if (!rdev->fence_drv[ring].initialized)
870 r = radeon_fence_wait_empty_locked(rdev, ring);
872 /* no need to trigger GPU reset as we are unloading */
873 radeon_fence_driver_force_completion(rdev);
875 wake_up_all(&rdev->fence_queue);
876 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
877 rdev->fence_drv[ring].initialized = false;
879 lockmgr(&rdev->ring_lock, LK_RELEASE);
883 * radeon_fence_driver_force_completion - force all fence waiter to complete
885 * @rdev: radeon device pointer
887 * In case of GPU reset failure make sure no process keep waiting on fence
888 * that will never complete.
890 void radeon_fence_driver_force_completion(struct radeon_device *rdev)
894 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
895 if (!rdev->fence_drv[ring].initialized)
897 radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
905 #if defined(CONFIG_DEBUG_FS)
906 static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
908 struct drm_info_node *node = (struct drm_info_node *)m->private;
909 struct drm_device *dev = node->minor->dev;
910 struct radeon_device *rdev = dev->dev_private;
913 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
914 if (!rdev->fence_drv[i].initialized)
917 seq_printf(m, "--- ring %d ---\n", i);
918 seq_printf(m, "Last signaled fence 0x%016llx\n",
919 (unsigned long long)atomic_load_acq_64(&rdev->fence_drv[i].last_seq));
920 seq_printf(m, "Last emitted 0x%016llx\n",
921 rdev->fence_drv[i].sync_seq[i]);
923 for (j = 0; j < RADEON_NUM_RINGS; ++j) {
924 if (i != j && rdev->fence_drv[j].initialized)
925 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
926 j, rdev->fence_drv[i].sync_seq[j]);
932 static struct drm_info_list radeon_debugfs_fence_list[] = {
933 {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
937 int radeon_debugfs_fence_init(struct radeon_device *rdev)
939 #if defined(CONFIG_DEBUG_FS)
940 return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);