2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
70 * MSI-X MUST NOT be enabled on 82574:
71 * <<82574 specification update>> errata #15
74 #include "opt_ifpoll.h"
78 #include <sys/param.h>
80 #include <sys/endian.h>
81 #include <sys/interrupt.h>
82 #include <sys/kernel.h>
84 #include <sys/malloc.h>
88 #include <sys/serialize.h>
89 #include <sys/serialize2.h>
90 #include <sys/socket.h>
91 #include <sys/sockio.h>
92 #include <sys/sysctl.h>
93 #include <sys/systm.h>
96 #include <net/ethernet.h>
98 #include <net/if_arp.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/ifq_var.h>
102 #include <net/toeplitz.h>
103 #include <net/toeplitz2.h>
104 #include <net/vlan/if_vlan_var.h>
105 #include <net/vlan/if_vlan_ether.h>
106 #include <net/if_poll.h>
108 #include <netinet/in_systm.h>
109 #include <netinet/in.h>
110 #include <netinet/ip.h>
111 #include <netinet/tcp.h>
112 #include <netinet/udp.h>
114 #include <bus/pci/pcivar.h>
115 #include <bus/pci/pcireg.h>
117 #include <dev/netif/ig_hal/e1000_api.h>
118 #include <dev/netif/ig_hal/e1000_82571.h>
119 #include <dev/netif/emx/if_emx.h>
122 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
124 if (sc->rss_debug >= lvl) \
125 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
127 #else /* !EMX_RSS_DEBUG */
128 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
129 #endif /* EMX_RSS_DEBUG */
131 #define EMX_TX_SERIALIZE 1
132 #define EMX_RX_SERIALIZE 2
134 #define EMX_NAME "Intel(R) PRO/1000 "
136 #define EMX_DEVICE(id) \
137 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
138 #define EMX_DEVICE_NULL { 0, 0, NULL }
140 static const struct emx_device {
145 EMX_DEVICE(82571EB_COPPER),
146 EMX_DEVICE(82571EB_FIBER),
147 EMX_DEVICE(82571EB_SERDES),
148 EMX_DEVICE(82571EB_SERDES_DUAL),
149 EMX_DEVICE(82571EB_SERDES_QUAD),
150 EMX_DEVICE(82571EB_QUAD_COPPER),
151 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
152 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
153 EMX_DEVICE(82571EB_QUAD_FIBER),
154 EMX_DEVICE(82571PT_QUAD_COPPER),
156 EMX_DEVICE(82572EI_COPPER),
157 EMX_DEVICE(82572EI_FIBER),
158 EMX_DEVICE(82572EI_SERDES),
162 EMX_DEVICE(82573E_IAMT),
165 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
166 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
167 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
168 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
173 /* required last entry */
177 static int emx_probe(device_t);
178 static int emx_attach(device_t);
179 static int emx_detach(device_t);
180 static int emx_shutdown(device_t);
181 static int emx_suspend(device_t);
182 static int emx_resume(device_t);
184 static void emx_init(void *);
185 static void emx_stop(struct emx_softc *);
186 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
187 static void emx_start(struct ifnet *);
189 static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
191 static void emx_watchdog(struct ifnet *);
192 static void emx_media_status(struct ifnet *, struct ifmediareq *);
193 static int emx_media_change(struct ifnet *);
194 static void emx_timer(void *);
195 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
196 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
197 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
199 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
203 static void emx_intr(void *);
204 static void emx_rxeof(struct emx_softc *, int, int);
205 static void emx_txeof(struct emx_softc *);
206 static void emx_tx_collect(struct emx_softc *);
207 static void emx_tx_purge(struct emx_softc *);
208 static void emx_enable_intr(struct emx_softc *);
209 static void emx_disable_intr(struct emx_softc *);
211 static int emx_dma_alloc(struct emx_softc *);
212 static void emx_dma_free(struct emx_softc *);
213 static void emx_init_tx_ring(struct emx_softc *);
214 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
215 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
216 static int emx_create_tx_ring(struct emx_softc *);
217 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
218 static void emx_destroy_tx_ring(struct emx_softc *, int);
219 static void emx_destroy_rx_ring(struct emx_softc *,
220 struct emx_rxdata *, int);
221 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
222 static int emx_encap(struct emx_softc *, struct mbuf **);
223 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
224 static int emx_txcsum(struct emx_softc *, struct mbuf *,
225 uint32_t *, uint32_t *);
227 static int emx_is_valid_eaddr(const uint8_t *);
228 static int emx_reset(struct emx_softc *);
229 static void emx_setup_ifp(struct emx_softc *);
230 static void emx_init_tx_unit(struct emx_softc *);
231 static void emx_init_rx_unit(struct emx_softc *);
232 static void emx_update_stats(struct emx_softc *);
233 static void emx_set_promisc(struct emx_softc *);
234 static void emx_disable_promisc(struct emx_softc *);
235 static void emx_set_multi(struct emx_softc *);
236 static void emx_update_link_status(struct emx_softc *);
237 static void emx_smartspeed(struct emx_softc *);
238 static void emx_set_itr(struct emx_softc *, uint32_t);
239 static void emx_disable_aspm(struct emx_softc *);
241 static void emx_print_debug_info(struct emx_softc *);
242 static void emx_print_nvm_info(struct emx_softc *);
243 static void emx_print_hw_stats(struct emx_softc *);
245 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
246 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
247 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
248 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
249 static void emx_add_sysctl(struct emx_softc *);
251 static void emx_serialize_skipmain(struct emx_softc *);
252 static void emx_deserialize_skipmain(struct emx_softc *);
254 /* Management and WOL Support */
255 static void emx_get_mgmt(struct emx_softc *);
256 static void emx_rel_mgmt(struct emx_softc *);
257 static void emx_get_hw_control(struct emx_softc *);
258 static void emx_rel_hw_control(struct emx_softc *);
259 static void emx_enable_wol(device_t);
261 static device_method_t emx_methods[] = {
262 /* Device interface */
263 DEVMETHOD(device_probe, emx_probe),
264 DEVMETHOD(device_attach, emx_attach),
265 DEVMETHOD(device_detach, emx_detach),
266 DEVMETHOD(device_shutdown, emx_shutdown),
267 DEVMETHOD(device_suspend, emx_suspend),
268 DEVMETHOD(device_resume, emx_resume),
272 static driver_t emx_driver = {
275 sizeof(struct emx_softc),
278 static devclass_t emx_devclass;
280 DECLARE_DUMMY_MODULE(if_emx);
281 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
282 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
287 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
288 static int emx_rxd = EMX_DEFAULT_RXD;
289 static int emx_txd = EMX_DEFAULT_TXD;
290 static int emx_smart_pwr_down = 0;
291 static int emx_rxr = 0;
293 /* Controls whether promiscuous also shows bad packets */
294 static int emx_debug_sbp = 0;
296 static int emx_82573_workaround = 1;
297 static int emx_msi_enable = 1;
299 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
300 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
301 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
302 TUNABLE_INT("hw.emx.txd", &emx_txd);
303 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
304 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
305 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
306 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
308 /* Global used in WOL setup with multiport cards */
309 static int emx_global_quad_port_a = 0;
311 /* Set this to one to display debug statistics */
312 static int emx_display_debug_stats = 0;
314 #if !defined(KTR_IF_EMX)
315 #define KTR_IF_EMX KTR_ALL
317 KTR_INFO_MASTER(if_emx);
318 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
319 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
320 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
321 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
322 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
323 #define logif(name) KTR_LOG(if_emx_ ## name)
326 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
328 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
329 /* DD bit must be cleared */
330 rxd->rxd_staterr = 0;
334 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
336 /* Ignore Checksum bit is set */
337 if (staterr & E1000_RXD_STAT_IXSM)
340 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
342 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
344 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
345 E1000_RXD_STAT_TCPCS) {
346 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
348 CSUM_FRAG_NOT_CHECKED;
349 mp->m_pkthdr.csum_data = htons(0xffff);
353 static __inline struct pktinfo *
354 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
355 uint32_t mrq, uint32_t hash, uint32_t staterr)
357 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
358 case EMX_RXDMRQ_IPV4_TCP:
359 pi->pi_netisr = NETISR_IP;
361 pi->pi_l3proto = IPPROTO_TCP;
364 case EMX_RXDMRQ_IPV6_TCP:
365 pi->pi_netisr = NETISR_IPV6;
367 pi->pi_l3proto = IPPROTO_TCP;
370 case EMX_RXDMRQ_IPV4:
371 if (staterr & E1000_RXD_STAT_IXSM)
375 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
376 E1000_RXD_STAT_TCPCS) {
377 pi->pi_netisr = NETISR_IP;
379 pi->pi_l3proto = IPPROTO_UDP;
387 m->m_flags |= M_HASH;
388 m->m_pkthdr.hash = toeplitz_hash(hash);
393 emx_probe(device_t dev)
395 const struct emx_device *d;
398 vid = pci_get_vendor(dev);
399 did = pci_get_device(dev);
401 for (d = emx_devices; d->desc != NULL; ++d) {
402 if (vid == d->vid && did == d->did) {
403 device_set_desc(dev, d->desc);
404 device_set_async_attach(dev, TRUE);
412 emx_attach(device_t dev)
414 struct emx_softc *sc = device_get_softc(dev);
415 struct ifnet *ifp = &sc->arpcom.ac_if;
416 int error = 0, i, throttle, msi_enable;
418 uint16_t eeprom_data, device_id, apme_mask;
420 lwkt_serialize_init(&sc->main_serialize);
421 lwkt_serialize_init(&sc->tx_serialize);
422 for (i = 0; i < EMX_NRX_RING; ++i)
423 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
426 sc->serializes[i++] = &sc->main_serialize;
427 sc->serializes[i++] = &sc->tx_serialize;
428 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
429 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
430 KKASSERT(i == EMX_NSERIALIZE);
432 callout_init_mp(&sc->timer);
434 sc->dev = sc->osdep.dev = dev;
437 * Determine hardware and mac type
439 sc->hw.vendor_id = pci_get_vendor(dev);
440 sc->hw.device_id = pci_get_device(dev);
441 sc->hw.revision_id = pci_get_revid(dev);
442 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
443 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
445 if (e1000_set_mac_type(&sc->hw))
448 /* Enable bus mastering */
449 pci_enable_busmaster(dev);
454 sc->memory_rid = EMX_BAR_MEM;
455 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
456 &sc->memory_rid, RF_ACTIVE);
457 if (sc->memory == NULL) {
458 device_printf(dev, "Unable to allocate bus resource: memory\n");
462 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
463 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
465 /* XXX This is quite goofy, it is not actually used */
466 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
469 * Don't enable MSI on 82571/82572, see:
470 * 82571EB/82572EI specification update
472 msi_enable = emx_msi_enable;
474 (sc->hw.mac.type == e1000_82571 ||
475 sc->hw.mac.type == e1000_82572))
481 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
482 &sc->intr_rid, &intr_flags);
484 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
486 if (sc->intr_res == NULL) {
487 device_printf(dev, "Unable to allocate bus resource: "
493 /* Save PCI command register for Shared Code */
494 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
495 sc->hw.back = &sc->osdep;
497 /* Do Shared Code initialization */
498 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
499 device_printf(dev, "Setup of Shared code failed\n");
503 e1000_get_bus_info(&sc->hw);
505 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
506 sc->hw.phy.autoneg_wait_to_complete = FALSE;
507 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
510 * Interrupt throttle rate
512 throttle = device_getenv_int(dev, "int_throttle_ceil",
513 emx_int_throttle_ceil);
515 sc->int_throttle_ceil = 0;
518 throttle = EMX_DEFAULT_ITR;
520 /* Recalculate the tunable value to get the exact frequency. */
521 throttle = 1000000000 / 256 / throttle;
523 /* Upper 16bits of ITR is reserved and should be zero */
524 if (throttle & 0xffff0000)
525 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
527 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
530 e1000_init_script_state_82541(&sc->hw, TRUE);
531 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
534 if (sc->hw.phy.media_type == e1000_media_type_copper) {
535 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
536 sc->hw.phy.disable_polarity_correction = FALSE;
537 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
540 /* Set the frame limits assuming standard ethernet sized frames. */
541 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
542 sc->min_frame_size = ETHER_MIN_LEN;
544 /* This controls when hardware reports transmit completion status. */
545 sc->hw.mac.report_tx_early = 1;
547 /* Calculate # of RX rings */
548 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
549 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
551 /* Allocate RX/TX rings' busdma(9) stuffs */
552 error = emx_dma_alloc(sc);
556 /* Allocate multicast array memory. */
557 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
560 /* Indicate SOL/IDER usage */
561 if (e1000_check_reset_block(&sc->hw)) {
563 "PHY reset is blocked due to SOL/IDER session.\n");
567 * Start from a known state, this is important in reading the
568 * nvm and mac from that.
570 e1000_reset_hw(&sc->hw);
572 /* Make sure we have a good EEPROM before we read from it */
573 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
575 * Some PCI-E parts fail the first check due to
576 * the link being in sleep state, call it again,
577 * if it fails a second time its a real issue.
579 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
581 "The EEPROM Checksum Is Not Valid\n");
587 /* Copy the permanent MAC address out of the EEPROM */
588 if (e1000_read_mac_addr(&sc->hw) < 0) {
589 device_printf(dev, "EEPROM read error while reading MAC"
594 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
595 device_printf(dev, "Invalid MAC address\n");
600 /* Determine if we have to control management hardware */
601 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
606 apme_mask = EMX_EEPROM_APME;
608 switch (sc->hw.mac.type) {
615 case e1000_80003es2lan:
616 if (sc->hw.bus.func == 1) {
617 e1000_read_nvm(&sc->hw,
618 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
620 e1000_read_nvm(&sc->hw,
621 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
626 e1000_read_nvm(&sc->hw,
627 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
630 if (eeprom_data & apme_mask)
631 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
634 * We have the eeprom settings, now apply the special cases
635 * where the eeprom may be wrong or the board won't support
636 * wake on lan on a particular port
638 device_id = pci_get_device(dev);
640 case E1000_DEV_ID_82571EB_FIBER:
642 * Wake events only supported on port A for dual fiber
643 * regardless of eeprom setting
645 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
650 case E1000_DEV_ID_82571EB_QUAD_COPPER:
651 case E1000_DEV_ID_82571EB_QUAD_FIBER:
652 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
653 /* if quad port sc, disable WoL on all but port A */
654 if (emx_global_quad_port_a != 0)
656 /* Reset for multiple quad port adapters */
657 if (++emx_global_quad_port_a == 4)
658 emx_global_quad_port_a = 0;
662 /* XXX disable wol */
665 /* Setup OS specific network interface */
668 /* Add sysctl tree, must after em_setup_ifp() */
671 /* Reset the hardware */
672 error = emx_reset(sc);
674 device_printf(dev, "Unable to reset the hardware\n");
678 /* Initialize statistics */
679 emx_update_stats(sc);
681 sc->hw.mac.get_link_status = 1;
682 emx_update_link_status(sc);
684 sc->spare_tx_desc = EMX_TX_SPARE;
687 * Keep following relationship between spare_tx_desc, oact_tx_desc
689 * (spare_tx_desc + EMX_TX_RESERVED) <=
690 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
692 sc->oact_tx_desc = sc->num_tx_desc / 8;
693 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
694 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
695 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
696 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
698 sc->tx_int_nsegs = sc->num_tx_desc / 16;
699 if (sc->tx_int_nsegs < sc->oact_tx_desc)
700 sc->tx_int_nsegs = sc->oact_tx_desc;
702 /* Non-AMT based hardware can now take control from firmware */
703 if (sc->has_manage && !sc->has_amt)
704 emx_get_hw_control(sc);
706 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
707 &sc->intr_tag, &sc->main_serialize);
709 device_printf(dev, "Failed to register interrupt handler");
710 ether_ifdetach(&sc->arpcom.ac_if);
714 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
715 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
723 emx_detach(device_t dev)
725 struct emx_softc *sc = device_get_softc(dev);
727 if (device_is_attached(dev)) {
728 struct ifnet *ifp = &sc->arpcom.ac_if;
730 ifnet_serialize_all(ifp);
734 e1000_phy_hw_reset(&sc->hw);
737 emx_rel_hw_control(sc);
740 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
741 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
745 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
747 ifnet_deserialize_all(ifp);
751 emx_rel_hw_control(sc);
753 bus_generic_detach(dev);
755 if (sc->intr_res != NULL) {
756 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
760 if (sc->intr_type == PCI_INTR_TYPE_MSI)
761 pci_release_msi(dev);
763 if (sc->memory != NULL) {
764 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
770 /* Free sysctl tree */
771 if (sc->sysctl_tree != NULL)
772 sysctl_ctx_free(&sc->sysctl_ctx);
778 emx_shutdown(device_t dev)
780 return emx_suspend(dev);
784 emx_suspend(device_t dev)
786 struct emx_softc *sc = device_get_softc(dev);
787 struct ifnet *ifp = &sc->arpcom.ac_if;
789 ifnet_serialize_all(ifp);
794 emx_rel_hw_control(sc);
797 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
798 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
802 ifnet_deserialize_all(ifp);
804 return bus_generic_suspend(dev);
808 emx_resume(device_t dev)
810 struct emx_softc *sc = device_get_softc(dev);
811 struct ifnet *ifp = &sc->arpcom.ac_if;
813 ifnet_serialize_all(ifp);
819 ifnet_deserialize_all(ifp);
821 return bus_generic_resume(dev);
825 emx_start(struct ifnet *ifp)
827 struct emx_softc *sc = ifp->if_softc;
830 ASSERT_SERIALIZED(&sc->tx_serialize);
832 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
835 if (!sc->link_active) {
836 ifq_purge(&ifp->if_snd);
840 while (!ifq_is_empty(&ifp->if_snd)) {
841 /* Now do we at least have a minimal? */
842 if (EMX_IS_OACTIVE(sc)) {
844 if (EMX_IS_OACTIVE(sc)) {
845 ifp->if_flags |= IFF_OACTIVE;
846 sc->no_tx_desc_avail1++;
852 m_head = ifq_dequeue(&ifp->if_snd, NULL);
856 if (emx_encap(sc, &m_head)) {
862 /* Send a copy of the frame to the BPF listener */
863 ETHER_BPF_MTAP(ifp, m_head);
865 /* Set timeout in case hardware has problems transmitting. */
866 ifp->if_timer = EMX_TX_TIMEOUT;
871 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
873 struct emx_softc *sc = ifp->if_softc;
874 struct ifreq *ifr = (struct ifreq *)data;
875 uint16_t eeprom_data = 0;
876 int max_frame_size, mask, reinit;
879 ASSERT_IFNET_SERIALIZED_ALL(ifp);
883 switch (sc->hw.mac.type) {
886 * 82573 only supports jumbo frames
887 * if ASPM is disabled.
889 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
891 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
892 max_frame_size = ETHER_MAX_LEN;
897 /* Limit Jumbo Frame size */
901 case e1000_80003es2lan:
902 max_frame_size = 9234;
906 max_frame_size = MAX_JUMBO_FRAME_SIZE;
909 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
915 ifp->if_mtu = ifr->ifr_mtu;
916 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
919 if (ifp->if_flags & IFF_RUNNING)
924 if (ifp->if_flags & IFF_UP) {
925 if ((ifp->if_flags & IFF_RUNNING)) {
926 if ((ifp->if_flags ^ sc->if_flags) &
927 (IFF_PROMISC | IFF_ALLMULTI)) {
928 emx_disable_promisc(sc);
934 } else if (ifp->if_flags & IFF_RUNNING) {
937 sc->if_flags = ifp->if_flags;
942 if (ifp->if_flags & IFF_RUNNING) {
943 emx_disable_intr(sc);
946 if (!(ifp->if_flags & IFF_NPOLLING))
953 /* Check SOL/IDER usage */
954 if (e1000_check_reset_block(&sc->hw)) {
955 device_printf(sc->dev, "Media change is"
956 " blocked due to SOL/IDER session.\n");
962 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
967 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
968 if (mask & IFCAP_HWCSUM) {
969 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
972 if (mask & IFCAP_VLAN_HWTAGGING) {
973 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
976 if (mask & IFCAP_RSS)
977 ifp->if_capenable ^= IFCAP_RSS;
978 if (reinit && (ifp->if_flags & IFF_RUNNING))
983 error = ether_ioctl(ifp, command, data);
990 emx_watchdog(struct ifnet *ifp)
992 struct emx_softc *sc = ifp->if_softc;
994 ASSERT_IFNET_SERIALIZED_ALL(ifp);
997 * The timer is set to 5 every time start queues a packet.
998 * Then txeof keeps resetting it as long as it cleans at
999 * least one descriptor.
1000 * Finally, anytime all descriptors are clean the timer is
1004 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1005 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1007 * If we reach here, all TX jobs are completed and
1008 * the TX engine should have been idled for some time.
1009 * We don't need to call if_devstart() here.
1011 ifp->if_flags &= ~IFF_OACTIVE;
1017 * If we are in this routine because of pause frames, then
1018 * don't reset the hardware.
1020 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1021 ifp->if_timer = EMX_TX_TIMEOUT;
1025 if (e1000_check_for_link(&sc->hw) == 0)
1026 if_printf(ifp, "watchdog timeout -- resetting\n");
1029 sc->watchdog_events++;
1033 if (!ifq_is_empty(&ifp->if_snd))
1040 struct emx_softc *sc = xsc;
1041 struct ifnet *ifp = &sc->arpcom.ac_if;
1042 device_t dev = sc->dev;
1046 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1051 * Packet Buffer Allocation (PBA)
1052 * Writing PBA sets the receive portion of the buffer
1053 * the remainder is used for the transmit buffer.
1055 switch (sc->hw.mac.type) {
1056 /* Total Packet Buffer on these is 48K */
1059 case e1000_80003es2lan:
1060 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1063 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1064 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1068 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1072 /* Devices before 82547 had a Packet Buffer of 64K. */
1073 if (sc->max_frame_size > 8192)
1074 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1076 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1078 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1080 /* Get the latest mac address, User can use a LAA */
1081 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1083 /* Put the address into the Receive Address Array */
1084 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1087 * With the 82571 sc, RAR[0] may be overwritten
1088 * when the other port is reset, we make a duplicate
1089 * in RAR[14] for that eventuality, this assures
1090 * the interface continues to function.
1092 if (sc->hw.mac.type == e1000_82571) {
1093 e1000_set_laa_state_82571(&sc->hw, TRUE);
1094 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1095 E1000_RAR_ENTRIES - 1);
1098 /* Initialize the hardware */
1099 if (emx_reset(sc)) {
1100 device_printf(dev, "Unable to reset the hardware\n");
1101 /* XXX emx_stop()? */
1104 emx_update_link_status(sc);
1106 /* Setup VLAN support, basic and offload if available */
1107 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1109 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1112 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1113 ctrl |= E1000_CTRL_VME;
1114 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1117 /* Set hardware offload abilities */
1118 if (ifp->if_capenable & IFCAP_TXCSUM)
1119 ifp->if_hwassist = EMX_CSUM_FEATURES;
1121 ifp->if_hwassist = 0;
1123 /* Configure for OS presence */
1126 /* Prepare transmit descriptors and buffers */
1127 emx_init_tx_ring(sc);
1128 emx_init_tx_unit(sc);
1130 /* Setup Multicast table */
1133 /* Prepare receive descriptors and buffers */
1134 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1135 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1137 "Could not setup receive structures\n");
1142 emx_init_rx_unit(sc);
1144 /* Don't lose promiscuous settings */
1145 emx_set_promisc(sc);
1147 ifp->if_flags |= IFF_RUNNING;
1148 ifp->if_flags &= ~IFF_OACTIVE;
1150 callout_reset(&sc->timer, hz, emx_timer, sc);
1151 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1153 /* MSI/X configuration for 82574 */
1154 if (sc->hw.mac.type == e1000_82574) {
1157 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1158 tmp |= E1000_CTRL_EXT_PBA_CLR;
1159 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1162 * Set the IVAR - interrupt vector routing.
1163 * Each nibble represents a vector, high bit
1164 * is enable, other 3 bits are the MSIX table
1165 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1166 * Link (other) to 2, hence the magic number.
1168 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1171 #ifdef IFPOLL_ENABLE
1173 * Only enable interrupts if we are not polling, make sure
1174 * they are off otherwise.
1176 if (ifp->if_flags & IFF_NPOLLING)
1177 emx_disable_intr(sc);
1179 #endif /* IFPOLL_ENABLE */
1180 emx_enable_intr(sc);
1182 /* AMT based hardware can now take control from firmware */
1183 if (sc->has_manage && sc->has_amt)
1184 emx_get_hw_control(sc);
1186 /* Don't reset the phy next time init gets called */
1187 sc->hw.phy.reset_disable = TRUE;
1193 struct emx_softc *sc = xsc;
1194 struct ifnet *ifp = &sc->arpcom.ac_if;
1198 ASSERT_SERIALIZED(&sc->main_serialize);
1200 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1202 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1208 * XXX: some laptops trigger several spurious interrupts
1209 * on emx(4) when in the resume cycle. The ICR register
1210 * reports all-ones value in this case. Processing such
1211 * interrupts would lead to a freeze. I don't know why.
1213 if (reg_icr == 0xffffffff) {
1218 if (ifp->if_flags & IFF_RUNNING) {
1220 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1223 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1224 lwkt_serialize_enter(
1225 &sc->rx_data[i].rx_serialize);
1226 emx_rxeof(sc, i, -1);
1227 lwkt_serialize_exit(
1228 &sc->rx_data[i].rx_serialize);
1231 if (reg_icr & E1000_ICR_TXDW) {
1232 lwkt_serialize_enter(&sc->tx_serialize);
1234 if (!ifq_is_empty(&ifp->if_snd))
1236 lwkt_serialize_exit(&sc->tx_serialize);
1240 /* Link status change */
1241 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1242 emx_serialize_skipmain(sc);
1244 callout_stop(&sc->timer);
1245 sc->hw.mac.get_link_status = 1;
1246 emx_update_link_status(sc);
1248 /* Deal with TX cruft when link lost */
1251 callout_reset(&sc->timer, hz, emx_timer, sc);
1253 emx_deserialize_skipmain(sc);
1256 if (reg_icr & E1000_ICR_RXO)
1263 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1265 struct emx_softc *sc = ifp->if_softc;
1267 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1269 emx_update_link_status(sc);
1271 ifmr->ifm_status = IFM_AVALID;
1272 ifmr->ifm_active = IFM_ETHER;
1274 if (!sc->link_active)
1277 ifmr->ifm_status |= IFM_ACTIVE;
1279 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1280 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1281 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1283 switch (sc->link_speed) {
1285 ifmr->ifm_active |= IFM_10_T;
1288 ifmr->ifm_active |= IFM_100_TX;
1292 ifmr->ifm_active |= IFM_1000_T;
1295 if (sc->link_duplex == FULL_DUPLEX)
1296 ifmr->ifm_active |= IFM_FDX;
1298 ifmr->ifm_active |= IFM_HDX;
1303 emx_media_change(struct ifnet *ifp)
1305 struct emx_softc *sc = ifp->if_softc;
1306 struct ifmedia *ifm = &sc->media;
1308 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1310 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1313 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1315 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1316 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1322 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1323 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1327 sc->hw.mac.autoneg = FALSE;
1328 sc->hw.phy.autoneg_advertised = 0;
1329 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1330 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1332 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1336 sc->hw.mac.autoneg = FALSE;
1337 sc->hw.phy.autoneg_advertised = 0;
1338 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1339 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1341 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1345 if_printf(ifp, "Unsupported media type\n");
1350 * As the speed/duplex settings my have changed we need to
1353 sc->hw.phy.reset_disable = FALSE;
1361 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1363 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1365 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1366 struct e1000_tx_desc *ctxd = NULL;
1367 struct mbuf *m_head = *m_headp;
1368 uint32_t txd_upper, txd_lower, cmd = 0;
1369 int maxsegs, nsegs, i, j, first, last = 0, error;
1371 if (m_head->m_len < EMX_TXCSUM_MINHL &&
1372 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1374 * Make sure that ethernet header and ip.ip_hl are in
1375 * contiguous memory, since if TXCSUM is enabled, later
1376 * TX context descriptor's setup need to access ip.ip_hl.
1378 error = emx_txcsum_pullup(sc, m_headp);
1380 KKASSERT(*m_headp == NULL);
1386 txd_upper = txd_lower = 0;
1389 * Capture the first descriptor index, this descriptor
1390 * will have the index of the EOP which is the only one
1391 * that now gets a DONE bit writeback.
1393 first = sc->next_avail_tx_desc;
1394 tx_buffer = &sc->tx_buf[first];
1395 tx_buffer_mapped = tx_buffer;
1396 map = tx_buffer->map;
1398 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1399 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
1400 if (maxsegs > EMX_MAX_SCATTER)
1401 maxsegs = EMX_MAX_SCATTER;
1403 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1404 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1406 if (error == ENOBUFS)
1407 sc->mbuf_alloc_failed++;
1409 sc->no_tx_dma_setup++;
1415 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1418 sc->tx_nsegs += nsegs;
1420 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1421 /* TX csum offloading will consume one TX desc */
1422 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1424 i = sc->next_avail_tx_desc;
1426 /* Set up our transmit descriptors */
1427 for (j = 0; j < nsegs; j++) {
1428 tx_buffer = &sc->tx_buf[i];
1429 ctxd = &sc->tx_desc_base[i];
1431 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1432 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1433 txd_lower | segs[j].ds_len);
1434 ctxd->upper.data = htole32(txd_upper);
1437 if (++i == sc->num_tx_desc)
1441 sc->next_avail_tx_desc = i;
1443 KKASSERT(sc->num_tx_desc_avail > nsegs);
1444 sc->num_tx_desc_avail -= nsegs;
1446 /* Handle VLAN tag */
1447 if (m_head->m_flags & M_VLANTAG) {
1448 /* Set the vlan id. */
1449 ctxd->upper.fields.special =
1450 htole16(m_head->m_pkthdr.ether_vlantag);
1452 /* Tell hardware to add tag */
1453 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1456 tx_buffer->m_head = m_head;
1457 tx_buffer_mapped->map = tx_buffer->map;
1458 tx_buffer->map = map;
1460 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1464 * Report Status (RS) is turned on
1465 * every tx_int_nsegs descriptors.
1467 cmd = E1000_TXD_CMD_RS;
1470 * Keep track of the descriptor, which will
1471 * be written back by hardware.
1473 sc->tx_dd[sc->tx_dd_tail] = last;
1474 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1475 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1479 * Last Descriptor of Packet needs End Of Packet (EOP)
1481 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1484 * Advance the Transmit Descriptor Tail (TDT), this tells
1485 * the E1000 that this frame is available to transmit.
1487 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1493 emx_set_promisc(struct emx_softc *sc)
1495 struct ifnet *ifp = &sc->arpcom.ac_if;
1498 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1500 if (ifp->if_flags & IFF_PROMISC) {
1501 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1502 /* Turn this on if you want to see bad packets */
1504 reg_rctl |= E1000_RCTL_SBP;
1505 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1506 } else if (ifp->if_flags & IFF_ALLMULTI) {
1507 reg_rctl |= E1000_RCTL_MPE;
1508 reg_rctl &= ~E1000_RCTL_UPE;
1509 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1514 emx_disable_promisc(struct emx_softc *sc)
1518 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1520 reg_rctl &= ~E1000_RCTL_UPE;
1521 reg_rctl &= ~E1000_RCTL_MPE;
1522 reg_rctl &= ~E1000_RCTL_SBP;
1523 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1527 emx_set_multi(struct emx_softc *sc)
1529 struct ifnet *ifp = &sc->arpcom.ac_if;
1530 struct ifmultiaddr *ifma;
1531 uint32_t reg_rctl = 0;
1536 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1538 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1539 if (ifma->ifma_addr->sa_family != AF_LINK)
1542 if (mcnt == EMX_MCAST_ADDR_MAX)
1545 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1546 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1550 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1551 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1552 reg_rctl |= E1000_RCTL_MPE;
1553 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1555 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1560 * This routine checks for link status and updates statistics.
1563 emx_timer(void *xsc)
1565 struct emx_softc *sc = xsc;
1566 struct ifnet *ifp = &sc->arpcom.ac_if;
1568 ifnet_serialize_all(ifp);
1570 emx_update_link_status(sc);
1571 emx_update_stats(sc);
1573 /* Reset LAA into RAR[0] on 82571 */
1574 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1575 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1577 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1578 emx_print_hw_stats(sc);
1582 callout_reset(&sc->timer, hz, emx_timer, sc);
1584 ifnet_deserialize_all(ifp);
1588 emx_update_link_status(struct emx_softc *sc)
1590 struct e1000_hw *hw = &sc->hw;
1591 struct ifnet *ifp = &sc->arpcom.ac_if;
1592 device_t dev = sc->dev;
1593 uint32_t link_check = 0;
1595 /* Get the cached link value or read phy for real */
1596 switch (hw->phy.media_type) {
1597 case e1000_media_type_copper:
1598 if (hw->mac.get_link_status) {
1599 /* Do the work to read phy */
1600 e1000_check_for_link(hw);
1601 link_check = !hw->mac.get_link_status;
1602 if (link_check) /* ESB2 fix */
1603 e1000_cfg_on_link_up(hw);
1609 case e1000_media_type_fiber:
1610 e1000_check_for_link(hw);
1611 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1614 case e1000_media_type_internal_serdes:
1615 e1000_check_for_link(hw);
1616 link_check = sc->hw.mac.serdes_has_link;
1619 case e1000_media_type_unknown:
1624 /* Now check for a transition */
1625 if (link_check && sc->link_active == 0) {
1626 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1630 * Check if we should enable/disable SPEED_MODE bit on
1633 if (sc->link_speed != SPEED_1000 &&
1634 (hw->mac.type == e1000_82571 ||
1635 hw->mac.type == e1000_82572)) {
1638 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1639 tarc0 &= ~EMX_TARC_SPEED_MODE;
1640 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1643 device_printf(dev, "Link is up %d Mbps %s\n",
1645 ((sc->link_duplex == FULL_DUPLEX) ?
1646 "Full Duplex" : "Half Duplex"));
1648 sc->link_active = 1;
1650 ifp->if_baudrate = sc->link_speed * 1000000;
1651 ifp->if_link_state = LINK_STATE_UP;
1652 if_link_state_change(ifp);
1653 } else if (!link_check && sc->link_active == 1) {
1654 ifp->if_baudrate = sc->link_speed = 0;
1655 sc->link_duplex = 0;
1657 device_printf(dev, "Link is Down\n");
1658 sc->link_active = 0;
1660 /* Link down, disable watchdog */
1663 ifp->if_link_state = LINK_STATE_DOWN;
1664 if_link_state_change(ifp);
1669 emx_stop(struct emx_softc *sc)
1671 struct ifnet *ifp = &sc->arpcom.ac_if;
1674 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1676 emx_disable_intr(sc);
1678 callout_stop(&sc->timer);
1680 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1684 * Disable multiple receive queues.
1687 * We should disable multiple receive queues before
1688 * resetting the hardware.
1690 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1692 e1000_reset_hw(&sc->hw);
1693 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1695 for (i = 0; i < sc->num_tx_desc; i++) {
1696 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1698 if (tx_buffer->m_head != NULL) {
1699 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1700 m_freem(tx_buffer->m_head);
1701 tx_buffer->m_head = NULL;
1705 for (i = 0; i < sc->rx_ring_cnt; ++i)
1706 emx_free_rx_ring(sc, &sc->rx_data[i]);
1710 sc->csum_iphlen = 0;
1718 emx_reset(struct emx_softc *sc)
1720 device_t dev = sc->dev;
1721 uint16_t rx_buffer_size;
1723 /* Set up smart power down as default off on newer adapters. */
1724 if (!emx_smart_pwr_down &&
1725 (sc->hw.mac.type == e1000_82571 ||
1726 sc->hw.mac.type == e1000_82572)) {
1727 uint16_t phy_tmp = 0;
1729 /* Speed up time to link by disabling smart power down. */
1730 e1000_read_phy_reg(&sc->hw,
1731 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1732 phy_tmp &= ~IGP02E1000_PM_SPD;
1733 e1000_write_phy_reg(&sc->hw,
1734 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1738 * These parameters control the automatic generation (Tx) and
1739 * response (Rx) to Ethernet PAUSE frames.
1740 * - High water mark should allow for at least two frames to be
1741 * received after sending an XOFF.
1742 * - Low water mark works best when it is very near the high water mark.
1743 * This allows the receiver to restart by sending XON when it has
1744 * drained a bit. Here we use an arbitary value of 1500 which will
1745 * restart after one full frame is pulled from the buffer. There
1746 * could be several smaller frames in the buffer and if so they will
1747 * not trigger the XON until their total number reduces the buffer
1749 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1751 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1753 sc->hw.fc.high_water = rx_buffer_size -
1754 roundup2(sc->max_frame_size, 1024);
1755 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1757 if (sc->hw.mac.type == e1000_80003es2lan)
1758 sc->hw.fc.pause_time = 0xFFFF;
1760 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1761 sc->hw.fc.send_xon = TRUE;
1762 sc->hw.fc.requested_mode = e1000_fc_full;
1764 /* Issue a global reset */
1765 e1000_reset_hw(&sc->hw);
1766 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1767 emx_disable_aspm(sc);
1769 if (e1000_init_hw(&sc->hw) < 0) {
1770 device_printf(dev, "Hardware Initialization Failed\n");
1774 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1775 e1000_get_phy_info(&sc->hw);
1776 e1000_check_for_link(&sc->hw);
1782 emx_setup_ifp(struct emx_softc *sc)
1784 struct ifnet *ifp = &sc->arpcom.ac_if;
1786 if_initname(ifp, device_get_name(sc->dev),
1787 device_get_unit(sc->dev));
1789 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1790 ifp->if_init = emx_init;
1791 ifp->if_ioctl = emx_ioctl;
1792 ifp->if_start = emx_start;
1793 #ifdef IFPOLL_ENABLE
1794 ifp->if_qpoll = emx_qpoll;
1796 ifp->if_watchdog = emx_watchdog;
1797 ifp->if_serialize = emx_serialize;
1798 ifp->if_deserialize = emx_deserialize;
1799 ifp->if_tryserialize = emx_tryserialize;
1801 ifp->if_serialize_assert = emx_serialize_assert;
1803 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1804 ifq_set_ready(&ifp->if_snd);
1806 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1808 ifp->if_capabilities = IFCAP_HWCSUM |
1809 IFCAP_VLAN_HWTAGGING |
1811 if (sc->rx_ring_cnt > 1)
1812 ifp->if_capabilities |= IFCAP_RSS;
1813 ifp->if_capenable = ifp->if_capabilities;
1814 ifp->if_hwassist = EMX_CSUM_FEATURES;
1817 * Tell the upper layer(s) we support long frames.
1819 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1822 * Specify the media types supported by this sc and register
1823 * callbacks to update media and link information
1825 ifmedia_init(&sc->media, IFM_IMASK,
1826 emx_media_change, emx_media_status);
1827 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1828 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1829 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1831 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1833 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1834 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1836 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1837 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1839 if (sc->hw.phy.type != e1000_phy_ife) {
1840 ifmedia_add(&sc->media,
1841 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1842 ifmedia_add(&sc->media,
1843 IFM_ETHER | IFM_1000_T, 0, NULL);
1846 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1847 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1851 * Workaround for SmartSpeed on 82541 and 82547 controllers
1854 emx_smartspeed(struct emx_softc *sc)
1858 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1859 sc->hw.mac.autoneg == 0 ||
1860 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1863 if (sc->smartspeed == 0) {
1865 * If Master/Slave config fault is asserted twice,
1866 * we assume back-to-back
1868 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1869 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1871 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1872 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1873 e1000_read_phy_reg(&sc->hw,
1874 PHY_1000T_CTRL, &phy_tmp);
1875 if (phy_tmp & CR_1000T_MS_ENABLE) {
1876 phy_tmp &= ~CR_1000T_MS_ENABLE;
1877 e1000_write_phy_reg(&sc->hw,
1878 PHY_1000T_CTRL, phy_tmp);
1880 if (sc->hw.mac.autoneg &&
1881 !e1000_phy_setup_autoneg(&sc->hw) &&
1882 !e1000_read_phy_reg(&sc->hw,
1883 PHY_CONTROL, &phy_tmp)) {
1884 phy_tmp |= MII_CR_AUTO_NEG_EN |
1885 MII_CR_RESTART_AUTO_NEG;
1886 e1000_write_phy_reg(&sc->hw,
1887 PHY_CONTROL, phy_tmp);
1892 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1893 /* If still no link, perhaps using 2/3 pair cable */
1894 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1895 phy_tmp |= CR_1000T_MS_ENABLE;
1896 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1897 if (sc->hw.mac.autoneg &&
1898 !e1000_phy_setup_autoneg(&sc->hw) &&
1899 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1900 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1901 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1905 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1906 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1911 emx_create_tx_ring(struct emx_softc *sc)
1913 device_t dev = sc->dev;
1914 struct emx_txbuf *tx_buffer;
1915 int error, i, tsize, ntxd;
1918 * Validate number of transmit descriptors. It must not exceed
1919 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1921 ntxd = device_getenv_int(dev, "txd", emx_txd);
1922 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1923 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
1924 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1925 EMX_DEFAULT_TXD, ntxd);
1926 sc->num_tx_desc = EMX_DEFAULT_TXD;
1928 sc->num_tx_desc = ntxd;
1932 * Allocate Transmit Descriptor ring
1934 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1936 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1937 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1938 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1939 &sc->tx_desc_paddr);
1940 if (sc->tx_desc_base == NULL) {
1941 device_printf(dev, "Unable to allocate tx_desc memory\n");
1945 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1946 M_DEVBUF, M_WAITOK | M_ZERO);
1949 * Create DMA tags for tx buffers
1951 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1952 1, 0, /* alignment, bounds */
1953 BUS_SPACE_MAXADDR, /* lowaddr */
1954 BUS_SPACE_MAXADDR, /* highaddr */
1955 NULL, NULL, /* filter, filterarg */
1956 EMX_TSO_SIZE, /* maxsize */
1957 EMX_MAX_SCATTER, /* nsegments */
1958 EMX_MAX_SEGSIZE, /* maxsegsize */
1959 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1960 BUS_DMA_ONEBPAGE, /* flags */
1963 device_printf(dev, "Unable to allocate TX DMA tag\n");
1964 kfree(sc->tx_buf, M_DEVBUF);
1970 * Create DMA maps for tx buffers
1972 for (i = 0; i < sc->num_tx_desc; i++) {
1973 tx_buffer = &sc->tx_buf[i];
1975 error = bus_dmamap_create(sc->txtag,
1976 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1979 device_printf(dev, "Unable to create TX DMA map\n");
1980 emx_destroy_tx_ring(sc, i);
1988 emx_init_tx_ring(struct emx_softc *sc)
1990 /* Clear the old ring contents */
1991 bzero(sc->tx_desc_base,
1992 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
1995 sc->next_avail_tx_desc = 0;
1996 sc->next_tx_to_clean = 0;
1997 sc->num_tx_desc_avail = sc->num_tx_desc;
2001 emx_init_tx_unit(struct emx_softc *sc)
2003 uint32_t tctl, tarc, tipg = 0;
2006 /* Setup the Base and Length of the Tx Descriptor Ring */
2007 bus_addr = sc->tx_desc_paddr;
2008 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2009 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2010 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2011 (uint32_t)(bus_addr >> 32));
2012 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2013 (uint32_t)bus_addr);
2014 /* Setup the HW Tx Head and Tail descriptor pointers */
2015 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2016 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2018 /* Set the default values for the Tx Inter Packet Gap timer */
2019 switch (sc->hw.mac.type) {
2020 case e1000_80003es2lan:
2021 tipg = DEFAULT_82543_TIPG_IPGR1;
2022 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2023 E1000_TIPG_IPGR2_SHIFT;
2027 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2028 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2029 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2031 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2032 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2033 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2037 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2039 /* NOTE: 0 is not allowed for TIDV */
2040 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2041 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2043 if (sc->hw.mac.type == e1000_82571 ||
2044 sc->hw.mac.type == e1000_82572) {
2045 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2046 tarc |= EMX_TARC_SPEED_MODE;
2047 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2048 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2049 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2051 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2052 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2054 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2057 /* Program the Transmit Control Register */
2058 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2059 tctl &= ~E1000_TCTL_CT;
2060 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2061 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2062 tctl |= E1000_TCTL_MULR;
2064 /* This write will effectively turn on the transmit unit. */
2065 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2069 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2071 struct emx_txbuf *tx_buffer;
2074 /* Free Transmit Descriptor ring */
2075 if (sc->tx_desc_base) {
2076 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2077 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2079 bus_dma_tag_destroy(sc->tx_desc_dtag);
2081 sc->tx_desc_base = NULL;
2084 if (sc->tx_buf == NULL)
2087 for (i = 0; i < ndesc; i++) {
2088 tx_buffer = &sc->tx_buf[i];
2090 KKASSERT(tx_buffer->m_head == NULL);
2091 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2093 bus_dma_tag_destroy(sc->txtag);
2095 kfree(sc->tx_buf, M_DEVBUF);
2100 * The offload context needs to be set when we transfer the first
2101 * packet of a particular protocol (TCP/UDP). This routine has been
2102 * enhanced to deal with inserted VLAN headers.
2104 * If the new packet's ether header length, ip header length and
2105 * csum offloading type are same as the previous packet, we should
2106 * avoid allocating a new csum context descriptor; mainly to take
2107 * advantage of the pipeline effect of the TX data read request.
2109 * This function returns number of TX descrptors allocated for
2113 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2114 uint32_t *txd_upper, uint32_t *txd_lower)
2116 struct e1000_context_desc *TXD;
2117 struct emx_txbuf *tx_buffer;
2118 struct ether_vlan_header *eh;
2120 int curr_txd, ehdrlen, csum_flags;
2121 uint32_t cmd, hdr_len, ip_hlen;
2125 * Determine where frame payload starts.
2126 * Jump over vlan headers if already present,
2127 * helpful for QinQ too.
2129 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2130 ("emx_txcsum_pullup is not called (eh)?"));
2131 eh = mtod(mp, struct ether_vlan_header *);
2132 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2133 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2134 ("emx_txcsum_pullup is not called (evh)?"));
2135 etype = ntohs(eh->evl_proto);
2136 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2138 etype = ntohs(eh->evl_encap_proto);
2139 ehdrlen = ETHER_HDR_LEN;
2143 * We only support TCP/UDP for IPv4 for the moment.
2144 * TODO: Support SCTP too when it hits the tree.
2146 if (etype != ETHERTYPE_IP)
2149 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2150 ("emx_txcsum_pullup is not called (eh+ip_vhl)?"));
2152 /* NOTE: We could only safely access ip.ip_vhl part */
2153 ip = (struct ip *)(mp->m_data + ehdrlen);
2154 ip_hlen = ip->ip_hl << 2;
2156 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2158 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2159 sc->csum_flags == csum_flags) {
2161 * Same csum offload context as the previous packets;
2164 *txd_upper = sc->csum_txd_upper;
2165 *txd_lower = sc->csum_txd_lower;
2170 * Setup a new csum offload context.
2173 curr_txd = sc->next_avail_tx_desc;
2174 tx_buffer = &sc->tx_buf[curr_txd];
2175 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2179 /* Setup of IP header checksum. */
2180 if (csum_flags & CSUM_IP) {
2182 * Start offset for header checksum calculation.
2183 * End offset for header checksum calculation.
2184 * Offset of place to put the checksum.
2186 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2187 TXD->lower_setup.ip_fields.ipcse =
2188 htole16(ehdrlen + ip_hlen - 1);
2189 TXD->lower_setup.ip_fields.ipcso =
2190 ehdrlen + offsetof(struct ip, ip_sum);
2191 cmd |= E1000_TXD_CMD_IP;
2192 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2194 hdr_len = ehdrlen + ip_hlen;
2196 if (csum_flags & CSUM_TCP) {
2198 * Start offset for payload checksum calculation.
2199 * End offset for payload checksum calculation.
2200 * Offset of place to put the checksum.
2202 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2203 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2204 TXD->upper_setup.tcp_fields.tucso =
2205 hdr_len + offsetof(struct tcphdr, th_sum);
2206 cmd |= E1000_TXD_CMD_TCP;
2207 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2208 } else if (csum_flags & CSUM_UDP) {
2210 * Start offset for header checksum calculation.
2211 * End offset for header checksum calculation.
2212 * Offset of place to put the checksum.
2214 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2215 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2216 TXD->upper_setup.tcp_fields.tucso =
2217 hdr_len + offsetof(struct udphdr, uh_sum);
2218 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2221 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2222 E1000_TXD_DTYP_D; /* Data descr */
2224 /* Save the information for this csum offloading context */
2225 sc->csum_ehlen = ehdrlen;
2226 sc->csum_iphlen = ip_hlen;
2227 sc->csum_flags = csum_flags;
2228 sc->csum_txd_upper = *txd_upper;
2229 sc->csum_txd_lower = *txd_lower;
2231 TXD->tcp_seg_setup.data = htole32(0);
2232 TXD->cmd_and_length =
2233 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2235 if (++curr_txd == sc->num_tx_desc)
2238 KKASSERT(sc->num_tx_desc_avail > 0);
2239 sc->num_tx_desc_avail--;
2241 sc->next_avail_tx_desc = curr_txd;
2246 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2248 struct mbuf *m = *m0;
2249 struct ether_header *eh;
2252 sc->tx_csum_try_pullup++;
2254 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2256 if (__predict_false(!M_WRITABLE(m))) {
2257 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2258 sc->tx_csum_drop1++;
2263 eh = mtod(m, struct ether_header *);
2265 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2266 len += EVL_ENCAPLEN;
2268 if (m->m_len < len) {
2269 sc->tx_csum_drop2++;
2277 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2278 sc->tx_csum_pullup1++;
2279 m = m_pullup(m, ETHER_HDR_LEN);
2281 sc->tx_csum_pullup1_failed++;
2287 eh = mtod(m, struct ether_header *);
2289 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2290 len += EVL_ENCAPLEN;
2292 if (m->m_len < len) {
2293 sc->tx_csum_pullup2++;
2294 m = m_pullup(m, len);
2296 sc->tx_csum_pullup2_failed++;
2306 emx_txeof(struct emx_softc *sc)
2308 struct ifnet *ifp = &sc->arpcom.ac_if;
2309 struct emx_txbuf *tx_buffer;
2310 int first, num_avail;
2312 if (sc->tx_dd_head == sc->tx_dd_tail)
2315 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2318 num_avail = sc->num_tx_desc_avail;
2319 first = sc->next_tx_to_clean;
2321 while (sc->tx_dd_head != sc->tx_dd_tail) {
2322 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2323 struct e1000_tx_desc *tx_desc;
2325 tx_desc = &sc->tx_desc_base[dd_idx];
2326 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2327 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2329 if (++dd_idx == sc->num_tx_desc)
2332 while (first != dd_idx) {
2337 tx_buffer = &sc->tx_buf[first];
2338 if (tx_buffer->m_head) {
2340 bus_dmamap_unload(sc->txtag,
2342 m_freem(tx_buffer->m_head);
2343 tx_buffer->m_head = NULL;
2346 if (++first == sc->num_tx_desc)
2353 sc->next_tx_to_clean = first;
2354 sc->num_tx_desc_avail = num_avail;
2356 if (sc->tx_dd_head == sc->tx_dd_tail) {
2361 if (!EMX_IS_OACTIVE(sc)) {
2362 ifp->if_flags &= ~IFF_OACTIVE;
2364 /* All clean, turn off the timer */
2365 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2371 emx_tx_collect(struct emx_softc *sc)
2373 struct ifnet *ifp = &sc->arpcom.ac_if;
2374 struct emx_txbuf *tx_buffer;
2375 int tdh, first, num_avail, dd_idx = -1;
2377 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2380 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2381 if (tdh == sc->next_tx_to_clean)
2384 if (sc->tx_dd_head != sc->tx_dd_tail)
2385 dd_idx = sc->tx_dd[sc->tx_dd_head];
2387 num_avail = sc->num_tx_desc_avail;
2388 first = sc->next_tx_to_clean;
2390 while (first != tdh) {
2395 tx_buffer = &sc->tx_buf[first];
2396 if (tx_buffer->m_head) {
2398 bus_dmamap_unload(sc->txtag,
2400 m_freem(tx_buffer->m_head);
2401 tx_buffer->m_head = NULL;
2404 if (first == dd_idx) {
2405 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2406 if (sc->tx_dd_head == sc->tx_dd_tail) {
2411 dd_idx = sc->tx_dd[sc->tx_dd_head];
2415 if (++first == sc->num_tx_desc)
2418 sc->next_tx_to_clean = first;
2419 sc->num_tx_desc_avail = num_avail;
2421 if (!EMX_IS_OACTIVE(sc)) {
2422 ifp->if_flags &= ~IFF_OACTIVE;
2424 /* All clean, turn off the timer */
2425 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2431 * When Link is lost sometimes there is work still in the TX ring
2432 * which will result in a watchdog, rather than allow that do an
2433 * attempted cleanup and then reinit here. Note that this has been
2434 * seens mostly with fiber adapters.
2437 emx_tx_purge(struct emx_softc *sc)
2439 struct ifnet *ifp = &sc->arpcom.ac_if;
2441 if (!sc->link_active && ifp->if_timer) {
2443 if (ifp->if_timer) {
2444 if_printf(ifp, "Link lost, TX pending, reinit\n");
2452 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2455 bus_dma_segment_t seg;
2457 struct emx_rxbuf *rx_buffer;
2460 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2462 rdata->mbuf_cluster_failed++;
2464 if_printf(&sc->arpcom.ac_if,
2465 "Unable to allocate RX mbuf\n");
2469 m->m_len = m->m_pkthdr.len = MCLBYTES;
2471 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2472 m_adj(m, ETHER_ALIGN);
2474 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2475 rdata->rx_sparemap, m,
2476 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2480 if_printf(&sc->arpcom.ac_if,
2481 "Unable to load RX mbuf\n");
2486 rx_buffer = &rdata->rx_buf[i];
2487 if (rx_buffer->m_head != NULL)
2488 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2490 map = rx_buffer->map;
2491 rx_buffer->map = rdata->rx_sparemap;
2492 rdata->rx_sparemap = map;
2494 rx_buffer->m_head = m;
2495 rx_buffer->paddr = seg.ds_addr;
2497 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2502 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2504 device_t dev = sc->dev;
2505 struct emx_rxbuf *rx_buffer;
2506 int i, error, rsize, nrxd;
2509 * Validate number of receive descriptors. It must not exceed
2510 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2512 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2513 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2514 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2515 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2516 EMX_DEFAULT_RXD, nrxd);
2517 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2519 rdata->num_rx_desc = nrxd;
2523 * Allocate Receive Descriptor ring
2525 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2527 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2528 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2529 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2530 &rdata->rx_desc_paddr);
2531 if (rdata->rx_desc == NULL) {
2532 device_printf(dev, "Unable to allocate rx_desc memory\n");
2536 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2537 M_DEVBUF, M_WAITOK | M_ZERO);
2540 * Create DMA tag for rx buffers
2542 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2543 1, 0, /* alignment, bounds */
2544 BUS_SPACE_MAXADDR, /* lowaddr */
2545 BUS_SPACE_MAXADDR, /* highaddr */
2546 NULL, NULL, /* filter, filterarg */
2547 MCLBYTES, /* maxsize */
2549 MCLBYTES, /* maxsegsize */
2550 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2553 device_printf(dev, "Unable to allocate RX DMA tag\n");
2554 kfree(rdata->rx_buf, M_DEVBUF);
2555 rdata->rx_buf = NULL;
2560 * Create spare DMA map for rx buffers
2562 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2563 &rdata->rx_sparemap);
2565 device_printf(dev, "Unable to create spare RX DMA map\n");
2566 bus_dma_tag_destroy(rdata->rxtag);
2567 kfree(rdata->rx_buf, M_DEVBUF);
2568 rdata->rx_buf = NULL;
2573 * Create DMA maps for rx buffers
2575 for (i = 0; i < rdata->num_rx_desc; i++) {
2576 rx_buffer = &rdata->rx_buf[i];
2578 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2581 device_printf(dev, "Unable to create RX DMA map\n");
2582 emx_destroy_rx_ring(sc, rdata, i);
2590 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2594 for (i = 0; i < rdata->num_rx_desc; i++) {
2595 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2597 if (rx_buffer->m_head != NULL) {
2598 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2599 m_freem(rx_buffer->m_head);
2600 rx_buffer->m_head = NULL;
2604 if (rdata->fmp != NULL)
2605 m_freem(rdata->fmp);
2611 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2615 /* Reset descriptor ring */
2616 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2618 /* Allocate new ones. */
2619 for (i = 0; i < rdata->num_rx_desc; i++) {
2620 error = emx_newbuf(sc, rdata, i, 1);
2625 /* Setup our descriptor pointers */
2626 rdata->next_rx_desc_to_check = 0;
2632 emx_init_rx_unit(struct emx_softc *sc)
2634 struct ifnet *ifp = &sc->arpcom.ac_if;
2636 uint32_t rctl, itr, rfctl;
2640 * Make sure receives are disabled while setting
2641 * up the descriptor ring
2643 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2644 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2647 * Set the interrupt throttling rate. Value is calculated
2648 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2650 if (sc->int_throttle_ceil)
2651 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2654 emx_set_itr(sc, itr);
2656 /* Use extended RX descriptor */
2657 rfctl = E1000_RFCTL_EXTEN;
2659 /* Disable accelerated ackknowledge */
2660 if (sc->hw.mac.type == e1000_82574)
2661 rfctl |= E1000_RFCTL_ACK_DIS;
2663 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2666 * Receive Checksum Offload for TCP and UDP
2668 * Checksum offloading is also enabled if multiple receive
2669 * queue is to be supported, since we need it to figure out
2672 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2673 sc->rx_ring_cnt > 1) {
2676 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2680 * PCSD must be enabled to enable multiple
2683 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2685 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2689 * Configure multiple receive queue (RSS)
2691 if (sc->rx_ring_cnt > 1) {
2692 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2695 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2696 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2700 * When we reach here, RSS has already been disabled
2701 * in emx_stop(), so we could safely configure RSS key
2702 * and redirect table.
2708 toeplitz_get_key(key, sizeof(key));
2709 for (i = 0; i < EMX_NRSSRK; ++i) {
2712 rssrk = EMX_RSSRK_VAL(key, i);
2713 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2715 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2719 * Configure RSS redirect table in following fashion:
2720 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2723 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2726 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2727 reta |= q << (8 * i);
2729 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2731 for (i = 0; i < EMX_NRETA; ++i)
2732 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2735 * Enable multiple receive queues.
2736 * Enable IPv4 RSS standard hash functions.
2737 * Disable RSS interrupt.
2739 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2740 E1000_MRQC_ENABLE_RSS_2Q |
2741 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2742 E1000_MRQC_RSS_FIELD_IPV4);
2746 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2747 * long latencies are observed, like Lenovo X60. This
2748 * change eliminates the problem, but since having positive
2749 * values in RDTR is a known source of problems on other
2750 * platforms another solution is being sought.
2752 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2753 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2754 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2757 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2758 struct emx_rxdata *rdata = &sc->rx_data[i];
2761 * Setup the Base and Length of the Rx Descriptor Ring
2763 bus_addr = rdata->rx_desc_paddr;
2764 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2765 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2766 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2767 (uint32_t)(bus_addr >> 32));
2768 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2769 (uint32_t)bus_addr);
2772 * Setup the HW Rx Head and Tail Descriptor Pointers
2774 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2775 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2776 sc->rx_data[i].num_rx_desc - 1);
2779 /* Setup the Receive Control Register */
2780 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2781 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2782 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2783 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2785 /* Make sure VLAN Filters are off */
2786 rctl &= ~E1000_RCTL_VFE;
2788 /* Don't store bad paket */
2789 rctl &= ~E1000_RCTL_SBP;
2792 rctl |= E1000_RCTL_SZ_2048;
2794 if (ifp->if_mtu > ETHERMTU)
2795 rctl |= E1000_RCTL_LPE;
2797 rctl &= ~E1000_RCTL_LPE;
2799 /* Enable Receives */
2800 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2804 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2806 struct emx_rxbuf *rx_buffer;
2809 /* Free Receive Descriptor ring */
2810 if (rdata->rx_desc) {
2811 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2812 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2813 rdata->rx_desc_dmap);
2814 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2816 rdata->rx_desc = NULL;
2819 if (rdata->rx_buf == NULL)
2822 for (i = 0; i < ndesc; i++) {
2823 rx_buffer = &rdata->rx_buf[i];
2825 KKASSERT(rx_buffer->m_head == NULL);
2826 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2828 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2829 bus_dma_tag_destroy(rdata->rxtag);
2831 kfree(rdata->rx_buf, M_DEVBUF);
2832 rdata->rx_buf = NULL;
2836 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2838 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2839 struct ifnet *ifp = &sc->arpcom.ac_if;
2841 emx_rxdesc_t *current_desc;
2845 i = rdata->next_rx_desc_to_check;
2846 current_desc = &rdata->rx_desc[i];
2847 staterr = le32toh(current_desc->rxd_staterr);
2849 if (!(staterr & E1000_RXD_STAT_DD))
2852 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2853 struct pktinfo *pi = NULL, pi0;
2854 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2855 struct mbuf *m = NULL;
2860 mp = rx_buf->m_head;
2863 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2864 * needs to access the last received byte in the mbuf.
2866 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2867 BUS_DMASYNC_POSTREAD);
2869 len = le16toh(current_desc->rxd_length);
2870 if (staterr & E1000_RXD_STAT_EOP) {
2877 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2879 uint32_t mrq, rss_hash;
2882 * Save several necessary information,
2883 * before emx_newbuf() destroy it.
2885 if ((staterr & E1000_RXD_STAT_VP) && eop)
2886 vlan = le16toh(current_desc->rxd_vlan);
2888 mrq = le32toh(current_desc->rxd_mrq);
2889 rss_hash = le32toh(current_desc->rxd_rss);
2891 EMX_RSS_DPRINTF(sc, 10,
2892 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2893 ring_idx, mrq, rss_hash);
2895 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2900 /* Assign correct length to the current fragment */
2903 if (rdata->fmp == NULL) {
2904 mp->m_pkthdr.len = len;
2905 rdata->fmp = mp; /* Store the first mbuf */
2909 * Chain mbuf's together
2911 rdata->lmp->m_next = mp;
2912 rdata->lmp = rdata->lmp->m_next;
2913 rdata->fmp->m_pkthdr.len += len;
2917 rdata->fmp->m_pkthdr.rcvif = ifp;
2920 if (ifp->if_capenable & IFCAP_RXCSUM)
2921 emx_rxcsum(staterr, rdata->fmp);
2923 if (staterr & E1000_RXD_STAT_VP) {
2924 rdata->fmp->m_pkthdr.ether_vlantag =
2926 rdata->fmp->m_flags |= M_VLANTAG;
2932 if (ifp->if_capenable & IFCAP_RSS) {
2933 pi = emx_rssinfo(m, &pi0, mrq,
2936 #ifdef EMX_RSS_DEBUG
2943 emx_setup_rxdesc(current_desc, rx_buf);
2944 if (rdata->fmp != NULL) {
2945 m_freem(rdata->fmp);
2953 ether_input_pkt(ifp, m, pi);
2955 /* Advance our pointers to the next descriptor. */
2956 if (++i == rdata->num_rx_desc)
2959 current_desc = &rdata->rx_desc[i];
2960 staterr = le32toh(current_desc->rxd_staterr);
2962 rdata->next_rx_desc_to_check = i;
2964 /* Advance the E1000's Receive Queue "Tail Pointer". */
2966 i = rdata->num_rx_desc - 1;
2967 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2971 emx_enable_intr(struct emx_softc *sc)
2973 uint32_t ims_mask = IMS_ENABLE_MASK;
2975 lwkt_serialize_handler_enable(&sc->main_serialize);
2978 if (sc->hw.mac.type == e1000_82574) {
2979 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2980 ims_mask |= EM_MSIX_MASK;
2983 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
2987 emx_disable_intr(struct emx_softc *sc)
2989 if (sc->hw.mac.type == e1000_82574)
2990 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
2991 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2993 lwkt_serialize_handler_disable(&sc->main_serialize);
2997 * Bit of a misnomer, what this really means is
2998 * to enable OS management of the system... aka
2999 * to disable special hardware management features
3002 emx_get_mgmt(struct emx_softc *sc)
3004 /* A shared code workaround */
3005 if (sc->has_manage) {
3006 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3007 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3009 /* disable hardware interception of ARP */
3010 manc &= ~(E1000_MANC_ARP_EN);
3012 /* enable receiving management packets to the host */
3013 manc |= E1000_MANC_EN_MNG2HOST;
3014 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3015 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3016 manc2h |= E1000_MNG2HOST_PORT_623;
3017 manc2h |= E1000_MNG2HOST_PORT_664;
3018 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3020 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3025 * Give control back to hardware management
3026 * controller if there is one.
3029 emx_rel_mgmt(struct emx_softc *sc)
3031 if (sc->has_manage) {
3032 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3034 /* re-enable hardware interception of ARP */
3035 manc |= E1000_MANC_ARP_EN;
3036 manc &= ~E1000_MANC_EN_MNG2HOST;
3038 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3043 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3044 * For ASF and Pass Through versions of f/w this means that
3045 * the driver is loaded. For AMT version (only with 82573)
3046 * of the f/w this means that the network i/f is open.
3049 emx_get_hw_control(struct emx_softc *sc)
3051 /* Let firmware know the driver has taken over */
3052 if (sc->hw.mac.type == e1000_82573) {
3055 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3056 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3057 swsm | E1000_SWSM_DRV_LOAD);
3061 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3062 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3063 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3069 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3070 * For ASF and Pass Through versions of f/w this means that the
3071 * driver is no longer loaded. For AMT version (only with 82573)
3072 * of the f/w this means that the network i/f is closed.
3075 emx_rel_hw_control(struct emx_softc *sc)
3077 if (!sc->control_hw)
3081 /* Let firmware taken over control of h/w */
3082 if (sc->hw.mac.type == e1000_82573) {
3085 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3086 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3087 swsm & ~E1000_SWSM_DRV_LOAD);
3091 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3092 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3093 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3098 emx_is_valid_eaddr(const uint8_t *addr)
3100 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3102 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3109 * Enable PCI Wake On Lan capability
3112 emx_enable_wol(device_t dev)
3114 uint16_t cap, status;
3117 /* First find the capabilities pointer*/
3118 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3120 /* Read the PM Capabilities */
3121 id = pci_read_config(dev, cap, 1);
3122 if (id != PCIY_PMG) /* Something wrong */
3126 * OK, we have the power capabilities,
3127 * so now get the status register
3129 cap += PCIR_POWER_STATUS;
3130 status = pci_read_config(dev, cap, 2);
3131 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3132 pci_write_config(dev, cap, status, 2);
3136 emx_update_stats(struct emx_softc *sc)
3138 struct ifnet *ifp = &sc->arpcom.ac_if;
3140 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3141 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3142 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3143 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3145 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3146 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3147 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3148 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3150 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3151 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3152 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3153 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3154 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3155 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3156 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3157 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3158 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3159 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3160 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3161 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3162 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3163 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3164 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3165 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3166 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3167 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3168 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3169 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3171 /* For the 64-bit byte counters the low dword must be read first. */
3172 /* Both registers clear on the read of the high dword */
3174 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3175 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3177 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3178 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3179 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3180 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3181 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3183 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3184 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3186 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3187 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3188 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3189 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3190 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3191 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3192 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3193 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3194 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3195 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3197 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3198 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3199 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3200 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3201 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3202 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3204 ifp->if_collisions = sc->stats.colc;
3207 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3208 sc->stats.crcerrs + sc->stats.algnerrc +
3209 sc->stats.ruc + sc->stats.roc +
3210 sc->stats.mpc + sc->stats.cexterr;
3213 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3214 sc->watchdog_events;
3218 emx_print_debug_info(struct emx_softc *sc)
3220 device_t dev = sc->dev;
3221 uint8_t *hw_addr = sc->hw.hw_addr;
3223 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3224 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3225 E1000_READ_REG(&sc->hw, E1000_CTRL),
3226 E1000_READ_REG(&sc->hw, E1000_RCTL));
3227 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3228 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3229 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3230 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3231 sc->hw.fc.high_water, sc->hw.fc.low_water);
3232 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3233 E1000_READ_REG(&sc->hw, E1000_TIDV),
3234 E1000_READ_REG(&sc->hw, E1000_TADV));
3235 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3236 E1000_READ_REG(&sc->hw, E1000_RDTR),
3237 E1000_READ_REG(&sc->hw, E1000_RADV));
3238 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3239 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3240 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3241 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3242 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3243 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3244 device_printf(dev, "Num Tx descriptors avail = %d\n",
3245 sc->num_tx_desc_avail);
3246 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3247 sc->no_tx_desc_avail1);
3248 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3249 sc->no_tx_desc_avail2);
3250 device_printf(dev, "Std mbuf failed = %ld\n",
3251 sc->mbuf_alloc_failed);
3252 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3253 sc->rx_data[0].mbuf_cluster_failed);
3254 device_printf(dev, "Driver dropped packets = %ld\n",
3256 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3257 sc->no_tx_dma_setup);
3259 device_printf(dev, "TXCSUM try pullup = %lu\n",
3260 sc->tx_csum_try_pullup);
3261 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3262 sc->tx_csum_pullup1);
3263 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3264 sc->tx_csum_pullup1_failed);
3265 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3266 sc->tx_csum_pullup2);
3267 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3268 sc->tx_csum_pullup2_failed);
3269 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3271 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3276 emx_print_hw_stats(struct emx_softc *sc)
3278 device_t dev = sc->dev;
3280 device_printf(dev, "Excessive collisions = %lld\n",
3281 (long long)sc->stats.ecol);
3282 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3283 device_printf(dev, "Symbol errors = %lld\n",
3284 (long long)sc->stats.symerrs);
3286 device_printf(dev, "Sequence errors = %lld\n",
3287 (long long)sc->stats.sec);
3288 device_printf(dev, "Defer count = %lld\n",
3289 (long long)sc->stats.dc);
3290 device_printf(dev, "Missed Packets = %lld\n",
3291 (long long)sc->stats.mpc);
3292 device_printf(dev, "Receive No Buffers = %lld\n",
3293 (long long)sc->stats.rnbc);
3294 /* RLEC is inaccurate on some hardware, calculate our own. */
3295 device_printf(dev, "Receive Length Errors = %lld\n",
3296 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3297 device_printf(dev, "Receive errors = %lld\n",
3298 (long long)sc->stats.rxerrc);
3299 device_printf(dev, "Crc errors = %lld\n",
3300 (long long)sc->stats.crcerrs);
3301 device_printf(dev, "Alignment errors = %lld\n",
3302 (long long)sc->stats.algnerrc);
3303 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3304 (long long)sc->stats.cexterr);
3305 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3306 device_printf(dev, "watchdog timeouts = %ld\n",
3307 sc->watchdog_events);
3308 device_printf(dev, "XON Rcvd = %lld\n",
3309 (long long)sc->stats.xonrxc);
3310 device_printf(dev, "XON Xmtd = %lld\n",
3311 (long long)sc->stats.xontxc);
3312 device_printf(dev, "XOFF Rcvd = %lld\n",
3313 (long long)sc->stats.xoffrxc);
3314 device_printf(dev, "XOFF Xmtd = %lld\n",
3315 (long long)sc->stats.xofftxc);
3316 device_printf(dev, "Good Packets Rcvd = %lld\n",
3317 (long long)sc->stats.gprc);
3318 device_printf(dev, "Good Packets Xmtd = %lld\n",
3319 (long long)sc->stats.gptc);
3323 emx_print_nvm_info(struct emx_softc *sc)
3325 uint16_t eeprom_data;
3328 /* Its a bit crude, but it gets the job done */
3329 kprintf("\nInterface EEPROM Dump:\n");
3330 kprintf("Offset\n0x0000 ");
3331 for (i = 0, j = 0; i < 32; i++, j++) {
3332 if (j == 8) { /* Make the offset block */
3334 kprintf("\n0x00%x0 ",row);
3336 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3337 kprintf("%04x ", eeprom_data);
3343 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3345 struct emx_softc *sc;
3350 error = sysctl_handle_int(oidp, &result, 0, req);
3351 if (error || !req->newptr)
3354 sc = (struct emx_softc *)arg1;
3355 ifp = &sc->arpcom.ac_if;
3357 ifnet_serialize_all(ifp);
3360 emx_print_debug_info(sc);
3363 * This value will cause a hex dump of the
3364 * first 32 16-bit words of the EEPROM to
3368 emx_print_nvm_info(sc);
3370 ifnet_deserialize_all(ifp);
3376 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3381 error = sysctl_handle_int(oidp, &result, 0, req);
3382 if (error || !req->newptr)
3386 struct emx_softc *sc = (struct emx_softc *)arg1;
3387 struct ifnet *ifp = &sc->arpcom.ac_if;
3389 ifnet_serialize_all(ifp);
3390 emx_print_hw_stats(sc);
3391 ifnet_deserialize_all(ifp);
3397 emx_add_sysctl(struct emx_softc *sc)
3399 #ifdef EMX_RSS_DEBUG
3404 sysctl_ctx_init(&sc->sysctl_ctx);
3405 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3406 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3407 device_get_nameunit(sc->dev),
3409 if (sc->sysctl_tree == NULL) {
3410 device_printf(sc->dev, "can't add sysctl node\n");
3414 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3415 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3416 emx_sysctl_debug_info, "I", "Debug Information");
3418 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3419 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3420 emx_sysctl_stats, "I", "Statistics");
3422 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3423 OID_AUTO, "rxd", CTLFLAG_RD,
3424 &sc->rx_data[0].num_rx_desc, 0, NULL);
3425 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3426 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3428 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3429 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3430 sc, 0, emx_sysctl_int_throttle, "I",
3431 "interrupt throttling rate");
3432 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3433 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3434 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3435 "# segments per TX interrupt");
3437 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3438 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3439 &sc->rx_ring_cnt, 0, "RX ring count");
3441 #ifdef EMX_RSS_DEBUG
3442 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3443 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3444 0, "RSS debug level");
3445 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3446 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3447 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3448 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3450 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3456 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3458 struct emx_softc *sc = (void *)arg1;
3459 struct ifnet *ifp = &sc->arpcom.ac_if;
3460 int error, throttle;
3462 throttle = sc->int_throttle_ceil;
3463 error = sysctl_handle_int(oidp, &throttle, 0, req);
3464 if (error || req->newptr == NULL)
3466 if (throttle < 0 || throttle > 1000000000 / 256)
3471 * Set the interrupt throttling rate in 256ns increments,
3472 * recalculate sysctl value assignment to get exact frequency.
3474 throttle = 1000000000 / 256 / throttle;
3476 /* Upper 16bits of ITR is reserved and should be zero */
3477 if (throttle & 0xffff0000)
3481 ifnet_serialize_all(ifp);
3484 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3486 sc->int_throttle_ceil = 0;
3488 if (ifp->if_flags & IFF_RUNNING)
3489 emx_set_itr(sc, throttle);
3491 ifnet_deserialize_all(ifp);
3494 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3495 sc->int_throttle_ceil);
3501 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3503 struct emx_softc *sc = (void *)arg1;
3504 struct ifnet *ifp = &sc->arpcom.ac_if;
3507 segs = sc->tx_int_nsegs;
3508 error = sysctl_handle_int(oidp, &segs, 0, req);
3509 if (error || req->newptr == NULL)
3514 ifnet_serialize_all(ifp);
3517 * Don't allow int_tx_nsegs to become:
3518 * o Less the oact_tx_desc
3519 * o Too large that no TX desc will cause TX interrupt to
3520 * be generated (OACTIVE will never recover)
3521 * o Too small that will cause tx_dd[] overflow
3523 if (segs < sc->oact_tx_desc ||
3524 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3525 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3529 sc->tx_int_nsegs = segs;
3532 ifnet_deserialize_all(ifp);
3538 emx_dma_alloc(struct emx_softc *sc)
3543 * Create top level busdma tag
3545 error = bus_dma_tag_create(NULL, 1, 0,
3546 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3548 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3549 0, &sc->parent_dtag);
3551 device_printf(sc->dev, "could not create top level DMA tag\n");
3556 * Allocate transmit descriptors ring and buffers
3558 error = emx_create_tx_ring(sc);
3560 device_printf(sc->dev, "Could not setup transmit structures\n");
3565 * Allocate receive descriptors ring and buffers
3567 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3568 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3570 device_printf(sc->dev,
3571 "Could not setup receive structures\n");
3579 emx_dma_free(struct emx_softc *sc)
3583 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3585 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3586 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3587 sc->rx_data[i].num_rx_desc);
3590 /* Free top level busdma tag */
3591 if (sc->parent_dtag != NULL)
3592 bus_dma_tag_destroy(sc->parent_dtag);
3596 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3598 struct emx_softc *sc = ifp->if_softc;
3600 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3601 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3605 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3607 struct emx_softc *sc = ifp->if_softc;
3609 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3610 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3614 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3616 struct emx_softc *sc = ifp->if_softc;
3618 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3619 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3623 emx_serialize_skipmain(struct emx_softc *sc)
3625 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3629 emx_deserialize_skipmain(struct emx_softc *sc)
3631 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3637 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3638 boolean_t serialized)
3640 struct emx_softc *sc = ifp->if_softc;
3642 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3643 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
3646 #endif /* INVARIANTS */
3648 #ifdef IFPOLL_ENABLE
3651 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3653 struct emx_softc *sc = ifp->if_softc;
3656 ASSERT_SERIALIZED(&sc->main_serialize);
3658 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3659 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3660 emx_serialize_skipmain(sc);
3662 callout_stop(&sc->timer);
3663 sc->hw.mac.get_link_status = 1;
3664 emx_update_link_status(sc);
3665 callout_reset(&sc->timer, hz, emx_timer, sc);
3667 emx_deserialize_skipmain(sc);
3672 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3674 struct emx_softc *sc = ifp->if_softc;
3676 ASSERT_SERIALIZED(&sc->tx_serialize);
3679 if (!ifq_is_empty(&ifp->if_snd))
3684 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3686 struct emx_softc *sc = ifp->if_softc;
3687 struct emx_rxdata *rdata = arg;
3689 ASSERT_SERIALIZED(&rdata->rx_serialize);
3691 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3695 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3697 struct emx_softc *sc = ifp->if_softc;
3699 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3704 info->ifpi_status.status_func = emx_qpoll_status;
3705 info->ifpi_status.serializer = &sc->main_serialize;
3707 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3708 info->ifpi_tx[0].arg = NULL;
3709 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3711 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3712 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3713 info->ifpi_rx[i].arg = &sc->rx_data[i];
3714 info->ifpi_rx[i].serializer =
3715 &sc->rx_data[i].rx_serialize;
3718 if (ifp->if_flags & IFF_RUNNING)
3719 emx_disable_intr(sc);
3720 } else if (ifp->if_flags & IFF_RUNNING) {
3721 emx_enable_intr(sc);
3725 #endif /* IFPOLL_ENABLE */
3728 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3730 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3731 if (sc->hw.mac.type == e1000_82574) {
3735 * When using MSIX interrupts we need to
3736 * throttle using the EITR register
3738 for (i = 0; i < 4; ++i)
3739 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3744 * Disable the L0s, 82574L Errata #20
3747 emx_disable_aspm(struct emx_softc *sc)
3749 uint16_t link_cap, link_ctrl, disable;
3750 uint8_t pcie_ptr, reg;
3751 device_t dev = sc->dev;
3753 switch (sc->hw.mac.type) {
3758 * 82573 specification update
3762 * 82571/82572 specification update
3766 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
3771 * 82574 specification update #20
3773 * There is no need to disable L1
3775 disable = PCIEM_LNKCTL_ASPM_L0S;
3782 pcie_ptr = pci_get_pciecap_ptr(dev);
3786 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
3787 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
3791 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
3793 reg = pcie_ptr + PCIER_LINKCTRL;
3794 link_ctrl = pci_read_config(dev, reg, 2);
3795 link_ctrl &= ~disable;
3796 pci_write_config(dev, reg, link_ctrl, 2);