3 /* The following enum is used to access the special registers in
4 the saved machine state. */
8 kDc_SavedPC = 0, /* really SRR0 */
9 kDc_SavedMSR = 1, /* really SRR1 */
20 kDc_SavedSR00 = 12, /* The Segement Registers are consecutive */
21 kDc_SavedSR01 = 13, /* kDc_SavedSR00 + n is supported */
47 kNumberSpecialRegisters = 39
48 } Dc_SavedRegisterName;
50 /* Access to floating points is not very easy. This allows the number to be
51 accessed both as a floating number and as a pair of Longs. */
55 double asfloat; /* access the variable as a floating number */
61 asLONG; /* access the variable as two Longs */
64 /* The following is the standard record for Saving a machine state */
66 struct SavedMachineState
68 FloatingPoints CSavedFPRegs[32]; /* The floating point registers [0->31] */
69 /* ***32bit assumption*** */
70 Long CsavedRegs[32]; /* space to save the General Registers */
71 /* These are saved 0->31 */
75 { /* must be 8-byte aligned, so doubleFPSCR is 8-byte aligned */
78 Long CsavedSRR0; /* Index 0 - The saved PC */
79 Long CsavedSRR1; /* 1 saved MSR */
80 Long CsavedCR; /* 2 */
81 Long CsavedLR; /* 3 */
82 Long CsavedDSISR; /* 4 */
83 Long CsavedDAR; /* 5 */
85 Long CsavedXER; /* 6 */
86 Long CsavedCTR; /* 7 */
87 Long CsavedSDR1; /* 8 */
88 Long CsavedRTCU; /* 9 */
89 Long CsavedRTCL; /* 10 */
90 Long CsavedDEC; /* 11 */
91 Long CsavedSR0; /* 12 */
92 Long CsavedSR1; /* 13 */
93 Long CsavedSR2; /* 14 */
94 Long CsavedSR3; /* 15 */
95 Long CsavedSR4; /* 16 */
96 Long CsavedSR5; /* 17 */
97 Long CsavedSR6; /* 18 */
98 Long CsavedSR7; /* 19 */
99 Long CsavedSR8; /* 20 */
100 Long CsavedSR9; /* 21 */
101 Long CsavedSR10; /* 22 */
102 Long CsavedSR11; /* 23 */
103 Long CsavedSR12; /* 24 */
104 Long CsavedSR13; /* 25 */
105 Long CsavedSR14; /* 26 */
106 Long CsavedSR15; /* 27 */
107 /* CdoubleFPSCR must be double word aligned */
108 Long CdoubleFPSCR; /* 28 this is the upper part of the store and has
110 Long CsavedFPSCR; /* 29 */
111 Long CsavedMQ; /* 30 */
112 Long CsavedBAT0U; /* 31 */
113 Long CsavedBAT0L; /* 32 */
114 Long CsavedBAT1U; /* 33 */
115 Long CsavedBAT1L; /* 34 */
116 Long CsavedBAT2U; /* 35 */
117 Long CsavedBAT2L; /* 36 */
118 Long CsavedBAT3U; /* 37 */
119 Long CsavedBAT3L; /* 38 */
121 SpecialRegistersEnumerated;
123 Long SpecialRegistersIndexed[kNumberSpecialRegisters];
126 Long Padding[3]; /* Needed for quad-word alignment */
131 LONG *ExceptionDomainID;
132 /*ProcessorStructure*/ int *ExceptionProcessorID;
133 BYTE *ExceptionDescription;
135 LONG ExceptionErrorCode;
136 LONG ExceptionNumber;
137 struct SavedMachineState ExceptionState;
140 /* Register values. All of these values *MUST* agree with tm.h */
141 #define GP0_REGNUM 0 /* GPR register 0 */
142 #define SP_REGNUM 1 /* Contains address of top of stack */
143 #define FP0_REGNUM 32 /* FPR (Floating point) register 0 */
144 #define PC_REGNUM 64 /* Contains program counter */
145 #define PS_REGNUM 65 /* Processor (or machine) status (%msr) */
146 #define CR_REGNUM 66 /* Condition register */
147 #define LR_REGNUM 67 /* Link register */
148 #define CTR_REGNUM 68 /* Count register */
149 #define XER_REGNUM 69 /* Fixed point exception registers */
150 #define MQ_REGNUM 70 /* Multiply/quotient register */
151 #define NUM_REGS 71 /* Number of machine registers */
152 #define REGISTER_BYTES (420) /* Total size of registers array */
154 #define ExceptionPC ExceptionState.u.SpecialRegistersEnumerated.CsavedSRR0
155 #define DECR_PC_AFTER_BREAK 0 /* PPCs get this right! */
156 #define BREAKPOINT {0x7d, 0x82, 0x10, 0x08}
157 extern unsigned char breakpoint_insn[];
158 #define BREAKPOINT_SIZE 4
161 #define ALTERNATE_MEM_FUNCS /* We need our own get_char/set_char */
164 extern int get_char (char *addr);
165 extern void set_char (char *addr, int val);