2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
39 #include "opt_debug_npx.h"
40 #include "opt_math_emulate.h"
42 #include <sys/param.h>
43 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/sysctl.h>
52 #include <sys/syslog.h>
54 #include <sys/signalvar.h>
56 #include <sys/thread2.h>
57 #include <sys/mplock2.h>
60 #include <machine/asmacros.h>
62 #include <machine/cputypes.h>
63 #include <machine/frame.h>
64 #include <machine/ipl.h>
65 #include <machine/md_var.h>
66 #include <machine/pcb.h>
67 #include <machine/psl.h>
69 #include <machine/clock.h>
71 #include <machine/specialreg.h>
72 #include <machine/segments.h>
73 #include <machine/globaldata.h>
76 #include <machine_base/icu/icu.h>
77 #include <machine/intr_machdep.h>
78 #include <bus/isa/isa.h>
82 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
85 /* Configuration flags. */
86 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
87 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
88 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
89 #define NPX_PREFER_EMULATOR (1 << 3)
93 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
94 #define fnclex() __asm("fnclex")
95 #define fninit() __asm("fninit")
96 #define fnop() __asm("fnop")
97 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
98 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
99 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
100 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
101 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
102 #ifndef CPU_DISABLE_SSE
103 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
104 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
106 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
107 : : "n" (CR0_TS) : "ax")
108 #define stop_emulating() __asm("clts")
110 #else /* not __GNUC__ */
112 void fldcw (caddr_t addr);
116 void fnsave (caddr_t addr);
117 void fnstcw (caddr_t addr);
118 void fnstsw (caddr_t addr);
119 void fp_divide_by_0 (void);
120 void frstor (caddr_t addr);
121 #ifndef CPU_DISABLE_SSE
122 void fxsave (caddr_t addr);
123 void fxrstor (caddr_t addr);
125 void start_emulating (void);
126 void stop_emulating (void);
128 #endif /* __GNUC__ */
130 typedef u_char bool_t;
131 #ifndef CPU_DISABLE_SSE
132 static void fpu_clean_state(void);
136 static int npx_attach (device_t dev);
137 void npx_intr (void *);
138 static int npx_probe (device_t dev);
139 static int npx_probe1 (device_t dev);
140 static void fpusave (union savefpu *);
141 static void fpurstor (union savefpu *);
143 int hw_float; /* XXX currently just alias for npx_exists */
145 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
146 CTLFLAG_RD, &hw_float, 0,
147 "Floatingpoint instructions executed in hardware");
148 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
150 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
151 "MMX/XMM optimized bcopy/copyin/copyout support");
155 static u_int npx0_imask;
156 static struct gate_descriptor npx_idt_probeintr;
157 static int npx_intrno;
158 static volatile u_int npx_intrs_while_probing;
159 static volatile u_int npx_traps_while_probing;
162 static bool_t npx_ex16;
163 static bool_t npx_exists;
164 static bool_t npx_irq13;
165 static int npx_irq; /* irq number */
169 * Special interrupt handlers. Someday intr0-intr15 will be used to count
170 * interrupts. We'll still need a special exception 16 handler. The busy
171 * latch stuff in probeintr() can be moved to npxprobe().
177 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
178 " __XSTRING(CNAME(probeintr)) ": \n\
180 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
182 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
183 outb %al,$0xa0 # IO_ICU2 \n\
184 outb %al,$0x20 # IO_ICU1 \n\
186 outb %al,$0xf0 # clear BUSY# latch \n\
195 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
196 " __XSTRING(CNAME(probetrap)) ": \n\
198 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
204 static struct krate badfprate = { 1 };
207 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
208 * whether the device exists or not (XXX should be elsewhere). Set flags
209 * to tell npxattach() what to do. Modify device struct if npx doesn't
210 * need to use interrupts. Return 1 if device exists.
213 npx_probe(device_t dev)
217 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
219 return npx_probe1(dev);
225 u_char save_icu1_mask;
226 u_char save_icu2_mask;
227 struct gate_descriptor save_idt_npxintr;
228 struct gate_descriptor save_idt_npxtrap;
230 * This routine is now just a wrapper for npxprobe1(), to install
231 * special npx interrupt and trap handlers, to enable npx interrupts
232 * and to disable other interrupts. Someday isa_configure() will
233 * install suitable handlers and run with interrupts enabled so we
234 * won't need to do so much here.
236 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
238 npx_intrno = IDT_OFFSET + npx_irq;
239 save_eflags = read_eflags();
241 save_icu1_mask = inb(IO_ICU1 + 1);
242 save_icu2_mask = inb(IO_ICU2 + 1);
243 save_idt_npxintr = idt[npx_intrno];
244 save_idt_npxtrap = idt[16];
245 outb(IO_ICU1 + 1, ~(1 << ICU_IRQ_SLAVE));
246 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
247 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
248 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
249 npx_idt_probeintr = idt[npx_intrno];
251 result = npx_probe1(dev);
253 outb(IO_ICU1 + 1, save_icu1_mask);
254 outb(IO_ICU2 + 1, save_icu2_mask);
255 idt[npx_intrno] = save_idt_npxintr;
256 idt[16] = save_idt_npxtrap;
257 write_eflags(save_eflags);
264 npx_probe1(device_t dev)
272 * Partially reset the coprocessor, if any. Some BIOS's don't reset
273 * it after a warm boot.
275 outb(0xf1, 0); /* full reset on some systems, NOP on others */
276 outb(0xf0, 0); /* clear BUSY# latch */
278 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
279 * instructions. We must set the CR0_MP bit and use the CR0_TS
280 * bit to control the trap, because setting the CR0_EM bit does
281 * not cause WAIT instructions to trap. It's important to trap
282 * WAIT instructions - otherwise the "wait" variants of no-wait
283 * control instructions would degenerate to the "no-wait" variants
284 * after FP context switches but work correctly otherwise. It's
285 * particularly important to trap WAITs when there is no NPX -
286 * otherwise the "wait" variants would always degenerate.
288 * Try setting CR0_NE to get correct error reporting on 486DX's.
289 * Setting it should fail or do nothing on lesser processors.
291 load_cr0(rcr0() | CR0_MP | CR0_NE);
293 * But don't trap while we're probing.
297 * Finish resetting the coprocessor, if any. If there is an error
298 * pending, then we may get a bogus IRQ13, but probeintr() will handle
299 * it OK. Bogus halts have never been observed, but we enabled
300 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
304 device_set_desc(dev, "math processor");
306 * Modern CPUs all have an FPU that uses the INT16 interface
307 * and provide a simple way to verify that, so handle the
308 * common case right away.
310 if (cpu_feature & CPUID_FPU) {
312 npx_ex16 = hw_float = npx_exists = 1;
318 * Don't use fwait here because it might hang.
319 * Don't use fnop here because it usually hangs if there is no FPU.
321 DELAY(1000); /* wait for any IRQ13 */
323 if (npx_intrs_while_probing != 0)
324 kprintf("fninit caused %u bogus npx interrupt(s)\n",
325 npx_intrs_while_probing);
326 if (npx_traps_while_probing != 0)
327 kprintf("fninit caused %u bogus npx trap(s)\n",
328 npx_traps_while_probing);
331 * Check for a status of mostly zero.
335 if ((status & 0xb8ff) == 0) {
337 * Good, now check for a proper control word.
341 if ((control & 0x1f3f) == 0x033f) {
342 hw_float = npx_exists = 1;
344 * We have an npx, now divide by 0 to see if exception
347 control &= ~(1 << 2); /* enable divide by 0 trap */
349 npx_traps_while_probing = npx_intrs_while_probing = 0;
351 if (npx_traps_while_probing != 0) {
353 * Good, exception 16 works.
358 if (npx_intrs_while_probing != 0) {
363 * Bad, we are stuck with IRQ13.
367 * npxattach would be too late to set npx0_imask
369 npx0_imask |= (1 << npx_irq);
372 * We allocate these resources permanently,
373 * so there is no need to keep track of them.
376 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
377 &rid, IO_NPX, IO_NPX,
378 IO_NPXSIZE, RF_ACTIVE);
380 panic("npx: can't get ports");
382 r = bus_alloc_legacy_irq_resource(dev, &rid,
385 panic("npx: can't get IRQ");
386 BUS_SETUP_INTR(device_get_parent(dev),
388 npx_intr, 0, &intr, NULL);
390 panic("npx: can't create intr");
395 * Worse, even IRQ13 is broken. Use emulator.
401 * Probe failed, but we want to get to npxattach to initialize the
402 * emulator and say that it has been installed. XXX handle devices
403 * that aren't really devices better.
409 * Attach routine - announce which it is, and wire into system
412 npx_attach(device_t dev)
416 if (resource_int_value("npx", 0, "flags", &flags) != 0)
420 device_printf(dev, "flags 0x%x ", flags);
422 device_printf(dev, "using IRQ 13 interface\n");
424 #if defined(MATH_EMULATE)
426 if (!(flags & NPX_PREFER_EMULATOR))
427 device_printf(dev, "INT 16 interface\n");
429 device_printf(dev, "FPU exists, but flags request "
431 hw_float = npx_exists = 0;
433 } else if (npx_exists) {
434 device_printf(dev, "error reporting broken; using 387 emulator\n");
435 hw_float = npx_exists = 0;
437 device_printf(dev, "387 emulator\n");
440 device_printf(dev, "INT 16 interface\n");
441 if (flags & NPX_PREFER_EMULATOR) {
442 device_printf(dev, "emulator requested, but none compiled "
443 "into kernel, using FPU\n");
446 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
449 npxinit(__INITIAL_NPXCW__);
451 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
453 * The asm_mmx_*() routines actually use XMM as well, so only
454 * enable them if we have SSE2 and are using FXSR (fxsave/fxrstore).
456 TUNABLE_INT_FETCH("kern.mmxopt", &mmxopt);
457 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
458 (cpu_feature & CPUID_SSE2) &&
459 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
461 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
462 bcopy_vector = (void **)asm_xmm_bcopy;
463 ovbcopy_vector = (void **)asm_xmm_bcopy;
464 memcpy_vector = (void **)asm_xmm_memcpy;
465 kprintf("Using XMM optimized bcopy/copyin/copyout\n");
467 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
470 } else if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
471 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
473 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
474 bcopy_vector = (void **)asm_mmx_bcopy;
475 ovbcopy_vector = (void **)asm_mmx_bcopy;
476 memcpy_vector = (void **)asm_mmx_memcpy;
477 kprintf("Using MMX optimized bcopy/copyin/copyout\n");
479 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
485 return (0); /* XXX unused */
489 * Initialize the floating point unit.
492 npxinit(u_short control)
494 static union savefpu dummy __aligned(16);
499 * fninit has the same h/w bugs as fnsave. Use the detoxified
500 * fnsave to throw away any junk in the fpu. npxsave() initializes
501 * the fpu and sets npxthread = NULL as important side effects.
507 fpusave(curthread->td_savefpu);
508 mdcpu->gd_npxthread = NULL;
514 * Free coprocessor (if we have it).
519 if (curthread == mdcpu->gd_npxthread)
520 npxsave(curthread->td_savefpu);
523 u_int masked_exceptions;
526 curthread->td_savefpu->sv_87.sv_env.en_cw
527 & curthread->td_savefpu->sv_87.sv_env.en_sw & 0x7f;
529 * Log exceptions that would have trapped with the old
530 * control word (overflow, divide by 0, and invalid operand).
532 if (masked_exceptions & 0x0d)
534 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
535 curproc->p_pid, curproc->p_comm, masked_exceptions);
541 * The following mechanism is used to ensure that the FPE_... value
542 * that is passed as a trapcode to the signal handler of the user
543 * process does not have more than one bit set.
545 * Multiple bits may be set if the user process modifies the control
546 * word while a status word bit is already set. While this is a sign
547 * of bad coding, we have no choise than to narrow them down to one
548 * bit, since we must not send a trapcode that is not exactly one of
551 * The mechanism has a static table with 127 entries. Each combination
552 * of the 7 FPU status word exception bits directly translates to a
553 * position in this table, where a single FPE_... value is stored.
554 * This FPE_... value stored there is considered the "most important"
555 * of the exception bits and will be sent as the signal code. The
556 * precedence of the bits is based upon Intel Document "Numerical
557 * Applications", Chapter "Special Computational Situations".
559 * The macro to choose one of these values does these steps: 1) Throw
560 * away status word bits that cannot be masked. 2) Throw away the bits
561 * currently masked in the control word, assuming the user isn't
562 * interested in them anymore. 3) Reinsert status word bit 7 (stack
563 * fault) if it is set, which cannot be masked but must be presered.
564 * 4) Use the remaining bits to point into the trapcode table.
566 * The 6 maskable bits in order of their preference, as stated in the
567 * above referenced Intel manual:
568 * 1 Invalid operation (FP_X_INV)
571 * 1c Operand of unsupported format
573 * 2 QNaN operand (not an exception, irrelavant here)
574 * 3 Any other invalid-operation not mentioned above or zero divide
575 * (FP_X_INV, FP_X_DZ)
576 * 4 Denormal operand (FP_X_DNML)
577 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
578 * 6 Inexact result (FP_X_IMP)
580 static char fpetable[128] = {
582 FPE_FLTINV, /* 1 - INV */
583 FPE_FLTUND, /* 2 - DNML */
584 FPE_FLTINV, /* 3 - INV | DNML */
585 FPE_FLTDIV, /* 4 - DZ */
586 FPE_FLTINV, /* 5 - INV | DZ */
587 FPE_FLTDIV, /* 6 - DNML | DZ */
588 FPE_FLTINV, /* 7 - INV | DNML | DZ */
589 FPE_FLTOVF, /* 8 - OFL */
590 FPE_FLTINV, /* 9 - INV | OFL */
591 FPE_FLTUND, /* A - DNML | OFL */
592 FPE_FLTINV, /* B - INV | DNML | OFL */
593 FPE_FLTDIV, /* C - DZ | OFL */
594 FPE_FLTINV, /* D - INV | DZ | OFL */
595 FPE_FLTDIV, /* E - DNML | DZ | OFL */
596 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
597 FPE_FLTUND, /* 10 - UFL */
598 FPE_FLTINV, /* 11 - INV | UFL */
599 FPE_FLTUND, /* 12 - DNML | UFL */
600 FPE_FLTINV, /* 13 - INV | DNML | UFL */
601 FPE_FLTDIV, /* 14 - DZ | UFL */
602 FPE_FLTINV, /* 15 - INV | DZ | UFL */
603 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
604 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
605 FPE_FLTOVF, /* 18 - OFL | UFL */
606 FPE_FLTINV, /* 19 - INV | OFL | UFL */
607 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
608 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
609 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
610 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
611 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
612 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
613 FPE_FLTRES, /* 20 - IMP */
614 FPE_FLTINV, /* 21 - INV | IMP */
615 FPE_FLTUND, /* 22 - DNML | IMP */
616 FPE_FLTINV, /* 23 - INV | DNML | IMP */
617 FPE_FLTDIV, /* 24 - DZ | IMP */
618 FPE_FLTINV, /* 25 - INV | DZ | IMP */
619 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
620 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
621 FPE_FLTOVF, /* 28 - OFL | IMP */
622 FPE_FLTINV, /* 29 - INV | OFL | IMP */
623 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
624 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
625 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
626 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
627 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
628 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
629 FPE_FLTUND, /* 30 - UFL | IMP */
630 FPE_FLTINV, /* 31 - INV | UFL | IMP */
631 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
632 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
633 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
634 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
635 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
636 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
637 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
638 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
639 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
640 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
641 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
642 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
643 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
644 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
645 FPE_FLTSUB, /* 40 - STK */
646 FPE_FLTSUB, /* 41 - INV | STK */
647 FPE_FLTUND, /* 42 - DNML | STK */
648 FPE_FLTSUB, /* 43 - INV | DNML | STK */
649 FPE_FLTDIV, /* 44 - DZ | STK */
650 FPE_FLTSUB, /* 45 - INV | DZ | STK */
651 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
652 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
653 FPE_FLTOVF, /* 48 - OFL | STK */
654 FPE_FLTSUB, /* 49 - INV | OFL | STK */
655 FPE_FLTUND, /* 4A - DNML | OFL | STK */
656 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
657 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
658 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
659 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
660 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
661 FPE_FLTUND, /* 50 - UFL | STK */
662 FPE_FLTSUB, /* 51 - INV | UFL | STK */
663 FPE_FLTUND, /* 52 - DNML | UFL | STK */
664 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
665 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
666 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
667 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
668 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
669 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
670 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
671 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
672 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
673 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
674 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
675 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
676 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
677 FPE_FLTRES, /* 60 - IMP | STK */
678 FPE_FLTSUB, /* 61 - INV | IMP | STK */
679 FPE_FLTUND, /* 62 - DNML | IMP | STK */
680 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
681 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
682 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
683 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
684 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
685 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
686 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
687 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
688 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
689 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
690 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
691 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
692 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
693 FPE_FLTUND, /* 70 - UFL | IMP | STK */
694 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
695 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
696 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
697 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
698 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
699 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
700 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
701 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
702 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
703 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
704 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
705 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
706 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
707 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
708 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
712 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
714 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
715 * depend on longjmp() restoring a usable state. Restoring the state
716 * or examining it might fail if we didn't clear exceptions.
718 * The error code chosen will be one of the FPE_... macros. It will be
719 * sent as the second argument to old BSD-style signal handlers and as
720 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
722 * XXX the FP state is not preserved across signal handlers. So signal
723 * handlers cannot afford to do FP unless they preserve the state or
724 * longjmp() out. Both preserving the state and longjmp()ing may be
725 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
726 * solution for signals other than SIGFPE.
728 * The MP lock is not held on entry (see i386/i386/exception.s) and
729 * should not be held on exit. Interrupts are enabled. We must enter
730 * a critical section to stabilize the FP system and prevent an interrupt
731 * or preemption from changing the FP state out from under us.
734 npx_intr(void *dummy)
739 struct intrframe *frame;
744 * This exception can only occur with CR0_TS clear, otherwise we
745 * would get a DNA exception. However, since interrupts were
746 * enabled a preemption could have sneaked in and used the FP system
747 * before we entered our critical section. If that occured, the
748 * TS bit will be set and npxthread will be NULL.
750 if (npx_exists && (rcr0() & CR0_TS)) {
751 KASSERT(mdcpu->gd_npxthread == NULL, ("gd_npxthread was %p with TS set!", mdcpu->gd_npxthread));
756 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
758 kprintf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
759 mdcpu->gd_npxthread, curthread, npx_exists);
760 panic("npxintr from nowhere");
762 if (mdcpu->gd_npxthread != curthread) {
764 kprintf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
765 mdcpu->gd_npxthread, curthread, npx_exists);
766 panic("npxintr from non-current process");
777 * Pass exception to process.
779 frame = (struct intrframe *)&dummy; /* XXX */
780 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
782 * Interrupt is essentially a trap, so we can afford to call
783 * the SIGFPE handler (if any) as soon as the interrupt
786 * XXX little or nothing is gained from this, and plenty is
787 * lost - the interrupt frame has to contain the trap frame
788 * (this is otherwise only necessary for the rescheduling trap
789 * in doreti, and the frame for that could easily be set up
790 * just before it is used).
792 curthread->td_lwp->lwp_md.md_regs = INTR_TO_TRAPFRAME(frame);
794 * Encode the appropriate code for detailed information on
798 fpetable[(status & ~control & 0x3f) | (status & 0x40)];
799 trapsignal(curthread->td_lwp, SIGFPE, code);
802 * Nested interrupt. These losers occur when:
803 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
804 * o immediately after an fnsave or frstor of an
806 * o a couple of 386 instructions after
807 * "fstpl _memvar" causes a stack overflow.
808 * These are especially nasty when combined with a
810 * o an IRQ13 occurs at the same time as another higher-
811 * priority interrupt.
813 * Treat them like a true async interrupt.
815 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
822 * Implement the device not available (DNA) exception. gd_npxthread had
823 * better be NULL. Restore the current thread's FP state and set gd_npxthread
826 * Interrupts are enabled and preemption can occur. Enter a critical
827 * section to stabilize the FP state.
832 thread_t td = curthread;
837 if (mdcpu->gd_npxthread != NULL) {
838 kprintf("npxdna: npxthread = %p, curthread = %p\n",
839 mdcpu->gd_npxthread, td);
844 * Setup the initial saved state if the thread has never before
845 * used the FP unit. This also occurs when a thread pushes a
846 * signal handler and uses FP in the handler.
848 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) {
849 td->td_flags |= TDF_USINGFP;
850 npxinit(__INITIAL_NPXCW__);
855 * The setting of gd_npxthread and the call to fpurstor() must not
856 * be preempted by an interrupt thread or we will take an npxdna
857 * trap and potentially save our current fpstate (which is garbage)
858 * and then restore the garbage rather then the originally saved
864 * Record new context early in case frstor causes an IRQ13.
866 mdcpu->gd_npxthread = td;
868 * The following frstor may cause an IRQ13 when the state being
869 * restored has a pending error. The error will appear to have been
870 * triggered by the current (npx) user instruction even when that
871 * instruction is a no-wait instruction that should not trigger an
872 * error (e.g., fnclex). On at least one 486 system all of the
873 * no-wait instructions are broken the same as frstor, so our
874 * treatment does not amplify the breakage. On at least one
875 * 386/Cyrix 387 system, fnclex works correctly while frstor and
876 * fnsave are broken, so our treatment breaks fnclex if it is the
877 * first FPU instruction after a context switch.
879 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
880 #ifndef CPU_DISABLE_SSE
884 krateprintf(&badfprate,
885 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n",
886 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit);
887 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
888 lwpsignal(curproc, curthread->td_lwp, SIGFPE);
890 fpurstor(td->td_savefpu);
897 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
898 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
899 * any IRQ13 to be handled immediately, and then ignore it. This routine is
900 * often called at splhigh so it must not use many system services. In
901 * particular, it's much easier to install a special handler than to
902 * guarantee that it's safe to use npxintr() and its supporting code.
904 * WARNING! This call is made during a switch and the MP lock will be
905 * setup for the new target thread rather then the current thread, so we
906 * cannot do anything here that depends on the *_mplock() functions as
907 * we may trip over their assertions.
909 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
910 * kernel will always assume that the FP state is 'safe' (will not cause
911 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
912 * setup a custom save area before actually using the FP unit, but it will
913 * not bother calling fninit. This greatly improves kernel performance when
914 * it wishes to use the FP unit.
917 npxsave(union savefpu *addr)
919 #if defined(SMP) || !defined(CPU_DISABLE_SSE)
924 mdcpu->gd_npxthread = NULL;
929 #else /* !SMP and CPU_DISABLE_SSE */
933 u_char old_icu1_mask;
934 u_char old_icu2_mask;
935 struct gate_descriptor save_idt_npxintr;
938 save_eflags = read_eflags();
940 old_icu1_mask = inb(IO_ICU1 + 1);
941 old_icu2_mask = inb(IO_ICU2 + 1);
942 save_idt_npxintr = idt[npx_intrno];
943 outb(IO_ICU1 + 1, old_icu1_mask & ~((1 << ICU_IRQ_SLAVE) | npx0_imask));
944 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
945 idt[npx_intrno] = npx_idt_probeintr;
951 mdcpu->gd_npxthread = NULL;
953 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
954 icu2_mask = inb(IO_ICU2 + 1);
956 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
958 (icu2_mask & ~(npx0_imask >> 8))
959 | (old_icu2_mask & (npx0_imask >> 8)));
960 idt[npx_intrno] = save_idt_npxintr;
961 write_eflags(save_eflags); /* back to usual state */
967 fpusave(union savefpu *addr)
969 #ifndef CPU_DISABLE_SSE
978 * Save the FP state to the mcontext structure.
980 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs,
981 * then it MUST be 16-byte aligned. Currently this is not guarenteed.
984 npxpush(mcontext_t *mctx)
986 thread_t td = curthread;
988 KKASSERT((td->td_flags & TDF_KERNELFP) == 0);
990 if (td->td_flags & TDF_USINGFP) {
991 if (mdcpu->gd_npxthread == td) {
993 * XXX Note: This is a bit inefficient if the signal
994 * handler uses floating point, extra faults will
997 mctx->mc_ownedfp = _MC_FPOWNED_FPU;
998 npxsave(td->td_savefpu);
1000 mctx->mc_ownedfp = _MC_FPOWNED_PCB;
1002 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs));
1003 td->td_flags &= ~TDF_USINGFP;
1005 #ifndef CPU_DISABLE_SSE
1006 (cpu_fxsr) ? _MC_FPFMT_XMM :
1010 mctx->mc_ownedfp = _MC_FPOWNED_NONE;
1011 mctx->mc_fpformat = _MC_FPFMT_NODEV;
1016 * Restore the FP state from the mcontext structure.
1019 npxpop(mcontext_t *mctx)
1021 thread_t td = curthread;
1023 KKASSERT((td->td_flags & TDF_KERNELFP) == 0);
1025 switch(mctx->mc_ownedfp) {
1026 case _MC_FPOWNED_NONE:
1028 * If the signal handler used the FP unit but the interrupted
1029 * code did not, release the FP unit. Clear TDF_USINGFP will
1030 * force the FP unit to reinit so the interrupted code sees
1033 if (td->td_flags & TDF_USINGFP) {
1034 if (td == mdcpu->gd_npxthread)
1035 npxsave(td->td_savefpu);
1036 td->td_flags &= ~TDF_USINGFP;
1039 case _MC_FPOWNED_FPU:
1040 case _MC_FPOWNED_PCB:
1042 * Clear ownership of the FP unit and restore our saved state.
1044 * NOTE: The signal handler may have set-up some FP state and
1045 * enabled the FP unit, so we have to restore no matter what.
1047 * XXX: This is bit inefficient, if the code being returned
1048 * to is actively using the FP this results in multiple
1051 * WARNING: The saved state was exposed to userland and may
1052 * have to be sanitized to avoid a GP fault in the kernel.
1054 if (td == mdcpu->gd_npxthread)
1055 npxsave(td->td_savefpu);
1056 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu));
1057 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF)
1058 #ifndef CPU_DISABLE_SSE
1062 krateprintf(&badfprate,
1063 "pid %d (%s) signal return from user: "
1064 "illegal FP MXCSR %08x\n",
1066 td->td_proc->p_comm,
1067 td->td_savefpu->sv_xmm.sv_env.en_mxcsr);
1068 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF;
1070 td->td_flags |= TDF_USINGFP;
1075 #ifndef CPU_DISABLE_SSE
1077 * On AuthenticAMD processors, the fxrstor instruction does not restore
1078 * the x87's stored last instruction pointer, last data pointer, and last
1079 * opcode values, except in the rare case in which the exception summary
1080 * (ES) bit in the x87 status word is set to 1.
1082 * In order to avoid leaking this information across processes, we clean
1083 * these values by performing a dummy load before executing fxrstor().
1085 static double dummy_variable = 0.0;
1087 fpu_clean_state(void)
1092 * Clear the ES bit in the x87 status word if it is currently
1093 * set, in order to avoid causing a fault in the upcoming load.
1100 * Load the dummy variable into the x87 stack. This mangles
1101 * the x87 stack, but we don't care since we're about to call
1104 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
1106 #endif /* CPU_DISABLE_SSE */
1109 fpurstor(union savefpu *addr)
1111 #ifndef CPU_DISABLE_SSE
1124 * Because npx is a static device that always exists under nexus,
1125 * and is not scanned by the nexus device, we need an identify
1126 * function to install the device.
1128 static device_method_t npx_methods[] = {
1129 /* Device interface */
1130 DEVMETHOD(device_identify, bus_generic_identify),
1131 DEVMETHOD(device_probe, npx_probe),
1132 DEVMETHOD(device_attach, npx_attach),
1133 DEVMETHOD(device_detach, bus_generic_detach),
1134 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1135 DEVMETHOD(device_suspend, bus_generic_suspend),
1136 DEVMETHOD(device_resume, bus_generic_resume),
1141 static driver_t npx_driver = {
1147 static devclass_t npx_devclass;
1150 * We prefer to attach to the root nexus so that the usual case (exception 16)
1151 * doesn't describe the processor as being `on isa'.
1153 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, NULL, NULL);