2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
71 #include <sys/param.h>
73 #include <sys/endian.h>
74 #include <sys/interrupt.h>
75 #include <sys/kernel.h>
77 #include <sys/malloc.h>
81 #include <sys/serialize.h>
82 #include <sys/serialize2.h>
83 #include <sys/socket.h>
84 #include <sys/sockio.h>
85 #include <sys/sysctl.h>
86 #include <sys/systm.h>
89 #include <net/ethernet.h>
91 #include <net/if_arp.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
94 #include <net/ifq_var.h>
95 #include <net/toeplitz.h>
96 #include <net/toeplitz2.h>
97 #include <net/vlan/if_vlan_var.h>
98 #include <net/vlan/if_vlan_ether.h>
99 #include <net/if_poll.h>
101 #include <netinet/in_systm.h>
102 #include <netinet/in.h>
103 #include <netinet/ip.h>
104 #include <netinet/tcp.h>
105 #include <netinet/udp.h>
107 #include <bus/pci/pcivar.h>
108 #include <bus/pci/pcireg.h>
110 #include <dev/netif/ig_hal/e1000_api.h>
111 #include <dev/netif/ig_hal/e1000_82571.h>
112 #include <dev/netif/emx/if_emx.h>
115 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
117 if (sc->rss_debug >= lvl) \
118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
120 #else /* !EMX_RSS_DEBUG */
121 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
122 #endif /* EMX_RSS_DEBUG */
124 #define EMX_NAME "Intel(R) PRO/1000 "
126 #define EMX_DEVICE(id) \
127 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
128 #define EMX_DEVICE_NULL { 0, 0, NULL }
130 static const struct emx_device {
135 EMX_DEVICE(82571EB_COPPER),
136 EMX_DEVICE(82571EB_FIBER),
137 EMX_DEVICE(82571EB_SERDES),
138 EMX_DEVICE(82571EB_SERDES_DUAL),
139 EMX_DEVICE(82571EB_SERDES_QUAD),
140 EMX_DEVICE(82571EB_QUAD_COPPER),
141 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
142 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
143 EMX_DEVICE(82571EB_QUAD_FIBER),
144 EMX_DEVICE(82571PT_QUAD_COPPER),
146 EMX_DEVICE(82572EI_COPPER),
147 EMX_DEVICE(82572EI_FIBER),
148 EMX_DEVICE(82572EI_SERDES),
152 EMX_DEVICE(82573E_IAMT),
155 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
156 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
157 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
163 /* required last entry */
167 static int emx_probe(device_t);
168 static int emx_attach(device_t);
169 static int emx_detach(device_t);
170 static int emx_shutdown(device_t);
171 static int emx_suspend(device_t);
172 static int emx_resume(device_t);
174 static void emx_init(void *);
175 static void emx_stop(struct emx_softc *);
176 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
177 static void emx_start(struct ifnet *);
179 static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
181 static void emx_watchdog(struct ifnet *);
182 static void emx_media_status(struct ifnet *, struct ifmediareq *);
183 static int emx_media_change(struct ifnet *);
184 static void emx_timer(void *);
185 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
186 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
187 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
189 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
193 static void emx_intr(void *);
194 static void emx_rxeof(struct emx_softc *, int, int);
195 static void emx_txeof(struct emx_softc *);
196 static void emx_tx_collect(struct emx_softc *);
197 static void emx_tx_purge(struct emx_softc *);
198 static void emx_enable_intr(struct emx_softc *);
199 static void emx_disable_intr(struct emx_softc *);
201 static int emx_dma_alloc(struct emx_softc *);
202 static void emx_dma_free(struct emx_softc *);
203 static void emx_init_tx_ring(struct emx_softc *);
204 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
205 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
206 static int emx_create_tx_ring(struct emx_softc *);
207 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
208 static void emx_destroy_tx_ring(struct emx_softc *, int);
209 static void emx_destroy_rx_ring(struct emx_softc *,
210 struct emx_rxdata *, int);
211 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
212 static int emx_encap(struct emx_softc *, struct mbuf **);
213 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
214 static int emx_txcsum(struct emx_softc *, struct mbuf *,
215 uint32_t *, uint32_t *);
217 static int emx_is_valid_eaddr(const uint8_t *);
218 static int emx_reset(struct emx_softc *);
219 static void emx_setup_ifp(struct emx_softc *);
220 static void emx_init_tx_unit(struct emx_softc *);
221 static void emx_init_rx_unit(struct emx_softc *);
222 static void emx_update_stats(struct emx_softc *);
223 static void emx_set_promisc(struct emx_softc *);
224 static void emx_disable_promisc(struct emx_softc *);
225 static void emx_set_multi(struct emx_softc *);
226 static void emx_update_link_status(struct emx_softc *);
227 static void emx_smartspeed(struct emx_softc *);
228 static void emx_set_itr(struct emx_softc *, uint32_t);
230 static void emx_print_debug_info(struct emx_softc *);
231 static void emx_print_nvm_info(struct emx_softc *);
232 static void emx_print_hw_stats(struct emx_softc *);
234 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
235 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
236 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
237 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
238 static void emx_add_sysctl(struct emx_softc *);
240 static void emx_serialize_skipmain(struct emx_softc *);
241 static void emx_deserialize_skipmain(struct emx_softc *);
243 /* Management and WOL Support */
244 static void emx_get_mgmt(struct emx_softc *);
245 static void emx_rel_mgmt(struct emx_softc *);
246 static void emx_get_hw_control(struct emx_softc *);
247 static void emx_rel_hw_control(struct emx_softc *);
248 static void emx_enable_wol(device_t);
250 static device_method_t emx_methods[] = {
251 /* Device interface */
252 DEVMETHOD(device_probe, emx_probe),
253 DEVMETHOD(device_attach, emx_attach),
254 DEVMETHOD(device_detach, emx_detach),
255 DEVMETHOD(device_shutdown, emx_shutdown),
256 DEVMETHOD(device_suspend, emx_suspend),
257 DEVMETHOD(device_resume, emx_resume),
261 static driver_t emx_driver = {
264 sizeof(struct emx_softc),
267 static devclass_t emx_devclass;
269 DECLARE_DUMMY_MODULE(if_emx);
270 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
271 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
276 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
277 static int emx_rxd = EMX_DEFAULT_RXD;
278 static int emx_txd = EMX_DEFAULT_TXD;
279 static int emx_smart_pwr_down = FALSE;
281 /* Controls whether promiscuous also shows bad packets */
282 static int emx_debug_sbp = FALSE;
284 static int emx_82573_workaround = TRUE;
286 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
287 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
288 TUNABLE_INT("hw.emx.txd", &emx_txd);
289 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
290 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
291 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
293 /* Global used in WOL setup with multiport cards */
294 static int emx_global_quad_port_a = 0;
296 /* Set this to one to display debug statistics */
297 static int emx_display_debug_stats = 0;
299 #if !defined(KTR_IF_EMX)
300 #define KTR_IF_EMX KTR_ALL
302 KTR_INFO_MASTER(if_emx);
303 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin", 0);
304 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end", 0);
305 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet", 0);
306 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet", 0);
307 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean", 0);
308 #define logif(name) KTR_LOG(if_emx_ ## name)
311 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
313 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
314 /* DD bit must be cleared */
315 rxd->rxd_staterr = 0;
319 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
321 /* Ignore Checksum bit is set */
322 if (staterr & E1000_RXD_STAT_IXSM)
325 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
327 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
329 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
330 E1000_RXD_STAT_TCPCS) {
331 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
333 CSUM_FRAG_NOT_CHECKED;
334 mp->m_pkthdr.csum_data = htons(0xffff);
338 static __inline struct pktinfo *
339 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
340 uint32_t mrq, uint32_t hash, uint32_t staterr)
342 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
343 case EMX_RXDMRQ_IPV4_TCP:
344 pi->pi_netisr = NETISR_IP;
346 pi->pi_l3proto = IPPROTO_TCP;
349 case EMX_RXDMRQ_IPV6_TCP:
350 pi->pi_netisr = NETISR_IPV6;
352 pi->pi_l3proto = IPPROTO_TCP;
355 case EMX_RXDMRQ_IPV4:
356 if (staterr & E1000_RXD_STAT_IXSM)
360 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
361 E1000_RXD_STAT_TCPCS) {
362 pi->pi_netisr = NETISR_IP;
364 pi->pi_l3proto = IPPROTO_UDP;
372 m->m_flags |= M_HASH;
373 m->m_pkthdr.hash = toeplitz_hash(hash);
378 emx_probe(device_t dev)
380 const struct emx_device *d;
383 vid = pci_get_vendor(dev);
384 did = pci_get_device(dev);
386 for (d = emx_devices; d->desc != NULL; ++d) {
387 if (vid == d->vid && did == d->did) {
388 device_set_desc(dev, d->desc);
389 device_set_async_attach(dev, TRUE);
397 emx_attach(device_t dev)
399 struct emx_softc *sc = device_get_softc(dev);
400 struct ifnet *ifp = &sc->arpcom.ac_if;
402 uint16_t eeprom_data, device_id, apme_mask;
404 lwkt_serialize_init(&sc->main_serialize);
405 lwkt_serialize_init(&sc->tx_serialize);
406 for (i = 0; i < EMX_NRX_RING; ++i)
407 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
410 sc->serializes[i++] = &sc->main_serialize;
411 sc->serializes[i++] = &sc->tx_serialize;
412 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
413 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
414 KKASSERT(i == EMX_NSERIALIZE);
416 callout_init(&sc->timer);
418 sc->dev = sc->osdep.dev = dev;
421 * Determine hardware and mac type
423 sc->hw.vendor_id = pci_get_vendor(dev);
424 sc->hw.device_id = pci_get_device(dev);
425 sc->hw.revision_id = pci_get_revid(dev);
426 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
427 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
429 if (e1000_set_mac_type(&sc->hw))
432 /* Enable bus mastering */
433 pci_enable_busmaster(dev);
438 sc->memory_rid = EMX_BAR_MEM;
439 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
440 &sc->memory_rid, RF_ACTIVE);
441 if (sc->memory == NULL) {
442 device_printf(dev, "Unable to allocate bus resource: memory\n");
446 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
447 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
449 /* XXX This is quite goofy, it is not actually used */
450 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
456 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
457 RF_SHAREABLE | RF_ACTIVE);
458 if (sc->intr_res == NULL) {
459 device_printf(dev, "Unable to allocate bus resource: "
465 /* Save PCI command register for Shared Code */
466 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
467 sc->hw.back = &sc->osdep;
469 /* Do Shared Code initialization */
470 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
471 device_printf(dev, "Setup of Shared code failed\n");
475 e1000_get_bus_info(&sc->hw);
477 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
478 sc->hw.phy.autoneg_wait_to_complete = FALSE;
479 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
482 * Interrupt throttle rate
484 if (emx_int_throttle_ceil == 0) {
485 sc->int_throttle_ceil = 0;
487 int throttle = emx_int_throttle_ceil;
490 throttle = EMX_DEFAULT_ITR;
492 /* Recalculate the tunable value to get the exact frequency. */
493 throttle = 1000000000 / 256 / throttle;
495 /* Upper 16bits of ITR is reserved and should be zero */
496 if (throttle & 0xffff0000)
497 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
499 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
502 e1000_init_script_state_82541(&sc->hw, TRUE);
503 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
506 if (sc->hw.phy.media_type == e1000_media_type_copper) {
507 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
508 sc->hw.phy.disable_polarity_correction = FALSE;
509 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
512 /* Set the frame limits assuming standard ethernet sized frames. */
513 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
514 sc->min_frame_size = ETHER_MIN_LEN;
516 /* This controls when hardware reports transmit completion status. */
517 sc->hw.mac.report_tx_early = 1;
519 /* Calculate # of RX rings */
521 sc->rx_ring_cnt = EMX_NRX_RING;
524 sc->rx_ring_inuse = sc->rx_ring_cnt;
526 /* Allocate RX/TX rings' busdma(9) stuffs */
527 error = emx_dma_alloc(sc);
531 /* Allocate multicast array memory. */
532 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
535 /* Indicate SOL/IDER usage */
536 if (e1000_check_reset_block(&sc->hw)) {
538 "PHY reset is blocked due to SOL/IDER session.\n");
542 * Start from a known state, this is important in reading the
543 * nvm and mac from that.
545 e1000_reset_hw(&sc->hw);
547 /* Make sure we have a good EEPROM before we read from it */
548 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
550 * Some PCI-E parts fail the first check due to
551 * the link being in sleep state, call it again,
552 * if it fails a second time its a real issue.
554 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
556 "The EEPROM Checksum Is Not Valid\n");
562 /* Copy the permanent MAC address out of the EEPROM */
563 if (e1000_read_mac_addr(&sc->hw) < 0) {
564 device_printf(dev, "EEPROM read error while reading MAC"
569 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
570 device_printf(dev, "Invalid MAC address\n");
575 /* Determine if we have to control management hardware */
576 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
581 apme_mask = EMX_EEPROM_APME;
583 switch (sc->hw.mac.type) {
590 case e1000_80003es2lan:
591 if (sc->hw.bus.func == 1) {
592 e1000_read_nvm(&sc->hw,
593 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
595 e1000_read_nvm(&sc->hw,
596 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
601 e1000_read_nvm(&sc->hw,
602 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
605 if (eeprom_data & apme_mask)
606 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
609 * We have the eeprom settings, now apply the special cases
610 * where the eeprom may be wrong or the board won't support
611 * wake on lan on a particular port
613 device_id = pci_get_device(dev);
615 case E1000_DEV_ID_82571EB_FIBER:
617 * Wake events only supported on port A for dual fiber
618 * regardless of eeprom setting
620 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
625 case E1000_DEV_ID_82571EB_QUAD_COPPER:
626 case E1000_DEV_ID_82571EB_QUAD_FIBER:
627 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
628 /* if quad port sc, disable WoL on all but port A */
629 if (emx_global_quad_port_a != 0)
631 /* Reset for multiple quad port adapters */
632 if (++emx_global_quad_port_a == 4)
633 emx_global_quad_port_a = 0;
637 /* XXX disable wol */
640 /* Setup OS specific network interface */
643 /* Add sysctl tree, must after em_setup_ifp() */
646 /* Reset the hardware */
647 error = emx_reset(sc);
649 device_printf(dev, "Unable to reset the hardware\n");
653 /* Initialize statistics */
654 emx_update_stats(sc);
656 sc->hw.mac.get_link_status = 1;
657 emx_update_link_status(sc);
659 sc->spare_tx_desc = EMX_TX_SPARE;
662 * Keep following relationship between spare_tx_desc, oact_tx_desc
664 * (spare_tx_desc + EMX_TX_RESERVED) <=
665 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
667 sc->oact_tx_desc = sc->num_tx_desc / 8;
668 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
669 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
670 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
671 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
673 sc->tx_int_nsegs = sc->num_tx_desc / 16;
674 if (sc->tx_int_nsegs < sc->oact_tx_desc)
675 sc->tx_int_nsegs = sc->oact_tx_desc;
677 /* Non-AMT based hardware can now take control from firmware */
678 if (sc->has_manage && !sc->has_amt)
679 emx_get_hw_control(sc);
681 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
682 &sc->intr_tag, &sc->main_serialize);
684 device_printf(dev, "Failed to register interrupt handler");
685 ether_ifdetach(&sc->arpcom.ac_if);
689 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->intr_res));
690 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
698 emx_detach(device_t dev)
700 struct emx_softc *sc = device_get_softc(dev);
702 if (device_is_attached(dev)) {
703 struct ifnet *ifp = &sc->arpcom.ac_if;
705 ifnet_serialize_all(ifp);
709 e1000_phy_hw_reset(&sc->hw);
712 emx_rel_hw_control(sc);
715 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
716 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
720 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
722 ifnet_deserialize_all(ifp);
726 emx_rel_hw_control(sc);
728 bus_generic_detach(dev);
730 if (sc->intr_res != NULL) {
731 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
735 if (sc->memory != NULL) {
736 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
742 /* Free sysctl tree */
743 if (sc->sysctl_tree != NULL)
744 sysctl_ctx_free(&sc->sysctl_ctx);
750 emx_shutdown(device_t dev)
752 return emx_suspend(dev);
756 emx_suspend(device_t dev)
758 struct emx_softc *sc = device_get_softc(dev);
759 struct ifnet *ifp = &sc->arpcom.ac_if;
761 ifnet_serialize_all(ifp);
766 emx_rel_hw_control(sc);
769 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
770 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
774 ifnet_deserialize_all(ifp);
776 return bus_generic_suspend(dev);
780 emx_resume(device_t dev)
782 struct emx_softc *sc = device_get_softc(dev);
783 struct ifnet *ifp = &sc->arpcom.ac_if;
785 ifnet_serialize_all(ifp);
791 ifnet_deserialize_all(ifp);
793 return bus_generic_resume(dev);
797 emx_start(struct ifnet *ifp)
799 struct emx_softc *sc = ifp->if_softc;
802 ASSERT_SERIALIZED(&sc->tx_serialize);
804 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
807 if (!sc->link_active) {
808 ifq_purge(&ifp->if_snd);
812 while (!ifq_is_empty(&ifp->if_snd)) {
813 /* Now do we at least have a minimal? */
814 if (EMX_IS_OACTIVE(sc)) {
816 if (EMX_IS_OACTIVE(sc)) {
817 ifp->if_flags |= IFF_OACTIVE;
818 sc->no_tx_desc_avail1++;
824 m_head = ifq_dequeue(&ifp->if_snd, NULL);
828 if (emx_encap(sc, &m_head)) {
834 /* Send a copy of the frame to the BPF listener */
835 ETHER_BPF_MTAP(ifp, m_head);
837 /* Set timeout in case hardware has problems transmitting. */
838 ifp->if_timer = EMX_TX_TIMEOUT;
843 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
845 struct emx_softc *sc = ifp->if_softc;
846 struct ifreq *ifr = (struct ifreq *)data;
847 uint16_t eeprom_data = 0;
848 int max_frame_size, mask, reinit;
851 ASSERT_IFNET_SERIALIZED_ALL(ifp);
855 switch (sc->hw.mac.type) {
858 * 82573 only supports jumbo frames
859 * if ASPM is disabled.
861 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
863 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
864 max_frame_size = ETHER_MAX_LEN;
869 /* Limit Jumbo Frame size */
873 case e1000_80003es2lan:
874 max_frame_size = 9234;
878 max_frame_size = MAX_JUMBO_FRAME_SIZE;
881 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
887 ifp->if_mtu = ifr->ifr_mtu;
888 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
891 if (ifp->if_flags & IFF_RUNNING)
896 if (ifp->if_flags & IFF_UP) {
897 if ((ifp->if_flags & IFF_RUNNING)) {
898 if ((ifp->if_flags ^ sc->if_flags) &
899 (IFF_PROMISC | IFF_ALLMULTI)) {
900 emx_disable_promisc(sc);
906 } else if (ifp->if_flags & IFF_RUNNING) {
909 sc->if_flags = ifp->if_flags;
914 if (ifp->if_flags & IFF_RUNNING) {
915 emx_disable_intr(sc);
918 if (!(ifp->if_flags & IFF_NPOLLING))
925 /* Check SOL/IDER usage */
926 if (e1000_check_reset_block(&sc->hw)) {
927 device_printf(sc->dev, "Media change is"
928 " blocked due to SOL/IDER session.\n");
934 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
939 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
940 if (mask & IFCAP_HWCSUM) {
941 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
944 if (mask & IFCAP_VLAN_HWTAGGING) {
945 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
948 if (mask & IFCAP_RSS) {
949 ifp->if_capenable ^= IFCAP_RSS;
952 if (reinit && (ifp->if_flags & IFF_RUNNING))
957 error = ether_ioctl(ifp, command, data);
964 emx_watchdog(struct ifnet *ifp)
966 struct emx_softc *sc = ifp->if_softc;
968 ASSERT_IFNET_SERIALIZED_ALL(ifp);
971 * The timer is set to 5 every time start queues a packet.
972 * Then txeof keeps resetting it as long as it cleans at
973 * least one descriptor.
974 * Finally, anytime all descriptors are clean the timer is
978 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
979 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
981 * If we reach here, all TX jobs are completed and
982 * the TX engine should have been idled for some time.
983 * We don't need to call if_devstart() here.
985 ifp->if_flags &= ~IFF_OACTIVE;
991 * If we are in this routine because of pause frames, then
992 * don't reset the hardware.
994 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
995 ifp->if_timer = EMX_TX_TIMEOUT;
999 if (e1000_check_for_link(&sc->hw) == 0)
1000 if_printf(ifp, "watchdog timeout -- resetting\n");
1003 sc->watchdog_events++;
1007 if (!ifq_is_empty(&ifp->if_snd))
1014 struct emx_softc *sc = xsc;
1015 struct ifnet *ifp = &sc->arpcom.ac_if;
1016 device_t dev = sc->dev;
1020 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1025 * Packet Buffer Allocation (PBA)
1026 * Writing PBA sets the receive portion of the buffer
1027 * the remainder is used for the transmit buffer.
1029 switch (sc->hw.mac.type) {
1030 /* Total Packet Buffer on these is 48K */
1033 case e1000_80003es2lan:
1034 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1037 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1038 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1042 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1046 /* Devices before 82547 had a Packet Buffer of 64K. */
1047 if (sc->max_frame_size > 8192)
1048 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1050 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1052 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1054 /* Get the latest mac address, User can use a LAA */
1055 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1057 /* Put the address into the Receive Address Array */
1058 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1061 * With the 82571 sc, RAR[0] may be overwritten
1062 * when the other port is reset, we make a duplicate
1063 * in RAR[14] for that eventuality, this assures
1064 * the interface continues to function.
1066 if (sc->hw.mac.type == e1000_82571) {
1067 e1000_set_laa_state_82571(&sc->hw, TRUE);
1068 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1069 E1000_RAR_ENTRIES - 1);
1072 /* Initialize the hardware */
1073 if (emx_reset(sc)) {
1074 device_printf(dev, "Unable to reset the hardware\n");
1075 /* XXX emx_stop()? */
1078 emx_update_link_status(sc);
1080 /* Setup VLAN support, basic and offload if available */
1081 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1083 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1086 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1087 ctrl |= E1000_CTRL_VME;
1088 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1091 /* Set hardware offload abilities */
1092 if (ifp->if_capenable & IFCAP_TXCSUM)
1093 ifp->if_hwassist = EMX_CSUM_FEATURES;
1095 ifp->if_hwassist = 0;
1097 /* Configure for OS presence */
1100 /* Prepare transmit descriptors and buffers */
1101 emx_init_tx_ring(sc);
1102 emx_init_tx_unit(sc);
1104 /* Setup Multicast table */
1108 * Adjust # of RX ring to be used based on IFCAP_RSS
1110 if (ifp->if_capenable & IFCAP_RSS)
1111 sc->rx_ring_inuse = sc->rx_ring_cnt;
1113 sc->rx_ring_inuse = 1;
1115 /* Prepare receive descriptors and buffers */
1116 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1117 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1119 "Could not setup receive structures\n");
1124 emx_init_rx_unit(sc);
1126 /* Don't lose promiscuous settings */
1127 emx_set_promisc(sc);
1129 ifp->if_flags |= IFF_RUNNING;
1130 ifp->if_flags &= ~IFF_OACTIVE;
1132 callout_reset(&sc->timer, hz, emx_timer, sc);
1133 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1135 /* MSI/X configuration for 82574 */
1136 if (sc->hw.mac.type == e1000_82574) {
1139 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1140 tmp |= E1000_CTRL_EXT_PBA_CLR;
1141 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1144 * Set the IVAR - interrupt vector routing.
1145 * Each nibble represents a vector, high bit
1146 * is enable, other 3 bits are the MSIX table
1147 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1148 * Link (other) to 2, hence the magic number.
1150 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1153 #ifdef IFPOLL_ENABLE
1155 * Only enable interrupts if we are not polling, make sure
1156 * they are off otherwise.
1158 if (ifp->if_flags & IFF_NPOLLING)
1159 emx_disable_intr(sc);
1161 #endif /* IFPOLL_ENABLE */
1162 emx_enable_intr(sc);
1164 /* AMT based hardware can now take control from firmware */
1165 if (sc->has_manage && sc->has_amt)
1166 emx_get_hw_control(sc);
1168 /* Don't reset the phy next time init gets called */
1169 sc->hw.phy.reset_disable = TRUE;
1175 struct emx_softc *sc = xsc;
1176 struct ifnet *ifp = &sc->arpcom.ac_if;
1180 ASSERT_SERIALIZED(&sc->main_serialize);
1182 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1184 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1190 * XXX: some laptops trigger several spurious interrupts
1191 * on emx(4) when in the resume cycle. The ICR register
1192 * reports all-ones value in this case. Processing such
1193 * interrupts would lead to a freeze. I don't know why.
1195 if (reg_icr == 0xffffffff) {
1200 if (ifp->if_flags & IFF_RUNNING) {
1202 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1205 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1206 lwkt_serialize_enter(
1207 &sc->rx_data[i].rx_serialize);
1208 emx_rxeof(sc, i, -1);
1209 lwkt_serialize_exit(
1210 &sc->rx_data[i].rx_serialize);
1213 if (reg_icr & E1000_ICR_TXDW) {
1214 lwkt_serialize_enter(&sc->tx_serialize);
1216 if (!ifq_is_empty(&ifp->if_snd))
1218 lwkt_serialize_exit(&sc->tx_serialize);
1222 /* Link status change */
1223 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1224 emx_serialize_skipmain(sc);
1226 callout_stop(&sc->timer);
1227 sc->hw.mac.get_link_status = 1;
1228 emx_update_link_status(sc);
1230 /* Deal with TX cruft when link lost */
1233 callout_reset(&sc->timer, hz, emx_timer, sc);
1235 emx_deserialize_skipmain(sc);
1238 if (reg_icr & E1000_ICR_RXO)
1245 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1247 struct emx_softc *sc = ifp->if_softc;
1249 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1251 emx_update_link_status(sc);
1253 ifmr->ifm_status = IFM_AVALID;
1254 ifmr->ifm_active = IFM_ETHER;
1256 if (!sc->link_active)
1259 ifmr->ifm_status |= IFM_ACTIVE;
1261 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1262 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1263 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1265 switch (sc->link_speed) {
1267 ifmr->ifm_active |= IFM_10_T;
1270 ifmr->ifm_active |= IFM_100_TX;
1274 ifmr->ifm_active |= IFM_1000_T;
1277 if (sc->link_duplex == FULL_DUPLEX)
1278 ifmr->ifm_active |= IFM_FDX;
1280 ifmr->ifm_active |= IFM_HDX;
1285 emx_media_change(struct ifnet *ifp)
1287 struct emx_softc *sc = ifp->if_softc;
1288 struct ifmedia *ifm = &sc->media;
1290 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1292 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1295 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1297 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1298 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1304 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1305 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1309 sc->hw.mac.autoneg = FALSE;
1310 sc->hw.phy.autoneg_advertised = 0;
1311 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1312 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1314 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1318 sc->hw.mac.autoneg = FALSE;
1319 sc->hw.phy.autoneg_advertised = 0;
1320 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1321 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1323 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1327 if_printf(ifp, "Unsupported media type\n");
1332 * As the speed/duplex settings my have changed we need to
1335 sc->hw.phy.reset_disable = FALSE;
1343 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1345 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1347 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1348 struct e1000_tx_desc *ctxd = NULL;
1349 struct mbuf *m_head = *m_headp;
1350 uint32_t txd_upper, txd_lower, cmd = 0;
1351 int maxsegs, nsegs, i, j, first, last = 0, error;
1353 if (m_head->m_len < EMX_TXCSUM_MINHL &&
1354 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1356 * Make sure that ethernet header and ip.ip_hl are in
1357 * contiguous memory, since if TXCSUM is enabled, later
1358 * TX context descriptor's setup need to access ip.ip_hl.
1360 error = emx_txcsum_pullup(sc, m_headp);
1362 KKASSERT(*m_headp == NULL);
1368 txd_upper = txd_lower = 0;
1371 * Capture the first descriptor index, this descriptor
1372 * will have the index of the EOP which is the only one
1373 * that now gets a DONE bit writeback.
1375 first = sc->next_avail_tx_desc;
1376 tx_buffer = &sc->tx_buf[first];
1377 tx_buffer_mapped = tx_buffer;
1378 map = tx_buffer->map;
1380 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1381 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n"));
1382 if (maxsegs > EMX_MAX_SCATTER)
1383 maxsegs = EMX_MAX_SCATTER;
1385 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1386 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1388 if (error == ENOBUFS)
1389 sc->mbuf_alloc_failed++;
1391 sc->no_tx_dma_setup++;
1397 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1400 sc->tx_nsegs += nsegs;
1402 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1403 /* TX csum offloading will consume one TX desc */
1404 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1406 i = sc->next_avail_tx_desc;
1408 /* Set up our transmit descriptors */
1409 for (j = 0; j < nsegs; j++) {
1410 tx_buffer = &sc->tx_buf[i];
1411 ctxd = &sc->tx_desc_base[i];
1413 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1414 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1415 txd_lower | segs[j].ds_len);
1416 ctxd->upper.data = htole32(txd_upper);
1419 if (++i == sc->num_tx_desc)
1423 sc->next_avail_tx_desc = i;
1425 KKASSERT(sc->num_tx_desc_avail > nsegs);
1426 sc->num_tx_desc_avail -= nsegs;
1428 /* Handle VLAN tag */
1429 if (m_head->m_flags & M_VLANTAG) {
1430 /* Set the vlan id. */
1431 ctxd->upper.fields.special =
1432 htole16(m_head->m_pkthdr.ether_vlantag);
1434 /* Tell hardware to add tag */
1435 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1438 tx_buffer->m_head = m_head;
1439 tx_buffer_mapped->map = tx_buffer->map;
1440 tx_buffer->map = map;
1442 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1446 * Report Status (RS) is turned on
1447 * every tx_int_nsegs descriptors.
1449 cmd = E1000_TXD_CMD_RS;
1452 * Keep track of the descriptor, which will
1453 * be written back by hardware.
1455 sc->tx_dd[sc->tx_dd_tail] = last;
1456 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1457 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1461 * Last Descriptor of Packet needs End Of Packet (EOP)
1463 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1466 * Advance the Transmit Descriptor Tail (TDT), this tells
1467 * the E1000 that this frame is available to transmit.
1469 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1475 emx_set_promisc(struct emx_softc *sc)
1477 struct ifnet *ifp = &sc->arpcom.ac_if;
1480 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1482 if (ifp->if_flags & IFF_PROMISC) {
1483 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1484 /* Turn this on if you want to see bad packets */
1486 reg_rctl |= E1000_RCTL_SBP;
1487 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1488 } else if (ifp->if_flags & IFF_ALLMULTI) {
1489 reg_rctl |= E1000_RCTL_MPE;
1490 reg_rctl &= ~E1000_RCTL_UPE;
1491 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1496 emx_disable_promisc(struct emx_softc *sc)
1500 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1502 reg_rctl &= ~E1000_RCTL_UPE;
1503 reg_rctl &= ~E1000_RCTL_MPE;
1504 reg_rctl &= ~E1000_RCTL_SBP;
1505 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1509 emx_set_multi(struct emx_softc *sc)
1511 struct ifnet *ifp = &sc->arpcom.ac_if;
1512 struct ifmultiaddr *ifma;
1513 uint32_t reg_rctl = 0;
1518 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1520 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1521 if (ifma->ifma_addr->sa_family != AF_LINK)
1524 if (mcnt == EMX_MCAST_ADDR_MAX)
1527 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1528 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1532 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1533 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1534 reg_rctl |= E1000_RCTL_MPE;
1535 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1537 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1542 * This routine checks for link status and updates statistics.
1545 emx_timer(void *xsc)
1547 struct emx_softc *sc = xsc;
1548 struct ifnet *ifp = &sc->arpcom.ac_if;
1550 ifnet_serialize_all(ifp);
1552 emx_update_link_status(sc);
1553 emx_update_stats(sc);
1555 /* Reset LAA into RAR[0] on 82571 */
1556 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1557 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1559 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1560 emx_print_hw_stats(sc);
1564 callout_reset(&sc->timer, hz, emx_timer, sc);
1566 ifnet_deserialize_all(ifp);
1570 emx_update_link_status(struct emx_softc *sc)
1572 struct e1000_hw *hw = &sc->hw;
1573 struct ifnet *ifp = &sc->arpcom.ac_if;
1574 device_t dev = sc->dev;
1575 uint32_t link_check = 0;
1577 /* Get the cached link value or read phy for real */
1578 switch (hw->phy.media_type) {
1579 case e1000_media_type_copper:
1580 if (hw->mac.get_link_status) {
1581 /* Do the work to read phy */
1582 e1000_check_for_link(hw);
1583 link_check = !hw->mac.get_link_status;
1584 if (link_check) /* ESB2 fix */
1585 e1000_cfg_on_link_up(hw);
1591 case e1000_media_type_fiber:
1592 e1000_check_for_link(hw);
1593 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1596 case e1000_media_type_internal_serdes:
1597 e1000_check_for_link(hw);
1598 link_check = sc->hw.mac.serdes_has_link;
1601 case e1000_media_type_unknown:
1606 /* Now check for a transition */
1607 if (link_check && sc->link_active == 0) {
1608 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1612 * Check if we should enable/disable SPEED_MODE bit on
1615 if (sc->link_speed != SPEED_1000 &&
1616 (hw->mac.type == e1000_82571 ||
1617 hw->mac.type == e1000_82572)) {
1620 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1621 tarc0 &= ~EMX_TARC_SPEED_MODE;
1622 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1625 device_printf(dev, "Link is up %d Mbps %s\n",
1627 ((sc->link_duplex == FULL_DUPLEX) ?
1628 "Full Duplex" : "Half Duplex"));
1630 sc->link_active = 1;
1632 ifp->if_baudrate = sc->link_speed * 1000000;
1633 ifp->if_link_state = LINK_STATE_UP;
1634 if_link_state_change(ifp);
1635 } else if (!link_check && sc->link_active == 1) {
1636 ifp->if_baudrate = sc->link_speed = 0;
1637 sc->link_duplex = 0;
1639 device_printf(dev, "Link is Down\n");
1640 sc->link_active = 0;
1642 /* Link down, disable watchdog */
1645 ifp->if_link_state = LINK_STATE_DOWN;
1646 if_link_state_change(ifp);
1651 emx_stop(struct emx_softc *sc)
1653 struct ifnet *ifp = &sc->arpcom.ac_if;
1656 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1658 emx_disable_intr(sc);
1660 callout_stop(&sc->timer);
1662 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1666 * Disable multiple receive queues.
1669 * We should disable multiple receive queues before
1670 * resetting the hardware.
1672 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1674 e1000_reset_hw(&sc->hw);
1675 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1677 for (i = 0; i < sc->num_tx_desc; i++) {
1678 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1680 if (tx_buffer->m_head != NULL) {
1681 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1682 m_freem(tx_buffer->m_head);
1683 tx_buffer->m_head = NULL;
1687 for (i = 0; i < sc->rx_ring_inuse; ++i)
1688 emx_free_rx_ring(sc, &sc->rx_data[i]);
1692 sc->csum_iphlen = 0;
1700 emx_reset(struct emx_softc *sc)
1702 device_t dev = sc->dev;
1703 uint16_t rx_buffer_size;
1705 /* Set up smart power down as default off on newer adapters. */
1706 if (!emx_smart_pwr_down &&
1707 (sc->hw.mac.type == e1000_82571 ||
1708 sc->hw.mac.type == e1000_82572)) {
1709 uint16_t phy_tmp = 0;
1711 /* Speed up time to link by disabling smart power down. */
1712 e1000_read_phy_reg(&sc->hw,
1713 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1714 phy_tmp &= ~IGP02E1000_PM_SPD;
1715 e1000_write_phy_reg(&sc->hw,
1716 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1720 * These parameters control the automatic generation (Tx) and
1721 * response (Rx) to Ethernet PAUSE frames.
1722 * - High water mark should allow for at least two frames to be
1723 * received after sending an XOFF.
1724 * - Low water mark works best when it is very near the high water mark.
1725 * This allows the receiver to restart by sending XON when it has
1726 * drained a bit. Here we use an arbitary value of 1500 which will
1727 * restart after one full frame is pulled from the buffer. There
1728 * could be several smaller frames in the buffer and if so they will
1729 * not trigger the XON until their total number reduces the buffer
1731 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1733 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1735 sc->hw.fc.high_water = rx_buffer_size -
1736 roundup2(sc->max_frame_size, 1024);
1737 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1739 if (sc->hw.mac.type == e1000_80003es2lan)
1740 sc->hw.fc.pause_time = 0xFFFF;
1742 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1743 sc->hw.fc.send_xon = TRUE;
1744 sc->hw.fc.requested_mode = e1000_fc_full;
1746 /* Issue a global reset */
1747 e1000_reset_hw(&sc->hw);
1748 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1750 if (e1000_init_hw(&sc->hw) < 0) {
1751 device_printf(dev, "Hardware Initialization Failed\n");
1755 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1756 e1000_get_phy_info(&sc->hw);
1757 e1000_check_for_link(&sc->hw);
1763 emx_setup_ifp(struct emx_softc *sc)
1765 struct ifnet *ifp = &sc->arpcom.ac_if;
1767 if_initname(ifp, device_get_name(sc->dev),
1768 device_get_unit(sc->dev));
1770 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1771 ifp->if_init = emx_init;
1772 ifp->if_ioctl = emx_ioctl;
1773 ifp->if_start = emx_start;
1774 #ifdef IFPOLL_ENABLE
1775 ifp->if_qpoll = emx_qpoll;
1777 ifp->if_watchdog = emx_watchdog;
1778 ifp->if_serialize = emx_serialize;
1779 ifp->if_deserialize = emx_deserialize;
1780 ifp->if_tryserialize = emx_tryserialize;
1782 ifp->if_serialize_assert = emx_serialize_assert;
1784 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1785 ifq_set_ready(&ifp->if_snd);
1787 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1789 ifp->if_capabilities = IFCAP_HWCSUM |
1790 IFCAP_VLAN_HWTAGGING |
1792 if (sc->rx_ring_cnt > 1)
1793 ifp->if_capabilities |= IFCAP_RSS;
1794 ifp->if_capenable = ifp->if_capabilities;
1795 ifp->if_hwassist = EMX_CSUM_FEATURES;
1798 * Tell the upper layer(s) we support long frames.
1800 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1803 * Specify the media types supported by this sc and register
1804 * callbacks to update media and link information
1806 ifmedia_init(&sc->media, IFM_IMASK,
1807 emx_media_change, emx_media_status);
1808 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1809 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1810 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1812 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1814 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1815 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1817 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1818 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1820 if (sc->hw.phy.type != e1000_phy_ife) {
1821 ifmedia_add(&sc->media,
1822 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1823 ifmedia_add(&sc->media,
1824 IFM_ETHER | IFM_1000_T, 0, NULL);
1827 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1828 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1832 * Workaround for SmartSpeed on 82541 and 82547 controllers
1835 emx_smartspeed(struct emx_softc *sc)
1839 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1840 sc->hw.mac.autoneg == 0 ||
1841 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1844 if (sc->smartspeed == 0) {
1846 * If Master/Slave config fault is asserted twice,
1847 * we assume back-to-back
1849 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1850 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1852 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1853 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1854 e1000_read_phy_reg(&sc->hw,
1855 PHY_1000T_CTRL, &phy_tmp);
1856 if (phy_tmp & CR_1000T_MS_ENABLE) {
1857 phy_tmp &= ~CR_1000T_MS_ENABLE;
1858 e1000_write_phy_reg(&sc->hw,
1859 PHY_1000T_CTRL, phy_tmp);
1861 if (sc->hw.mac.autoneg &&
1862 !e1000_phy_setup_autoneg(&sc->hw) &&
1863 !e1000_read_phy_reg(&sc->hw,
1864 PHY_CONTROL, &phy_tmp)) {
1865 phy_tmp |= MII_CR_AUTO_NEG_EN |
1866 MII_CR_RESTART_AUTO_NEG;
1867 e1000_write_phy_reg(&sc->hw,
1868 PHY_CONTROL, phy_tmp);
1873 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1874 /* If still no link, perhaps using 2/3 pair cable */
1875 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1876 phy_tmp |= CR_1000T_MS_ENABLE;
1877 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1878 if (sc->hw.mac.autoneg &&
1879 !e1000_phy_setup_autoneg(&sc->hw) &&
1880 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1881 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1882 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1886 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1887 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1892 emx_create_tx_ring(struct emx_softc *sc)
1894 device_t dev = sc->dev;
1895 struct emx_txbuf *tx_buffer;
1896 int error, i, tsize;
1899 * Validate number of transmit descriptors. It must not exceed
1900 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1902 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1903 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) {
1904 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1905 EMX_DEFAULT_TXD, emx_txd);
1906 sc->num_tx_desc = EMX_DEFAULT_TXD;
1908 sc->num_tx_desc = emx_txd;
1912 * Allocate Transmit Descriptor ring
1914 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1916 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1917 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1918 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1919 &sc->tx_desc_paddr);
1920 if (sc->tx_desc_base == NULL) {
1921 device_printf(dev, "Unable to allocate tx_desc memory\n");
1925 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1926 M_DEVBUF, M_WAITOK | M_ZERO);
1929 * Create DMA tags for tx buffers
1931 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1932 1, 0, /* alignment, bounds */
1933 BUS_SPACE_MAXADDR, /* lowaddr */
1934 BUS_SPACE_MAXADDR, /* highaddr */
1935 NULL, NULL, /* filter, filterarg */
1936 EMX_TSO_SIZE, /* maxsize */
1937 EMX_MAX_SCATTER, /* nsegments */
1938 EMX_MAX_SEGSIZE, /* maxsegsize */
1939 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1940 BUS_DMA_ONEBPAGE, /* flags */
1943 device_printf(dev, "Unable to allocate TX DMA tag\n");
1944 kfree(sc->tx_buf, M_DEVBUF);
1950 * Create DMA maps for tx buffers
1952 for (i = 0; i < sc->num_tx_desc; i++) {
1953 tx_buffer = &sc->tx_buf[i];
1955 error = bus_dmamap_create(sc->txtag,
1956 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1959 device_printf(dev, "Unable to create TX DMA map\n");
1960 emx_destroy_tx_ring(sc, i);
1968 emx_init_tx_ring(struct emx_softc *sc)
1970 /* Clear the old ring contents */
1971 bzero(sc->tx_desc_base,
1972 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
1975 sc->next_avail_tx_desc = 0;
1976 sc->next_tx_to_clean = 0;
1977 sc->num_tx_desc_avail = sc->num_tx_desc;
1981 emx_init_tx_unit(struct emx_softc *sc)
1983 uint32_t tctl, tarc, tipg = 0;
1986 /* Setup the Base and Length of the Tx Descriptor Ring */
1987 bus_addr = sc->tx_desc_paddr;
1988 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
1989 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
1990 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
1991 (uint32_t)(bus_addr >> 32));
1992 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
1993 (uint32_t)bus_addr);
1994 /* Setup the HW Tx Head and Tail descriptor pointers */
1995 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
1996 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
1998 /* Set the default values for the Tx Inter Packet Gap timer */
1999 switch (sc->hw.mac.type) {
2000 case e1000_80003es2lan:
2001 tipg = DEFAULT_82543_TIPG_IPGR1;
2002 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2003 E1000_TIPG_IPGR2_SHIFT;
2007 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2008 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2009 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2011 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2012 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2013 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2017 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2019 /* NOTE: 0 is not allowed for TIDV */
2020 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2021 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2023 if (sc->hw.mac.type == e1000_82571 ||
2024 sc->hw.mac.type == e1000_82572) {
2025 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2026 tarc |= EMX_TARC_SPEED_MODE;
2027 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2028 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2029 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2031 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2032 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2034 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2037 /* Program the Transmit Control Register */
2038 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2039 tctl &= ~E1000_TCTL_CT;
2040 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2041 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2042 tctl |= E1000_TCTL_MULR;
2044 /* This write will effectively turn on the transmit unit. */
2045 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2049 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2051 struct emx_txbuf *tx_buffer;
2054 /* Free Transmit Descriptor ring */
2055 if (sc->tx_desc_base) {
2056 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2057 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2059 bus_dma_tag_destroy(sc->tx_desc_dtag);
2061 sc->tx_desc_base = NULL;
2064 if (sc->tx_buf == NULL)
2067 for (i = 0; i < ndesc; i++) {
2068 tx_buffer = &sc->tx_buf[i];
2070 KKASSERT(tx_buffer->m_head == NULL);
2071 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2073 bus_dma_tag_destroy(sc->txtag);
2075 kfree(sc->tx_buf, M_DEVBUF);
2080 * The offload context needs to be set when we transfer the first
2081 * packet of a particular protocol (TCP/UDP). This routine has been
2082 * enhanced to deal with inserted VLAN headers.
2084 * If the new packet's ether header length, ip header length and
2085 * csum offloading type are same as the previous packet, we should
2086 * avoid allocating a new csum context descriptor; mainly to take
2087 * advantage of the pipeline effect of the TX data read request.
2089 * This function returns number of TX descrptors allocated for
2093 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2094 uint32_t *txd_upper, uint32_t *txd_lower)
2096 struct e1000_context_desc *TXD;
2097 struct emx_txbuf *tx_buffer;
2098 struct ether_vlan_header *eh;
2100 int curr_txd, ehdrlen, csum_flags;
2101 uint32_t cmd, hdr_len, ip_hlen;
2105 * Determine where frame payload starts.
2106 * Jump over vlan headers if already present,
2107 * helpful for QinQ too.
2109 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2110 ("emx_txcsum_pullup is not called (eh)?\n"));
2111 eh = mtod(mp, struct ether_vlan_header *);
2112 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2113 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2114 ("emx_txcsum_pullup is not called (evh)?\n"));
2115 etype = ntohs(eh->evl_proto);
2116 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2118 etype = ntohs(eh->evl_encap_proto);
2119 ehdrlen = ETHER_HDR_LEN;
2123 * We only support TCP/UDP for IPv4 for the moment.
2124 * TODO: Support SCTP too when it hits the tree.
2126 if (etype != ETHERTYPE_IP)
2129 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2130 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2132 /* NOTE: We could only safely access ip.ip_vhl part */
2133 ip = (struct ip *)(mp->m_data + ehdrlen);
2134 ip_hlen = ip->ip_hl << 2;
2136 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2138 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2139 sc->csum_flags == csum_flags) {
2141 * Same csum offload context as the previous packets;
2144 *txd_upper = sc->csum_txd_upper;
2145 *txd_lower = sc->csum_txd_lower;
2150 * Setup a new csum offload context.
2153 curr_txd = sc->next_avail_tx_desc;
2154 tx_buffer = &sc->tx_buf[curr_txd];
2155 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2159 /* Setup of IP header checksum. */
2160 if (csum_flags & CSUM_IP) {
2162 * Start offset for header checksum calculation.
2163 * End offset for header checksum calculation.
2164 * Offset of place to put the checksum.
2166 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2167 TXD->lower_setup.ip_fields.ipcse =
2168 htole16(ehdrlen + ip_hlen - 1);
2169 TXD->lower_setup.ip_fields.ipcso =
2170 ehdrlen + offsetof(struct ip, ip_sum);
2171 cmd |= E1000_TXD_CMD_IP;
2172 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2174 hdr_len = ehdrlen + ip_hlen;
2176 if (csum_flags & CSUM_TCP) {
2178 * Start offset for payload checksum calculation.
2179 * End offset for payload checksum calculation.
2180 * Offset of place to put the checksum.
2182 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2183 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2184 TXD->upper_setup.tcp_fields.tucso =
2185 hdr_len + offsetof(struct tcphdr, th_sum);
2186 cmd |= E1000_TXD_CMD_TCP;
2187 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2188 } else if (csum_flags & CSUM_UDP) {
2190 * Start offset for header checksum calculation.
2191 * End offset for header checksum calculation.
2192 * Offset of place to put the checksum.
2194 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2195 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2196 TXD->upper_setup.tcp_fields.tucso =
2197 hdr_len + offsetof(struct udphdr, uh_sum);
2198 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2201 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2202 E1000_TXD_DTYP_D; /* Data descr */
2204 /* Save the information for this csum offloading context */
2205 sc->csum_ehlen = ehdrlen;
2206 sc->csum_iphlen = ip_hlen;
2207 sc->csum_flags = csum_flags;
2208 sc->csum_txd_upper = *txd_upper;
2209 sc->csum_txd_lower = *txd_lower;
2211 TXD->tcp_seg_setup.data = htole32(0);
2212 TXD->cmd_and_length =
2213 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2215 if (++curr_txd == sc->num_tx_desc)
2218 KKASSERT(sc->num_tx_desc_avail > 0);
2219 sc->num_tx_desc_avail--;
2221 sc->next_avail_tx_desc = curr_txd;
2226 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2228 struct mbuf *m = *m0;
2229 struct ether_header *eh;
2232 sc->tx_csum_try_pullup++;
2234 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2236 if (__predict_false(!M_WRITABLE(m))) {
2237 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2238 sc->tx_csum_drop1++;
2243 eh = mtod(m, struct ether_header *);
2245 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2246 len += EVL_ENCAPLEN;
2248 if (m->m_len < len) {
2249 sc->tx_csum_drop2++;
2257 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2258 sc->tx_csum_pullup1++;
2259 m = m_pullup(m, ETHER_HDR_LEN);
2261 sc->tx_csum_pullup1_failed++;
2267 eh = mtod(m, struct ether_header *);
2269 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2270 len += EVL_ENCAPLEN;
2272 if (m->m_len < len) {
2273 sc->tx_csum_pullup2++;
2274 m = m_pullup(m, len);
2276 sc->tx_csum_pullup2_failed++;
2286 emx_txeof(struct emx_softc *sc)
2288 struct ifnet *ifp = &sc->arpcom.ac_if;
2289 struct emx_txbuf *tx_buffer;
2290 int first, num_avail;
2292 if (sc->tx_dd_head == sc->tx_dd_tail)
2295 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2298 num_avail = sc->num_tx_desc_avail;
2299 first = sc->next_tx_to_clean;
2301 while (sc->tx_dd_head != sc->tx_dd_tail) {
2302 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2303 struct e1000_tx_desc *tx_desc;
2305 tx_desc = &sc->tx_desc_base[dd_idx];
2306 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2307 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2309 if (++dd_idx == sc->num_tx_desc)
2312 while (first != dd_idx) {
2317 tx_buffer = &sc->tx_buf[first];
2318 if (tx_buffer->m_head) {
2320 bus_dmamap_unload(sc->txtag,
2322 m_freem(tx_buffer->m_head);
2323 tx_buffer->m_head = NULL;
2326 if (++first == sc->num_tx_desc)
2333 sc->next_tx_to_clean = first;
2334 sc->num_tx_desc_avail = num_avail;
2336 if (sc->tx_dd_head == sc->tx_dd_tail) {
2341 if (!EMX_IS_OACTIVE(sc)) {
2342 ifp->if_flags &= ~IFF_OACTIVE;
2344 /* All clean, turn off the timer */
2345 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2351 emx_tx_collect(struct emx_softc *sc)
2353 struct ifnet *ifp = &sc->arpcom.ac_if;
2354 struct emx_txbuf *tx_buffer;
2355 int tdh, first, num_avail, dd_idx = -1;
2357 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2360 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2361 if (tdh == sc->next_tx_to_clean)
2364 if (sc->tx_dd_head != sc->tx_dd_tail)
2365 dd_idx = sc->tx_dd[sc->tx_dd_head];
2367 num_avail = sc->num_tx_desc_avail;
2368 first = sc->next_tx_to_clean;
2370 while (first != tdh) {
2375 tx_buffer = &sc->tx_buf[first];
2376 if (tx_buffer->m_head) {
2378 bus_dmamap_unload(sc->txtag,
2380 m_freem(tx_buffer->m_head);
2381 tx_buffer->m_head = NULL;
2384 if (first == dd_idx) {
2385 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2386 if (sc->tx_dd_head == sc->tx_dd_tail) {
2391 dd_idx = sc->tx_dd[sc->tx_dd_head];
2395 if (++first == sc->num_tx_desc)
2398 sc->next_tx_to_clean = first;
2399 sc->num_tx_desc_avail = num_avail;
2401 if (!EMX_IS_OACTIVE(sc)) {
2402 ifp->if_flags &= ~IFF_OACTIVE;
2404 /* All clean, turn off the timer */
2405 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2411 * When Link is lost sometimes there is work still in the TX ring
2412 * which will result in a watchdog, rather than allow that do an
2413 * attempted cleanup and then reinit here. Note that this has been
2414 * seens mostly with fiber adapters.
2417 emx_tx_purge(struct emx_softc *sc)
2419 struct ifnet *ifp = &sc->arpcom.ac_if;
2421 if (!sc->link_active && ifp->if_timer) {
2423 if (ifp->if_timer) {
2424 if_printf(ifp, "Link lost, TX pending, reinit\n");
2432 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2435 bus_dma_segment_t seg;
2437 struct emx_rxbuf *rx_buffer;
2440 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2442 rdata->mbuf_cluster_failed++;
2444 if_printf(&sc->arpcom.ac_if,
2445 "Unable to allocate RX mbuf\n");
2449 m->m_len = m->m_pkthdr.len = MCLBYTES;
2451 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2452 m_adj(m, ETHER_ALIGN);
2454 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2455 rdata->rx_sparemap, m,
2456 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2460 if_printf(&sc->arpcom.ac_if,
2461 "Unable to load RX mbuf\n");
2466 rx_buffer = &rdata->rx_buf[i];
2467 if (rx_buffer->m_head != NULL)
2468 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2470 map = rx_buffer->map;
2471 rx_buffer->map = rdata->rx_sparemap;
2472 rdata->rx_sparemap = map;
2474 rx_buffer->m_head = m;
2475 rx_buffer->paddr = seg.ds_addr;
2477 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2482 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2484 device_t dev = sc->dev;
2485 struct emx_rxbuf *rx_buffer;
2486 int i, error, rsize;
2489 * Validate number of receive descriptors. It must not exceed
2490 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2492 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2493 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) {
2494 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2495 EMX_DEFAULT_RXD, emx_rxd);
2496 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2498 rdata->num_rx_desc = emx_rxd;
2502 * Allocate Receive Descriptor ring
2504 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2506 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2507 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2508 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2509 &rdata->rx_desc_paddr);
2510 if (rdata->rx_desc == NULL) {
2511 device_printf(dev, "Unable to allocate rx_desc memory\n");
2515 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2516 M_DEVBUF, M_WAITOK | M_ZERO);
2519 * Create DMA tag for rx buffers
2521 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2522 1, 0, /* alignment, bounds */
2523 BUS_SPACE_MAXADDR, /* lowaddr */
2524 BUS_SPACE_MAXADDR, /* highaddr */
2525 NULL, NULL, /* filter, filterarg */
2526 MCLBYTES, /* maxsize */
2528 MCLBYTES, /* maxsegsize */
2529 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2532 device_printf(dev, "Unable to allocate RX DMA tag\n");
2533 kfree(rdata->rx_buf, M_DEVBUF);
2534 rdata->rx_buf = NULL;
2539 * Create spare DMA map for rx buffers
2541 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2542 &rdata->rx_sparemap);
2544 device_printf(dev, "Unable to create spare RX DMA map\n");
2545 bus_dma_tag_destroy(rdata->rxtag);
2546 kfree(rdata->rx_buf, M_DEVBUF);
2547 rdata->rx_buf = NULL;
2552 * Create DMA maps for rx buffers
2554 for (i = 0; i < rdata->num_rx_desc; i++) {
2555 rx_buffer = &rdata->rx_buf[i];
2557 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2560 device_printf(dev, "Unable to create RX DMA map\n");
2561 emx_destroy_rx_ring(sc, rdata, i);
2569 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2573 for (i = 0; i < rdata->num_rx_desc; i++) {
2574 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2576 if (rx_buffer->m_head != NULL) {
2577 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2578 m_freem(rx_buffer->m_head);
2579 rx_buffer->m_head = NULL;
2583 if (rdata->fmp != NULL)
2584 m_freem(rdata->fmp);
2590 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2594 /* Reset descriptor ring */
2595 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2597 /* Allocate new ones. */
2598 for (i = 0; i < rdata->num_rx_desc; i++) {
2599 error = emx_newbuf(sc, rdata, i, 1);
2604 /* Setup our descriptor pointers */
2605 rdata->next_rx_desc_to_check = 0;
2611 emx_init_rx_unit(struct emx_softc *sc)
2613 struct ifnet *ifp = &sc->arpcom.ac_if;
2615 uint32_t rctl, itr, rfctl;
2619 * Make sure receives are disabled while setting
2620 * up the descriptor ring
2622 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2623 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2626 * Set the interrupt throttling rate. Value is calculated
2627 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2629 if (sc->int_throttle_ceil)
2630 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2633 emx_set_itr(sc, itr);
2635 /* Use extended RX descriptor */
2636 rfctl = E1000_RFCTL_EXTEN;
2638 /* Disable accelerated ackknowledge */
2639 if (sc->hw.mac.type == e1000_82574)
2640 rfctl |= E1000_RFCTL_ACK_DIS;
2642 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2645 * Receive Checksum Offload for TCP and UDP
2647 * Checksum offloading is also enabled if multiple receive
2648 * queue is to be supported, since we need it to figure out
2651 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) {
2654 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2658 * PCSD must be enabled to enable multiple
2661 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2663 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2667 * Configure multiple receive queue (RSS)
2669 if (ifp->if_capenable & IFCAP_RSS) {
2670 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2673 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING,
2674 ("invalid number of RX ring (%d)",
2675 sc->rx_ring_inuse));
2679 * When we reach here, RSS has already been disabled
2680 * in emx_stop(), so we could safely configure RSS key
2681 * and redirect table.
2687 toeplitz_get_key(key, sizeof(key));
2688 for (i = 0; i < EMX_NRSSRK; ++i) {
2691 rssrk = EMX_RSSRK_VAL(key, i);
2692 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2694 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2698 * Configure RSS redirect table in following fashion:
2699 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2702 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2705 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT;
2706 reta |= q << (8 * i);
2708 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2710 for (i = 0; i < EMX_NRETA; ++i)
2711 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2714 * Enable multiple receive queues.
2715 * Enable IPv4 RSS standard hash functions.
2716 * Disable RSS interrupt.
2718 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2719 E1000_MRQC_ENABLE_RSS_2Q |
2720 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2721 E1000_MRQC_RSS_FIELD_IPV4);
2725 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2726 * long latencies are observed, like Lenovo X60. This
2727 * change eliminates the problem, but since having positive
2728 * values in RDTR is a known source of problems on other
2729 * platforms another solution is being sought.
2731 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2732 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2733 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2736 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2737 struct emx_rxdata *rdata = &sc->rx_data[i];
2740 * Setup the Base and Length of the Rx Descriptor Ring
2742 bus_addr = rdata->rx_desc_paddr;
2743 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2744 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2745 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2746 (uint32_t)(bus_addr >> 32));
2747 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2748 (uint32_t)bus_addr);
2751 * Setup the HW Rx Head and Tail Descriptor Pointers
2753 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2754 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2755 sc->rx_data[i].num_rx_desc - 1);
2758 /* Setup the Receive Control Register */
2759 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2760 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2761 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2762 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2764 /* Make sure VLAN Filters are off */
2765 rctl &= ~E1000_RCTL_VFE;
2767 /* Don't store bad paket */
2768 rctl &= ~E1000_RCTL_SBP;
2771 rctl |= E1000_RCTL_SZ_2048;
2773 if (ifp->if_mtu > ETHERMTU)
2774 rctl |= E1000_RCTL_LPE;
2776 rctl &= ~E1000_RCTL_LPE;
2778 /* Enable Receives */
2779 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2783 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2785 struct emx_rxbuf *rx_buffer;
2788 /* Free Receive Descriptor ring */
2789 if (rdata->rx_desc) {
2790 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2791 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2792 rdata->rx_desc_dmap);
2793 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2795 rdata->rx_desc = NULL;
2798 if (rdata->rx_buf == NULL)
2801 for (i = 0; i < ndesc; i++) {
2802 rx_buffer = &rdata->rx_buf[i];
2804 KKASSERT(rx_buffer->m_head == NULL);
2805 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2807 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2808 bus_dma_tag_destroy(rdata->rxtag);
2810 kfree(rdata->rx_buf, M_DEVBUF);
2811 rdata->rx_buf = NULL;
2815 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2817 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2818 struct ifnet *ifp = &sc->arpcom.ac_if;
2820 emx_rxdesc_t *current_desc;
2823 struct mbuf_chain chain[MAXCPU];
2825 i = rdata->next_rx_desc_to_check;
2826 current_desc = &rdata->rx_desc[i];
2827 staterr = le32toh(current_desc->rxd_staterr);
2829 if (!(staterr & E1000_RXD_STAT_DD))
2832 ether_input_chain_init(chain);
2834 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2835 struct pktinfo *pi = NULL, pi0;
2836 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2837 struct mbuf *m = NULL;
2842 mp = rx_buf->m_head;
2845 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2846 * needs to access the last received byte in the mbuf.
2848 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2849 BUS_DMASYNC_POSTREAD);
2851 len = le16toh(current_desc->rxd_length);
2852 if (staterr & E1000_RXD_STAT_EOP) {
2859 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2861 uint32_t mrq, rss_hash;
2864 * Save several necessary information,
2865 * before emx_newbuf() destroy it.
2867 if ((staterr & E1000_RXD_STAT_VP) && eop)
2868 vlan = le16toh(current_desc->rxd_vlan);
2870 mrq = le32toh(current_desc->rxd_mrq);
2871 rss_hash = le32toh(current_desc->rxd_rss);
2873 EMX_RSS_DPRINTF(sc, 10,
2874 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2875 ring_idx, mrq, rss_hash);
2877 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2882 /* Assign correct length to the current fragment */
2885 if (rdata->fmp == NULL) {
2886 mp->m_pkthdr.len = len;
2887 rdata->fmp = mp; /* Store the first mbuf */
2891 * Chain mbuf's together
2893 rdata->lmp->m_next = mp;
2894 rdata->lmp = rdata->lmp->m_next;
2895 rdata->fmp->m_pkthdr.len += len;
2899 rdata->fmp->m_pkthdr.rcvif = ifp;
2902 if (ifp->if_capenable & IFCAP_RXCSUM)
2903 emx_rxcsum(staterr, rdata->fmp);
2905 if (staterr & E1000_RXD_STAT_VP) {
2906 rdata->fmp->m_pkthdr.ether_vlantag =
2908 rdata->fmp->m_flags |= M_VLANTAG;
2914 if (ifp->if_capenable & IFCAP_RSS) {
2915 pi = emx_rssinfo(m, &pi0, mrq,
2918 #ifdef EMX_RSS_DEBUG
2925 emx_setup_rxdesc(current_desc, rx_buf);
2926 if (rdata->fmp != NULL) {
2927 m_freem(rdata->fmp);
2935 ether_input_chain(ifp, m, pi, chain);
2937 /* Advance our pointers to the next descriptor. */
2938 if (++i == rdata->num_rx_desc)
2941 current_desc = &rdata->rx_desc[i];
2942 staterr = le32toh(current_desc->rxd_staterr);
2944 rdata->next_rx_desc_to_check = i;
2946 ether_input_dispatch(chain);
2948 /* Advance the E1000's Receive Queue "Tail Pointer". */
2950 i = rdata->num_rx_desc - 1;
2951 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2955 emx_enable_intr(struct emx_softc *sc)
2957 uint32_t ims_mask = IMS_ENABLE_MASK;
2959 lwkt_serialize_handler_enable(&sc->main_serialize);
2962 if (sc->hw.mac.type == e1000_82574) {
2963 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2964 ims_mask |= EM_MSIX_MASK;
2967 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
2971 emx_disable_intr(struct emx_softc *sc)
2973 if (sc->hw.mac.type == e1000_82574)
2974 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
2975 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2977 lwkt_serialize_handler_disable(&sc->main_serialize);
2981 * Bit of a misnomer, what this really means is
2982 * to enable OS management of the system... aka
2983 * to disable special hardware management features
2986 emx_get_mgmt(struct emx_softc *sc)
2988 /* A shared code workaround */
2989 if (sc->has_manage) {
2990 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2991 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2993 /* disable hardware interception of ARP */
2994 manc &= ~(E1000_MANC_ARP_EN);
2996 /* enable receiving management packets to the host */
2997 manc |= E1000_MANC_EN_MNG2HOST;
2998 #define E1000_MNG2HOST_PORT_623 (1 << 5)
2999 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3000 manc2h |= E1000_MNG2HOST_PORT_623;
3001 manc2h |= E1000_MNG2HOST_PORT_664;
3002 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3004 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3009 * Give control back to hardware management
3010 * controller if there is one.
3013 emx_rel_mgmt(struct emx_softc *sc)
3015 if (sc->has_manage) {
3016 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3018 /* re-enable hardware interception of ARP */
3019 manc |= E1000_MANC_ARP_EN;
3020 manc &= ~E1000_MANC_EN_MNG2HOST;
3022 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3027 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3028 * For ASF and Pass Through versions of f/w this means that
3029 * the driver is loaded. For AMT version (only with 82573)
3030 * of the f/w this means that the network i/f is open.
3033 emx_get_hw_control(struct emx_softc *sc)
3035 /* Let firmware know the driver has taken over */
3036 if (sc->hw.mac.type == e1000_82573) {
3039 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3040 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3041 swsm | E1000_SWSM_DRV_LOAD);
3045 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3046 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3047 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3053 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3054 * For ASF and Pass Through versions of f/w this means that the
3055 * driver is no longer loaded. For AMT version (only with 82573)
3056 * of the f/w this means that the network i/f is closed.
3059 emx_rel_hw_control(struct emx_softc *sc)
3061 if (!sc->control_hw)
3065 /* Let firmware taken over control of h/w */
3066 if (sc->hw.mac.type == e1000_82573) {
3069 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3070 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3071 swsm & ~E1000_SWSM_DRV_LOAD);
3075 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3076 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3077 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3082 emx_is_valid_eaddr(const uint8_t *addr)
3084 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3086 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3093 * Enable PCI Wake On Lan capability
3096 emx_enable_wol(device_t dev)
3098 uint16_t cap, status;
3101 /* First find the capabilities pointer*/
3102 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3104 /* Read the PM Capabilities */
3105 id = pci_read_config(dev, cap, 1);
3106 if (id != PCIY_PMG) /* Something wrong */
3110 * OK, we have the power capabilities,
3111 * so now get the status register
3113 cap += PCIR_POWER_STATUS;
3114 status = pci_read_config(dev, cap, 2);
3115 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3116 pci_write_config(dev, cap, status, 2);
3120 emx_update_stats(struct emx_softc *sc)
3122 struct ifnet *ifp = &sc->arpcom.ac_if;
3124 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3125 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3126 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3127 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3129 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3130 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3131 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3132 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3134 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3135 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3136 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3137 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3138 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3139 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3140 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3141 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3142 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3143 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3144 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3145 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3146 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3147 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3148 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3149 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3150 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3151 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3152 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3153 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3155 /* For the 64-bit byte counters the low dword must be read first. */
3156 /* Both registers clear on the read of the high dword */
3158 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3159 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3161 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3162 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3163 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3164 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3165 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3167 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3168 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3170 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3171 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3172 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3173 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3174 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3175 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3176 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3177 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3178 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3179 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3181 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3182 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3183 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3184 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3185 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3186 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3188 ifp->if_collisions = sc->stats.colc;
3191 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3192 sc->stats.crcerrs + sc->stats.algnerrc +
3193 sc->stats.ruc + sc->stats.roc +
3194 sc->stats.mpc + sc->stats.cexterr;
3197 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3198 sc->watchdog_events;
3202 emx_print_debug_info(struct emx_softc *sc)
3204 device_t dev = sc->dev;
3205 uint8_t *hw_addr = sc->hw.hw_addr;
3207 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3208 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3209 E1000_READ_REG(&sc->hw, E1000_CTRL),
3210 E1000_READ_REG(&sc->hw, E1000_RCTL));
3211 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3212 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3213 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3214 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3215 sc->hw.fc.high_water, sc->hw.fc.low_water);
3216 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3217 E1000_READ_REG(&sc->hw, E1000_TIDV),
3218 E1000_READ_REG(&sc->hw, E1000_TADV));
3219 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3220 E1000_READ_REG(&sc->hw, E1000_RDTR),
3221 E1000_READ_REG(&sc->hw, E1000_RADV));
3222 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3223 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3224 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3225 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3226 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3227 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3228 device_printf(dev, "Num Tx descriptors avail = %d\n",
3229 sc->num_tx_desc_avail);
3230 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3231 sc->no_tx_desc_avail1);
3232 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3233 sc->no_tx_desc_avail2);
3234 device_printf(dev, "Std mbuf failed = %ld\n",
3235 sc->mbuf_alloc_failed);
3236 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3237 sc->rx_data[0].mbuf_cluster_failed);
3238 device_printf(dev, "Driver dropped packets = %ld\n",
3240 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3241 sc->no_tx_dma_setup);
3243 device_printf(dev, "TXCSUM try pullup = %lu\n",
3244 sc->tx_csum_try_pullup);
3245 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3246 sc->tx_csum_pullup1);
3247 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3248 sc->tx_csum_pullup1_failed);
3249 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3250 sc->tx_csum_pullup2);
3251 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3252 sc->tx_csum_pullup2_failed);
3253 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3255 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3260 emx_print_hw_stats(struct emx_softc *sc)
3262 device_t dev = sc->dev;
3264 device_printf(dev, "Excessive collisions = %lld\n",
3265 (long long)sc->stats.ecol);
3266 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3267 device_printf(dev, "Symbol errors = %lld\n",
3268 (long long)sc->stats.symerrs);
3270 device_printf(dev, "Sequence errors = %lld\n",
3271 (long long)sc->stats.sec);
3272 device_printf(dev, "Defer count = %lld\n",
3273 (long long)sc->stats.dc);
3274 device_printf(dev, "Missed Packets = %lld\n",
3275 (long long)sc->stats.mpc);
3276 device_printf(dev, "Receive No Buffers = %lld\n",
3277 (long long)sc->stats.rnbc);
3278 /* RLEC is inaccurate on some hardware, calculate our own. */
3279 device_printf(dev, "Receive Length Errors = %lld\n",
3280 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3281 device_printf(dev, "Receive errors = %lld\n",
3282 (long long)sc->stats.rxerrc);
3283 device_printf(dev, "Crc errors = %lld\n",
3284 (long long)sc->stats.crcerrs);
3285 device_printf(dev, "Alignment errors = %lld\n",
3286 (long long)sc->stats.algnerrc);
3287 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3288 (long long)sc->stats.cexterr);
3289 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3290 device_printf(dev, "watchdog timeouts = %ld\n",
3291 sc->watchdog_events);
3292 device_printf(dev, "XON Rcvd = %lld\n",
3293 (long long)sc->stats.xonrxc);
3294 device_printf(dev, "XON Xmtd = %lld\n",
3295 (long long)sc->stats.xontxc);
3296 device_printf(dev, "XOFF Rcvd = %lld\n",
3297 (long long)sc->stats.xoffrxc);
3298 device_printf(dev, "XOFF Xmtd = %lld\n",
3299 (long long)sc->stats.xofftxc);
3300 device_printf(dev, "Good Packets Rcvd = %lld\n",
3301 (long long)sc->stats.gprc);
3302 device_printf(dev, "Good Packets Xmtd = %lld\n",
3303 (long long)sc->stats.gptc);
3307 emx_print_nvm_info(struct emx_softc *sc)
3309 uint16_t eeprom_data;
3312 /* Its a bit crude, but it gets the job done */
3313 kprintf("\nInterface EEPROM Dump:\n");
3314 kprintf("Offset\n0x0000 ");
3315 for (i = 0, j = 0; i < 32; i++, j++) {
3316 if (j == 8) { /* Make the offset block */
3318 kprintf("\n0x00%x0 ",row);
3320 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3321 kprintf("%04x ", eeprom_data);
3327 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3329 struct emx_softc *sc;
3334 error = sysctl_handle_int(oidp, &result, 0, req);
3335 if (error || !req->newptr)
3338 sc = (struct emx_softc *)arg1;
3339 ifp = &sc->arpcom.ac_if;
3341 ifnet_serialize_all(ifp);
3344 emx_print_debug_info(sc);
3347 * This value will cause a hex dump of the
3348 * first 32 16-bit words of the EEPROM to
3352 emx_print_nvm_info(sc);
3354 ifnet_deserialize_all(ifp);
3360 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3365 error = sysctl_handle_int(oidp, &result, 0, req);
3366 if (error || !req->newptr)
3370 struct emx_softc *sc = (struct emx_softc *)arg1;
3371 struct ifnet *ifp = &sc->arpcom.ac_if;
3373 ifnet_serialize_all(ifp);
3374 emx_print_hw_stats(sc);
3375 ifnet_deserialize_all(ifp);
3381 emx_add_sysctl(struct emx_softc *sc)
3383 #ifdef EMX_RSS_DEBUG
3388 sysctl_ctx_init(&sc->sysctl_ctx);
3389 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3390 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3391 device_get_nameunit(sc->dev),
3393 if (sc->sysctl_tree == NULL) {
3394 device_printf(sc->dev, "can't add sysctl node\n");
3398 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3399 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3400 emx_sysctl_debug_info, "I", "Debug Information");
3402 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3403 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3404 emx_sysctl_stats, "I", "Statistics");
3406 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3407 OID_AUTO, "rxd", CTLFLAG_RD,
3408 &sc->rx_data[0].num_rx_desc, 0, NULL);
3409 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3410 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3412 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3413 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3414 sc, 0, emx_sysctl_int_throttle, "I",
3415 "interrupt throttling rate");
3416 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3417 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3418 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3419 "# segments per TX interrupt");
3421 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3422 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD,
3423 &sc->rx_ring_inuse, 0, "RX ring in use");
3425 #ifdef EMX_RSS_DEBUG
3426 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3427 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3428 0, "RSS debug level");
3429 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3430 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3431 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3432 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3434 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3440 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3442 struct emx_softc *sc = (void *)arg1;
3443 struct ifnet *ifp = &sc->arpcom.ac_if;
3444 int error, throttle;
3446 throttle = sc->int_throttle_ceil;
3447 error = sysctl_handle_int(oidp, &throttle, 0, req);
3448 if (error || req->newptr == NULL)
3450 if (throttle < 0 || throttle > 1000000000 / 256)
3455 * Set the interrupt throttling rate in 256ns increments,
3456 * recalculate sysctl value assignment to get exact frequency.
3458 throttle = 1000000000 / 256 / throttle;
3460 /* Upper 16bits of ITR is reserved and should be zero */
3461 if (throttle & 0xffff0000)
3465 ifnet_serialize_all(ifp);
3468 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3470 sc->int_throttle_ceil = 0;
3472 if (ifp->if_flags & IFF_RUNNING)
3473 emx_set_itr(sc, throttle);
3475 ifnet_deserialize_all(ifp);
3478 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3479 sc->int_throttle_ceil);
3485 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3487 struct emx_softc *sc = (void *)arg1;
3488 struct ifnet *ifp = &sc->arpcom.ac_if;
3491 segs = sc->tx_int_nsegs;
3492 error = sysctl_handle_int(oidp, &segs, 0, req);
3493 if (error || req->newptr == NULL)
3498 ifnet_serialize_all(ifp);
3501 * Don't allow int_tx_nsegs to become:
3502 * o Less the oact_tx_desc
3503 * o Too large that no TX desc will cause TX interrupt to
3504 * be generated (OACTIVE will never recover)
3505 * o Too small that will cause tx_dd[] overflow
3507 if (segs < sc->oact_tx_desc ||
3508 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3509 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3513 sc->tx_int_nsegs = segs;
3516 ifnet_deserialize_all(ifp);
3522 emx_dma_alloc(struct emx_softc *sc)
3527 * Create top level busdma tag
3529 error = bus_dma_tag_create(NULL, 1, 0,
3530 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3532 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3533 0, &sc->parent_dtag);
3535 device_printf(sc->dev, "could not create top level DMA tag\n");
3540 * Allocate transmit descriptors ring and buffers
3542 error = emx_create_tx_ring(sc);
3544 device_printf(sc->dev, "Could not setup transmit structures\n");
3549 * Allocate receive descriptors ring and buffers
3551 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3552 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3554 device_printf(sc->dev,
3555 "Could not setup receive structures\n");
3563 emx_dma_free(struct emx_softc *sc)
3567 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3569 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3570 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3571 sc->rx_data[i].num_rx_desc);
3574 /* Free top level busdma tag */
3575 if (sc->parent_dtag != NULL)
3576 bus_dma_tag_destroy(sc->parent_dtag);
3580 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3582 struct emx_softc *sc = ifp->if_softc;
3585 case IFNET_SERIALIZE_ALL:
3586 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0);
3589 case IFNET_SERIALIZE_MAIN:
3590 lwkt_serialize_enter(&sc->main_serialize);
3593 case IFNET_SERIALIZE_TX:
3594 lwkt_serialize_enter(&sc->tx_serialize);
3597 case IFNET_SERIALIZE_RX(0):
3598 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize);
3601 case IFNET_SERIALIZE_RX(1):
3602 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize);
3606 panic("%s unsupported serialize type\n", ifp->if_xname);
3611 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3613 struct emx_softc *sc = ifp->if_softc;
3616 case IFNET_SERIALIZE_ALL:
3617 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0);
3620 case IFNET_SERIALIZE_MAIN:
3621 lwkt_serialize_exit(&sc->main_serialize);
3624 case IFNET_SERIALIZE_TX:
3625 lwkt_serialize_exit(&sc->tx_serialize);
3628 case IFNET_SERIALIZE_RX(0):
3629 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize);
3632 case IFNET_SERIALIZE_RX(1):
3633 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize);
3637 panic("%s unsupported serialize type\n", ifp->if_xname);
3642 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3644 struct emx_softc *sc = ifp->if_softc;
3647 case IFNET_SERIALIZE_ALL:
3648 return lwkt_serialize_array_try(sc->serializes,
3651 case IFNET_SERIALIZE_MAIN:
3652 return lwkt_serialize_try(&sc->main_serialize);
3654 case IFNET_SERIALIZE_TX:
3655 return lwkt_serialize_try(&sc->tx_serialize);
3657 case IFNET_SERIALIZE_RX(0):
3658 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize);
3660 case IFNET_SERIALIZE_RX(1):
3661 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize);
3664 panic("%s unsupported serialize type\n", ifp->if_xname);
3669 emx_serialize_skipmain(struct emx_softc *sc)
3671 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3675 emx_deserialize_skipmain(struct emx_softc *sc)
3677 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3683 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3684 boolean_t serialized)
3686 struct emx_softc *sc = ifp->if_softc;
3690 case IFNET_SERIALIZE_ALL:
3692 for (i = 0; i < EMX_NSERIALIZE; ++i)
3693 ASSERT_SERIALIZED(sc->serializes[i]);
3695 for (i = 0; i < EMX_NSERIALIZE; ++i)
3696 ASSERT_NOT_SERIALIZED(sc->serializes[i]);
3700 case IFNET_SERIALIZE_MAIN:
3702 ASSERT_SERIALIZED(&sc->main_serialize);
3704 ASSERT_NOT_SERIALIZED(&sc->main_serialize);
3707 case IFNET_SERIALIZE_TX:
3709 ASSERT_SERIALIZED(&sc->tx_serialize);
3711 ASSERT_NOT_SERIALIZED(&sc->tx_serialize);
3714 case IFNET_SERIALIZE_RX(0):
3716 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3718 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3721 case IFNET_SERIALIZE_RX(1):
3723 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3725 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3729 panic("%s unsupported serialize type\n", ifp->if_xname);
3733 #endif /* INVARIANTS */
3735 #ifdef IFPOLL_ENABLE
3738 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3740 struct emx_softc *sc = ifp->if_softc;
3743 ASSERT_SERIALIZED(&sc->main_serialize);
3745 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3746 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3747 emx_serialize_skipmain(sc);
3749 callout_stop(&sc->timer);
3750 sc->hw.mac.get_link_status = 1;
3751 emx_update_link_status(sc);
3752 callout_reset(&sc->timer, hz, emx_timer, sc);
3754 emx_deserialize_skipmain(sc);
3759 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3761 struct emx_softc *sc = ifp->if_softc;
3763 ASSERT_SERIALIZED(&sc->tx_serialize);
3766 if (!ifq_is_empty(&ifp->if_snd))
3771 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3773 struct emx_softc *sc = ifp->if_softc;
3774 struct emx_rxdata *rdata = arg;
3776 ASSERT_SERIALIZED(&rdata->rx_serialize);
3778 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3782 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3784 struct emx_softc *sc = ifp->if_softc;
3786 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3791 info->ifpi_status.status_func = emx_qpoll_status;
3792 info->ifpi_status.serializer = &sc->main_serialize;
3794 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3795 info->ifpi_tx[0].arg = NULL;
3796 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3798 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3799 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3800 info->ifpi_rx[i].arg = &sc->rx_data[i];
3801 info->ifpi_rx[i].serializer =
3802 &sc->rx_data[i].rx_serialize;
3805 if (ifp->if_flags & IFF_RUNNING)
3806 emx_disable_intr(sc);
3807 } else if (ifp->if_flags & IFF_RUNNING) {
3808 emx_enable_intr(sc);
3812 #endif /* IFPOLL_ENABLE */
3815 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3817 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3818 if (sc->hw.mac.type == e1000_82574) {
3822 * When using MSIX interrupts we need to
3823 * throttle using the EITR register
3825 for (i = 0; i < 4; ++i)
3826 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);